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gerrit-public.fairphone.software / kernel / msm-4.19 / f30f9a5e7bc130c727712342dd064ae8d188b170 / . / arch / x86 / pci / olpc.c
blob: 5262603b04d9d0b849df61ab98890705c1bed155 [file] [log] [blame]
Andres Salomon3ef0e1f2008-04-29 00:59:53 -0700[diff] [blame]1/*
2 * Low-level PCI config space access for OLPC systems who lack the VSA
3 * PCI virtualization software.
4 *
5 * Copyright © 2006 Advanced Micro Devices, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * The AMD Geode chipset (ie: GX2 processor, cs5536 I/O companion device)
13 * has some I/O functions (display, southbridge, sound, USB HCIs, etc)
14 * that more or less behave like PCI devices, but the hardware doesn't
15 * directly implement the PCI configuration space headers. AMD provides
16 * "VSA" (Virtual System Architecture) software that emulates PCI config
17 * space for these devices, by trapping I/O accesses to PCI config register
18 * (CF8/CFC) and running some code in System Management Mode interrupt state.
19 * On the OLPC platform, we don't want to use that VSA code because
20 * (a) it slows down suspend/resume, and (b) recompiling it requires special
21 * compilers that are hard to get. So instead of letting the complex VSA
22 * code simulate the PCI config registers for the on-chip devices, we
23 * just simulate them the easy way, by inserting the code into the
24 * pci_write_config and pci_read_config path. Most of the config registers
25 * are read-only anyway, so the bulk of the simulation is just table lookup.
26 */
27
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <asm/olpc.h>
31#include <asm/geode.h>
Jaswinder Singh Rajput82487712008-12-27 18:32:28 +0530[diff] [blame]32#include <asm/pci_x86.h>
Andres Salomon3ef0e1f2008-04-29 00:59:53 -0700[diff] [blame]33
34/*
35 * In the tables below, the first two line (8 longwords) are the
36 * size masks that are used when the higher level PCI code determines
37 * the size of the region by writing ~0 to a base address register
38 * and reading back the result.
39 *
40 * The following lines are the values that are read during normal
41 * PCI config access cycles, i.e. not after just having written
42 * ~0 to a base address register.
43 */
44
45static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
46 0x0, 0x0, 0x0, 0x0,
47 0x0, 0x0, 0x0, 0x0,
48
49 0x281022, 0x2200005, 0x6000021, 0x80f808, /* AMD Vendor ID */
50 0x0, 0x0, 0x0, 0x0, /* No virtual registers, hence no BAR */
51 0x0, 0x0, 0x0, 0x28100b,
52 0x0, 0x0, 0x0, 0x0,
53 0x0, 0x0, 0x0, 0x0,
54 0x0, 0x0, 0x0, 0x0,
55 0x0, 0x0, 0x0, 0x0,
56};
57
58static const uint32_t gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
59 0xfffffffd, 0x0, 0x0, 0x0,
60 0x0, 0x0, 0x0, 0x0,
61
62 0x28100b, 0x2200005, 0x6000021, 0x80f808, /* NSC Vendor ID */
63 0xac1d, 0x0, 0x0, 0x0, /* I/O BAR - base of virtual registers */
64 0x0, 0x0, 0x0, 0x28100b,
65 0x0, 0x0, 0x0, 0x0,
66 0x0, 0x0, 0x0, 0x0,
67 0x0, 0x0, 0x0, 0x0,
68 0x0, 0x0, 0x0, 0x0,
69};
70
71static const uint32_t lxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */
72 0xff000008, 0xffffc000, 0xffffc000, 0xffffc000,
73 0xffffc000, 0x0, 0x0, 0x0,
74
75 0x20811022, 0x2200003, 0x3000000, 0x0, /* AMD Vendor ID */
76 0xfd000000, 0xfe000000, 0xfe004000, 0xfe008000, /* FB, GP, VG, DF */
77 0xfe00c000, 0x0, 0x0, 0x30100b, /* VIP */
78 0x0, 0x0, 0x0, 0x10e, /* INTA, IRQ14 for graphics accel */
79 0x0, 0x0, 0x0, 0x0,
80 0x3d0, 0x3c0, 0xa0000, 0x0, /* VG IO, VG IO, EGA FB, MONO FB */
81 0x0, 0x0, 0x0, 0x0,
82};
83
84static const uint32_t gxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */
85 0xff800008, 0xffffc000, 0xffffc000, 0xffffc000,
86 0x0, 0x0, 0x0, 0x0,
87
88 0x30100b, 0x2200003, 0x3000000, 0x0, /* NSC Vendor ID */
89 0xfd000000, 0xfe000000, 0xfe004000, 0xfe008000, /* FB, GP, VG, DF */
90 0x0, 0x0, 0x0, 0x30100b,
91 0x0, 0x0, 0x0, 0x0,
92 0x0, 0x0, 0x0, 0x0,
93 0x3d0, 0x3c0, 0xa0000, 0x0, /* VG IO, VG IO, EGA FB, MONO FB */
94 0x0, 0x0, 0x0, 0x0,
95};
96
97static const uint32_t aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */
98 0xffffc000, 0x0, 0x0, 0x0,
99 0x0, 0x0, 0x0, 0x0,
100
101 0x20821022, 0x2a00006, 0x10100000, 0x8, /* NSC Vendor ID */
102 0xfe010000, 0x0, 0x0, 0x0, /* AES registers */
103 0x0, 0x0, 0x0, 0x20821022,
104 0x0, 0x0, 0x0, 0x0,
105 0x0, 0x0, 0x0, 0x0,
106 0x0, 0x0, 0x0, 0x0,
107 0x0, 0x0, 0x0, 0x0,
108};
109
110
111static const uint32_t isa_hdr[] = { /* dev f function 0 - devfn = 78 */
112 0xfffffff9, 0xffffff01, 0xffffffc1, 0xffffffe1,
113 0xffffff81, 0xffffffc1, 0x0, 0x0,
114
115 0x20901022, 0x2a00049, 0x6010003, 0x802000,
116 0x18b1, 0x1001, 0x1801, 0x1881, /* SMB-8 GPIO-256 MFGPT-64 IRQ-32 */
117 0x1401, 0x1841, 0x0, 0x20901022, /* PMS-128 ACPI-64 */
118 0x0, 0x0, 0x0, 0x0,
119 0x0, 0x0, 0x0, 0x0,
120 0x0, 0x0, 0x0, 0xaa5b, /* IRQ steering */
121 0x0, 0x0, 0x0, 0x0,
122};
123
124static const uint32_t ac97_hdr[] = { /* dev f function 3 - devfn = 7b */
125 0xffffff81, 0x0, 0x0, 0x0,
126 0x0, 0x0, 0x0, 0x0,
127
128 0x20931022, 0x2a00041, 0x4010001, 0x0,
129 0x1481, 0x0, 0x0, 0x0, /* I/O BAR-128 */
130 0x0, 0x0, 0x0, 0x20931022,
131 0x0, 0x0, 0x0, 0x205, /* IntB, IRQ5 */
132 0x0, 0x0, 0x0, 0x0,
133 0x0, 0x0, 0x0, 0x0,
134 0x0, 0x0, 0x0, 0x0,
135};
136
137static const uint32_t ohci_hdr[] = { /* dev f function 4 - devfn = 7c */
138 0xfffff000, 0x0, 0x0, 0x0,
139 0x0, 0x0, 0x0, 0x0,
140
141 0x20941022, 0x2300006, 0xc031002, 0x0,
142 0xfe01a000, 0x0, 0x0, 0x0, /* MEMBAR-1000 */
143 0x0, 0x0, 0x0, 0x20941022,
144 0x0, 0x40, 0x0, 0x40a, /* CapPtr INT-D, IRQA */
145 0xc8020001, 0x0, 0x0, 0x0, /* Capabilities - 40 is R/O,
146 44 is mask 8103 (power control) */
147 0x0, 0x0, 0x0, 0x0,
148 0x0, 0x0, 0x0, 0x0,
149};
150
151static const uint32_t ehci_hdr[] = { /* dev f function 4 - devfn = 7d */
152 0xfffff000, 0x0, 0x0, 0x0,
153 0x0, 0x0, 0x0, 0x0,
154
155 0x20951022, 0x2300006, 0xc032002, 0x0,
156 0xfe01b000, 0x0, 0x0, 0x0, /* MEMBAR-1000 */
157 0x0, 0x0, 0x0, 0x20951022,
158 0x0, 0x40, 0x0, 0x40a, /* CapPtr INT-D, IRQA */
159 0xc8020001, 0x0, 0x0, 0x0, /* Capabilities - 40 is R/O, 44 is
160 mask 8103 (power control) */
161#if 0
162 0x1, 0x40080000, 0x0, 0x0, /* EECP - see EHCI spec section 2.1.7 */
163#endif
164 0x01000001, 0x0, 0x0, 0x0, /* EECP - see EHCI spec section 2.1.7 */
165 0x2020, 0x0, 0x0, 0x0, /* (EHCI page 8) 60 SBRN (R/O),
166 61 FLADJ (R/W), PORTWAKECAP */
167};
168
169static uint32_t ff_loc = ~0;
170static uint32_t zero_loc;
171static int bar_probing; /* Set after a write of ~0 to a BAR */
172static int is_lx;
173
174#define NB_SLOT 0x1 /* Northbridge - GX chip - Device 1 */
175#define SB_SLOT 0xf /* Southbridge - CS5536 chip - Device F */
176
177static int is_simulated(unsigned int bus, unsigned int devfn)
178{
179 return (!bus && ((PCI_SLOT(devfn) == NB_SLOT) ||
180 (PCI_SLOT(devfn) == SB_SLOT)));
181}
182
183static uint32_t *hdr_addr(const uint32_t *hdr, int reg)
184{
185 uint32_t addr;
186
187 /*
188 * This is a little bit tricky. The header maps consist of
189 * 0x20 bytes of size masks, followed by 0x70 bytes of header data.
190 * In the normal case, when not probing a BAR's size, we want
191 * to access the header data, so we add 0x20 to the reg offset,
192 * thus skipping the size mask area.
193 * In the BAR probing case, we want to access the size mask for
194 * the BAR, so we subtract 0x10 (the config header offset for
195 * BAR0), and don't skip the size mask area.
196 */
197
198 addr = (uint32_t)hdr + reg + (bar_probing ? -0x10 : 0x20);
199
200 bar_probing = 0;
201 return (uint32_t *)addr;
202}
203
204static int pci_olpc_read(unsigned int seg, unsigned int bus,
205 unsigned int devfn, int reg, int len, uint32_t *value)
206{
207 uint32_t *addr;
208
Jan Beulichdb34a362011-07-22 08:13:05 +0100[diff] [blame]209 WARN_ON(seg);
210
Andres Salomon3ef0e1f2008-04-29 00:59:53 -0700[diff] [blame]211 /* Use the hardware mechanism for non-simulated devices */
212 if (!is_simulated(bus, devfn))
213 return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
214
215 /*
216 * No device has config registers past 0x70, so we save table space
217 * by not storing entries for the nonexistent registers
218 */
219 if (reg >= 0x70)
220 addr = &zero_loc;
221 else {
222 switch (devfn) {
223 case 0x8:
224 addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg);
225 break;
226 case 0x9:
227 addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg);
228 break;
229 case 0xa:
230 addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc;
231 break;
232 case 0x78:
233 addr = hdr_addr(isa_hdr, reg);
234 break;
235 case 0x7b:
236 addr = hdr_addr(ac97_hdr, reg);
237 break;
238 case 0x7c:
239 addr = hdr_addr(ohci_hdr, reg);
240 break;
241 case 0x7d:
242 addr = hdr_addr(ehci_hdr, reg);
243 break;
244 default:
245 addr = &ff_loc;
246 break;
247 }
248 }
249 switch (len) {
250 case 1:
251 *value = *(uint8_t *)addr;
252 break;
253 case 2:
254 *value = *(uint16_t *)addr;
255 break;
256 case 4:
257 *value = *addr;
258 break;
259 default:
260 BUG();
261 }
262
263 return 0;
264}
265
266static int pci_olpc_write(unsigned int seg, unsigned int bus,
267 unsigned int devfn, int reg, int len, uint32_t value)
268{
Jan Beulichdb34a362011-07-22 08:13:05 +0100[diff] [blame]269 WARN_ON(seg);
270
Andres Salomon3ef0e1f2008-04-29 00:59:53 -0700[diff] [blame]271 /* Use the hardware mechanism for non-simulated devices */
272 if (!is_simulated(bus, devfn))
273 return pci_direct_conf1.write(seg, bus, devfn, reg, len, value);
274
275 /* XXX we may want to extend this to simulate EHCI power management */
276
277 /*
278 * Mostly we just discard writes, but if the write is a size probe
279 * (i.e. writing ~0 to a BAR), we remember it and arrange to return
280 * the appropriate size mask on the next read. This is cheating
281 * to some extent, because it depends on the fact that the next
282 * access after such a write will always be a read to the same BAR.
283 */
284
285 if ((reg >= 0x10) && (reg < 0x2c)) {
286 /* write is to a BAR */
287 if (value == ~0)
288 bar_probing = 1;
289 } else {
290 /*
291 * No warning on writes to ROM BAR, CMD, LATENCY_TIMER,
292 * CACHE_LINE_SIZE, or PM registers.
293 */
294 if ((reg != PCI_ROM_ADDRESS) && (reg != PCI_COMMAND_MASTER) &&
295 (reg != PCI_LATENCY_TIMER) &&
296 (reg != PCI_CACHE_LINE_SIZE) && (reg != 0x44))
297 printk(KERN_WARNING "OLPC PCI: Config write to devfn"
298 " %x reg %x value %x\n", devfn, reg, value);
299 }
300
301 return 0;
302}
303
304static struct pci_raw_ops pci_olpc_conf = {
305 .read = pci_olpc_read,
306 .write = pci_olpc_write,
307};
308
Andres Salomon2bdd1b02008-06-05 14:14:41 -0700[diff] [blame]309int __init pci_olpc_init(void)
Andres Salomon3ef0e1f2008-04-29 00:59:53 -0700[diff] [blame]310{
Daniel Drake76fb6572010-09-23 17:28:04 +0100[diff] [blame]311 printk(KERN_INFO "PCI: Using configuration type OLPC XO-1\n");
Andres Salomon3ef0e1f2008-04-29 00:59:53 -0700[diff] [blame]312 raw_pci_ops = &pci_olpc_conf;
313 is_lx = is_geode_lx();
Andres Salomon2bdd1b02008-06-05 14:14:41 -0700[diff] [blame]314 return 0;
Andres Salomon3ef0e1f2008-04-29 00:59:53 -0700[diff] [blame]315}