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Huang Shijiee10db1f2012-05-04 21:42:05 -04001* Freescale General-Purpose Media Interface (GPMI)
2
3The GPMI nand controller provides an interface to control the
4NAND flash chips. We support only one NAND chip now.
5
6Required properties:
7 - compatible : should be "fsl,<chip>-gpmi-nand"
8 - reg : should contain registers location and length for gpmi and bch.
9 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
Shawn Guo5fac0e12013-02-26 11:44:28 +080010 - interrupts : BCH interrupt number.
11 - interrupt-names : Should be "bch".
12 - dmas: DMA specifier, consisting of a phandle to DMA controller node
13 and GPMI DMA channel ID.
14 Refer to dma.txt and fsl-mxs-dma.txt for details.
15 - dma-names: Must be "rx-tx".
Huang Shijiee10db1f2012-05-04 21:42:05 -040016
Huang Shijiec50c6942012-07-03 16:24:32 +080017Optional properties:
18 - nand-on-flash-bbt: boolean to enable on flash bbt option if not
19 present false
Huang Shijie89b59e62013-11-07 18:07:38 +080020 - fsl,use-minimum-ecc: Protect this NAND flash with the minimum ECC
21 strength required. The required ECC strength is
22 automatically discoverable for some flash
23 (e.g., according to the ONFI standard).
24 However, note that if this strength is not
25 discoverable or this property is not enabled,
26 the software may chooses an implementation-defined
27 ECC scheme.
Huang Shijiec50c6942012-07-03 16:24:32 +080028
Huang Shijiee10db1f2012-05-04 21:42:05 -040029The device tree may optionally contain sub-nodes describing partitions of the
30address space. See partition.txt for more detail.
31
32Examples:
33
34gpmi-nand@8000c000 {
35 compatible = "fsl,imx28-gpmi-nand";
36 #address-cells = <1>;
37 #size-cells = <1>;
38 reg = <0x8000c000 2000>, <0x8000a000 2000>;
39 reg-names = "gpmi-nand", "bch";
Shawn Guo5fac0e12013-02-26 11:44:28 +080040 interrupts = <41>;
41 interrupt-names = "bch";
42 dmas = <&dma_apbh 4>;
43 dma-names = "rx-tx";
Huang Shijiee10db1f2012-05-04 21:42:05 -040044
45 partition@0 {
46 ...
47 };
48};