| Simon Horman | f45b114 | 2011-01-11 04:01:08 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * sh7372 MMCIF loader |
| 3 | * |
| 4 | * Copyright (C) 2010 Magnus Damm |
| 5 | * Copyright (C) 2010 Simon Horman |
| 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General Public |
| 8 | * License. See the file "COPYING" in the main directory of this archive |
| 9 | * for more details. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/mmc/sh_mmcif.h> |
| 13 | #include <mach/mmcif.h> |
| 14 | |
| 15 | #define MMCIF_BASE (void __iomem *)0xe6bd0000 |
| 16 | |
| 17 | #define PORT84CR (void __iomem *)0xe6050054 |
| 18 | #define PORT85CR (void __iomem *)0xe6050055 |
| 19 | #define PORT86CR (void __iomem *)0xe6050056 |
| 20 | #define PORT87CR (void __iomem *)0xe6050057 |
| 21 | #define PORT88CR (void __iomem *)0xe6050058 |
| 22 | #define PORT89CR (void __iomem *)0xe6050059 |
| 23 | #define PORT90CR (void __iomem *)0xe605005a |
| 24 | #define PORT91CR (void __iomem *)0xe605005b |
| 25 | #define PORT92CR (void __iomem *)0xe605005c |
| 26 | #define PORT99CR (void __iomem *)0xe6050063 |
| 27 | |
| 28 | #define SMSTPCR3 (void __iomem *)0xe615013c |
| 29 | |
| 30 | /* SH7372 specific MMCIF loader |
| 31 | * |
| 32 | * loads the zImage from an MMC card starting from block 1. |
| 33 | * |
| 34 | * The image must be start with a vrl4 header and |
| 35 | * the zImage must start at offset 512 of the image. That is, |
| 36 | * at block 2 (=byte 1024) on the media |
| 37 | * |
| 38 | * Use the following line to write the vrl4 formated zImage |
| 39 | * to an MMC card |
| 40 | * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1 |
| 41 | */ |
| 42 | asmlinkage void mmcif_loader(unsigned char *buf, unsigned long len) |
| 43 | { |
| 44 | mmcif_init_progress(); |
| 45 | mmcif_update_progress(MMCIF_PROGRESS_ENTER); |
| 46 | |
| 47 | /* Initialise MMC |
| 48 | * registers: PORT84CR-PORT92CR |
| 49 | * (MMCD0_0-MMCD0_7,MMCCMD0 Control) |
| 50 | * value: 0x04 - select function 4 |
| 51 | */ |
| 52 | __raw_writeb(0x04, PORT84CR); |
| 53 | __raw_writeb(0x04, PORT85CR); |
| 54 | __raw_writeb(0x04, PORT86CR); |
| 55 | __raw_writeb(0x04, PORT87CR); |
| 56 | __raw_writeb(0x04, PORT88CR); |
| 57 | __raw_writeb(0x04, PORT89CR); |
| 58 | __raw_writeb(0x04, PORT90CR); |
| 59 | __raw_writeb(0x04, PORT91CR); |
| 60 | __raw_writeb(0x04, PORT92CR); |
| 61 | |
| 62 | /* Initialise MMC |
| 63 | * registers: PORT99CR (MMCCLK0 Control) |
| 64 | * value: 0x10 | 0x04 - enable output | select function 4 |
| 65 | */ |
| 66 | __raw_writeb(0x14, PORT99CR); |
| 67 | |
| 68 | /* Enable clock to MMC hardware block */ |
| 69 | __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3); |
| 70 | |
| 71 | mmcif_update_progress(MMCIF_PROGRESS_INIT); |
| 72 | |
| 73 | /* setup MMCIF hardware */ |
| 74 | sh_mmcif_boot_init(MMCIF_BASE); |
| 75 | |
| 76 | mmcif_update_progress(MMCIF_PROGRESS_LOAD); |
| 77 | |
| 78 | /* load kernel via MMCIF interface */ |
| 79 | sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */ |
| 80 | (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf); |
| 81 | |
| 82 | |
| 83 | /* Disable clock to MMC hardware block */ |
| 84 | __raw_writel(__raw_readl(SMSTPCR3) & (1 << 12), SMSTPCR3); |
| 85 | |
| 86 | mmcif_update_progress(MMCIF_PROGRESS_DONE); |
| 87 | } |