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Steffen Trumtrarbe3a5682013-01-10 11:27:27 +01001/*
2 * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3 * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
Shawn Guo36dffd82013-04-07 10:49:34 +080014#include "imx53-tqma53.dtsi"
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +010015
16/ {
17 model = "TQ MBa53 starter kit";
18 compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
Sascha Hauer4fa8cf72013-06-04 13:07:09 +020019
Sascha Hauer4fa8cf72013-06-04 13:07:09 +020020 backlight {
21 compatible = "pwm-backlight";
Laurent Pinchart15968f12013-07-11 16:37:47 +020022 pwms = <&pwm2 0 50000>;
Sascha Hauer4fa8cf72013-06-04 13:07:09 +020023 brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
24 default-brightness-level = <10>;
25 enable-gpios = <&gpio7 7 0>;
26 power-supply = <&reg_backlight>;
27 };
28
29 disp1: display@disp1 {
30 compatible = "fsl,imx-parallel-display";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_disp1_1>;
33 crtcs = <&ipu 1>;
34 interface-pix-fmt = "rgb24";
35 status = "disabled";
36 };
Markus Niebeleefb8002013-06-04 13:07:11 +020037
Shawn Guoa4a2aa92013-11-06 15:43:36 +080038 regulators {
39 compatible = "simple-bus";
Shawn Guo352d3182014-02-07 23:18:30 +080040 #address-cells = <1>;
41 #size-cells = <0>;
Shawn Guoa4a2aa92013-11-06 15:43:36 +080042
Shawn Guo352d3182014-02-07 23:18:30 +080043 reg_backlight: regulator@0 {
Shawn Guoa4a2aa92013-11-06 15:43:36 +080044 compatible = "regulator-fixed";
Shawn Guo352d3182014-02-07 23:18:30 +080045 reg = <0>;
Shawn Guoa4a2aa92013-11-06 15:43:36 +080046 regulator-name = "lcd-supply";
47 gpio = <&gpio2 5 0>;
48 startup-delay-us = <5000>;
49 enable-active-low;
50 };
51
Shawn Guo352d3182014-02-07 23:18:30 +080052 reg_3p2v: regulator@1 {
Shawn Guoa4a2aa92013-11-06 15:43:36 +080053 compatible = "regulator-fixed";
Shawn Guo352d3182014-02-07 23:18:30 +080054 reg = <1>;
Shawn Guoa4a2aa92013-11-06 15:43:36 +080055 regulator-name = "3P2V";
56 regulator-min-microvolt = <3200000>;
57 regulator-max-microvolt = <3200000>;
58 regulator-always-on;
59 };
Markus Niebeleefb8002013-06-04 13:07:11 +020060 };
61
62 sound {
63 compatible = "tq,imx53-mba53-sgtl5000",
64 "fsl,imx-audio-sgtl5000";
65 model = "imx53-mba53-sgtl5000";
66 ssi-controller = <&ssi2>;
67 audio-codec = <&codec>;
68 audio-routing =
69 "MIC_IN", "Mic Jack",
70 "Mic Jack", "Mic Bias",
71 "Headphone Jack", "HP_OUT";
72 mux-int-port = <2>;
73 mux-ext-port = <5>;
74 };
Sascha Hauer4fa8cf72013-06-04 13:07:09 +020075};
76
77&ldb {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_lvds1_1>;
80 status = "disabled";
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +010081};
82
83&iomuxc {
84 lvds1 {
85 pinctrl_lvds1_1: lvds1-grp1 {
Shawn Guoe1641532013-02-20 10:32:52 +080086 fsl,pins = <
Steffen Trumtrar188e97d2013-06-04 13:07:14 +020087 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
88 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
89 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
90 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
91 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
Shawn Guoe1641532013-02-20 10:32:52 +080092 >;
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +010093 };
94
95 pinctrl_lvds1_2: lvds1-grp2 {
Shawn Guoe1641532013-02-20 10:32:52 +080096 fsl,pins = <
Steffen Trumtrar188e97d2013-06-04 13:07:14 +020097 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
98 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
99 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
100 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
101 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
Shawn Guoe1641532013-02-20 10:32:52 +0800102 >;
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +0100103 };
104 };
105
106 disp1 {
107 pinctrl_disp1_1: disp1-grp1 {
Shawn Guoe1641532013-02-20 10:32:52 +0800108 fsl,pins = <
Markus Niebel81b8a3c2013-06-04 13:07:15 +0200109 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
Steffen Trumtrar188e97d2013-06-04 13:07:14 +0200110 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */
111 MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */
112 MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */
113 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
114 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
115 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
116 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
117 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
118 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
119 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
120 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
121 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
122 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
123 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
124 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
125 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
126 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
127 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000
128 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000
129 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000
130 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000
131 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000
132 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000
133 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000
134 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000
135 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000
136 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000
Shawn Guoe1641532013-02-20 10:32:52 +0800137 >;
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +0100138 };
139 };
Philipp Zabeld7db5392013-06-04 13:07:10 +0200140
141 tve {
142 pinctrl_vga_sync_1: vgasync-grp1 {
143 fsl,pins = <
144 /* VGA_VSYNC, HSYNC with max drive strength */
145 MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
146 MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
147 >;
148 };
149 };
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +0100150};
151
152&cspi {
153 status = "okay";
154};
155
Markus Niebeleefb8002013-06-04 13:07:11 +0200156&audmux {
157 status = "okay";
158 pinctrl-names = "default";
Shawn Guo7ac0f702013-11-04 14:45:46 +0800159 pinctrl-0 = <&pinctrl_audmux>;
Markus Niebeleefb8002013-06-04 13:07:11 +0200160};
161
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +0100162&i2c2 {
163 codec: sgtl5000@a {
164 compatible = "fsl,sgtl5000";
165 reg = <0x0a>;
Markus Niebeleefb8002013-06-04 13:07:11 +0200166 clocks = <&clks 150>;
167 VDDA-supply = <&reg_3p2v>;
168 VDDIO-supply = <&reg_3p2v>;
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +0100169 };
170
171 expander: pca9554@20 {
172 compatible = "pca9554";
173 reg = <0x20>;
174 interrupts = <109>;
Markus Niebel74154be2013-06-04 13:07:12 +0200175 #gpio-cells = <2>;
176 gpio-controller;
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +0100177 };
178
179 sensor2: lm75@49 {
180 compatible = "lm75";
181 reg = <0x49>;
182 };
183};
184
185&fec {
Markus Niebeldeb19eb2013-06-04 13:07:13 +0200186 phy-reset-gpios = <&gpio7 6 0>;
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +0100187 status = "okay";
188};
189
190&esdhc2 {
191 status = "okay";
192};
193
194&uart3 {
195 status = "okay";
196};
197
198&ecspi1 {
199 status = "okay";
200};
201
Michael Olbrich3b1a0f22013-06-04 13:07:08 +0200202&usbotg {
203 dr_mode = "host";
204 status = "okay";
205};
206
207&usbh1 {
208 status = "okay";
209};
210
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +0100211&uart1 {
212 status = "okay";
213};
214
Markus Niebeleefb8002013-06-04 13:07:11 +0200215&ssi2 {
216 fsl,mode = "i2s-slave";
217 status = "okay";
218};
219
Steffen Trumtrarbe3a5682013-01-10 11:27:27 +0100220&uart2 {
221 status = "okay";
222};
223
224&can1 {
225 status = "okay";
226};
227
228&can2 {
229 status = "okay";
230};
231
232&i2c3 {
233 status = "okay";
234};
Philipp Zabeld7db5392013-06-04 13:07:10 +0200235
236&tve {
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_vga_sync_1>;
239 ddc = <&i2c3>;
240 fsl,tve-mode = "vga";
241 fsl,hsync-pin = <4>;
242 fsl,vsync-pin = <6>;
243 status = "okay";
244};