blob: 23735a36af00c5fae6131f1b5a28ebde5aae4584 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * This file is licenced under the GPL.
8 */
9
10/*-------------------------------------------------------------------------*/
11
12/*
13 * There's basically three types of memory:
14 * - data used only by the HCD ... kmalloc is fine
15 * - async and periodic schedules, shared by HC and HCD ... these
16 * need to use dma_pool or dma_alloc_coherent
17 * - driver buffers, read/written by HC ... the hcd glue or the
18 * device driver provides us with dma addresses
19 *
20 * There's also PCI "register" data, which is memory mapped.
21 * No memory seen by this driver is pagable.
22 */
23
24/*-------------------------------------------------------------------------*/
25
26static void ohci_hcd_init (struct ohci_hcd *ohci)
27{
28 ohci->next_statechange = jiffies;
29 spin_lock_init (&ohci->lock);
30 INIT_LIST_HEAD (&ohci->pending);
31 INIT_WORK (&ohci->rh_resume, ohci_rh_resume, ohci_to_hcd(ohci));
David Brownellf4df0e32005-04-23 12:49:16 -070032 ohci->reboot_notifier.notifier_call = ohci_reboot;
Linus Torvalds1da177e2005-04-16 15:20:36 -070033}
34
35/*-------------------------------------------------------------------------*/
36
37static int ohci_mem_init (struct ohci_hcd *ohci)
38{
39 ohci->td_cache = dma_pool_create ("ohci_td",
40 ohci_to_hcd(ohci)->self.controller,
41 sizeof (struct td),
42 32 /* byte alignment */,
43 0 /* no page-crossing issues */);
44 if (!ohci->td_cache)
45 return -ENOMEM;
46 ohci->ed_cache = dma_pool_create ("ohci_ed",
47 ohci_to_hcd(ohci)->self.controller,
48 sizeof (struct ed),
49 16 /* byte alignment */,
50 0 /* no page-crossing issues */);
51 if (!ohci->ed_cache) {
52 dma_pool_destroy (ohci->td_cache);
53 return -ENOMEM;
54 }
55 return 0;
56}
57
58static void ohci_mem_cleanup (struct ohci_hcd *ohci)
59{
60 if (ohci->td_cache) {
61 dma_pool_destroy (ohci->td_cache);
62 ohci->td_cache = NULL;
63 }
64 if (ohci->ed_cache) {
65 dma_pool_destroy (ohci->ed_cache);
66 ohci->ed_cache = NULL;
67 }
68}
69
70/*-------------------------------------------------------------------------*/
71
72/* ohci "done list" processing needs this mapping */
73static inline struct td *
74dma_to_td (struct ohci_hcd *hc, dma_addr_t td_dma)
75{
76 struct td *td;
77
78 td_dma &= TD_MASK;
79 td = hc->td_hash [TD_HASH_FUNC(td_dma)];
80 while (td && td->td_dma != td_dma)
81 td = td->td_hash;
82 return td;
83}
84
85/* TDs ... */
86static struct td *
87td_alloc (struct ohci_hcd *hc, int mem_flags)
88{
89 dma_addr_t dma;
90 struct td *td;
91
92 td = dma_pool_alloc (hc->td_cache, mem_flags, &dma);
93 if (td) {
94 /* in case hc fetches it, make it look dead */
95 memset (td, 0, sizeof *td);
96 td->hwNextTD = cpu_to_hc32 (hc, dma);
97 td->td_dma = dma;
98 /* hashed in td_fill */
99 }
100 return td;
101}
102
103static void
104td_free (struct ohci_hcd *hc, struct td *td)
105{
106 struct td **prev = &hc->td_hash [TD_HASH_FUNC (td->td_dma)];
107
108 while (*prev && *prev != td)
109 prev = &(*prev)->td_hash;
110 if (*prev)
111 *prev = td->td_hash;
112 else if ((td->hwINFO & cpu_to_hc32(hc, TD_DONE)) != 0)
113 ohci_dbg (hc, "no hash for td %p\n", td);
114 dma_pool_free (hc->td_cache, td, td->td_dma);
115}
116
117/*-------------------------------------------------------------------------*/
118
119/* EDs ... */
120static struct ed *
121ed_alloc (struct ohci_hcd *hc, int mem_flags)
122{
123 dma_addr_t dma;
124 struct ed *ed;
125
126 ed = dma_pool_alloc (hc->ed_cache, mem_flags, &dma);
127 if (ed) {
128 memset (ed, 0, sizeof (*ed));
129 INIT_LIST_HEAD (&ed->td_list);
130 ed->dma = dma;
131 }
132 return ed;
133}
134
135static void
136ed_free (struct ohci_hcd *hc, struct ed *ed)
137{
138 dma_pool_free (hc->ed_cache, ed, ed->dma);
139}
140