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Ben Dooks431107e2010-01-26 10:11:04 +09001/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
Ben Dooks5718df92008-10-21 14:07:09 +01002 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
Ben Dooks096941e2008-10-31 16:14:59 +000023#include <linux/i2c.h>
Ben Dooks438a5d42008-11-19 15:41:34 +000024#include <linux/fb.h>
25#include <linux/gpio.h>
26#include <linux/delay.h>
Mark Brown3056ea02009-01-27 16:18:01 +000027#include <linux/smsc911x.h>
Mark Brown42015c12009-11-03 14:42:06 +000028#include <linux/regulator/fixed.h>
Ben Dooks438a5d42008-11-19 15:41:34 +000029
Mark Brownecc558a2009-02-17 15:59:38 +000030#ifdef CONFIG_SMDK6410_WM1190_EV1
31#include <linux/mfd/wm8350/core.h>
32#include <linux/mfd/wm8350/pmic.h>
33#endif
Ben Dooks438a5d42008-11-19 15:41:34 +000034
35#include <video/platform_lcd.h>
Ben Dooks5718df92008-10-21 14:07:09 +010036
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <mach/hardware.h>
Ben Dooks438a5d42008-11-19 15:41:34 +000042#include <mach/regs-fb.h>
Ben Dooks5718df92008-10-21 14:07:09 +010043#include <mach/map.h>
44
45#include <asm/irq.h>
46#include <asm/mach-types.h>
47
48#include <plat/regs-serial.h>
Ben Dooks3501c9a2010-01-26 10:45:40 +090049#include <mach/regs-modem.h>
50#include <mach/regs-gpio.h>
51#include <mach/regs-sys.h>
52#include <mach/regs-srom.h>
Ben Dooksd85fa242008-10-31 16:14:52 +000053#include <plat/iic.h>
Ben Dooks438a5d42008-11-19 15:41:34 +000054#include <plat/fb.h>
Mark Brown3056ea02009-01-27 16:18:01 +000055#include <plat/gpio-cfg.h>
Ben Dooks5718df92008-10-21 14:07:09 +010056
Ben Dooksf7be9ab2010-01-26 13:41:30 +090057#include <mach/s3c6410.h>
Ben Dooks5718df92008-10-21 14:07:09 +010058#include <plat/clock.h>
59#include <plat/devs.h>
60#include <plat/cpu.h>
61
62#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
63#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
64#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
65
66static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
67 [0] = {
68 .hwport = 0,
69 .flags = 0,
Matt Hsubd258e52009-06-29 19:03:41 +080070 .ucon = UCON,
71 .ulcon = ULCON,
72 .ufcon = UFCON,
Ben Dooks5718df92008-10-21 14:07:09 +010073 },
74 [1] = {
75 .hwport = 1,
76 .flags = 0,
Matt Hsubd258e52009-06-29 19:03:41 +080077 .ucon = UCON,
78 .ulcon = ULCON,
79 .ufcon = UFCON,
80 },
81 [2] = {
82 .hwport = 2,
83 .flags = 0,
84 .ucon = UCON,
85 .ulcon = ULCON,
86 .ufcon = UFCON,
87 },
88 [3] = {
89 .hwport = 3,
90 .flags = 0,
91 .ucon = UCON,
92 .ulcon = ULCON,
93 .ufcon = UFCON,
Ben Dooks5718df92008-10-21 14:07:09 +010094 },
95};
96
Ben Dooks438a5d42008-11-19 15:41:34 +000097/* framebuffer and LCD setup. */
98
99/* GPF15 = LCD backlight control
100 * GPF13 => Panel power
101 * GPN5 = LCD nRESET signal
102 * PWM_TOUT1 => backlight brightness
103 */
104
105static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
106 unsigned int power)
107{
108 if (power) {
109 gpio_direction_output(S3C64XX_GPF(13), 1);
110 gpio_direction_output(S3C64XX_GPF(15), 1);
111
112 /* fire nRESET on power up */
113 gpio_direction_output(S3C64XX_GPN(5), 0);
114 msleep(10);
115 gpio_direction_output(S3C64XX_GPN(5), 1);
116 msleep(1);
117 } else {
118 gpio_direction_output(S3C64XX_GPF(15), 0);
119 gpio_direction_output(S3C64XX_GPF(13), 0);
120 }
121}
122
123static struct plat_lcd_data smdk6410_lcd_power_data = {
124 .set_power = smdk6410_lcd_power_set,
125};
126
127static struct platform_device smdk6410_lcd_powerdev = {
128 .name = "platform-lcd",
129 .dev.parent = &s3c_device_fb.dev,
130 .dev.platform_data = &smdk6410_lcd_power_data,
131};
132
133static struct s3c_fb_pd_win smdk6410_fb_win0 = {
134 /* this is to ensure we use win0 */
135 .win_mode = {
136 .pixclock = 41094,
137 .left_margin = 8,
138 .right_margin = 13,
139 .upper_margin = 7,
140 .lower_margin = 5,
141 .hsync_len = 3,
142 .vsync_len = 1,
143 .xres = 800,
144 .yres = 480,
145 },
146 .max_bpp = 32,
147 .default_bpp = 16,
148};
149
150/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
151static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
152 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
153 .win[0] = &smdk6410_fb_win0,
154 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
155 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
156};
157
Andy Greena4e94692009-12-29 14:40:43 +0000158/*
159 * Configuring Ethernet on SMDK6410
160 *
161 * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
162 * The constant address below corresponds to nCS1
163 *
164 * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
165 * 2) CFG6 needs to be switched to "LAN9115" side
166 */
167
Mark Brown3056ea02009-01-27 16:18:01 +0000168static struct resource smdk6410_smsc911x_resources[] = {
169 [0] = {
Andy Greenf01fdac2009-12-29 14:40:36 +0000170 .start = S3C64XX_PA_XM0CSN1,
171 .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
Mark Brown3056ea02009-01-27 16:18:01 +0000172 .flags = IORESOURCE_MEM,
173 },
174 [1] = {
175 .start = S3C_EINT(10),
176 .end = S3C_EINT(10),
177 .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
178 },
179};
180
181static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
182 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
183 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
184 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
185 .phy_interface = PHY_INTERFACE_MODE_MII,
186};
187
188
189static struct platform_device smdk6410_smsc911x = {
190 .name = "smsc911x",
191 .id = -1,
192 .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
193 .resource = &smdk6410_smsc911x_resources[0],
194 .dev = {
195 .platform_data = &smdk6410_smsc911x_pdata,
196 },
197};
198
Mark Brown42015c12009-11-03 14:42:06 +0000199#ifdef CONFIG_REGULATOR
200static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
201 {
202 /* WM8580 */
203 .supply = "PVDD",
204 .dev_name = "0-001b",
205 },
206 {
207 /* WM8580 */
208 .supply = "AVDD",
209 .dev_name = "0-001b",
210 },
211};
212
213static struct regulator_init_data smdk6410_b_pwr_5v_data = {
214 .constraints = {
215 .always_on = 1,
216 },
217 .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
218 .consumer_supplies = smdk6410_b_pwr_5v_consumers,
219};
220
221static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
222 .supply_name = "B_PWR_5V",
223 .microvolts = 5000000,
224 .init_data = &smdk6410_b_pwr_5v_data,
Mark Brownd3cf4482010-01-13 13:57:04 +0000225 .gpio = -EINVAL,
Mark Brown42015c12009-11-03 14:42:06 +0000226};
227
228static struct platform_device smdk6410_b_pwr_5v = {
229 .name = "reg-fixed-voltage",
230 .id = -1,
231 .dev = {
232 .platform_data = &smdk6410_b_pwr_5v_pdata,
233 },
234};
235#endif
236
Mark Brown027191a2009-01-23 16:29:43 +0000237static struct map_desc smdk6410_iodesc[] = {};
Ben Dooks5718df92008-10-21 14:07:09 +0100238
239static struct platform_device *smdk6410_devices[] __initdata = {
Ben Dooksb24636c2008-11-03 20:14:53 +0000240#ifdef CONFIG_SMDK6410_SD_CH0
Ben Dooks39057f22008-10-31 16:14:29 +0000241 &s3c_device_hsmmc0,
Ben Dooksb24636c2008-11-03 20:14:53 +0000242#endif
243#ifdef CONFIG_SMDK6410_SD_CH1
244 &s3c_device_hsmmc1,
245#endif
Ben Dooksd85fa242008-10-31 16:14:52 +0000246 &s3c_device_i2c0,
Ben Dooksd7ea3742008-10-31 16:14:57 +0000247 &s3c_device_i2c1,
Ben Dooks438a5d42008-11-19 15:41:34 +0000248 &s3c_device_fb,
Ben Dooksb8132482009-11-23 00:13:39 +0000249 &s3c_device_ohci,
Ben Dooks06fa1d32009-05-16 22:11:20 +0100250 &s3c_device_usb_hsotg,
Mark Brown42015c12009-11-03 14:42:06 +0000251
252#ifdef CONFIG_REGULATOR
253 &smdk6410_b_pwr_5v,
254#endif
Ben Dooks438a5d42008-11-19 15:41:34 +0000255 &smdk6410_lcd_powerdev,
Mark Brown3056ea02009-01-27 16:18:01 +0000256
257 &smdk6410_smsc911x,
Ben Dooks5718df92008-10-21 14:07:09 +0100258};
259
Mark Brownecc558a2009-02-17 15:59:38 +0000260#ifdef CONFIG_SMDK6410_WM1190_EV1
261/* S3C64xx internal logic & PLL */
262static struct regulator_init_data wm8350_dcdc1_data = {
263 .constraints = {
264 .name = "PVDD_INT/PVDD_PLL",
265 .min_uV = 1200000,
266 .max_uV = 1200000,
267 .always_on = 1,
268 .apply_uV = 1,
269 },
270};
271
272/* Memory */
273static struct regulator_init_data wm8350_dcdc3_data = {
274 .constraints = {
275 .name = "PVDD_MEM",
276 .min_uV = 1800000,
277 .max_uV = 1800000,
278 .always_on = 1,
279 .state_mem = {
280 .uV = 1800000,
281 .mode = REGULATOR_MODE_NORMAL,
282 .enabled = 1,
283 },
284 .initial_state = PM_SUSPEND_MEM,
285 },
286};
287
288/* USB, EXT, PCM, ADC/DAC, USB, MMC */
Mark Brown42015c12009-11-03 14:42:06 +0000289static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
290 {
291 /* WM8580 */
292 .supply = "DVDD",
293 .dev_name = "0-001b",
294 },
295};
296
Mark Brownecc558a2009-02-17 15:59:38 +0000297static struct regulator_init_data wm8350_dcdc4_data = {
298 .constraints = {
299 .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
300 .min_uV = 3000000,
301 .max_uV = 3000000,
302 .always_on = 1,
303 },
Mark Brown42015c12009-11-03 14:42:06 +0000304 .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
305 .consumer_supplies = wm8350_dcdc4_consumers,
Mark Brownecc558a2009-02-17 15:59:38 +0000306};
307
308/* ARM core */
Mark Browne3980b62009-04-15 17:11:53 +0100309static struct regulator_consumer_supply dcdc6_consumers[] = {
310 {
311 .supply = "vddarm",
312 }
313};
314
Mark Brownecc558a2009-02-17 15:59:38 +0000315static struct regulator_init_data wm8350_dcdc6_data = {
316 .constraints = {
317 .name = "PVDD_ARM",
318 .min_uV = 1000000,
319 .max_uV = 1300000,
320 .always_on = 1,
Mark Browne3980b62009-04-15 17:11:53 +0100321 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Mark Brownecc558a2009-02-17 15:59:38 +0000322 },
Mark Browne3980b62009-04-15 17:11:53 +0100323 .num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
324 .consumer_supplies = dcdc6_consumers,
Mark Brownecc558a2009-02-17 15:59:38 +0000325};
326
327/* Alive */
328static struct regulator_init_data wm8350_ldo1_data = {
329 .constraints = {
330 .name = "PVDD_ALIVE",
331 .min_uV = 1200000,
332 .max_uV = 1200000,
333 .always_on = 1,
334 .apply_uV = 1,
335 },
336};
337
338/* OTG */
339static struct regulator_init_data wm8350_ldo2_data = {
340 .constraints = {
341 .name = "PVDD_OTG",
342 .min_uV = 3300000,
343 .max_uV = 3300000,
Mark Brownf53aee22009-04-09 16:30:40 +0100344 .always_on = 1,
Mark Brownecc558a2009-02-17 15:59:38 +0000345 },
346};
347
348/* LCD */
349static struct regulator_init_data wm8350_ldo3_data = {
350 .constraints = {
351 .name = "PVDD_LCD",
352 .min_uV = 3000000,
353 .max_uV = 3000000,
Mark Brownf53aee22009-04-09 16:30:40 +0100354 .always_on = 1,
Mark Brownecc558a2009-02-17 15:59:38 +0000355 },
356};
357
358/* OTGi/1190-EV1 HPVDD & AVDD */
359static struct regulator_init_data wm8350_ldo4_data = {
360 .constraints = {
361 .name = "PVDD_OTGI/HPVDD/AVDD",
362 .min_uV = 1200000,
363 .max_uV = 1200000,
364 .apply_uV = 1,
Mark Brownf53aee22009-04-09 16:30:40 +0100365 .always_on = 1,
Mark Brownecc558a2009-02-17 15:59:38 +0000366 },
367};
368
369static struct {
370 int regulator;
371 struct regulator_init_data *initdata;
372} wm1190_regulators[] = {
373 { WM8350_DCDC_1, &wm8350_dcdc1_data },
374 { WM8350_DCDC_3, &wm8350_dcdc3_data },
375 { WM8350_DCDC_4, &wm8350_dcdc4_data },
376 { WM8350_DCDC_6, &wm8350_dcdc6_data },
377 { WM8350_LDO_1, &wm8350_ldo1_data },
378 { WM8350_LDO_2, &wm8350_ldo2_data },
379 { WM8350_LDO_3, &wm8350_ldo3_data },
380 { WM8350_LDO_4, &wm8350_ldo4_data },
381};
382
383static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
384{
385 int i;
386
Mark Browna3323b72009-11-03 14:42:04 +0000387 /* Configure the IRQ line */
388 s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
389
Mark Brownecc558a2009-02-17 15:59:38 +0000390 /* Instantiate the regulators */
391 for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
392 wm8350_register_regulator(wm8350,
393 wm1190_regulators[i].regulator,
394 wm1190_regulators[i].initdata);
395
396 return 0;
397}
398
399static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
400 .init = smdk6410_wm8350_init,
Mark Browndb9256f2009-04-09 19:00:19 +0100401 .irq_high = 1,
Mark Brown9fca8782010-01-19 15:26:56 +0000402 .irq_base = IRQ_BOARD_START,
Mark Brownecc558a2009-02-17 15:59:38 +0000403};
404#endif
405
Ben Dooks096941e2008-10-31 16:14:59 +0000406static struct i2c_board_info i2c_devs0[] __initdata = {
407 { I2C_BOARD_INFO("24c08", 0x50), },
Mark Brown77897472009-01-23 16:29:41 +0000408 { I2C_BOARD_INFO("wm8580", 0x1b), },
Mark Brownecc558a2009-02-17 15:59:38 +0000409
410#ifdef CONFIG_SMDK6410_WM1190_EV1
411 { I2C_BOARD_INFO("wm8350", 0x1a),
412 .platform_data = &smdk6410_wm8350_pdata,
413 .irq = S3C_EINT(12),
414 },
415#endif
Ben Dooks096941e2008-10-31 16:14:59 +0000416};
417
418static struct i2c_board_info i2c_devs1[] __initdata = {
419 { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
Ben Dooks5718df92008-10-21 14:07:09 +0100420};
421
Ben Dooks5718df92008-10-21 14:07:09 +0100422static void __init smdk6410_map_io(void)
423{
Ben Dooksd6662c32008-12-12 00:24:40 +0000424 u32 tmp;
425
Ben Dooks5718df92008-10-21 14:07:09 +0100426 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
427 s3c24xx_init_clocks(12000000);
428 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
Ben Dooksd6662c32008-12-12 00:24:40 +0000429
430 /* set the LCD type */
431
432 tmp = __raw_readl(S3C64XX_SPCON);
433 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
434 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
435 __raw_writel(tmp, S3C64XX_SPCON);
436
437 /* remove the lcd bypass */
438 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
439 tmp &= ~MIFPCON_LCD_BYPASS;
440 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
Ben Dooks5718df92008-10-21 14:07:09 +0100441}
442
443static void __init smdk6410_machine_init(void)
444{
Andy Greenf01fdac2009-12-29 14:40:36 +0000445 u32 cs1;
446
Ben Dooksd85fa242008-10-31 16:14:52 +0000447 s3c_i2c0_set_platdata(NULL);
Ben Dooksd7ea3742008-10-31 16:14:57 +0000448 s3c_i2c1_set_platdata(NULL);
Ben Dooks438a5d42008-11-19 15:41:34 +0000449 s3c_fb_set_platdata(&smdk6410_lcd_pdata);
Ben Dooks096941e2008-10-31 16:14:59 +0000450
Andy Greenf01fdac2009-12-29 14:40:36 +0000451 /* configure nCS1 width to 16 bits */
452
453 cs1 = __raw_readl(S3C64XX_SROM_BW) &
454 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
455 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
456 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
457 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
458 S3C64XX_SROM_BW__NCS1__SHIFT;
459 __raw_writel(cs1, S3C64XX_SROM_BW);
460
461 /* set timing for nCS1 suitable for ethernet chip */
462
463 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
464 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
465 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
466 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
467 (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
468 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
469 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
470
Mark Brownb7f9a942009-04-08 16:12:35 +0100471 gpio_request(S3C64XX_GPN(5), "LCD power");
472 gpio_request(S3C64XX_GPF(13), "LCD power");
473 gpio_request(S3C64XX_GPF(15), "LCD power");
474
Ben Dooks096941e2008-10-31 16:14:59 +0000475 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
476 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
477
Ben Dooks5718df92008-10-21 14:07:09 +0100478 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
479}
480
481MACHINE_START(SMDK6410, "SMDK6410")
482 /* Maintainer: Ben Dooks <ben@fluff.org> */
483 .phys_io = S3C_PA_UART & 0xfff00000,
484 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
485 .boot_params = S3C64XX_PA_SDRAM + 0x100,
486
487 .init_irq = s3c6410_init_irq,
488 .map_io = smdk6410_map_io,
489 .init_machine = smdk6410_machine_init,
490 .timer = &s3c24xx_timer,
491MACHINE_END