blob: e50513a627351983edbea71e2d369e959434e069 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "radeon_drm.h"
31#include "radeon_reg.h"
32#include "radeon.h"
33#include "atom.h"
34
35int radeon_debugfs_ib_init(struct radeon_device *rdev);
36
Jerome Glisse9f93ed32010-01-28 18:22:31 +010037void radeon_ib_bogus_cleanup(struct radeon_device *rdev)
38{
39 struct radeon_ib *ib, *n;
40
41 list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) {
42 list_del(&ib->list);
43 vfree(ib->ptr);
44 kfree(ib);
45 }
46}
47
48void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib)
49{
50 struct radeon_ib *bib;
51
52 bib = kmalloc(sizeof(*bib), GFP_KERNEL);
53 if (bib == NULL)
54 return;
55 bib->ptr = vmalloc(ib->length_dw * 4);
56 if (bib->ptr == NULL) {
57 kfree(bib);
58 return;
59 }
60 memcpy(bib->ptr, ib->ptr, ib->length_dw * 4);
61 bib->length_dw = ib->length_dw;
62 mutex_lock(&rdev->ib_pool.mutex);
63 list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib);
64 mutex_unlock(&rdev->ib_pool.mutex);
65}
66
Jerome Glisse771fe6b2009-06-05 14:42:42 +020067/*
68 * IB.
69 */
70int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
71{
72 struct radeon_fence *fence;
73 struct radeon_ib *nib;
Jerome Glisse91cb91b2010-02-15 21:36:13 +010074 int r = 0, i, c;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020075
76 *ib = NULL;
77 r = radeon_fence_create(rdev, &fence);
78 if (r) {
Jerome Glisse91cb91b2010-02-15 21:36:13 +010079 dev_err(rdev->dev, "failed to create fence for new IB\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +020080 return r;
81 }
82 mutex_lock(&rdev->ib_pool.mutex);
Jerome Glisse91cb91b2010-02-15 21:36:13 +010083 for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
84 i &= (RADEON_IB_POOL_SIZE - 1);
85 if (rdev->ib_pool.ibs[i].free) {
86 nib = &rdev->ib_pool.ibs[i];
87 break;
88 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +020089 }
Jerome Glisse91cb91b2010-02-15 21:36:13 +010090 if (nib == NULL) {
91 /* This should never happen, it means we allocated all
92 * IB and haven't scheduled one yet, return EBUSY to
93 * userspace hoping that on ioctl recall we get better
94 * luck
95 */
96 dev_err(rdev->dev, "no free indirect buffer !\n");
Dave Airlieecb114a2009-09-15 11:12:56 +100097 mutex_unlock(&rdev->ib_pool.mutex);
Jerome Glisse91cb91b2010-02-15 21:36:13 +010098 radeon_fence_unref(&fence);
99 return -EBUSY;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200100 }
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100101 rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
102 nib->free = false;
103 if (nib->fence) {
Dave Airlieecb114a2009-09-15 11:12:56 +1000104 mutex_unlock(&rdev->ib_pool.mutex);
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100105 r = radeon_fence_wait(nib->fence, false);
106 if (r) {
107 dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
108 nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
109 mutex_lock(&rdev->ib_pool.mutex);
110 nib->free = true;
111 mutex_unlock(&rdev->ib_pool.mutex);
112 radeon_fence_unref(&fence);
113 return r;
114 }
115 mutex_lock(&rdev->ib_pool.mutex);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200116 }
117 radeon_fence_unref(&nib->fence);
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100118 nib->fence = fence;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200119 nib->length_dw = 0;
Dave Airlieecb114a2009-09-15 11:12:56 +1000120 mutex_unlock(&rdev->ib_pool.mutex);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200121 *ib = nib;
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100122 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200123}
124
125void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
126{
127 struct radeon_ib *tmp = *ib;
128
129 *ib = NULL;
130 if (tmp == NULL) {
131 return;
132 }
Jerome Glisse7d404c72010-02-18 13:13:29 +0000133 if (!tmp->fence->emited)
134 radeon_fence_unref(&tmp->fence);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200135 mutex_lock(&rdev->ib_pool.mutex);
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100136 tmp->free = true;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200137 mutex_unlock(&rdev->ib_pool.mutex);
138}
139
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200140int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
141{
142 int r = 0;
143
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200144 if (!ib->length_dw || !rdev->cp.ready) {
145 /* TODO: Nothings in the ib we should report. */
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100146 DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200147 return -EINVAL;
148 }
Dave Airlieecb114a2009-09-15 11:12:56 +1000149
Dave Airlie6cdf6582009-06-29 18:29:13 +1000150 /* 64 dwords should be enough for fence too */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200151 r = radeon_ring_lock(rdev, 64);
152 if (r) {
153 DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200154 return r;
155 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000156 radeon_ring_ib_execute(rdev, ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200157 radeon_fence_emit(rdev, ib->fence);
Dave Airlieecb114a2009-09-15 11:12:56 +1000158 mutex_lock(&rdev->ib_pool.mutex);
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100159 /* once scheduled IB is considered free and protected by the fence */
160 ib->free = true;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200161 mutex_unlock(&rdev->ib_pool.mutex);
Dave Airlieecb114a2009-09-15 11:12:56 +1000162 radeon_ring_unlock_commit(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200163 return 0;
164}
165
166int radeon_ib_pool_init(struct radeon_device *rdev)
167{
168 void *ptr;
169 uint64_t gpu_addr;
170 int i;
171 int r = 0;
172
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200173 if (rdev->ib_pool.robj)
174 return 0;
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100175 INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200176 /* Allocate 1M object buffer */
Jerome Glisse4c788672009-11-20 14:29:23 +0100177 r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
178 true, RADEON_GEM_DOMAIN_GTT,
179 &rdev->ib_pool.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200180 if (r) {
181 DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
182 return r;
183 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100184 r = radeon_bo_reserve(rdev->ib_pool.robj, false);
185 if (unlikely(r != 0))
186 return r;
187 r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200188 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100189 radeon_bo_unreserve(rdev->ib_pool.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200190 DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
191 return r;
192 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100193 r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
194 radeon_bo_unreserve(rdev->ib_pool.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200195 if (r) {
196 DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
197 return r;
198 }
199 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
200 unsigned offset;
201
202 offset = i * 64 * 1024;
203 rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
204 rdev->ib_pool.ibs[i].ptr = ptr + offset;
205 rdev->ib_pool.ibs[i].idx = i;
206 rdev->ib_pool.ibs[i].length_dw = 0;
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100207 rdev->ib_pool.ibs[i].free = true;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200208 }
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100209 rdev->ib_pool.head_id = 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200210 rdev->ib_pool.ready = true;
211 DRM_INFO("radeon: ib pool ready.\n");
212 if (radeon_debugfs_ib_init(rdev)) {
213 DRM_ERROR("Failed to register debugfs file for IB !\n");
214 }
215 return r;
216}
217
218void radeon_ib_pool_fini(struct radeon_device *rdev)
219{
Jerome Glisse4c788672009-11-20 14:29:23 +0100220 int r;
221
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200222 if (!rdev->ib_pool.ready) {
223 return;
224 }
225 mutex_lock(&rdev->ib_pool.mutex);
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100226 radeon_ib_bogus_cleanup(rdev);
Dave Airlieeb6b6d72010-02-25 13:44:04 +1000227
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200228 if (rdev->ib_pool.robj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100229 r = radeon_bo_reserve(rdev->ib_pool.robj, false);
230 if (likely(r == 0)) {
231 radeon_bo_kunmap(rdev->ib_pool.robj);
232 radeon_bo_unpin(rdev->ib_pool.robj);
233 radeon_bo_unreserve(rdev->ib_pool.robj);
234 }
235 radeon_bo_unref(&rdev->ib_pool.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200236 rdev->ib_pool.robj = NULL;
237 }
238 mutex_unlock(&rdev->ib_pool.mutex);
239}
240
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200241
242/*
243 * Ring.
244 */
245void radeon_ring_free_size(struct radeon_device *rdev)
246{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000247 if (rdev->family >= CHIP_R600)
248 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
249 else
250 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200251 /* This works because ring_size is a power of 2 */
252 rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
253 rdev->cp.ring_free_dw -= rdev->cp.wptr;
254 rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
255 if (!rdev->cp.ring_free_dw) {
256 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
257 }
258}
259
260int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
261{
262 int r;
263
264 /* Align requested size with padding so unlock_commit can
265 * pad safely */
266 ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
267 mutex_lock(&rdev->cp.mutex);
268 while (ndw > (rdev->cp.ring_free_dw - 1)) {
269 radeon_ring_free_size(rdev);
270 if (ndw < rdev->cp.ring_free_dw) {
271 break;
272 }
273 r = radeon_fence_wait_next(rdev);
274 if (r) {
275 mutex_unlock(&rdev->cp.mutex);
276 return r;
277 }
278 }
279 rdev->cp.count_dw = ndw;
280 rdev->cp.wptr_old = rdev->cp.wptr;
281 return 0;
282}
283
284void radeon_ring_unlock_commit(struct radeon_device *rdev)
285{
286 unsigned count_dw_pad;
287 unsigned i;
288
289 /* We pad to match fetch size */
290 count_dw_pad = (rdev->cp.align_mask + 1) -
291 (rdev->cp.wptr & rdev->cp.align_mask);
292 for (i = 0; i < count_dw_pad; i++) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000293 radeon_ring_write(rdev, 2 << 30);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200294 }
295 DRM_MEMORYBARRIER();
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000296 radeon_cp_commit(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200297 mutex_unlock(&rdev->cp.mutex);
298}
299
300void radeon_ring_unlock_undo(struct radeon_device *rdev)
301{
302 rdev->cp.wptr = rdev->cp.wptr_old;
303 mutex_unlock(&rdev->cp.mutex);
304}
305
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200306int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
307{
308 int r;
309
310 rdev->cp.ring_size = ring_size;
311 /* Allocate ring buffer */
312 if (rdev->cp.ring_obj == NULL) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100313 r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,
314 RADEON_GEM_DOMAIN_GTT,
315 &rdev->cp.ring_obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200316 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100317 dev_err(rdev->dev, "(%d) ring create failed\n", r);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200318 return r;
319 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100320 r = radeon_bo_reserve(rdev->cp.ring_obj, false);
321 if (unlikely(r != 0))
322 return r;
323 r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
324 &rdev->cp.gpu_addr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200325 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100326 radeon_bo_unreserve(rdev->cp.ring_obj);
327 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200328 return r;
329 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100330 r = radeon_bo_kmap(rdev->cp.ring_obj,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200331 (void **)&rdev->cp.ring);
Jerome Glisse4c788672009-11-20 14:29:23 +0100332 radeon_bo_unreserve(rdev->cp.ring_obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200333 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100334 dev_err(rdev->dev, "(%d) ring map failed\n", r);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200335 return r;
336 }
337 }
338 rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
339 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
340 return 0;
341}
342
343void radeon_ring_fini(struct radeon_device *rdev)
344{
Jerome Glisse4c788672009-11-20 14:29:23 +0100345 int r;
346
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200347 mutex_lock(&rdev->cp.mutex);
348 if (rdev->cp.ring_obj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100349 r = radeon_bo_reserve(rdev->cp.ring_obj, false);
350 if (likely(r == 0)) {
351 radeon_bo_kunmap(rdev->cp.ring_obj);
352 radeon_bo_unpin(rdev->cp.ring_obj);
353 radeon_bo_unreserve(rdev->cp.ring_obj);
354 }
355 radeon_bo_unref(&rdev->cp.ring_obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200356 rdev->cp.ring = NULL;
357 rdev->cp.ring_obj = NULL;
358 }
359 mutex_unlock(&rdev->cp.mutex);
360}
361
362
363/*
364 * Debugfs info
365 */
366#if defined(CONFIG_DEBUG_FS)
367static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
368{
369 struct drm_info_node *node = (struct drm_info_node *) m->private;
370 struct radeon_ib *ib = node->info_ent->data;
371 unsigned i;
372
373 if (ib == NULL) {
374 return 0;
375 }
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100376 seq_printf(m, "IB %04u\n", ib->idx);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200377 seq_printf(m, "IB fence %p\n", ib->fence);
378 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
379 for (i = 0; i < ib->length_dw; i++) {
380 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
381 }
382 return 0;
383}
384
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100385static int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data)
386{
387 struct drm_info_node *node = (struct drm_info_node *) m->private;
388 struct radeon_device *rdev = node->info_ent->data;
389 struct radeon_ib *ib;
390 unsigned i;
391
392 mutex_lock(&rdev->ib_pool.mutex);
393 if (list_empty(&rdev->ib_pool.bogus_ib)) {
394 mutex_unlock(&rdev->ib_pool.mutex);
395 seq_printf(m, "no bogus IB recorded\n");
396 return 0;
397 }
398 ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list);
399 list_del_init(&ib->list);
400 mutex_unlock(&rdev->ib_pool.mutex);
401 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
402 for (i = 0; i < ib->length_dw; i++) {
403 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
404 }
405 vfree(ib->ptr);
406 kfree(ib);
407 return 0;
408}
409
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200410static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
411static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100412
413static struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = {
414 {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL},
415};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200416#endif
417
418int radeon_debugfs_ib_init(struct radeon_device *rdev)
419{
420#if defined(CONFIG_DEBUG_FS)
421 unsigned i;
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100422 int r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200423
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100424 radeon_debugfs_ib_bogus_info_list[0].data = rdev;
425 r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1);
426 if (r)
427 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200428 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
429 sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
430 radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
431 radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
432 radeon_debugfs_ib_list[i].driver_features = 0;
433 radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
434 }
435 return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
436 RADEON_IB_POOL_SIZE);
437#else
438 return 0;
439#endif
440}