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Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +08001/*
2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +080011#include "skeleton.dtsi"
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +080012#include <dt-bindings/pinctrl/at91.h>
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080013#include <dt-bindings/interrupt-controller/irq.h>
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +080014#include <dt-bindings/gpio/gpio.h>
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080015
16/ {
17 model = "Atmel AT91SAM9260 family SoC";
18 compatible = "atmel,at91sam9260";
19 interrupt-parent = <&aic>;
20
21 aliases {
22 serial0 = &dbgu;
23 serial1 = &usart0;
24 serial2 = &usart1;
25 serial3 = &usart2;
26 serial4 = &usart3;
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +080027 serial5 = &uart0;
28 serial6 = &uart1;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080029 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 tcb0 = &tcb0;
33 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020034 i2c0 = &i2c0;
Bo Shen099343c2012-11-07 11:41:41 +080035 ssc0 = &ssc0;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080036 };
37 cpus {
38 cpu@0 {
39 compatible = "arm,arm926ejs";
40 };
41 };
42
43 memory {
44 reg = <0x20000000 0x04000000>;
45 };
46
47 ahb {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52
53 apb {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020060 #interrupt-cells = <3>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080061 compatible = "atmel,at91rm9200-aic";
62 interrupt-controller;
63 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080064 atmel,external-irqs = <29 30 31>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080065 };
66
67 ramc0: ramc@ffffea00 {
68 compatible = "atmel,at91sam9260-sdramc";
69 reg = <0xffffea00 0x200>;
70 };
71
72 pmc: pmc@fffffc00 {
73 compatible = "atmel,at91rm9200-pmc";
74 reg = <0xfffffc00 0x100>;
75 };
76
77 rstc@fffffd00 {
78 compatible = "atmel,at91sam9260-rstc";
79 reg = <0xfffffd00 0x10>;
80 };
81
82 shdwc@fffffd10 {
83 compatible = "atmel,at91sam9260-shdwc";
84 reg = <0xfffffd10 0x10>;
85 };
86
87 pit: timer@fffffd30 {
88 compatible = "atmel,at91sam9260-pit";
89 reg = <0xfffffd30 0xf>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080090 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080091 };
92
93 tcb0: timer@fffa0000 {
94 compatible = "atmel,at91rm9200-tcb";
95 reg = <0xfffa0000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080096 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
97 18 IRQ_TYPE_LEVEL_HIGH 0
98 19 IRQ_TYPE_LEVEL_HIGH 0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080099 };
100
101 tcb1: timer@fffdc000 {
102 compatible = "atmel,at91rm9200-tcb";
103 reg = <0xfffdc000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800104 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
105 27 IRQ_TYPE_LEVEL_HIGH 0
106 28 IRQ_TYPE_LEVEL_HIGH 0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800107 };
108
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800109 pinctrl@fffff400 {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
113 ranges = <0xfffff400 0xfffff400 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800114
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800115 atmel,mux-mask = <
116 /* A B */
117 0xffffffff 0xffc00c3b /* pioA */
118 0xffffffff 0x7fff3ccf /* pioB */
119 0xffffffff 0x007fffff /* pioC */
120 >;
121
122 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800123 dbgu {
124 pinctrl_dbgu: dbgu-0 {
125 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800126 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
127 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800128 };
129 };
130
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800131 usart0 {
132 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800133 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800134 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
135 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800136 };
137
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800138 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800139 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800140 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800141 };
142
143 pinctrl_usart0_cts: usart0_cts-0 {
144 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800145 <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800146 };
147
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800148 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800149 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800150 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */
151 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800152 };
153
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800154 pinctrl_usart0_dcd: usart0_dcd-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800155 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800156 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800157 };
158
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800159 pinctrl_usart0_ri: usart0_ri-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800160 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800161 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800162 };
163 };
164
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800165 usart1 {
166 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800167 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800168 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
169 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800170 };
171
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800172 pinctrl_usart1_rts: usart1_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800173 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800174 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800175 };
176
177 pinctrl_usart1_cts: usart1_cts-0 {
178 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800179 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800180 };
181 };
182
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800183 usart2 {
184 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800185 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800186 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */
187 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800188 };
189
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800190 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800191 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800192 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800193 };
194
195 pinctrl_usart2_cts: usart2_cts-0 {
196 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800197 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800198 };
199 };
200
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800201 usart3 {
202 pinctrl_usart3: usart3-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800203 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800204 <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */
205 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800206 };
207
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800208 pinctrl_usart3_rts: usart3_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800209 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800210 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800211 };
212
213 pinctrl_usart3_cts: usart3_cts-0 {
214 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800215 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800216 };
217 };
218
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800219 uart0 {
220 pinctrl_uart0: uart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800221 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800222 <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */
223 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800224 };
225 };
226
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800227 uart1 {
228 pinctrl_uart1: uart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800229 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800230 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */
231 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800232 };
233 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800234
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800235 nand {
236 pinctrl_nand: nand-0 {
237 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800238 <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */
239 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800240 };
241 };
242
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800243 macb {
244 pinctrl_macb_rmii: macb_rmii-0 {
245 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800246 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
247 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
248 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
249 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
250 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
251 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
252 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
253 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */
254 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */
255 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800256 };
257
258 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
259 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800260 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
261 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */
262 AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
263 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
264 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
265 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
266 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
267 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800268 };
269
270 pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
271 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800272 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */
273 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */
274 AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
275 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
276 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
277 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
278 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
279 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800280 };
281 };
282
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800283 mmc0 {
284 pinctrl_mmc0_clk: mmc0_clk-0 {
285 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800286 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800287 };
288
289 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
290 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800291 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
292 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800293 };
294
295 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
296 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800297 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
298 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
299 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800300 };
301
302 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
303 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800304 <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */
305 AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800306 };
307
308 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
309 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800310 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
311 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */
312 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800313 };
314 };
315
Bo Shen544ae6b2013-01-11 15:08:30 +0100316 ssc0 {
317 pinctrl_ssc0_tx: ssc0_tx-0 {
318 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800319 <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
320 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */
321 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
Bo Shen544ae6b2013-01-11 15:08:30 +0100322 };
323
324 pinctrl_ssc0_rx: ssc0_rx-0 {
325 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800326 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
327 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */
328 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
Bo Shen544ae6b2013-01-11 15:08:30 +0100329 };
330 };
331
Wenyou Yanga68b7282013-04-03 14:03:52 +0800332 spi0 {
333 pinctrl_spi0: spi0-0 {
334 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800335 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
336 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
337 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
Wenyou Yanga68b7282013-04-03 14:03:52 +0800338 };
339 };
340
341 spi1 {
342 pinctrl_spi1: spi1-0 {
343 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800344 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */
345 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */
346 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */
Wenyou Yanga68b7282013-04-03 14:03:52 +0800347 };
348 };
349
Jean-Christophe PLAGNIOL-VILLARDf89ae612013-05-26 16:55:59 +0800350 i2c_gpio0 {
351 pinctrl_i2c_gpio0: i2c_gpio0-0 {
352 atmel,pins =
353 <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
354 AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
355 };
356 };
357
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800358 pioA: gpio@fffff400 {
359 compatible = "atmel,at91rm9200-gpio";
360 reg = <0xfffff400 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800361 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800362 #gpio-cells = <2>;
363 gpio-controller;
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800367
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800368 pioB: gpio@fffff600 {
369 compatible = "atmel,at91rm9200-gpio";
370 reg = <0xfffff600 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800371 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800372 #gpio-cells = <2>;
373 gpio-controller;
374 interrupt-controller;
375 #interrupt-cells = <2>;
376 };
377
378 pioC: gpio@fffff800 {
379 compatible = "atmel,at91rm9200-gpio";
380 reg = <0xfffff800 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800381 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800382 #gpio-cells = <2>;
383 gpio-controller;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800387 };
388
389 dbgu: serial@fffff200 {
390 compatible = "atmel,at91sam9260-usart";
391 reg = <0xfffff200 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800392 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_dbgu>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800395 status = "disabled";
396 };
397
398 usart0: serial@fffb0000 {
399 compatible = "atmel,at91sam9260-usart";
400 reg = <0xfffb0000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800401 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800402 atmel,use-dma-rx;
403 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800404 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800405 pinctrl-0 = <&pinctrl_usart0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800406 status = "disabled";
407 };
408
409 usart1: serial@fffb4000 {
410 compatible = "atmel,at91sam9260-usart";
411 reg = <0xfffb4000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800412 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800413 atmel,use-dma-rx;
414 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800415 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800416 pinctrl-0 = <&pinctrl_usart1>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800417 status = "disabled";
418 };
419
420 usart2: serial@fffb8000 {
421 compatible = "atmel,at91sam9260-usart";
422 reg = <0xfffb8000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800423 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800424 atmel,use-dma-rx;
425 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800426 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800427 pinctrl-0 = <&pinctrl_usart2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800428 status = "disabled";
429 };
430
431 usart3: serial@fffd0000 {
432 compatible = "atmel,at91sam9260-usart";
433 reg = <0xfffd0000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800434 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800435 atmel,use-dma-rx;
436 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800437 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800438 pinctrl-0 = <&pinctrl_usart3>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800439 status = "disabled";
440 };
441
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800442 uart0: serial@fffd4000 {
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800443 compatible = "atmel,at91sam9260-usart";
444 reg = <0xfffd4000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800445 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800446 atmel,use-dma-rx;
447 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800448 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800449 pinctrl-0 = <&pinctrl_uart0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800450 status = "disabled";
451 };
452
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800453 uart1: serial@fffd8000 {
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800454 compatible = "atmel,at91sam9260-usart";
455 reg = <0xfffd8000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800456 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800457 atmel,use-dma-rx;
458 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800459 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800460 pinctrl-0 = <&pinctrl_uart1>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800461 status = "disabled";
462 };
463
464 macb0: ethernet@fffc4000 {
465 compatible = "cdns,at32ap7000-macb", "cdns,macb";
466 reg = <0xfffc4000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800467 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800468 pinctrl-names = "default";
469 pinctrl-0 = <&pinctrl_macb_rmii>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800470 status = "disabled";
471 };
472
473 usb1: gadget@fffa4000 {
474 compatible = "atmel,at91rm9200-udc";
475 reg = <0xfffa4000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800476 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800477 status = "disabled";
478 };
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200479
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200480 i2c0: i2c@fffac000 {
481 compatible = "atmel,at91sam9260-i2c";
482 reg = <0xfffac000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800483 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200484 #address-cells = <1>;
485 #size-cells = <0>;
486 status = "disabled";
487 };
488
Ludovic Desroches98731372012-11-19 12:23:36 +0100489 mmc0: mmc@fffa8000 {
490 compatible = "atmel,hsmci";
491 reg = <0xfffa8000 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800492 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
Ludovic Desroches98731372012-11-19 12:23:36 +0100493 #address-cells = <1>;
494 #size-cells = <0>;
495 status = "disabled";
496 };
497
Bo Shen099343c2012-11-07 11:41:41 +0800498 ssc0: ssc@fffbc000 {
499 compatible = "atmel,at91rm9200-ssc";
500 reg = <0xfffbc000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800501 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
Linus Torvalds046e7d62012-12-13 11:51:23 -0800504 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800505 };
506
Richard Genoudd50f88a2013-04-03 14:02:18 +0800507 spi0: spi@fffc8000 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "atmel,at91rm9200-spi";
511 reg = <0xfffc8000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800512 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_spi0>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800515 status = "disabled";
516 };
517
518 spi1: spi@fffcc000 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 compatible = "atmel,at91rm9200-spi";
522 reg = <0xfffcc000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800523 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800524 pinctrl-names = "default";
525 pinctrl-0 = <&pinctrl_spi1>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800526 status = "disabled";
527 };
528
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200529 adc0: adc@fffe0000 {
530 compatible = "atmel,at91sam9260-adc";
531 reg = <0xfffe0000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800532 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200533 atmel,adc-use-external-triggers;
534 atmel,adc-channels-used = <0xf>;
535 atmel,adc-vref = <3300>;
536 atmel,adc-num-channels = <4>;
537 atmel,adc-startup-time = <15>;
538 atmel,adc-channel-base = <0x30>;
539 atmel,adc-drdy-mask = <0x10000>;
540 atmel,adc-status-register = <0x1c>;
541 atmel,adc-trigger-register = <0x04>;
Ludovic Desroches4b50da62013-03-29 10:13:19 +0100542 atmel,adc-res = <8 10>;
543 atmel,adc-res-names = "lowres", "highres";
544 atmel,adc-use-res = "highres";
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200545
546 trigger@0 {
547 trigger-name = "timer-counter-0";
548 trigger-value = <0x1>;
549 };
550 trigger@1 {
551 trigger-name = "timer-counter-1";
552 trigger-value = <0x3>;
553 };
554
555 trigger@2 {
556 trigger-name = "timer-counter-2";
557 trigger-value = <0x5>;
558 };
559
560 trigger@3 {
561 trigger-name = "external";
562 trigger-value = <0x13>;
563 trigger-external;
564 };
565 };
Fabio Porcedda7492e7c2012-11-12 09:37:26 +0100566
567 watchdog@fffffd40 {
568 compatible = "atmel,at91sam9260-wdt";
569 reg = <0xfffffd40 0x10>;
570 status = "disabled";
571 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800572 };
573
574 nand0: nand@40000000 {
575 compatible = "atmel,at91rm9200-nand";
576 #address-cells = <1>;
577 #size-cells = <1>;
578 reg = <0x40000000 0x10000000
579 0xffffe800 0x200
580 >;
581 atmel,nand-addr-offset = <21>;
582 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800585 gpios = <&pioC 13 GPIO_ACTIVE_HIGH
586 &pioC 14 GPIO_ACTIVE_HIGH
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800587 0
588 >;
589 status = "disabled";
590 };
591
592 usb0: ohci@00500000 {
593 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
594 reg = <0x00500000 0x100000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800595 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800596 status = "disabled";
597 };
598 };
599
600 i2c@0 {
601 compatible = "i2c-gpio";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800602 gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
603 &pioA 24 GPIO_ACTIVE_HIGH /* scl */
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800604 >;
605 i2c-gpio,sda-open-drain;
606 i2c-gpio,scl-open-drain;
607 i2c-gpio,delay-us = <2>; /* ~100 kHz */
608 #address-cells = <1>;
609 #size-cells = <0>;
Jean-Christophe PLAGNIOL-VILLARDf89ae612013-05-26 16:55:59 +0800610 pinctrl-names = "default";
611 pinctrl-0 = <&pinctrl_i2c_gpio0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800612 status = "disabled";
613 };
614};