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Chunfeng Yun0cbd4b32015-11-24 13:09:55 +02001/*
2 * MediaTek xHCI Host Controller Driver
3 *
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author:
6 * Chunfeng Yun <chunfeng.yun@mediatek.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/clk.h>
20#include <linux/dma-mapping.h>
21#include <linux/iopoll.h>
22#include <linux/kernel.h>
23#include <linux/mfd/syscon.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/phy/phy.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/regmap.h>
30#include <linux/regulator/consumer.h>
31
32#include "xhci.h"
33#include "xhci-mtk.h"
34
35/* ip_pw_ctrl0 register */
36#define CTRL0_IP_SW_RST BIT(0)
37
38/* ip_pw_ctrl1 register */
39#define CTRL1_IP_HOST_PDN BIT(0)
40
41/* ip_pw_ctrl2 register */
42#define CTRL2_IP_DEV_PDN BIT(0)
43
44/* ip_pw_sts1 register */
45#define STS1_IP_SLEEP_STS BIT(30)
46#define STS1_XHCI_RST BIT(11)
47#define STS1_SYS125_RST BIT(10)
48#define STS1_REF_RST BIT(8)
49#define STS1_SYSPLL_STABLE BIT(0)
50
51/* ip_xhci_cap register */
52#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
53#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
54
55/* u3_ctrl_p register */
56#define CTRL_U3_PORT_HOST_SEL BIT(2)
57#define CTRL_U3_PORT_PDN BIT(1)
58#define CTRL_U3_PORT_DIS BIT(0)
59
60/* u2_ctrl_p register */
61#define CTRL_U2_PORT_HOST_SEL BIT(2)
62#define CTRL_U2_PORT_PDN BIT(1)
63#define CTRL_U2_PORT_DIS BIT(0)
64
65/* u2_phy_pll register */
66#define CTRL_U2_FORCE_PLL_STB BIT(28)
67
68#define PERI_WK_CTRL0 0x400
69#define UWK_CTR0_0P_LS_PE BIT(8) /* posedge */
70#define UWK_CTR0_0P_LS_NE BIT(7) /* negedge for 0p linestate*/
71#define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1)
72#define UWK_CTL1_1P_LS_E BIT(0)
73
74#define PERI_WK_CTRL1 0x404
75#define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
76#define UWK_CTL1_IS_E BIT(25)
77#define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21)
78#define UWK_CTL1_0P_LS_E BIT(20)
79#define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
80#define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */
81#define UWK_CTL1_IDDIG_P BIT(9) /* polarity */
82#define UWK_CTL1_0P_LS_P BIT(7)
83#define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */
84
85enum ssusb_wakeup_src {
86 SSUSB_WK_IP_SLEEP = 1,
87 SSUSB_WK_LINE_STATE = 2,
88};
89
90static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
91{
92 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
93 u32 value, check_val;
94 int ret;
95 int i;
96
Chunfeng Yun065d48c2016-10-19 10:28:22 +080097 if (!mtk->has_ippc)
98 return 0;
99
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200100 /* power on host ip */
101 value = readl(&ippc->ip_pw_ctr1);
102 value &= ~CTRL1_IP_HOST_PDN;
103 writel(value, &ippc->ip_pw_ctr1);
104
105 /* power on and enable all u3 ports */
106 for (i = 0; i < mtk->num_u3_ports; i++) {
107 value = readl(&ippc->u3_ctrl_p[i]);
108 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
109 value |= CTRL_U3_PORT_HOST_SEL;
110 writel(value, &ippc->u3_ctrl_p[i]);
111 }
112
113 /* power on and enable all u2 ports */
114 for (i = 0; i < mtk->num_u2_ports; i++) {
115 value = readl(&ippc->u2_ctrl_p[i]);
116 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
117 value |= CTRL_U2_PORT_HOST_SEL;
118 writel(value, &ippc->u2_ctrl_p[i]);
119 }
120
121 /*
122 * wait for clocks to be stable, and clock domains reset to
123 * be inactive after power on and enable ports
124 */
125 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
126 STS1_SYS125_RST | STS1_XHCI_RST;
127
128 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
129 (check_val == (value & check_val)), 100, 20000);
130 if (ret) {
131 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
132 return ret;
133 }
134
135 return 0;
136}
137
138static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
139{
140 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
141 u32 value;
142 int ret;
143 int i;
144
Chunfeng Yun065d48c2016-10-19 10:28:22 +0800145 if (!mtk->has_ippc)
146 return 0;
147
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200148 /* power down all u3 ports */
149 for (i = 0; i < mtk->num_u3_ports; i++) {
150 value = readl(&ippc->u3_ctrl_p[i]);
151 value |= CTRL_U3_PORT_PDN;
152 writel(value, &ippc->u3_ctrl_p[i]);
153 }
154
155 /* power down all u2 ports */
156 for (i = 0; i < mtk->num_u2_ports; i++) {
157 value = readl(&ippc->u2_ctrl_p[i]);
158 value |= CTRL_U2_PORT_PDN;
159 writel(value, &ippc->u2_ctrl_p[i]);
160 }
161
162 /* power down host ip */
163 value = readl(&ippc->ip_pw_ctr1);
164 value |= CTRL1_IP_HOST_PDN;
165 writel(value, &ippc->ip_pw_ctr1);
166
167 /* wait for host ip to sleep */
168 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
169 (value & STS1_IP_SLEEP_STS), 100, 100000);
170 if (ret) {
171 dev_err(mtk->dev, "ip sleep failed!!!\n");
172 return ret;
173 }
174 return 0;
175}
176
177static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
178{
179 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
180 u32 value;
181
Chunfeng Yun065d48c2016-10-19 10:28:22 +0800182 if (!mtk->has_ippc)
183 return 0;
184
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200185 /* reset whole ip */
186 value = readl(&ippc->ip_pw_ctr0);
187 value |= CTRL0_IP_SW_RST;
188 writel(value, &ippc->ip_pw_ctr0);
189 udelay(1);
190 value = readl(&ippc->ip_pw_ctr0);
191 value &= ~CTRL0_IP_SW_RST;
192 writel(value, &ippc->ip_pw_ctr0);
193
194 /*
195 * device ip is default power-on in fact
196 * power down device ip, otherwise ip-sleep will fail
197 */
198 value = readl(&ippc->ip_pw_ctr2);
199 value |= CTRL2_IP_DEV_PDN;
200 writel(value, &ippc->ip_pw_ctr2);
201
202 value = readl(&ippc->ip_xhci_cap);
203 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
204 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
205 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
206 mtk->num_u2_ports, mtk->num_u3_ports);
207
208 return xhci_mtk_host_enable(mtk);
209}
210
211static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
212{
213 int ret;
214
Chunfeng Yun9c4afd42017-01-18 14:08:24 +0800215 ret = clk_prepare_enable(mtk->ref_clk);
216 if (ret) {
217 dev_err(mtk->dev, "failed to enable ref_clk\n");
218 goto ref_clk_err;
219 }
220
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200221 ret = clk_prepare_enable(mtk->sys_clk);
222 if (ret) {
223 dev_err(mtk->dev, "failed to enable sys_clk\n");
224 goto sys_clk_err;
225 }
226
227 if (mtk->wakeup_src) {
228 ret = clk_prepare_enable(mtk->wk_deb_p0);
229 if (ret) {
230 dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
231 goto usb_p0_err;
232 }
233
234 ret = clk_prepare_enable(mtk->wk_deb_p1);
235 if (ret) {
236 dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
237 goto usb_p1_err;
238 }
239 }
240 return 0;
241
242usb_p1_err:
243 clk_disable_unprepare(mtk->wk_deb_p0);
244usb_p0_err:
245 clk_disable_unprepare(mtk->sys_clk);
246sys_clk_err:
Chunfeng Yun9c4afd42017-01-18 14:08:24 +0800247 clk_disable_unprepare(mtk->ref_clk);
248ref_clk_err:
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200249 return -EINVAL;
250}
251
252static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
253{
254 if (mtk->wakeup_src) {
255 clk_disable_unprepare(mtk->wk_deb_p1);
256 clk_disable_unprepare(mtk->wk_deb_p0);
257 }
258 clk_disable_unprepare(mtk->sys_clk);
Chunfeng Yun9c4afd42017-01-18 14:08:24 +0800259 clk_disable_unprepare(mtk->ref_clk);
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200260}
261
262/* only clocks can be turn off for ip-sleep wakeup mode */
263static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk)
264{
265 u32 tmp;
266 struct regmap *pericfg = mtk->pericfg;
267
268 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
269 tmp &= ~UWK_CTL1_IS_P;
270 tmp &= ~(UWK_CTL1_IS_C(0xf));
271 tmp |= UWK_CTL1_IS_C(0x8);
272 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
273 regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
274
275 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
276 dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
277 __func__, tmp);
278}
279
280static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk)
281{
282 u32 tmp;
283
284 regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp);
285 tmp &= ~UWK_CTL1_IS_E;
286 regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp);
287}
288
289/*
290* for line-state wakeup mode, phy's power should not power-down
291* and only support cable plug in/out
292*/
293static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk)
294{
295 u32 tmp;
296 struct regmap *pericfg = mtk->pericfg;
297
298 /* line-state of u2-port0 */
299 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
300 tmp &= ~UWK_CTL1_0P_LS_P;
301 tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
302 tmp |= UWK_CTL1_0P_LS_C(0x8);
303 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
304 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
305 regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
306
307 /* line-state of u2-port1 */
308 regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
309 tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
310 tmp |= UWK_CTL1_1P_LS_C(0x8);
311 regmap_write(pericfg, PERI_WK_CTRL0, tmp);
312 regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
313}
314
315static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk)
316{
317 u32 tmp;
318 struct regmap *pericfg = mtk->pericfg;
319
320 /* line-state of u2-port0 */
321 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
322 tmp &= ~UWK_CTL1_0P_LS_E;
323 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
324
325 /* line-state of u2-port1 */
326 regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
327 tmp &= ~UWK_CTL1_1P_LS_E;
328 regmap_write(pericfg, PERI_WK_CTRL0, tmp);
329}
330
331static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk)
332{
333 if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
334 usb_wakeup_ip_sleep_en(mtk);
335 else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
336 usb_wakeup_line_state_en(mtk);
337}
338
339static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk)
340{
341 if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
342 usb_wakeup_ip_sleep_dis(mtk);
343 else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
344 usb_wakeup_line_state_dis(mtk);
345}
346
347static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
348 struct device_node *dn)
349{
350 struct device *dev = mtk->dev;
351
352 /*
353 * wakeup function is optional, so it is not an error if this property
354 * does not exist, and in such case, no need to get relative
355 * properties anymore.
356 */
357 of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);
358 if (!mtk->wakeup_src)
359 return 0;
360
361 mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
362 if (IS_ERR(mtk->wk_deb_p0)) {
363 dev_err(dev, "fail to get wakeup_deb_p0\n");
364 return PTR_ERR(mtk->wk_deb_p0);
365 }
366
367 mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
368 if (IS_ERR(mtk->wk_deb_p1)) {
369 dev_err(dev, "fail to get wakeup_deb_p1\n");
370 return PTR_ERR(mtk->wk_deb_p1);
371 }
372
373 mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
374 "mediatek,syscon-wakeup");
375 if (IS_ERR(mtk->pericfg)) {
376 dev_err(dev, "fail to get pericfg regs\n");
377 return PTR_ERR(mtk->pericfg);
378 }
379
380 return 0;
381}
382
383static int xhci_mtk_setup(struct usb_hcd *hcd);
384static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
385 .extra_priv_size = sizeof(struct xhci_hcd),
386 .reset = xhci_mtk_setup,
387};
388
389static struct hc_driver __read_mostly xhci_mtk_hc_driver;
390
391static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk)
392{
393 int i;
394 int ret;
395
396 for (i = 0; i < mtk->num_phys; i++) {
397 ret = phy_init(mtk->phys[i]);
398 if (ret)
399 goto exit_phy;
400 }
401 return 0;
402
403exit_phy:
404 for (; i > 0; i--)
405 phy_exit(mtk->phys[i - 1]);
406
407 return ret;
408}
409
410static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk)
411{
412 int i;
413
414 for (i = 0; i < mtk->num_phys; i++)
415 phy_exit(mtk->phys[i]);
416
417 return 0;
418}
419
420static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk)
421{
422 int i;
423 int ret;
424
425 for (i = 0; i < mtk->num_phys; i++) {
426 ret = phy_power_on(mtk->phys[i]);
427 if (ret)
428 goto power_off_phy;
429 }
430 return 0;
431
432power_off_phy:
433 for (; i > 0; i--)
434 phy_power_off(mtk->phys[i - 1]);
435
436 return ret;
437}
438
439static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk)
440{
441 unsigned int i;
442
443 for (i = 0; i < mtk->num_phys; i++)
444 phy_power_off(mtk->phys[i]);
445}
446
447static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
448{
449 int ret;
450
451 ret = regulator_enable(mtk->vbus);
452 if (ret) {
453 dev_err(mtk->dev, "failed to enable vbus\n");
454 return ret;
455 }
456
457 ret = regulator_enable(mtk->vusb33);
458 if (ret) {
459 dev_err(mtk->dev, "failed to enable vusb33\n");
460 regulator_disable(mtk->vbus);
461 return ret;
462 }
463 return 0;
464}
465
466static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
467{
468 regulator_disable(mtk->vbus);
469 regulator_disable(mtk->vusb33);
470}
471
472static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
473{
474 struct usb_hcd *hcd = xhci_to_hcd(xhci);
475 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
476
477 /*
478 * As of now platform drivers don't provide MSI support so we ensure
479 * here that the generic code does not try to make a pci_dev from our
480 * dev struct in order to setup MSI
481 */
482 xhci->quirks |= XHCI_PLAT;
483 xhci->quirks |= XHCI_MTK_HOST;
484 /*
485 * MTK host controller gives a spurious successful event after a
486 * short transfer. Ignore it.
487 */
488 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
489 if (mtk->lpm_support)
490 xhci->quirks |= XHCI_LPM_SUPPORT;
491}
492
493/* called during probe() after chip reset completes */
494static int xhci_mtk_setup(struct usb_hcd *hcd)
495{
Chunfeng Yun065d48c2016-10-19 10:28:22 +0800496 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200497 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
498 int ret;
499
500 if (usb_hcd_is_primary_hcd(hcd)) {
501 ret = xhci_mtk_ssusb_config(mtk);
502 if (ret)
503 return ret;
Chunfeng Yun065d48c2016-10-19 10:28:22 +0800504 }
505
506 ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
507 if (ret)
508 return ret;
509
510 if (usb_hcd_is_primary_hcd(hcd)) {
511 mtk->num_u3_ports = xhci->num_usb3_ports;
512 mtk->num_u2_ports = xhci->num_usb2_ports;
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200513 ret = xhci_mtk_sch_init(mtk);
514 if (ret)
515 return ret;
516 }
517
Chunfeng Yun065d48c2016-10-19 10:28:22 +0800518 return ret;
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200519}
520
521static int xhci_mtk_probe(struct platform_device *pdev)
522{
523 struct device *dev = &pdev->dev;
524 struct device_node *node = dev->of_node;
525 struct xhci_hcd_mtk *mtk;
526 const struct hc_driver *driver;
527 struct xhci_hcd *xhci;
528 struct resource *res;
529 struct usb_hcd *hcd;
530 struct phy *phy;
531 int phy_num;
532 int ret = -ENODEV;
533 int irq;
534
535 if (usb_disabled())
536 return -ENODEV;
537
538 driver = &xhci_mtk_hc_driver;
539 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
540 if (!mtk)
541 return -ENOMEM;
542
543 mtk->dev = dev;
544 mtk->vbus = devm_regulator_get(dev, "vbus");
545 if (IS_ERR(mtk->vbus)) {
546 dev_err(dev, "fail to get vbus\n");
547 return PTR_ERR(mtk->vbus);
548 }
549
550 mtk->vusb33 = devm_regulator_get(dev, "vusb33");
551 if (IS_ERR(mtk->vusb33)) {
552 dev_err(dev, "fail to get vusb33\n");
553 return PTR_ERR(mtk->vusb33);
554 }
555
556 mtk->sys_clk = devm_clk_get(dev, "sys_ck");
557 if (IS_ERR(mtk->sys_clk)) {
558 dev_err(dev, "fail to get sys_ck\n");
559 return PTR_ERR(mtk->sys_clk);
560 }
561
Chunfeng Yunf3c4c732017-02-07 14:13:33 +0800562 /*
563 * reference clock is usually a "fixed-clock", make it optional
564 * for backward compatibility and ignore the error if it does
565 * not exist.
566 */
Chunfeng Yun9c4afd42017-01-18 14:08:24 +0800567 mtk->ref_clk = devm_clk_get(dev, "ref_ck");
568 if (IS_ERR(mtk->ref_clk)) {
Chunfeng Yunf3c4c732017-02-07 14:13:33 +0800569 if (PTR_ERR(mtk->ref_clk) == -EPROBE_DEFER)
570 return -EPROBE_DEFER;
571
572 mtk->ref_clk = NULL;
Chunfeng Yun9c4afd42017-01-18 14:08:24 +0800573 }
574
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200575 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
576
577 ret = usb_wakeup_of_property_parse(mtk, node);
578 if (ret)
579 return ret;
580
581 mtk->num_phys = of_count_phandle_with_args(node,
582 "phys", "#phy-cells");
583 if (mtk->num_phys > 0) {
584 mtk->phys = devm_kcalloc(dev, mtk->num_phys,
585 sizeof(*mtk->phys), GFP_KERNEL);
586 if (!mtk->phys)
587 return -ENOMEM;
588 } else {
589 mtk->num_phys = 0;
590 }
591 pm_runtime_enable(dev);
592 pm_runtime_get_sync(dev);
593 device_enable_async_suspend(dev);
594
595 ret = xhci_mtk_ldos_enable(mtk);
596 if (ret)
597 goto disable_pm;
598
599 ret = xhci_mtk_clks_enable(mtk);
600 if (ret)
601 goto disable_ldos;
602
603 irq = platform_get_irq(pdev, 0);
Pan Bian28bedb52017-01-03 18:28:45 +0200604 if (irq < 0) {
605 ret = irq;
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200606 goto disable_clk;
Pan Bian28bedb52017-01-03 18:28:45 +0200607 }
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200608
609 /* Initialize dma_mask and coherent_dma_mask to 32-bits */
610 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
611 if (ret)
612 goto disable_clk;
613
614 if (!dev->dma_mask)
615 dev->dma_mask = &dev->coherent_dma_mask;
616 else
617 dma_set_mask(dev, DMA_BIT_MASK(32));
618
619 hcd = usb_create_hcd(driver, dev, dev_name(dev));
620 if (!hcd) {
621 ret = -ENOMEM;
622 goto disable_clk;
623 }
624
625 /*
626 * USB 2.0 roothub is stored in the platform_device.
627 * Swap it with mtk HCD.
628 */
629 mtk->hcd = platform_get_drvdata(pdev);
630 platform_set_drvdata(pdev, mtk);
631
Chunfeng Yun065d48c2016-10-19 10:28:22 +0800632 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200633 hcd->regs = devm_ioremap_resource(dev, res);
634 if (IS_ERR(hcd->regs)) {
635 ret = PTR_ERR(hcd->regs);
636 goto put_usb2_hcd;
637 }
638 hcd->rsrc_start = res->start;
639 hcd->rsrc_len = resource_size(res);
640
Chunfeng Yun065d48c2016-10-19 10:28:22 +0800641 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
642 if (res) { /* ippc register is optional */
643 mtk->ippc_regs = devm_ioremap_resource(dev, res);
644 if (IS_ERR(mtk->ippc_regs)) {
645 ret = PTR_ERR(mtk->ippc_regs);
646 goto put_usb2_hcd;
647 }
648 mtk->has_ippc = true;
649 } else {
650 mtk->has_ippc = false;
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200651 }
652
653 for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
654 phy = devm_of_phy_get_by_index(dev, node, phy_num);
655 if (IS_ERR(phy)) {
656 ret = PTR_ERR(phy);
657 goto put_usb2_hcd;
658 }
659 mtk->phys[phy_num] = phy;
660 }
661
662 ret = xhci_mtk_phy_init(mtk);
663 if (ret)
664 goto put_usb2_hcd;
665
666 ret = xhci_mtk_phy_power_on(mtk);
667 if (ret)
668 goto exit_phys;
669
670 device_init_wakeup(dev, true);
671
672 xhci = hcd_to_xhci(hcd);
673 xhci->main_hcd = hcd;
674 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
675 dev_name(dev), hcd);
676 if (!xhci->shared_hcd) {
677 ret = -ENOMEM;
678 goto power_off_phys;
679 }
680
681 if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
682 xhci->shared_hcd->can_do_streams = 1;
683
684 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
685 if (ret)
686 goto put_usb3_hcd;
687
688 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
689 if (ret)
690 goto dealloc_usb2_hcd;
691
692 return 0;
693
694dealloc_usb2_hcd:
695 usb_remove_hcd(hcd);
696
697put_usb3_hcd:
698 xhci_mtk_sch_exit(mtk);
699 usb_put_hcd(xhci->shared_hcd);
700
701power_off_phys:
702 xhci_mtk_phy_power_off(mtk);
703 device_init_wakeup(dev, false);
704
705exit_phys:
706 xhci_mtk_phy_exit(mtk);
707
708put_usb2_hcd:
709 usb_put_hcd(hcd);
710
711disable_clk:
712 xhci_mtk_clks_disable(mtk);
713
714disable_ldos:
715 xhci_mtk_ldos_disable(mtk);
716
717disable_pm:
718 pm_runtime_put_sync(dev);
719 pm_runtime_disable(dev);
720 return ret;
721}
722
723static int xhci_mtk_remove(struct platform_device *dev)
724{
725 struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
726 struct usb_hcd *hcd = mtk->hcd;
727 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
728
729 usb_remove_hcd(xhci->shared_hcd);
730 xhci_mtk_phy_power_off(mtk);
731 xhci_mtk_phy_exit(mtk);
732 device_init_wakeup(&dev->dev, false);
733
734 usb_remove_hcd(hcd);
735 usb_put_hcd(xhci->shared_hcd);
736 usb_put_hcd(hcd);
737 xhci_mtk_sch_exit(mtk);
738 xhci_mtk_clks_disable(mtk);
739 xhci_mtk_ldos_disable(mtk);
740 pm_runtime_put_sync(&dev->dev);
741 pm_runtime_disable(&dev->dev);
742
743 return 0;
744}
745
Chunfeng Yun882fa272016-01-26 17:50:10 +0200746/*
747 * if ip sleep fails, and all clocks are disabled, access register will hang
748 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend.
749 * and no need to check whether ip sleep failed or not; this will cause SPM
750 * to wake up system immediately after system suspend complete if ip sleep
751 * fails, it is what we wanted.
752 */
Arnd Bergmann8dac5302016-03-02 16:24:04 +0100753static int __maybe_unused xhci_mtk_suspend(struct device *dev)
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200754{
755 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
Chunfeng Yun882fa272016-01-26 17:50:10 +0200756 struct usb_hcd *hcd = mtk->hcd;
757 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
758
759 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
760 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
761 del_timer_sync(&hcd->rh_timer);
762 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
763 del_timer_sync(&xhci->shared_hcd->rh_timer);
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200764
765 xhci_mtk_host_disable(mtk);
766 xhci_mtk_phy_power_off(mtk);
767 xhci_mtk_clks_disable(mtk);
768 usb_wakeup_enable(mtk);
769 return 0;
770}
771
Arnd Bergmann8dac5302016-03-02 16:24:04 +0100772static int __maybe_unused xhci_mtk_resume(struct device *dev)
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200773{
774 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
Chunfeng Yun882fa272016-01-26 17:50:10 +0200775 struct usb_hcd *hcd = mtk->hcd;
776 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200777
778 usb_wakeup_disable(mtk);
779 xhci_mtk_clks_enable(mtk);
780 xhci_mtk_phy_power_on(mtk);
781 xhci_mtk_host_enable(mtk);
Chunfeng Yun882fa272016-01-26 17:50:10 +0200782
783 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
784 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
785 usb_hcd_poll_rh_status(hcd);
786 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
787 usb_hcd_poll_rh_status(xhci->shared_hcd);
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200788 return 0;
789}
790
791static const struct dev_pm_ops xhci_mtk_pm_ops = {
792 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
793};
Arnd Bergmann8dac5302016-03-02 16:24:04 +0100794#define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL
Chunfeng Yun0cbd4b32015-11-24 13:09:55 +0200795
796#ifdef CONFIG_OF
797static const struct of_device_id mtk_xhci_of_match[] = {
798 { .compatible = "mediatek,mt8173-xhci"},
799 { },
800};
801MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
802#endif
803
804static struct platform_driver mtk_xhci_driver = {
805 .probe = xhci_mtk_probe,
806 .remove = xhci_mtk_remove,
807 .driver = {
808 .name = "xhci-mtk",
809 .pm = DEV_PM_OPS,
810 .of_match_table = of_match_ptr(mtk_xhci_of_match),
811 },
812};
813MODULE_ALIAS("platform:xhci-mtk");
814
815static int __init xhci_mtk_init(void)
816{
817 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
818 return platform_driver_register(&mtk_xhci_driver);
819}
820module_init(xhci_mtk_init);
821
822static void __exit xhci_mtk_exit(void)
823{
824 platform_driver_unregister(&mtk_xhci_driver);
825}
826module_exit(xhci_mtk_exit);
827
828MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
829MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
830MODULE_LICENSE("GPL v2");