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gerrit-public.fairphone.software / kernel / msm-4.19 / f9eb26a4e11c63bba2fb71b58dff5ed6f33091f9 / . / arch / arm / boot / dts / tegra20.dtsi
blob: a6b135164ae0e6406944ad5f38b16eac6e8eb7a1 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame^]7 pmc {
Stephen Warrend17adfd2012-01-25 14:43:27 -0700[diff] [blame]8 compatible = "nvidia,tegra20-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame^]12 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]13 compatible = "arm,cortex-a9-gic";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]14 interrupt-controller;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]15 #interrupt-cells = <3>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]16 reg = <0x50041000 0x1000>,
17 <0x50040100 0x0100>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]18 };
19
Stephen Warren583553b2012-02-27 18:26:36 -0700[diff] [blame]20 pmu {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 56 0x04
23 0 57 0x04>;
24 };
25
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame^]26 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]27 compatible = "nvidia,tegra20-apbdma";
28 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]29 interrupts = <0 104 0x04
30 0 105 0x04
31 0 106 0x04
32 0 107 0x04
33 0 108 0x04
34 0 109 0x04
35 0 110 0x04
36 0 111 0x04
37 0 112 0x04
38 0 113 0x04
39 0 114 0x04
40 0 115 0x04
41 0 116 0x04
42 0 117 0x04
43 0 118 0x04
44 0 119 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]45 };
46
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]47 i2c@7000c000 {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 compatible = "nvidia,tegra20-i2c";
51 reg = <0x7000C000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]52 interrupts = <0 38 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]53 };
54
55 i2c@7000c400 {
56 #address-cells = <1>;
57 #size-cells = <0>;
58 compatible = "nvidia,tegra20-i2c";
59 reg = <0x7000C400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]60 interrupts = <0 84 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]61 };
62
63 i2c@7000c500 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 compatible = "nvidia,tegra20-i2c";
67 reg = <0x7000C500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]68 interrupts = <0 92 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]69 };
70
71 i2c@7000d000 {
72 #address-cells = <1>;
73 #size-cells = <0>;
Stephen Warren0bc2ecb2011-12-17 23:29:31 -0700[diff] [blame]74 compatible = "nvidia,tegra20-i2c-dvc";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]75 reg = <0x7000D000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]76 interrupts = <0 53 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]77 };
78
Stephen Warrenc404af02012-01-11 16:09:56 -0700[diff] [blame]79 tegra_i2s1: i2s@70002800 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]80 compatible = "nvidia,tegra20-i2s";
81 reg = <0x70002800 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]82 interrupts = <0 13 0x04>;
83 nvidia,dma-request-selector = <&apbdma 2>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]84 };
85
Stephen Warrenc404af02012-01-11 16:09:56 -0700[diff] [blame]86 tegra_i2s2: i2s@70002a00 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]87 compatible = "nvidia,tegra20-i2s";
88 reg = <0x70002a00 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]89 interrupts = <0 3 0x04>;
90 nvidia,dma-request-selector = <&apbdma 1>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]91 };
92
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame^]93 das {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]94 compatible = "nvidia,tegra20-das";
95 reg = <0x70000c00 0x80>;
96 };
97
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame^]98 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]99 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]100 reg = <0x6000d000 0x1000>;
101 interrupts = <0 32 0x04
102 0 33 0x04
103 0 34 0x04
104 0 35 0x04
105 0 55 0x04
106 0 87 0x04
107 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]108 #gpio-cells = <2>;
109 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]110 #interrupt-cells = <2>;
111 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]112 };
113
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame^]114 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]115 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]116 reg = <0x70000014 0x10 /* Tri-state registers */
117 0x70000080 0x20 /* Mux registers */
118 0x700000a0 0x14 /* Pull-up/down registers */
119 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]120 };
121
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]122 serial@70006000 {
123 compatible = "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>;
125 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]126 interrupts = <0 36 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]127 };
128
129 serial@70006040 {
130 compatible = "nvidia,tegra20-uart";
131 reg = <0x70006040 0x40>;
132 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]133 interrupts = <0 37 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]134 };
135
136 serial@70006200 {
137 compatible = "nvidia,tegra20-uart";
138 reg = <0x70006200 0x100>;
139 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]140 interrupts = <0 46 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]141 };
142
143 serial@70006300 {
144 compatible = "nvidia,tegra20-uart";
145 reg = <0x70006300 0x100>;
146 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]147 interrupts = <0 90 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]148 };
149
150 serial@70006400 {
151 compatible = "nvidia,tegra20-uart";
152 reg = <0x70006400 0x100>;
153 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]154 interrupts = <0 91 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]155 };
156
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame^]157 emc {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "nvidia,tegra20-emc";
161 reg = <0x7000f400 0x200>;
162 };
163
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]164 sdhci@c8000000 {
165 compatible = "nvidia,tegra20-sdhci";
166 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]167 interrupts = <0 14 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]168 };
169
170 sdhci@c8000200 {
171 compatible = "nvidia,tegra20-sdhci";
172 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]173 interrupts = <0 15 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]174 };
175
176 sdhci@c8000400 {
177 compatible = "nvidia,tegra20-sdhci";
178 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]179 interrupts = <0 19 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]180 };
181
182 sdhci@c8000600 {
183 compatible = "nvidia,tegra20-sdhci";
184 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]185 interrupts = <0 31 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]186 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]187
188 usb@c5000000 {
189 compatible = "nvidia,tegra20-ehci", "usb-ehci";
190 reg = <0xc5000000 0x4000>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]191 interrupts = <0 20 0x04>;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]192 phy_type = "utmi";
Simon Glassba202f12012-03-06 21:04:33 -0800[diff] [blame]193 nvidia,has-legacy-mode;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]194 };
195
196 usb@c5004000 {
197 compatible = "nvidia,tegra20-ehci", "usb-ehci";
198 reg = <0xc5004000 0x4000>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]199 interrupts = <0 21 0x04>;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]200 phy_type = "ulpi";
201 };
202
203 usb@c5008000 {
204 compatible = "nvidia,tegra20-ehci", "usb-ehci";
205 reg = <0xc5008000 0x4000>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]206 interrupts = <0 97 0x04>;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]207 phy_type = "utmi";
208 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]209
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame^]210 ahb {
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]211 compatible = "nvidia,tegra20-ahb";
212 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
213 };
hdoyu@nvidia.com4a82f2b2012-05-09 21:42:31 +0000[diff] [blame]214
215 mc {
216 compatible = "nvidia,tegra20-mc";
217 reg = <0x7000f000 0x024
218 0x7000f03c 0x3c4>;
219 interrupts = <0 77 0x04>;
220 };
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]221
222 gart {
223 compatible = "nvidia,tegra20-gart";
224 reg = <0x7000f024 0x00000018 /* controller registers */
225 0x58000000 0x02000000>; /* GART aperture */
226 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]227};