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gerrit-public.fairphone.software / kernel / msm-4.19 / efcf1e502012cc2cc9ee8165fa0a7679725c525c / . / arch / arm / boot / dts / omap3.dtsi
blob: 4615ebb6cb93f03d2bc1a4c1606c46e1ebd78307 [file] [log] [blame]
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,omap3430", "ti,omap3";
15
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 };
22
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]23 cpus {
24 cpu@0 {
25 compatible = "arm,cortex-a8";
26 };
27 };
28
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]29 /*
30 * The soc node represents the soc top level view. It is uses for IPs
31 * that are not memory mapped in the MPU view or for the MPU itself.
32 */
33 soc {
34 compatible = "ti,omap-infra";
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]35 mpu {
36 compatible = "ti,omap3-mpu";
37 ti,hwmods = "mpu";
38 };
39
40 iva {
41 compatible = "ti,iva2.2";
42 ti,hwmods = "iva";
43
44 dsp {
45 compatible = "ti,omap3-c64";
46 };
47 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]48 };
49
50 /*
51 * XXX: Use a flat representation of the OMAP3 interconnect.
52 * The real OMAP interconnect network is quite complex.
53 * Since that will not bring real advantage to represent that in DT for
54 * the moment, just use a fake OCP bus entry to represent the whole bus
55 * hierarchy.
56 */
57 ocp {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62 ti,hwmods = "l3_main";
63
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]64 intc: interrupt-controller@48200000 {
65 compatible = "ti,omap2-intc";
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]66 interrupt-controller;
67 #interrupt-cells = <1>;
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]68 ti,intc-size = <96>;
69 reg = <0x48200000 0x1000>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]70 };
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]71
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]72 gpio1: gpio@48310000 {
73 compatible = "ti,omap3-gpio";
74 ti,hwmods = "gpio1";
75 gpio-controller;
76 #gpio-cells = <2>;
77 interrupt-controller;
78 #interrupt-cells = <1>;
79 };
80
81 gpio2: gpio@49050000 {
82 compatible = "ti,omap3-gpio";
83 ti,hwmods = "gpio2";
84 gpio-controller;
85 #gpio-cells = <2>;
86 interrupt-controller;
87 #interrupt-cells = <1>;
88 };
89
90 gpio3: gpio@49052000 {
91 compatible = "ti,omap3-gpio";
92 ti,hwmods = "gpio3";
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <1>;
97 };
98
99 gpio4: gpio@49054000 {
100 compatible = "ti,omap3-gpio";
101 ti,hwmods = "gpio4";
102 gpio-controller;
103 #gpio-cells = <2>;
104 interrupt-controller;
105 #interrupt-cells = <1>;
106 };
107
108 gpio5: gpio@49056000 {
109 compatible = "ti,omap3-gpio";
110 ti,hwmods = "gpio5";
111 gpio-controller;
112 #gpio-cells = <2>;
113 interrupt-controller;
114 #interrupt-cells = <1>;
115 };
116
117 gpio6: gpio@49058000 {
118 compatible = "ti,omap3-gpio";
119 ti,hwmods = "gpio6";
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <1>;
124 };
125
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]126 uart1: serial@4806a000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]127 compatible = "ti,omap3-uart";
128 ti,hwmods = "uart1";
129 clock-frequency = <48000000>;
130 };
131
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]132 uart2: serial@4806c000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]133 compatible = "ti,omap3-uart";
134 ti,hwmods = "uart2";
135 clock-frequency = <48000000>;
136 };
137
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]138 uart3: serial@49020000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]139 compatible = "ti,omap3-uart";
140 ti,hwmods = "uart3";
141 clock-frequency = <48000000>;
142 };
143
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]144 uart4: serial@49042000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]145 compatible = "ti,omap3-uart";
146 ti,hwmods = "uart4";
147 clock-frequency = <48000000>;
148 };
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]149
150 i2c1: i2c@48070000 {
151 compatible = "ti,omap3-i2c";
152 #address-cells = <1>;
153 #size-cells = <0>;
154 ti,hwmods = "i2c1";
155 };
156
157 i2c2: i2c@48072000 {
158 compatible = "ti,omap3-i2c";
159 #address-cells = <1>;
160 #size-cells = <0>;
161 ti,hwmods = "i2c2";
162 };
163
164 i2c3: i2c@48060000 {
165 compatible = "ti,omap3-i2c";
166 #address-cells = <1>;
167 #size-cells = <0>;
168 ti,hwmods = "i2c3";
169 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]170 };
171};