Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 1 | /* |
| 2 | * CXL Flash Device Driver |
| 3 | * |
| 4 | * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation |
| 5 | * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation |
| 6 | * |
| 7 | * Copyright (C) 2015 IBM Corporation |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | */ |
| 14 | |
| 15 | #ifndef _CXLFLASH_COMMON_H |
| 16 | #define _CXLFLASH_COMMON_H |
| 17 | |
Matthew R. Ochs | cba06e6 | 2017-04-12 14:13:20 -0500 | [diff] [blame] | 18 | #include <linux/irq_poll.h> |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 19 | #include <linux/list.h> |
Matthew R. Ochs | 0a27ae5 | 2015-10-21 15:11:52 -0500 | [diff] [blame] | 20 | #include <linux/rwsem.h> |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 21 | #include <linux/types.h> |
| 22 | #include <scsi/scsi.h> |
Matthew R. Ochs | 5fbb96c | 2016-11-28 18:42:19 -0600 | [diff] [blame] | 23 | #include <scsi/scsi_cmnd.h> |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 24 | #include <scsi/scsi_device.h> |
| 25 | |
Matthew R. Ochs | 17ead26 | 2015-10-21 15:15:37 -0500 | [diff] [blame] | 26 | extern const struct file_operations cxlflash_cxl_fops; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 27 | |
Matthew R. Ochs | 78ae028 | 2017-04-12 14:13:50 -0500 | [diff] [blame] | 28 | #define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */ |
Matthew R. Ochs | 56518072 | 2017-04-12 14:14:28 -0500 | [diff] [blame] | 29 | #define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */ |
| 30 | #define LEGACY_FC_PORTS 2 /* legacy ports per AFU */ |
| 31 | |
| 32 | #define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK)) |
| 33 | #define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1)) |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 34 | |
Matthew R. Ochs | 8fa4f17 | 2017-04-12 14:14:05 -0500 | [diff] [blame] | 35 | #define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */ |
| 36 | #define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */ |
| 37 | #define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */ |
| 38 | |
Matthew R. Ochs | fcc87e7 | 2017-04-12 14:15:20 -0500 | [diff] [blame^] | 39 | #define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */ |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 40 | #define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */ |
| 41 | #define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants |
Matthew R. Ochs | fcc87e7 | 2017-04-12 14:15:20 -0500 | [diff] [blame^] | 42 | * max_sectors |
| 43 | * in units of |
| 44 | * 512 byte |
| 45 | * sectors |
| 46 | */ |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 47 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 48 | #define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry)) |
| 49 | |
| 50 | /* AFU command retry limit */ |
Matthew R. Ochs | fcc87e7 | 2017-04-12 14:15:20 -0500 | [diff] [blame^] | 51 | #define MC_RETRY_CNT 5 /* Sufficient for SCSI and certain AFU errors */ |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 52 | |
| 53 | /* Command management definitions */ |
Manoj N. Kumar | 8343083 | 2016-03-04 15:55:20 -0600 | [diff] [blame] | 54 | #define CXLFLASH_MAX_CMDS 256 |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 55 | #define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS |
| 56 | |
Manoj N. Kumar | 8343083 | 2016-03-04 15:55:20 -0600 | [diff] [blame] | 57 | /* RRQ for master issued cmds */ |
| 58 | #define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS |
| 59 | |
Matthew R. Ochs | 696d0b0 | 2017-01-11 19:19:33 -0600 | [diff] [blame] | 60 | /* SQ for master issued cmds */ |
| 61 | #define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS |
| 62 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 63 | |
| 64 | static inline void check_sizes(void) |
| 65 | { |
Matthew R. Ochs | 56518072 | 2017-04-12 14:14:28 -0500 | [diff] [blame] | 66 | BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK); |
Matthew R. Ochs | cd41e18 | 2017-04-12 14:15:11 -0500 | [diff] [blame] | 67 | BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS); |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | /* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */ |
| 71 | #define CMD_BUFSIZE SIZE_4K |
| 72 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 73 | enum cxlflash_lr_state { |
| 74 | LINK_RESET_INVALID, |
| 75 | LINK_RESET_REQUIRED, |
| 76 | LINK_RESET_COMPLETE |
| 77 | }; |
| 78 | |
| 79 | enum cxlflash_init_state { |
| 80 | INIT_STATE_NONE, |
| 81 | INIT_STATE_PCI, |
| 82 | INIT_STATE_AFU, |
| 83 | INIT_STATE_SCSI |
| 84 | }; |
| 85 | |
Matthew R. Ochs | 5cdac81 | 2015-08-13 21:47:34 -0500 | [diff] [blame] | 86 | enum cxlflash_state { |
Matthew R. Ochs | 323e334 | 2017-04-12 14:14:51 -0500 | [diff] [blame] | 87 | STATE_PROBING, /* Initial state during probe */ |
| 88 | STATE_PROBED, /* Temporary state, probe completed but EEH occurred */ |
Matthew R. Ochs | 5cdac81 | 2015-08-13 21:47:34 -0500 | [diff] [blame] | 89 | STATE_NORMAL, /* Normal running state, everything good */ |
Matthew R. Ochs | 439e85c | 2015-10-21 15:12:00 -0500 | [diff] [blame] | 90 | STATE_RESET, /* Reset state, trying to reset/recover */ |
Matthew R. Ochs | 5cdac81 | 2015-08-13 21:47:34 -0500 | [diff] [blame] | 91 | STATE_FAILTERM /* Failed/terminating state, error out users/threads */ |
| 92 | }; |
| 93 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 94 | /* |
| 95 | * Each context has its own set of resource handles that is visible |
| 96 | * only from that context. |
| 97 | */ |
| 98 | |
| 99 | struct cxlflash_cfg { |
| 100 | struct afu *afu; |
| 101 | struct cxl_context *mcctx; |
| 102 | |
| 103 | struct pci_dev *dev; |
| 104 | struct pci_device_id *dev_id; |
| 105 | struct Scsi_Host *host; |
Matthew R. Ochs | 78ae028 | 2017-04-12 14:13:50 -0500 | [diff] [blame] | 106 | int num_fc_ports; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 107 | |
| 108 | ulong cxlflash_regs_pci; |
| 109 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 110 | struct work_struct work_q; |
| 111 | enum cxlflash_init_state init_state; |
| 112 | enum cxlflash_lr_state lr_state; |
| 113 | int lr_port; |
Matthew R. Ochs | ef51074 | 2015-10-21 15:13:37 -0500 | [diff] [blame] | 114 | atomic_t scan_host_needed; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 115 | |
| 116 | struct cxl_afu *cxl_afu; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 117 | |
Matthew R. Ochs | 65be2c7 | 2015-08-13 21:47:43 -0500 | [diff] [blame] | 118 | atomic_t recovery_threads; |
| 119 | struct mutex ctx_recovery_mutex; |
| 120 | struct mutex ctx_tbl_list_mutex; |
Matthew R. Ochs | 0a27ae5 | 2015-10-21 15:11:52 -0500 | [diff] [blame] | 121 | struct rw_semaphore ioctl_rwsem; |
Matthew R. Ochs | 65be2c7 | 2015-08-13 21:47:43 -0500 | [diff] [blame] | 122 | struct ctx_info *ctx_tbl[MAX_CONTEXT]; |
| 123 | struct list_head ctx_err_recovery; /* contexts w/ recovery pending */ |
| 124 | struct file_operations cxl_fops; |
| 125 | |
Matthew R. Ochs | 2cb7926 | 2015-08-13 21:47:53 -0500 | [diff] [blame] | 126 | /* Parameters that are LUN table related */ |
Matthew R. Ochs | 78ae028 | 2017-04-12 14:13:50 -0500 | [diff] [blame] | 127 | int last_lun_index[MAX_FC_PORTS]; |
Matthew R. Ochs | 2cb7926 | 2015-08-13 21:47:53 -0500 | [diff] [blame] | 128 | int promote_lun_index; |
Matthew R. Ochs | 65be2c7 | 2015-08-13 21:47:43 -0500 | [diff] [blame] | 129 | struct list_head lluns; /* list of llun_info structs */ |
| 130 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 131 | wait_queue_head_t tmf_waitq; |
Matthew R. Ochs | 018d1dc95 | 2015-10-21 15:13:21 -0500 | [diff] [blame] | 132 | spinlock_t tmf_slock; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 133 | bool tmf_active; |
Matthew R. Ochs | 439e85c | 2015-10-21 15:12:00 -0500 | [diff] [blame] | 134 | wait_queue_head_t reset_waitq; |
Matthew R. Ochs | 5cdac81 | 2015-08-13 21:47:34 -0500 | [diff] [blame] | 135 | enum cxlflash_state state; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 136 | }; |
| 137 | |
| 138 | struct afu_cmd { |
| 139 | struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */ |
| 140 | struct sisl_ioasa sa; /* IOASA must follow IOARCB */ |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 141 | struct afu *parent; |
Matthew R. Ochs | fe7f969 | 2016-11-28 18:43:18 -0600 | [diff] [blame] | 142 | struct scsi_cmnd *scp; |
Matthew R. Ochs | 9ba848a | 2016-11-28 18:42:42 -0600 | [diff] [blame] | 143 | struct completion cevent; |
Matthew R. Ochs | f918b4a | 2017-04-12 14:12:55 -0500 | [diff] [blame] | 144 | struct list_head queue; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 145 | |
| 146 | u8 cmd_tmf:1; |
| 147 | |
| 148 | /* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned. |
| 149 | * However for performance reasons the IOARCB/IOASA should be |
| 150 | * cache line aligned. |
| 151 | */ |
| 152 | } __aligned(cache_line_size()); |
| 153 | |
Matthew R. Ochs | 5fbb96c | 2016-11-28 18:42:19 -0600 | [diff] [blame] | 154 | static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc) |
| 155 | { |
| 156 | return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd)); |
| 157 | } |
| 158 | |
| 159 | static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc) |
| 160 | { |
| 161 | struct afu_cmd *afuc = sc_to_afuc(sc); |
| 162 | |
| 163 | memset(afuc, 0, sizeof(*afuc)); |
| 164 | return afuc; |
| 165 | } |
| 166 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 167 | struct afu { |
| 168 | /* Stuff requiring alignment go first. */ |
Matthew R. Ochs | 696d0b0 | 2017-01-11 19:19:33 -0600 | [diff] [blame] | 169 | struct sisl_ioarcb sq[NUM_SQ_ENTRY]; /* 16K SQ */ |
| 170 | u64 rrq_entry[NUM_RRQ_ENTRY]; /* 2K RRQ */ |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 171 | |
| 172 | /* Beware of alignment till here. Preferably introduce new |
| 173 | * fields after this point |
| 174 | */ |
| 175 | |
Matthew R. Ochs | 48b4be3 | 2016-11-28 18:43:09 -0600 | [diff] [blame] | 176 | int (*send_cmd)(struct afu *, struct afu_cmd *); |
| 177 | void (*context_reset)(struct afu_cmd *); |
| 178 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 179 | /* AFU HW */ |
| 180 | struct cxl_ioctl_start_work work; |
Matthew R. Ochs | 1786f4a | 2015-10-21 15:14:48 -0500 | [diff] [blame] | 181 | struct cxlflash_afu_map __iomem *afu_map; /* entire MMIO map */ |
| 182 | struct sisl_host_map __iomem *host_map; /* MC host map */ |
| 183 | struct sisl_ctrl_map __iomem *ctrl_map; /* MC control map */ |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 184 | |
| 185 | ctx_hndl_t ctx_hndl; /* master's context handle */ |
Matthew R. Ochs | 696d0b0 | 2017-01-11 19:19:33 -0600 | [diff] [blame] | 186 | |
| 187 | atomic_t hsq_credits; |
| 188 | spinlock_t hsq_slock; |
| 189 | struct sisl_ioarcb *hsq_start; |
| 190 | struct sisl_ioarcb *hsq_end; |
| 191 | struct sisl_ioarcb *hsq_curr; |
Matthew R. Ochs | f918b4a | 2017-04-12 14:12:55 -0500 | [diff] [blame] | 192 | spinlock_t hrrq_slock; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 193 | u64 *hrrq_start; |
| 194 | u64 *hrrq_end; |
| 195 | u64 *hrrq_curr; |
| 196 | bool toggle; |
Matthew R. Ochs | de01283 | 2016-11-28 18:42:33 -0600 | [diff] [blame] | 197 | atomic_t cmds_active; /* Number of currently active AFU commands */ |
Uma Krishnan | 11f7b18 | 2016-11-28 18:41:45 -0600 | [diff] [blame] | 198 | s64 room; |
| 199 | spinlock_t rrin_slock; /* Lock to rrin queuing and cmd_room updates */ |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 200 | u64 hb; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 201 | u32 internal_lun; /* User-desired LUN mode for this AFU */ |
| 202 | |
Matthew R. Ochs | e5ce067 | 2015-10-21 15:14:01 -0500 | [diff] [blame] | 203 | char version[16]; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 204 | u64 interface_version; |
| 205 | |
Matthew R. Ochs | cba06e6 | 2017-04-12 14:13:20 -0500 | [diff] [blame] | 206 | u32 irqpoll_weight; |
| 207 | struct irq_poll irqpoll; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 208 | struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */ |
| 209 | |
| 210 | }; |
| 211 | |
Matthew R. Ochs | cba06e6 | 2017-04-12 14:13:20 -0500 | [diff] [blame] | 212 | static inline bool afu_is_irqpoll_enabled(struct afu *afu) |
| 213 | { |
| 214 | return !!afu->irqpoll_weight; |
| 215 | } |
| 216 | |
Matthew R. Ochs | 696d0b0 | 2017-01-11 19:19:33 -0600 | [diff] [blame] | 217 | static inline bool afu_is_cmd_mode(struct afu *afu, u64 cmd_mode) |
| 218 | { |
| 219 | u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT; |
| 220 | |
| 221 | return afu_cap & cmd_mode; |
| 222 | } |
| 223 | |
| 224 | static inline bool afu_is_sq_cmd_mode(struct afu *afu) |
| 225 | { |
| 226 | return afu_is_cmd_mode(afu, SISL_INTVER_CAP_SQ_CMD_MODE); |
| 227 | } |
| 228 | |
| 229 | static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu) |
| 230 | { |
| 231 | return afu_is_cmd_mode(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE); |
| 232 | } |
| 233 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 234 | static inline u64 lun_to_lunid(u64 lun) |
| 235 | { |
Matthew R. Ochs | 1786f4a | 2015-10-21 15:14:48 -0500 | [diff] [blame] | 236 | __be64 lun_id; |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 237 | |
| 238 | int_to_scsilun(lun, (struct scsi_lun *)&lun_id); |
Matthew R. Ochs | 1786f4a | 2015-10-21 15:14:48 -0500 | [diff] [blame] | 239 | return be64_to_cpu(lun_id); |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 240 | } |
| 241 | |
Matthew R. Ochs | 56518072 | 2017-04-12 14:14:28 -0500 | [diff] [blame] | 242 | static inline struct fc_port_bank __iomem *get_fc_port_bank( |
| 243 | struct cxlflash_cfg *cfg, int i) |
Matthew R. Ochs | 0aa14887 | 2017-04-12 14:14:17 -0500 | [diff] [blame] | 244 | { |
| 245 | struct afu *afu = cfg->afu; |
| 246 | |
Matthew R. Ochs | 56518072 | 2017-04-12 14:14:28 -0500 | [diff] [blame] | 247 | return &afu->afu_map->global.bank[CHAN2PORTBANK(i)]; |
| 248 | } |
| 249 | |
| 250 | static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i) |
| 251 | { |
| 252 | struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i); |
| 253 | |
| 254 | return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0]; |
Matthew R. Ochs | 0aa14887 | 2017-04-12 14:14:17 -0500 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i) |
| 258 | { |
Matthew R. Ochs | 56518072 | 2017-04-12 14:14:28 -0500 | [diff] [blame] | 259 | struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i); |
Matthew R. Ochs | 0aa14887 | 2017-04-12 14:14:17 -0500 | [diff] [blame] | 260 | |
Matthew R. Ochs | 56518072 | 2017-04-12 14:14:28 -0500 | [diff] [blame] | 261 | return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0]; |
Matthew R. Ochs | 0aa14887 | 2017-04-12 14:14:17 -0500 | [diff] [blame] | 262 | } |
| 263 | |
Matthew R. Ochs | fcc87e7 | 2017-04-12 14:15:20 -0500 | [diff] [blame^] | 264 | int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode); |
Matthew R. Ochs | 65be2c7 | 2015-08-13 21:47:43 -0500 | [diff] [blame] | 265 | void cxlflash_list_init(void); |
| 266 | void cxlflash_term_global_luns(void); |
| 267 | void cxlflash_free_errpage(void); |
Matthew R. Ochs | fcc87e7 | 2017-04-12 14:15:20 -0500 | [diff] [blame^] | 268 | int cxlflash_ioctl(struct scsi_device *sdev, int cmd, void __user *arg); |
| 269 | void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg); |
| 270 | int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg); |
| 271 | void cxlflash_term_local_luns(struct cxlflash_cfg *cfg); |
| 272 | void cxlflash_restore_luntable(struct cxlflash_cfg *cfg); |
Matthew R. Ochs | 65be2c7 | 2015-08-13 21:47:43 -0500 | [diff] [blame] | 273 | |
Matthew R. Ochs | c21e0bb | 2015-06-09 17:15:52 -0500 | [diff] [blame] | 274 | #endif /* ifndef _CXLFLASH_COMMON_H */ |