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Magnus Damm3d5de272012-05-16 15:45:54 +09001/*
2 * Device Tree Source for the EMEV2 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,emev2";
15 interrupt-parent = <&gic>;
16
17 cpus {
Simon Hormanfe681d22013-01-28 09:41:40 +090018 #address-cells = <1>;
19 #size-cells = <0>;
20
Magnus Damm3d5de272012-05-16 15:45:54 +090021 cpu@0 {
Simon Hormanfe681d22013-01-28 09:41:40 +090022 device_type = "cpu";
Magnus Damm3d5de272012-05-16 15:45:54 +090023 compatible = "arm,cortex-a9";
Simon Hormanfe681d22013-01-28 09:41:40 +090024 reg = <0>;
Magnus Damm3d5de272012-05-16 15:45:54 +090025 };
26 cpu@1 {
Simon Hormanfe681d22013-01-28 09:41:40 +090027 device_type = "cpu";
Magnus Damm3d5de272012-05-16 15:45:54 +090028 compatible = "arm,cortex-a9";
Simon Hormanfe681d22013-01-28 09:41:40 +090029 reg = <1>;
Magnus Damm3d5de272012-05-16 15:45:54 +090030 };
31 };
32
33 gic: interrupt-controller@e0020000 {
34 compatible = "arm,cortex-a9-gic";
35 interrupt-controller;
36 #interrupt-cells = <3>;
37 reg = <0xe0028000 0x1000>,
38 <0xe0020000 0x0100>;
39 };
40
41 sti@e0180000 {
42 compatible = "renesas,em-sti";
43 reg = <0xe0180000 0x54>;
44 interrupts = <0 125 0>;
45 };
46
47 uart@e1020000 {
48 compatible = "renesas,em-uart";
49 reg = <0xe1020000 0x38>;
50 interrupts = <0 8 0>;
51 };
52
53 uart@e1030000 {
54 compatible = "renesas,em-uart";
55 reg = <0xe1030000 0x38>;
56 interrupts = <0 9 0>;
57 };
58
59 uart@e1040000 {
60 compatible = "renesas,em-uart";
61 reg = <0xe1040000 0x38>;
62 interrupts = <0 10 0>;
63 };
64
65 uart@e1050000 {
66 compatible = "renesas,em-uart";
67 reg = <0xe1050000 0x38>;
68 interrupts = <0 11 0>;
69 };
70};