blob: 61044c889f7fec11ef8f0f6b81c78fafd15c87a3 [file] [log] [blame]
Erik Gilling3c92db92010-03-15 19:40:06 -07001/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/init.h>
21#include <linux/irq.h>
Colin Cross2e47b8b2010-04-07 12:59:42 -070022#include <linux/interrupt.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070023#include <linux/io.h>
24#include <linux/gpio.h>
Grant Likelydf221222011-06-15 14:54:14 -060025#include <linux/of.h>
Stephen Warren88d89512011-10-11 16:16:14 -060026#include <linux/platform_device.h>
27#include <linux/module.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070028
Will Deacon98022942011-02-21 13:58:10 +000029#include <asm/mach/irq.h>
30
Stephen Warrenea5abbd2011-09-26 19:00:02 +010031#include <mach/gpio-tegra.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070032#include <mach/iomap.h>
Colin Cross2ea67fd2010-10-04 08:49:49 -070033#include <mach/suspend.h>
Erik Gilling3c92db92010-03-15 19:40:06 -070034
35#define GPIO_BANK(x) ((x) >> 5)
36#define GPIO_PORT(x) (((x) >> 3) & 0x3)
37#define GPIO_BIT(x) ((x) & 0x7)
38
Stephen Warren88d89512011-10-11 16:16:14 -060039#define GPIO_REG(x) (GPIO_BANK(x) * 0x80 + GPIO_PORT(x) * 4)
Erik Gilling3c92db92010-03-15 19:40:06 -070040
41#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
42#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
43#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
44#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
45#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
46#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
47#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
48#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
49
50#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800)
51#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810)
52#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820)
53#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840)
54#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850)
55#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860)
56
57#define GPIO_INT_LVL_MASK 0x010101
58#define GPIO_INT_LVL_EDGE_RISING 0x000101
59#define GPIO_INT_LVL_EDGE_FALLING 0x000100
60#define GPIO_INT_LVL_EDGE_BOTH 0x010100
61#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
62#define GPIO_INT_LVL_LEVEL_LOW 0x000000
63
64struct tegra_gpio_bank {
65 int bank;
66 int irq;
67 spinlock_t lvl_lock[4];
Colin Cross2e47b8b2010-04-07 12:59:42 -070068#ifdef CONFIG_PM
69 u32 cnf[4];
70 u32 out[4];
71 u32 oe[4];
72 u32 int_enb[4];
73 u32 int_lvl[4];
74#endif
Erik Gilling3c92db92010-03-15 19:40:06 -070075};
76
77
Stephen Warren88d89512011-10-11 16:16:14 -060078static void __iomem *regs;
79static struct tegra_gpio_bank tegra_gpio_banks[7];
80
81static inline void tegra_gpio_writel(u32 val, u32 reg)
82{
83 __raw_writel(val, regs + reg);
84}
85
86static inline u32 tegra_gpio_readl(u32 reg)
87{
88 return __raw_readl(regs + reg);
89}
Erik Gilling3c92db92010-03-15 19:40:06 -070090
91static int tegra_gpio_compose(int bank, int port, int bit)
92{
93 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
94}
95
96static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
97{
98 u32 val;
99
100 val = 0x100 << GPIO_BIT(gpio);
101 if (value)
102 val |= 1 << GPIO_BIT(gpio);
Stephen Warren88d89512011-10-11 16:16:14 -0600103 tegra_gpio_writel(val, reg);
Erik Gilling3c92db92010-03-15 19:40:06 -0700104}
105
106void tegra_gpio_enable(int gpio)
107{
108 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
109}
110
111void tegra_gpio_disable(int gpio)
112{
113 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
114}
115
116static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
117{
118 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
119}
120
121static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
122{
Stephen Warren88d89512011-10-11 16:16:14 -0600123 return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
Erik Gilling3c92db92010-03-15 19:40:06 -0700124}
125
126static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
127{
128 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
129 return 0;
130}
131
132static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
133 int value)
134{
135 tegra_gpio_set(chip, offset, value);
136 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
137 return 0;
138}
139
Stephen Warren438a99c2011-08-23 00:39:56 +0100140static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
141{
142 return TEGRA_GPIO_TO_IRQ(offset);
143}
Erik Gilling3c92db92010-03-15 19:40:06 -0700144
145static struct gpio_chip tegra_gpio_chip = {
146 .label = "tegra-gpio",
147 .direction_input = tegra_gpio_direction_input,
148 .get = tegra_gpio_get,
149 .direction_output = tegra_gpio_direction_output,
150 .set = tegra_gpio_set,
Stephen Warren438a99c2011-08-23 00:39:56 +0100151 .to_irq = tegra_gpio_to_irq,
Erik Gilling3c92db92010-03-15 19:40:06 -0700152 .base = 0,
Colin Cross2e47b8b2010-04-07 12:59:42 -0700153 .ngpio = TEGRA_NR_GPIOS,
Erik Gilling3c92db92010-03-15 19:40:06 -0700154};
155
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100156static void tegra_gpio_irq_ack(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700157{
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100158 int gpio = d->irq - INT_GPIO_BASE;
Erik Gilling3c92db92010-03-15 19:40:06 -0700159
Stephen Warren88d89512011-10-11 16:16:14 -0600160 tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700161}
162
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100163static void tegra_gpio_irq_mask(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700164{
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100165 int gpio = d->irq - INT_GPIO_BASE;
Erik Gilling3c92db92010-03-15 19:40:06 -0700166
167 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
168}
169
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100170static void tegra_gpio_irq_unmask(struct irq_data *d)
Erik Gilling3c92db92010-03-15 19:40:06 -0700171{
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100172 int gpio = d->irq - INT_GPIO_BASE;
Erik Gilling3c92db92010-03-15 19:40:06 -0700173
174 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
175}
176
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100177static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
Erik Gilling3c92db92010-03-15 19:40:06 -0700178{
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100179 int gpio = d->irq - INT_GPIO_BASE;
180 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
Erik Gilling3c92db92010-03-15 19:40:06 -0700181 int port = GPIO_PORT(gpio);
182 int lvl_type;
183 int val;
184 unsigned long flags;
185
186 switch (type & IRQ_TYPE_SENSE_MASK) {
187 case IRQ_TYPE_EDGE_RISING:
188 lvl_type = GPIO_INT_LVL_EDGE_RISING;
189 break;
190
191 case IRQ_TYPE_EDGE_FALLING:
192 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
193 break;
194
195 case IRQ_TYPE_EDGE_BOTH:
196 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
197 break;
198
199 case IRQ_TYPE_LEVEL_HIGH:
200 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
201 break;
202
203 case IRQ_TYPE_LEVEL_LOW:
204 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
205 break;
206
207 default:
208 return -EINVAL;
209 }
210
211 spin_lock_irqsave(&bank->lvl_lock[port], flags);
212
Stephen Warren88d89512011-10-11 16:16:14 -0600213 val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700214 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
215 val |= lvl_type << GPIO_BIT(gpio);
Stephen Warren88d89512011-10-11 16:16:14 -0600216 tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700217
218 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
219
220 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100221 __irq_set_handler_locked(d->irq, handle_level_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700222 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100223 __irq_set_handler_locked(d->irq, handle_edge_irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700224
225 return 0;
226}
227
228static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
229{
230 struct tegra_gpio_bank *bank;
231 int port;
232 int pin;
233 int unmasked = 0;
Will Deacon98022942011-02-21 13:58:10 +0000234 struct irq_chip *chip = irq_desc_get_chip(desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700235
Will Deacon98022942011-02-21 13:58:10 +0000236 chained_irq_enter(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700237
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100238 bank = irq_get_handler_data(irq);
Erik Gilling3c92db92010-03-15 19:40:06 -0700239
240 for (port = 0; port < 4; port++) {
241 int gpio = tegra_gpio_compose(bank->bank, port, 0);
Stephen Warren88d89512011-10-11 16:16:14 -0600242 unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
243 tegra_gpio_readl(GPIO_INT_ENB(gpio));
244 u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700245
246 for_each_set_bit(pin, &sta, 8) {
Stephen Warren88d89512011-10-11 16:16:14 -0600247 tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700248
249 /* if gpio is edge triggered, clear condition
250 * before executing the hander so that we don't
251 * miss edges
252 */
253 if (lvl & (0x100 << pin)) {
254 unmasked = 1;
Will Deacon98022942011-02-21 13:58:10 +0000255 chained_irq_exit(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700256 }
257
258 generic_handle_irq(gpio_to_irq(gpio + pin));
259 }
260 }
261
262 if (!unmasked)
Will Deacon98022942011-02-21 13:58:10 +0000263 chained_irq_exit(chip, desc);
Erik Gilling3c92db92010-03-15 19:40:06 -0700264
265}
266
Colin Cross2e47b8b2010-04-07 12:59:42 -0700267#ifdef CONFIG_PM
268void tegra_gpio_resume(void)
269{
270 unsigned long flags;
Colin Crossc8309ef2011-03-30 00:24:43 -0700271 int b;
272 int p;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700273
274 local_irq_save(flags);
275
276 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
277 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
278
279 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
280 unsigned int gpio = (b<<5) | (p<<3);
Stephen Warren88d89512011-10-11 16:16:14 -0600281 tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
282 tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
283 tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
284 tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
285 tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
Colin Cross2e47b8b2010-04-07 12:59:42 -0700286 }
287 }
288
289 local_irq_restore(flags);
Colin Cross2e47b8b2010-04-07 12:59:42 -0700290}
291
292void tegra_gpio_suspend(void)
293{
294 unsigned long flags;
Colin Crossc8309ef2011-03-30 00:24:43 -0700295 int b;
296 int p;
Colin Cross2e47b8b2010-04-07 12:59:42 -0700297
Colin Cross2e47b8b2010-04-07 12:59:42 -0700298 local_irq_save(flags);
299 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
300 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
301
302 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
303 unsigned int gpio = (b<<5) | (p<<3);
Stephen Warren88d89512011-10-11 16:16:14 -0600304 bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
305 bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
306 bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
307 bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
308 bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
Colin Cross2e47b8b2010-04-07 12:59:42 -0700309 }
310 }
311 local_irq_restore(flags);
312}
313
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100314static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
Colin Cross2e47b8b2010-04-07 12:59:42 -0700315{
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100316 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100317 return irq_set_irq_wake(bank->irq, enable);
Colin Cross2e47b8b2010-04-07 12:59:42 -0700318}
319#endif
Erik Gilling3c92db92010-03-15 19:40:06 -0700320
321static struct irq_chip tegra_gpio_irq_chip = {
322 .name = "GPIO",
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100323 .irq_ack = tegra_gpio_irq_ack,
324 .irq_mask = tegra_gpio_irq_mask,
325 .irq_unmask = tegra_gpio_irq_unmask,
326 .irq_set_type = tegra_gpio_irq_set_type,
Colin Cross2e47b8b2010-04-07 12:59:42 -0700327#ifdef CONFIG_PM
Lennert Buytenhek37337a82010-11-29 11:14:46 +0100328 .irq_set_wake = tegra_gpio_wake_enable,
Colin Cross2e47b8b2010-04-07 12:59:42 -0700329#endif
Erik Gilling3c92db92010-03-15 19:40:06 -0700330};
331
332
333/* This lock class tells lockdep that GPIO irqs are in a different
334 * category than their parents, so it won't report false recursion.
335 */
336static struct lock_class_key gpio_lock_class;
337
Stephen Warren88d89512011-10-11 16:16:14 -0600338static int __devinit tegra_gpio_probe(struct platform_device *pdev)
Erik Gilling3c92db92010-03-15 19:40:06 -0700339{
Stephen Warren88d89512011-10-11 16:16:14 -0600340 struct resource *res;
Erik Gilling3c92db92010-03-15 19:40:06 -0700341 struct tegra_gpio_bank *bank;
Stephen Warren47008002011-08-23 00:39:55 +0100342 int gpio;
Erik Gilling3c92db92010-03-15 19:40:06 -0700343 int i;
344 int j;
345
Stephen Warren88d89512011-10-11 16:16:14 -0600346 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
347 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
348 if (!res) {
349 dev_err(&pdev->dev, "Missing IRQ resource\n");
350 return -ENODEV;
351 }
352
353 bank = &tegra_gpio_banks[i];
354 bank->bank = i;
355 bank->irq = res->start;
356 }
357
358 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
359 if (!res) {
360 dev_err(&pdev->dev, "Missing MEM resource\n");
361 return -ENODEV;
362 }
363
364 if (!devm_request_mem_region(&pdev->dev, res->start,
365 resource_size(res),
366 dev_name(&pdev->dev))) {
367 dev_err(&pdev->dev, "Couldn't request MEM resource\n");
368 return -ENODEV;
369 }
370
371 regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
372 if (!regs) {
373 dev_err(&pdev->dev, "Couldn't ioremap regs\n");
374 return -ENODEV;
375 }
376
Erik Gilling3c92db92010-03-15 19:40:06 -0700377 for (i = 0; i < 7; i++) {
378 for (j = 0; j < 4; j++) {
379 int gpio = tegra_gpio_compose(i, j, 0);
Stephen Warren88d89512011-10-11 16:16:14 -0600380 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
Erik Gilling3c92db92010-03-15 19:40:06 -0700381 }
382 }
383
Grant Likelydf221222011-06-15 14:54:14 -0600384#ifdef CONFIG_OF_GPIO
Stephen Warren88d89512011-10-11 16:16:14 -0600385 tegra_gpio_chip.of_node = pdev->dev.of_node;
386#endif
Grant Likelydf221222011-06-15 14:54:14 -0600387
Erik Gilling3c92db92010-03-15 19:40:06 -0700388 gpiochip_add(&tegra_gpio_chip);
389
Stephen Warren47008002011-08-23 00:39:55 +0100390 for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
391 int irq = TEGRA_GPIO_TO_IRQ(gpio);
392 /* No validity check; all Tegra GPIOs are valid IRQs */
Erik Gilling3c92db92010-03-15 19:40:06 -0700393
Stephen Warren47008002011-08-23 00:39:55 +0100394 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
395
396 irq_set_lockdep_class(irq, &gpio_lock_class);
397 irq_set_chip_data(irq, bank);
398 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100399 handle_simple_irq);
Stephen Warren47008002011-08-23 00:39:55 +0100400 set_irq_flags(irq, IRQF_VALID);
Erik Gilling3c92db92010-03-15 19:40:06 -0700401 }
402
403 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
404 bank = &tegra_gpio_banks[i];
405
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100406 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
407 irq_set_handler_data(bank->irq, bank);
Erik Gilling3c92db92010-03-15 19:40:06 -0700408
409 for (j = 0; j < 4; j++)
410 spin_lock_init(&bank->lvl_lock[j]);
411 }
412
413 return 0;
414}
415
Stephen Warren88d89512011-10-11 16:16:14 -0600416static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
417 { .compatible = "nvidia,tegra20-gpio", },
418 { },
419};
420
421static struct platform_driver tegra_gpio_driver = {
422 .driver = {
423 .name = "tegra-gpio",
424 .owner = THIS_MODULE,
425 .of_match_table = tegra_gpio_of_match,
426 },
427 .probe = tegra_gpio_probe,
428};
429
430static int __init tegra_gpio_init(void)
431{
432 return platform_driver_register(&tegra_gpio_driver);
433}
Erik Gilling3c92db92010-03-15 19:40:06 -0700434postcore_initcall(tegra_gpio_init);
435
Olof Johansson632095e2011-02-13 19:12:27 -0800436void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
437{
438 int i;
439
440 for (i = 0; i < num; i++) {
441 int gpio = table[i].gpio;
442
443 if (table[i].enable)
444 tegra_gpio_enable(gpio);
445 else
446 tegra_gpio_disable(gpio);
447 }
448}
449
Erik Gilling3c92db92010-03-15 19:40:06 -0700450#ifdef CONFIG_DEBUG_FS
451
452#include <linux/debugfs.h>
453#include <linux/seq_file.h>
454
455static int dbg_gpio_show(struct seq_file *s, void *unused)
456{
457 int i;
458 int j;
459
460 for (i = 0; i < 7; i++) {
461 for (j = 0; j < 4; j++) {
462 int gpio = tegra_gpio_compose(i, j, 0);
Colin Cross2e47b8b2010-04-07 12:59:42 -0700463 seq_printf(s,
464 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
465 i, j,
Stephen Warren88d89512011-10-11 16:16:14 -0600466 tegra_gpio_readl(GPIO_CNF(gpio)),
467 tegra_gpio_readl(GPIO_OE(gpio)),
468 tegra_gpio_readl(GPIO_OUT(gpio)),
469 tegra_gpio_readl(GPIO_IN(gpio)),
470 tegra_gpio_readl(GPIO_INT_STA(gpio)),
471 tegra_gpio_readl(GPIO_INT_ENB(gpio)),
472 tegra_gpio_readl(GPIO_INT_LVL(gpio)));
Erik Gilling3c92db92010-03-15 19:40:06 -0700473 }
474 }
475 return 0;
476}
477
478static int dbg_gpio_open(struct inode *inode, struct file *file)
479{
480 return single_open(file, dbg_gpio_show, &inode->i_private);
481}
482
483static const struct file_operations debug_fops = {
484 .open = dbg_gpio_open,
485 .read = seq_read,
486 .llseek = seq_lseek,
487 .release = single_release,
488};
489
490static int __init tegra_gpio_debuginit(void)
491{
492 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
493 NULL, NULL, &debug_fops);
494 return 0;
495}
496late_initcall(tegra_gpio_debuginit);
497#endif