blob: ef6a5111eaa1c702ead5330d78bbe7c716486bcd [file] [log] [blame]
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -03001==================================
2VFIO - "Virtual Function I/O" [1]_
3==================================
4
Alex Williamson4a5b2a22012-07-31 08:16:23 -06005Many modern system now provide DMA and interrupt remapping facilities
6to help ensure I/O devices behave within the boundaries they've been
7allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
8POWER systems with Partitionable Endpoints (PEs) and embedded PowerPC
9systems such as Freescale PAMU. The VFIO driver is an IOMMU/device
10agnostic framework for exposing direct device access to userspace, in
11a secure, IOMMU protected environment. In other words, this allows
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -030012safe [2]_, non-privileged, userspace drivers.
Alex Williamson4a5b2a22012-07-31 08:16:23 -060013
14Why do we want that? Virtual machines often make use of direct device
15access ("device assignment") when configured for the highest possible
16I/O performance. From a device and host perspective, this simply
17turns the VM into a userspace driver, with the benefits of
18significantly reduced latency, higher bandwidth, and direct use of
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -030019bare-metal device drivers [3]_.
Alex Williamson4a5b2a22012-07-31 08:16:23 -060020
21Some applications, particularly in the high performance computing
22field, also benefit from low-overhead, direct device access from
23userspace. Examples include network adapters (often non-TCP/IP based)
24and compute accelerators. Prior to VFIO, these drivers had to either
25go through the full development cycle to become proper upstream
26driver, be maintained out of tree, or make use of the UIO framework,
27which has no notion of IOMMU protection, limited interrupt support,
28and requires root privileges to access things like PCI configuration
29space.
30
31The VFIO driver framework intends to unify these, replacing both the
32KVM PCI specific device assignment code as well as provide a more
33secure, more featureful userspace driver environment than UIO.
34
35Groups, Devices, and IOMMUs
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -030036---------------------------
Alex Williamson4a5b2a22012-07-31 08:16:23 -060037
38Devices are the main target of any I/O driver. Devices typically
39create a programming interface made up of I/O access, interrupts,
40and DMA. Without going into the details of each of these, DMA is
41by far the most critical aspect for maintaining a secure environment
42as allowing a device read-write access to system memory imposes the
43greatest risk to the overall system integrity.
44
45To help mitigate this risk, many modern IOMMUs now incorporate
46isolation properties into what was, in many cases, an interface only
47meant for translation (ie. solving the addressing problems of devices
48with limited address spaces). With this, devices can now be isolated
49from each other and from arbitrary memory access, thus allowing
50things like secure direct assignment of devices into virtual machines.
51
52This isolation is not always at the granularity of a single device
53though. Even when an IOMMU is capable of this, properties of devices,
54interconnects, and IOMMU topologies can each reduce this isolation.
55For instance, an individual device may be part of a larger multi-
56function enclosure. While the IOMMU may be able to distinguish
57between devices within the enclosure, the enclosure may not require
58transactions between devices to reach the IOMMU. Examples of this
59could be anything from a multi-function PCI device with backdoors
60between functions to a non-PCI-ACS (Access Control Services) capable
61bridge allowing redirection without reaching the IOMMU. Topology
62can also play a factor in terms of hiding devices. A PCIe-to-PCI
63bridge masks the devices behind it, making transaction appear as if
64from the bridge itself. Obviously IOMMU design plays a major factor
65as well.
66
67Therefore, while for the most part an IOMMU may have device level
68granularity, any system is susceptible to reduced granularity. The
69IOMMU API therefore supports a notion of IOMMU groups. A group is
70a set of devices which is isolatable from all other devices in the
71system. Groups are therefore the unit of ownership used by VFIO.
72
73While the group is the minimum granularity that must be used to
74ensure secure user access, it's not necessarily the preferred
75granularity. In IOMMUs which make use of page tables, it may be
76possible to share a set of page tables between different groups,
77reducing the overhead both to the platform (reduced TLB thrashing,
78reduced duplicate page tables), and to the user (programming only
79a single set of translations). For this reason, VFIO makes use of
80a container class, which may hold one or more groups. A container
81is created by simply opening the /dev/vfio/vfio character device.
82
83On its own, the container provides little functionality, with all
84but a couple version and extension query interfaces locked away.
85The user needs to add a group into the container for the next level
86of functionality. To do this, the user first needs to identify the
87group associated with the desired device. This can be done using
88the sysfs links described in the example below. By unbinding the
89device from the host driver and binding it to a VFIO driver, a new
90VFIO group will appear for the group as /dev/vfio/$GROUP, where
91$GROUP is the IOMMU group number of which the device is a member.
92If the IOMMU group contains multiple devices, each will need to
93be bound to a VFIO driver before operations on the VFIO group
94are allowed (it's also sufficient to only unbind the device from
95host drivers if a VFIO driver is unavailable; this will make the
96group available, but not that particular device). TBD - interface
97for disabling driver probing/locking a device.
98
99Once the group is ready, it may be added to the container by opening
100the VFIO group character device (/dev/vfio/$GROUP) and using the
101VFIO_GROUP_SET_CONTAINER ioctl, passing the file descriptor of the
102previously opened container file. If desired and if the IOMMU driver
103supports sharing the IOMMU context between groups, multiple groups may
104be set to the same container. If a group fails to set to a container
105with existing groups, a new empty container will need to be used
106instead.
107
108With a group (or groups) attached to a container, the remaining
109ioctls become available, enabling access to the VFIO IOMMU interfaces.
110Additionally, it now becomes possible to get file descriptors for each
111device within a group using an ioctl on the VFIO group file descriptor.
112
113The VFIO device API includes ioctls for describing the device, the I/O
114regions and their read/write/mmap offsets on the device descriptor, as
115well as mechanisms for describing and registering interrupt
116notifications.
117
118VFIO Usage Example
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300119------------------
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600120
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300121Assume user wants to access PCI device 0000:06:0d.0::
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600122
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300123 $ readlink /sys/bus/pci/devices/0000:06:0d.0/iommu_group
124 ../../../../kernel/iommu_groups/26
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600125
126This device is therefore in IOMMU group 26. This device is on the
127pci bus, therefore the user will make use of vfio-pci to manage the
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300128group::
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600129
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300130 # modprobe vfio-pci
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600131
132Binding this device to the vfio-pci driver creates the VFIO group
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300133character devices for this group::
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600134
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300135 $ lspci -n -s 0000:06:0d.0
136 06:0d.0 0401: 1102:0002 (rev 08)
137 # echo 0000:06:0d.0 > /sys/bus/pci/devices/0000:06:0d.0/driver/unbind
138 # echo 1102 0002 > /sys/bus/pci/drivers/vfio-pci/new_id
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600139
140Now we need to look at what other devices are in the group to free
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300141it for use by VFIO::
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600142
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300143 $ ls -l /sys/bus/pci/devices/0000:06:0d.0/iommu_group/devices
144 total 0
145 lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:00:1e.0 ->
146 ../../../../devices/pci0000:00/0000:00:1e.0
147 lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:06:0d.0 ->
148 ../../../../devices/pci0000:00/0000:00:1e.0/0000:06:0d.0
149 lrwxrwxrwx. 1 root root 0 Apr 23 16:13 0000:06:0d.1 ->
150 ../../../../devices/pci0000:00/0000:00:1e.0/0000:06:0d.1
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600151
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300152This device is behind a PCIe-to-PCI bridge [4]_, therefore we also
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600153need to add device 0000:06:0d.1 to the group following the same
154procedure as above. Device 0000:00:1e.0 is a bridge that does
155not currently have a host driver, therefore it's not required to
156bind this device to the vfio-pci driver (vfio-pci does not currently
157support PCI bridges).
158
159The final step is to provide the user with access to the group if
160unprivileged operation is desired (note that /dev/vfio/vfio provides
161no capabilities on its own and is therefore expected to be set to
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300162mode 0666 by the system)::
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600163
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300164 # chown user:user /dev/vfio/26
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600165
166The user now has full access to all the devices and the iommu for this
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300167group and can access them as follows::
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600168
169 int container, group, device, i;
170 struct vfio_group_status group_status =
171 { .argsz = sizeof(group_status) };
Zi Shen Limdac09b52013-09-05 16:36:21 -0600172 struct vfio_iommu_type1_info iommu_info = { .argsz = sizeof(iommu_info) };
173 struct vfio_iommu_type1_dma_map dma_map = { .argsz = sizeof(dma_map) };
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600174 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
175
176 /* Create a new container */
Alexey Kardashevskiyb0e59b82013-06-21 09:43:21 -0600177 container = open("/dev/vfio/vfio", O_RDWR);
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600178
179 if (ioctl(container, VFIO_GET_API_VERSION) != VFIO_API_VERSION)
180 /* Unknown API version */
181
Alexey Kardashevskiyb0e59b82013-06-21 09:43:21 -0600182 if (!ioctl(container, VFIO_CHECK_EXTENSION, VFIO_TYPE1_IOMMU))
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600183 /* Doesn't support the IOMMU driver we want. */
184
185 /* Open the group */
186 group = open("/dev/vfio/26", O_RDWR);
187
188 /* Test the group is viable and available */
189 ioctl(group, VFIO_GROUP_GET_STATUS, &group_status);
190
191 if (!(group_status.flags & VFIO_GROUP_FLAGS_VIABLE))
192 /* Group is not viable (ie, not all devices bound for vfio) */
193
194 /* Add the group to the container */
195 ioctl(group, VFIO_GROUP_SET_CONTAINER, &container);
196
197 /* Enable the IOMMU model we want */
Zi Shen Limdac09b52013-09-05 16:36:21 -0600198 ioctl(container, VFIO_SET_IOMMU, VFIO_TYPE1_IOMMU);
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600199
200 /* Get addition IOMMU info */
201 ioctl(container, VFIO_IOMMU_GET_INFO, &iommu_info);
202
203 /* Allocate some space and setup a DMA mapping */
204 dma_map.vaddr = mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
205 MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);
206 dma_map.size = 1024 * 1024;
207 dma_map.iova = 0; /* 1MB starting at 0x0 from device view */
208 dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE;
209
210 ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map);
211
212 /* Get a file descriptor for the device */
213 device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0");
214
215 /* Test and setup the device */
216 ioctl(device, VFIO_DEVICE_GET_INFO, &device_info);
217
218 for (i = 0; i < device_info.num_regions; i++) {
219 struct vfio_region_info reg = { .argsz = sizeof(reg) };
220
221 reg.index = i;
222
223 ioctl(device, VFIO_DEVICE_GET_REGION_INFO, &reg);
224
225 /* Setup mappings... read/write offsets, mmaps
226 * For PCI devices, config space is a region */
227 }
228
229 for (i = 0; i < device_info.num_irqs; i++) {
230 struct vfio_irq_info irq = { .argsz = sizeof(irq) };
231
232 irq.index = i;
233
Zi Shen Limdac09b52013-09-05 16:36:21 -0600234 ioctl(device, VFIO_DEVICE_GET_IRQ_INFO, &irq);
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600235
236 /* Setup IRQs... eventfds, VFIO_DEVICE_SET_IRQS */
237 }
238
239 /* Gratuitous device reset and go... */
240 ioctl(device, VFIO_DEVICE_RESET);
241
242VFIO User API
243-------------------------------------------------------------------------------
244
245Please see include/linux/vfio.h for complete API documentation.
246
247VFIO bus driver API
248-------------------------------------------------------------------------------
249
250VFIO bus drivers, such as vfio-pci make use of only a few interfaces
251into VFIO core. When devices are bound and unbound to the driver,
252the driver should call vfio_add_group_dev() and vfio_del_group_dev()
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300253respectively::
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600254
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300255 extern int vfio_add_group_dev(struct iommu_group *iommu_group,
256 struct device *dev,
257 const struct vfio_device_ops *ops,
258 void *device_data);
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600259
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300260 extern void *vfio_del_group_dev(struct device *dev);
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600261
262vfio_add_group_dev() indicates to the core to begin tracking the
263specified iommu_group and register the specified dev as owned by
264a VFIO bus driver. The driver provides an ops structure for callbacks
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300265similar to a file operations structure::
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600266
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300267 struct vfio_device_ops {
268 int (*open)(void *device_data);
269 void (*release)(void *device_data);
270 ssize_t (*read)(void *device_data, char __user *buf,
271 size_t count, loff_t *ppos);
272 ssize_t (*write)(void *device_data, const char __user *buf,
273 size_t size, loff_t *ppos);
274 long (*ioctl)(void *device_data, unsigned int cmd,
275 unsigned long arg);
276 int (*mmap)(void *device_data, struct vm_area_struct *vma);
277 };
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600278
279Each function is passed the device_data that was originally registered
280in the vfio_add_group_dev() call above. This allows the bus driver
281an easy place to store its opaque, private data. The open/release
282callbacks are issued when a new file descriptor is created for a
283device (via VFIO_GROUP_GET_DEVICE_FD). The ioctl interface provides
284a direct pass through for VFIO_DEVICE_* ioctls. The read/write/mmap
285interfaces implement the device region access defined by the device's
286own VFIO_DEVICE_GET_REGION_INFO ioctl.
287
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000288
289PPC64 sPAPR implementation note
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300290-------------------------------
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000291
292This implementation has some specifics:
293
Alexey Kardashevskiy2157e7b2015-06-05 16:35:25 +10002941) On older systems (POWER7 with P5IOC2/IODA1) only one IOMMU group per
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300295 container is supported as an IOMMU table is allocated at the boot time,
296 one table per a IOMMU group which is a Partitionable Endpoint (PE)
297 (PE is often a PCI domain but not always).
298
299 Newer systems (POWER8 with IODA2) have improved hardware design which allows
300 to remove this limitation and have multiple IOMMU groups per a VFIO
301 container.
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000302
3032) The hardware supports so called DMA windows - the PCI address range
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300304 within which DMA transfer is allowed, any attempt to access address space
305 out of the window leads to the whole PE isolation.
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000306
3073) PPC64 guests are paravirtualized but not fully emulated. There is an API
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300308 to map/unmap pages for DMA, and it normally maps 1..32 pages per call and
309 currently there is no way to reduce the number of calls. In order to make
310 things faster, the map/unmap handling has been implemented in real mode
311 which provides an excellent performance which has limitations such as
312 inability to do locked pages accounting in real time.
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000313
Gavin Shan1b69be52014-06-10 11:41:57 +10003144) According to sPAPR specification, A Partitionable Endpoint (PE) is an I/O
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300315 subtree that can be treated as a unit for the purposes of partitioning and
316 error recovery. A PE may be a single or multi-function IOA (IO Adapter), a
317 function of a multi-function IOA, or multiple IOAs (possibly including
318 switch and bridge structures above the multiple IOAs). PPC64 guests detect
319 PCI errors and recover from them via EEH RTAS services, which works on the
320 basis of additional ioctl commands.
Gavin Shan1b69be52014-06-10 11:41:57 +1000321
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300322 So 4 additional ioctls have been added:
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000323
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300324 VFIO_IOMMU_SPAPR_TCE_GET_INFO
325 returns the size and the start of the DMA window on the PCI bus.
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000326
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300327 VFIO_IOMMU_ENABLE
328 enables the container. The locked pages accounting
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000329 is done at this point. This lets user first to know what
330 the DMA window is and adjust rlimit before doing any real job.
331
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300332 VFIO_IOMMU_DISABLE
333 disables the container.
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000334
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300335 VFIO_EEH_PE_OP
336 provides an API for EEH setup, error detection and recovery.
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000337
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300338 The code flow from the example above should be slightly changed::
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000339
Gavin Shan1b69be52014-06-10 11:41:57 +1000340 struct vfio_eeh_pe_op pe_op = { .argsz = sizeof(pe_op), .flags = 0 };
341
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000342 .....
343 /* Add the group to the container */
344 ioctl(group, VFIO_GROUP_SET_CONTAINER, &container);
345
346 /* Enable the IOMMU model we want */
347 ioctl(container, VFIO_SET_IOMMU, VFIO_SPAPR_TCE_IOMMU)
348
349 /* Get addition sPAPR IOMMU info */
350 vfio_iommu_spapr_tce_info spapr_iommu_info;
351 ioctl(container, VFIO_IOMMU_SPAPR_TCE_GET_INFO, &spapr_iommu_info);
352
353 if (ioctl(container, VFIO_IOMMU_ENABLE))
354 /* Cannot enable container, may be low rlimit */
355
356 /* Allocate some space and setup a DMA mapping */
357 dma_map.vaddr = mmap(0, 1024 * 1024, PROT_READ | PROT_WRITE,
358 MAP_PRIVATE | MAP_ANONYMOUS, 0, 0);
359
360 dma_map.size = 1024 * 1024;
361 dma_map.iova = 0; /* 1MB starting at 0x0 from device view */
362 dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE;
363
364 /* Check here is .iova/.size are within DMA window from spapr_iommu_info */
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000365 ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map);
Gavin Shan1b69be52014-06-10 11:41:57 +1000366
367 /* Get a file descriptor for the device */
368 device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0");
369
370 ....
371
372 /* Gratuitous device reset and go... */
373 ioctl(device, VFIO_DEVICE_RESET);
374
375 /* Make sure EEH is supported */
376 ioctl(container, VFIO_CHECK_EXTENSION, VFIO_EEH);
377
378 /* Enable the EEH functionality on the device */
379 pe_op.op = VFIO_EEH_PE_ENABLE;
380 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
381
382 /* You're suggested to create additional data struct to represent
383 * PE, and put child devices belonging to same IOMMU group to the
384 * PE instance for later reference.
385 */
386
387 /* Check the PE's state and make sure it's in functional state */
388 pe_op.op = VFIO_EEH_PE_GET_STATE;
389 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
390
391 /* Save device state using pci_save_state().
392 * EEH should be enabled on the specified device.
393 */
394
395 ....
396
Gavin Shan68cbbc32015-03-26 16:42:09 +1100397 /* Inject EEH error, which is expected to be caused by 32-bits
398 * config load.
399 */
400 pe_op.op = VFIO_EEH_PE_INJECT_ERR;
401 pe_op.err.type = EEH_ERR_TYPE_32;
402 pe_op.err.func = EEH_ERR_FUNC_LD_CFG_ADDR;
403 pe_op.err.addr = 0ul;
404 pe_op.err.mask = 0ul;
405 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
406
407 ....
408
Gavin Shan1b69be52014-06-10 11:41:57 +1000409 /* When 0xFF's returned from reading PCI config space or IO BARs
410 * of the PCI device. Check the PE's state to see if that has been
411 * frozen.
412 */
413 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
414
415 /* Waiting for pending PCI transactions to be completed and don't
416 * produce any more PCI traffic from/to the affected PE until
417 * recovery is finished.
418 */
419
420 /* Enable IO for the affected PE and collect logs. Usually, the
421 * standard part of PCI config space, AER registers are dumped
422 * as logs for further analysis.
423 */
424 pe_op.op = VFIO_EEH_PE_UNFREEZE_IO;
425 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
426
427 /*
428 * Issue PE reset: hot or fundamental reset. Usually, hot reset
429 * is enough. However, the firmware of some PCI adapters would
430 * require fundamental reset.
431 */
432 pe_op.op = VFIO_EEH_PE_RESET_HOT;
433 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
434 pe_op.op = VFIO_EEH_PE_RESET_DEACTIVATE;
435 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
436
437 /* Configure the PCI bridges for the affected PE */
438 pe_op.op = VFIO_EEH_PE_CONFIGURE;
439 ioctl(container, VFIO_EEH_PE_OP, &pe_op);
440
441 /* Restored state we saved at initialization time. pci_restore_state()
442 * is good enough as an example.
443 */
444
445 /* Hopefully, error is recovered successfully. Now, you can resume to
446 * start PCI traffic to/from the affected PE.
447 */
448
449 ....
Alexey Kardashevskiy5ffd2292013-05-21 13:33:10 +1000450
Alexey Kardashevskiy2157e7b2015-06-05 16:35:25 +10004515) There is v2 of SPAPR TCE IOMMU. It deprecates VFIO_IOMMU_ENABLE/
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300452 VFIO_IOMMU_DISABLE and implements 2 new ioctls:
453 VFIO_IOMMU_SPAPR_REGISTER_MEMORY and VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY
454 (which are unsupported in v1 IOMMU).
Alexey Kardashevskiy2157e7b2015-06-05 16:35:25 +1000455
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300456 PPC64 paravirtualized guests generate a lot of map/unmap requests,
457 and the handling of those includes pinning/unpinning pages and updating
458 mm::locked_vm counter to make sure we do not exceed the rlimit.
459 The v2 IOMMU splits accounting and pinning into separate operations:
Alexey Kardashevskiy2157e7b2015-06-05 16:35:25 +1000460
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300461 - VFIO_IOMMU_SPAPR_REGISTER_MEMORY/VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY ioctls
462 receive a user space address and size of the block to be pinned.
463 Bisecting is not supported and VFIO_IOMMU_UNREGISTER_MEMORY is expected to
464 be called with the exact address and size used for registering
465 the memory block. The userspace is not expected to call these often.
466 The ranges are stored in a linked list in a VFIO container.
Alexey Kardashevskiy2157e7b2015-06-05 16:35:25 +1000467
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300468 - VFIO_IOMMU_MAP_DMA/VFIO_IOMMU_UNMAP_DMA ioctls only update the actual
469 IOMMU table and do not do pinning; instead these check that the userspace
470 address is from pre-registered range.
Alexey Kardashevskiy2157e7b2015-06-05 16:35:25 +1000471
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300472 This separation helps in optimizing DMA for guests.
Alexey Kardashevskiy2157e7b2015-06-05 16:35:25 +1000473
Alexey Kardashevskiye633bc82015-06-05 16:35:26 +10004746) sPAPR specification allows guests to have an additional DMA window(s) on
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300475 a PCI bus with a variable page size. Two ioctls have been added to support
476 this: VFIO_IOMMU_SPAPR_TCE_CREATE and VFIO_IOMMU_SPAPR_TCE_REMOVE.
477 The platform has to support the functionality or error will be returned to
478 the userspace. The existing hardware supports up to 2 DMA windows, one is
479 2GB long, uses 4K pages and called "default 32bit window"; the other can
480 be as big as entire RAM, use different page size, it is optional - guests
481 create those in run-time if the guest driver supports 64bit DMA.
Alexey Kardashevskiye633bc82015-06-05 16:35:26 +1000482
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300483 VFIO_IOMMU_SPAPR_TCE_CREATE receives a page shift, a DMA window size and
484 a number of TCE table levels (if a TCE table is going to be big enough and
485 the kernel may not be able to allocate enough of physically contiguous
486 memory). It creates a new window in the available slot and returns the bus
487 address where the new window starts. Due to hardware limitation, the user
488 space cannot choose the location of DMA windows.
Alexey Kardashevskiye633bc82015-06-05 16:35:26 +1000489
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300490 VFIO_IOMMU_SPAPR_TCE_REMOVE receives the bus start address of the window
491 and removes it.
Alexey Kardashevskiye633bc82015-06-05 16:35:26 +1000492
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600493-------------------------------------------------------------------------------
494
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300495.. [1] VFIO was originally an acronym for "Virtual Function I/O" in its
496 initial implementation by Tom Lyon while as Cisco. We've since
497 outgrown the acronym, but it's catchy.
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600498
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300499.. [2] "safe" also depends upon a device being "well behaved". It's
500 possible for multi-function devices to have backdoors between
501 functions and even for single function devices to have alternative
502 access to things like PCI config space through MMIO registers. To
503 guard against the former we can include additional precautions in the
504 IOMMU driver to group multi-function PCI devices together
505 (iommu=group_mf). The latter we can't prevent, but the IOMMU should
506 still provide isolation. For PCI, SR-IOV Virtual Functions are the
507 best indicator of "well behaved", as these are designed for
508 virtualization usage models.
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600509
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300510.. [3] As always there are trade-offs to virtual machine device
511 assignment that are beyond the scope of VFIO. It's expected that
512 future IOMMU technologies will reduce some, but maybe not all, of
513 these trade-offs.
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600514
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300515.. [4] In this case the device is below a PCI bridge, so transactions
516 from either function of the device are indistinguishable to the iommu::
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600517
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300518 -[0000:00]-+-1e.0-[06]--+-0d.0
519 \-0d.1
Alex Williamson4a5b2a22012-07-31 08:16:23 -0600520
Mauro Carvalho Chehabc6f4d412017-05-17 09:38:00 -0300521 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 90)