| Qualcomm Technologies, Inc. OSM Bindings |
| |
| Operating State Manager (OSM) is a hardware engine used by some Qualcomm |
| Technologies, Inc. (QTI) SoCs to manage frequency and voltage scaling |
| in hardware. OSM is capable of controlling frequency and voltage requests |
| for multiple clusters via the existence of multiple OSM domains. |
| |
| Properties: |
| - compatible |
| Usage: required |
| Value type: <string> |
| Definition: must be "qcom,clk-cpu-osm" or "qcom,clk-cpu-osm-v2". |
| |
| - reg |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Addresses and sizes for the memory of the OSM controller, |
| cluster PLL management, and APCS common register regions. |
| Optionally, the address of the efuse registers used to |
| determine the pwrcl or perfcl speed-bins and/or the ACD |
| register space to initialize prior to enabling OSM. |
| |
| - reg-names |
| Usage: required |
| Value type: <stringlist> |
| Definition: Address names. Must be "osm_l3_base", "osm_pwrcl_base", |
| "osm_perfcl_base", "l3_pll", "pwrcl_pll", "perfcl_pll", |
| "l3_sequencer", "pwrcl_sequencer", or "perfcl_sequencer". |
| Optionally, "l3_efuse", "pwrcl_efuse", "perfcl_efuse", |
| "pwrcl_acd", "perfcl_acd", "l3_acd". |
| Must be specified in the same order as the corresponding |
| addresses are specified in the reg property. |
| |
| - vdd-l3-supply |
| Usage: required |
| Value type: <phandle> |
| Definition: phandle of the underlying regulator device that manages |
| the voltage supply of the L3 cluster. |
| |
| - vdd-pwrcl-supply |
| Usage: required |
| Value type: <phandle> |
| Definition: phandle of the underlying regulator device that manages |
| the voltage supply of the Power cluster. |
| |
| - vdd-perfcl-supply |
| Usage: required |
| Value type: <phandle> |
| Definition: phandle of the underlying regulator device that manages |
| the voltage supply of the Performance cluster. |
| |
| - interrupts |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: OSM interrupt specifier. |
| |
| - interrupt-names |
| Usage: required |
| Value type: <stringlist> |
| Definition: Interrupt names. this list must match up 1-to-1 with the |
| interrupts specified in the 'interrupts' property. |
| "pwrcl-irq" and "perfcl-irq" must be specified. |
| |
| - qcom,l3-speedbinX-v0 |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the frequency in Hertz, frequency, |
| PLL override data, ACC level, and virtual corner used |
| by the OSM hardware for each supported DCVS setpoint |
| of the L3 cluster. |
| |
| - qcom,pwrcl-speedbinX-v0 |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the frequency in Hertz, frequency, |
| PLL override data, ACC level, and virtual corner used |
| by the OSM hardware for each supported DCVS setpoint |
| of the Power cluster. |
| |
| - qcom,perfcl-speedbinX-v0 |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the frequency in Hertz, frequency, |
| PLL override data, ACC level and virtual corner used |
| by the OSM hardware for each supported DCVS setpoint |
| of the Performance cluster. |
| |
| - qcom,osm-no-tz |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates that there is no programming |
| of the OSM hardware performed by the secure world. |
| |
| - qcom,osm-pll-setup |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates that the PLL setup sequence |
| must be executed for each clock domain managed by the OSM |
| controller. |
| |
| - qcom,up-timer |
| Usage: optional |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the DCVS up timer value in nanoseconds |
| for each of the three clock domains managed by the OSM |
| controller. |
| |
| - qcom,down-timer |
| Usage: optional |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the DCVS down timer value in nanoseconds |
| for each of the three clock domains managed by the OSM |
| controller. |
| |
| - qcom,pc-override-index |
| Usage: optional |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the OSM performance index to be used |
| when each cluster enters certain low power modes. |
| |
| - qcom,set-ret-inactive |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if domains in retention must |
| be treated as inactive. |
| |
| - qcom,enable-llm-freq-vote |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if Limits hardware frequency |
| votes must be honored by OSM. |
| |
| - qcom,llm-freq-up-timer |
| Usage: optional |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the LLM frequency up timer value in |
| nanoseconds for each of the three clock domains managed by |
| the OSM controller. |
| |
| - qcom,llm-freq-down-timer |
| Usage: optional |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the LLM frequency down timer value in |
| nanoseconds for each of the three clock domains managed by |
| the OSM controller. |
| |
| - qcom,enable-llm-volt-vote |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if Limits hardware voltage |
| votes must be honored by OSM. |
| |
| - qcom,llm-volt-up-timer |
| Usage: optional |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the LLM voltage up timer value in |
| nanoseconds for each of the three clock domains managed by |
| the OSM controller. |
| |
| - qcom,llm-volt-down-timer |
| Usage: optional |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the LLM voltage down timer value in |
| nanoseconds for each of the three clock domains managed by |
| the OSM controller. |
| |
| - qcom,cc-reads |
| Usage: optional |
| Value type: <integer> |
| Definition: Defines the number of times the cycle counters must be |
| read to determine the performance level of each clock |
| domain. |
| |
| - qcom,l-val-base |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the register addresses of the L_VAL |
| control register for each of the three clock domains |
| managed by the OSM controller. |
| |
| - qcom,apcs-pll-user-ctl |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the register addresses of the PLL |
| user control register for each of the three clock domains |
| managed by the OSM controller. |
| |
| - qcom,perfcl-apcs-apm-threshold-voltage |
| Usage: required |
| Value type: <u32> |
| Definition: Specifies the APM threshold voltage in microvolts. If the |
| VDD_APCC supply voltage is above or at this level, then the |
| APM is switched to use VDD_APCC. If VDD_APCC is below |
| this level, then the APM is switched to use VDD_MX. |
| |
| - qcom,apm-mode-ctl |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the register addresses of the APM |
| control register for each of the two clusters managed |
| by the OSM controller. |
| |
| - qcom,apm-status-ctrl |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the register addresses of the APM |
| controller status register for each of the three clock |
| domains managed by the OSM controller. |
| |
| - qcom,perfcl-isense-addr |
| Usage: required |
| Value type: <u32> |
| Definition: Contains the ISENSE register address. |
| |
| - qcom,l3-mem-acc-addr |
| Usage: required if qcom,osm-no-tz is specified |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the addresses of the mem-acc |
| configuration registers for the L3 cluster. |
| The array must contain exactly three elements. |
| |
| - qcom,pwrcl-mem-acc-addr |
| Usage: required if qcom,osm-no-tz is specified |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the addresses of the mem-acc |
| configuration registers for the Power cluster. |
| The array must contain exactly three elements. |
| |
| - qcom,perfcl-mem-acc-addr |
| Usage: required if qcom,osm-no-tz is specified |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the addresses of the mem-acc |
| configuration registers for the Performance cluster. |
| The array must contain exactly three elements. |
| |
| - qcom,perfcl-apcs-mem-acc-threshold-voltage |
| Usage: optional |
| Value type: <u32> |
| Definition: Specifies the highest MEM ACC threshold voltage in |
| microvolts for the Performance cluster. This voltage is |
| used to determine which MEM ACC setting is used for the |
| highest frequencies. If specified, the voltage must match |
| the MEM ACC threshold voltage specified for the |
| corresponding CPRh device. |
| |
| - qcom,l3-memacc-level-vc-binX |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the NOM and TURBO VCs for the L3 clock |
| on that BIN part. |
| The array must contain exactly two elements. |
| |
| - qcom,pwrcl-memacc-level-vc-binX |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the NOM and TURBO VCs for the Power |
| cluster clock on that BIN part. |
| The array must contain exactly two elements. |
| |
| - qcom,perfcl-memacc-level-vc-binX |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the NOM and TURBO VCs for the |
| Performance cluster clock on that BIN part. |
| The array must contain exactly two elements. |
| |
| - qcom,apcs-cbc-addr |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the addresses of the APCS_CBC_ADDR |
| registers for all three clock domains. |
| |
| - qcom,apcs-ramp-ctl-addr |
| Usage: required |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the addresses of the APCS_RAMP_CTL_ADDR |
| registers for all three clock domains. |
| |
| - qcom,red-fsm-en |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if the reduction FSM |
| should be enabled. |
| |
| - qcom,boost-fsm-en |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if the boost FSM should |
| be enabled. |
| |
| - qcom,safe-fsm-en |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if the safe FSM should |
| be enabled. |
| |
| - qcom,ps-fsm-en |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if the PS FSM should be |
| enabled. |
| |
| - qcom,droop-fsm-en |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if the droop FSM should |
| be enabled. |
| |
| - qcom,set-c3-active |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if the cores in C3 are to |
| be treated as active for core count calculations. |
| |
| - qcom,set-c2-active |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if the cores in C2 are to |
| be treated as active for core count calculations. |
| |
| - qcom,disable-cc-dvcs |
| Usage: optional |
| Value type: <empty> |
| Definition: Boolean flag which indicates if core count based DCVS is |
| to be disabled. |
| |
| - qcom,apcs-pll-min-freq |
| Usage: required |
| Value type: <u32> |
| Definition: Contains the addresses of the RAILx_CLKDOMy_PLL_MIN_FREQ |
| registers for the three clock domains. |
| |
| - qcom,acdtd-val |
| Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are |
| specified |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the values to program to the ACD |
| Tunable-Length Delay register for the L3, power and |
| performance clusters. |
| |
| - qcom,acdcr-val |
| Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are |
| specified |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the values for the ACD control register |
| for the L3, power and performance clusters. |
| |
| - qcom,acdsscr-val |
| Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are |
| specified |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the values for the ACD Soft Start Control |
| register for the L3, power and performance clusters. |
| |
| - qcom,acdextint0-val |
| Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are |
| specified |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the initial values for the ACD |
| external interface configuration register for the L3, power |
| and performance clusters. |
| |
| - qcom,acdextint1-val |
| Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are |
| specified |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the final values for the ACD |
| external interface configuration register for the L3, power |
| and performance clusters. |
| |
| - qcom,acdautoxfer-val |
| Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are |
| specified |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the values for the ACD auto transfer |
| control register for the L3, power and performance clusters. |
| |
| - qcom,acdavg-init |
| Usage: optional if pwrcl_acd, perfcl_acd or l3_acd registers are |
| specified |
| Value type: <prop-encoded-array> |
| Definition: Array which defines if the AVG feature for ACD should be |
| initialized for the L3, power and performance clusters. |
| Valid values are 0 or 1. |
| |
| - qcom,acdavgcfg0-val |
| Usage: required if qcom,acdavg-init is true for an ACD clock domain |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the values for the ACD AVG CFG0 |
| registers for the L3, power and performance clusters. |
| |
| - qcom,acdavgcfg1-val |
| Usage: required if qcom,acdavg-init is true for an ACD clock domain |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the values for the ACD AVG CFG1 |
| registers for the L3, power and performance clusters. |
| |
| - qcom,acdavgcfg2-val |
| Usage: required if qcom,acdavg-init is true for an ACD clock domain |
| Value type: <prop-encoded-array> |
| Definition: Array which defines the values for the ACD AVG CFG2 |
| registers for the L3, power and performance clusters. |
| |
| - clock-names |
| Usage: required |
| Value type: <string> |
| Definition: Must be "aux_clk". |
| |
| - clocks |
| Usage: required |
| Value type: <phandle> |
| Definition: Phandle to the aux clock device. |
| |
| Example: |
| clock_cpucc: qcom,cpucc@0x17d41000 { |
| compatible = "qcom,clk-cpu-osm"; |
| reg = <0x17d41000 0x1400>, |
| <0x17d43000 0x1400>, |
| <0x17d45800 0x1400>, |
| <0x178d0000 0x1000>, |
| <0x178c0000 0x1000>, |
| <0x178b0000 0x1000>, |
| <0x17d42400 0x0c00>, |
| <0x17d44400 0x0c00>, |
| <0x17d46c00 0x0c00>, |
| <0x17930000 0x10000>, |
| <0x17920000 0x10000>, |
| <0x17910000 0x10000>; |
| reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base", |
| "l3_pll", "pwrcl_pll", "perfcl_pll", |
| "l3_sequencer", "pwrcl_sequencer", |
| "perfcl_sequencer", "l3_acd", "pwrcl_acd", |
| "perfcl_acd"; |
| |
| /* ACD configurations for L3, Silver, and Gold clusters */ |
| qcom,acdtd-val = <0x0000b411 0x0000b411 0x0000b411>; |
| qcom,acdcr-val = <0x002c5ffd 0x002c5ffd 0x002c5ffd>; |
| qcom,acdsscr-val = <0x00000901 0x00000901 0x00000901>; |
| qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8 0x2cf9ae8>; |
| qcom,acdextint1-val = <0x2cf9afe 0x2cf9afe 0x2cf9afe>; |
| qcom,acdautoxfer-val = <0x00000015 0x00000015 0x00000015>; |
| qcom,acdavgcfg2-val = <0x0 0x56a38822 0x56a38822>; |
| qcom,acdavgcfg1-val = <0x0 0x27104e20 0x27104e20>; |
| qcom,acdavgcfg0-val = <0x0 0xa08007a1 0xa08007a1>; |
| qcom,acdavg-init = <0 1 1>; |
| |
| vdd-l3-supply = <&apc0_l3_vreg>; |
| vdd-pwrcl-supply = <&apc0_pwrcl_vreg>; |
| vdd-perfcl-supply = <&apc1_perfcl_vreg>; |
| |
| qcom,l3-speedbin0-v0 = |
| < 300000000 0x000c000f 0x00002020 0x1 1 >, |
| < 422400000 0x50140116 0x00002020 0x1 2 >, |
| < 499200000 0x5014021a 0x00002020 0x1 3 >, |
| < 576000000 0x5014031e 0x00002020 0x1 4 >, |
| < 652800000 0x501c0422 0x00002020 0x1 5 >, |
| < 729600000 0x501c0526 0x00002020 0x1 6 >, |
| < 806400000 0x501c062a 0x00002222 0x1 7 >, |
| < 883200000 0x4024072b 0x00002525 0x1 8 >, |
| < 960000000 0x40240832 0x00002828 0x2 9 >; |
| |
| qcom,pwrcl-speedbin0-v0 = |
| < 300000000 0x000c000f 0x00002020 0x1 1 >, |
| < 422400000 0x50140116 0x00002020 0x1 2 >, |
| < 499200000 0x5014021a 0x00002020 0x1 3 >, |
| < 576000000 0x5014031e 0x00002020 0x1 4 >, |
| < 652800000 0x501c0422 0x00002020 0x1 5 >, |
| < 748800000 0x501c0527 0x00002020 0x1 6 >, |
| < 825600000 0x401c062b 0x00002222 0x1 7 >, |
| < 902400000 0x4024072f 0x00002626 0x1 8 >, |
| < 979200000 0x40240833 0x00002929 0x1 9 >, |
| < 1056000000 0x402c0937 0x00002c2c 0x1 10 >, |
| < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >, |
| < 1209600000 0x402c0b3f 0x00003333 0x1 12 >, |
| < 1286400000 0x40340c43 0x00003636 0x1 13 >, |
| < 1363200000 0x40340d47 0x00003939 0x1 14 >, |
| < 1440000000 0x403c0e4b 0x00003c3c 0x1 15 >, |
| < 1516800000 0x403c0f4f 0x00004040 0x2 16 >, |
| < 1593600000 0x403c1053 0x00004343 0x2 17 >; |
| |
| qcom,perfcl-speedbin0-v0 = |
| < 300000000 0x000c000f 0x00002020 0x1 1 >, |
| < 422400000 0x50140116 0x00002020 0x1 2 >, |
| < 499200000 0x5014021a 0x00002020 0x1 3 >, |
| < 576000000 0x5014031e 0x00002020 0x1 4 >, |
| < 652800000 0x501c0422 0x00002020 0x1 5 >, |
| < 729600000 0x501c0526 0x00002020 0x1 6 >, |
| < 806400000 0x501c062a 0x00002222 0x1 7 >, |
| < 883200000 0x4024072b 0x00002525 0x1 8 >, |
| < 960000000 0x40240832 0x00002828 0x1 9 >, |
| < 1036800000 0x40240936 0x00002b2b 0x1 10 >, |
| < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >, |
| < 1190400000 0x402c0b3e 0x00003232 0x1 12 >, |
| < 1267200000 0x40340c42 0x00003535 0x1 13 >, |
| < 1344000000 0x40340d46 0x00003838 0x1 14 >, |
| < 1420800000 0x40340e4a 0x00003b3b 0x1 15 >, |
| < 1497600000 0x403c0f4e 0x00003e3e 0x1 16 >, |
| < 1574400000 0x403c1052 0x00004242 0x2 17 >, |
| < 1651200000 0x403c1156 0x00004545 0x2 18 >, |
| < 1728000000 0x4044125a 0x00004848 0x2 19 >, |
| < 1804800000 0x4044135e 0x00004b4b 0x2 20 >, |
| < 1881600000 0x404c1462 0x00004e4e 0x2 21 >, |
| < 1958400000 0x404c1566 0x00005252 0x3 22 >; |
| |
| qcom,l3-memacc-level-vc-bin0 = <7 63>; |
| qcom,l3-memacc-level-vc-bin1 = <7 9>; |
| qcom,l3-memacc-level-vc-bin2 = <7 9>; |
| |
| qcom,pwrcl-memacc-level-vc-bin0 = <12 63>; |
| qcom,pwrcl-memacc-level-vc-bin1 = <12 17>; |
| qcom,pwrcl-memacc-level-vc-bin2 = <12 17>; |
| |
| qcom,perfcl-memacc-level-vc-bin0 = <12 18>; |
| qcom,perfcl-memacc-level-vc-bin1 = <12 18>; |
| qcom,perfcl-memacc-level-vc-bin2 = <12 18>; |
| |
| qcom,up-timer = |
| <1000 1000 1000>; |
| qcom,down-timer = |
| <100000 100000 100000>; |
| qcom,pc-override-index = |
| <0 0 0>; |
| qcom,set-ret-inactive; |
| qcom,enable-llm-freq-vote; |
| qcom,llm-freq-up-timer = |
| <1000 1000 1000>; |
| qcom,llm-freq-down-timer = |
| <327675 327675 327675>; |
| qcom,enable-llm-volt-vote; |
| qcom,llm-volt-up-timer = |
| <1000 1000 1000>; |
| qcom,llm-volt-down-timer = |
| <327675 327675 327675>; |
| qcom,cc-reads = <10>; |
| qcom,cc-delay = <5>; |
| qcom,cc-factor = <100>; |
| qcom,osm-clk-rate = <100000000>; |
| qcom,xo-clk-rate = <19200000>; |
| |
| qcom,l-val-base = |
| <0x178d0004 0x178c0004 0x178b0004>; |
| qcom,apcs-pll-user-ctl = |
| <0x178d000c 0x178c000c 0x178b000c>; |
| qcom,apcs-pll-min-freq = |
| <0x17d41094 0x17d43094 0x17d45894>; |
| qcom,apm-mode-ctl = |
| <0x0 0x0 0x17d20010>; |
| qcom,apm-status-ctrl = |
| <0x0 0x0 0x17d20000>; |
| qcom,perfcl-isense-addr = <0x17871480>; |
| qcom,l3-mem-acc-addr = <0x17990170 0x17990170 0x17990170>; |
| qcom,pwrcl-mem-acc-addr = <0x17990160 0x17990164 0x17990164>; |
| qcom,perfcl-mem-acc-addr = <0x17990168 0x1799016c 0x1799016c>; |
| qcom,cfg-gfmux-addr =<0x178d0084 0x178c0084 0x178b0084>; |
| qcom,apcs-cbc-addr = <0x178d008c 0x178c008c 0x178b008c>; |
| qcom,apcs-ramp-ctl-addr = <0x17840904 0x17840904 0x17830904>; |
| |
| qcom,perfcl-apcs-apm-threshold-voltage = <800000>; |
| qcom,perfcl-apcs-mem-acc-threshold-voltage = <852000>; |
| qcom,boost-fsm-en; |
| qcom,safe-fsm-en; |
| qcom,ps-fsm-en; |
| qcom,droop-fsm-en; |
| qcom,osm-no-tz; |
| qcom,osm-pll-setup; |
| |
| clock-names = "xo_ao"; |
| clocks = <&clock_rpmh RPMH_CXO_CLK_A>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |