| commit | 0689aad70d719842c3a07f5782b7d35bb12efe9d | [log] [tgz] |
|---|---|---|
| author | Xia Yang <xiay@nvidia.com> | Thu Feb 25 17:59:08 2016 +0900 |
| committer | Ben Skeggs <bskeggs@redhat.com> | Mon Mar 14 10:13:30 2016 +1000 |
| tree | 74ae1433a9d3923472ba49d47a57a31c0a352de4 | |
| parent | 9d0394c6bed5b4b78167cc0eea294754a9cb2bbc [diff] |
drm/nouveau/fifo/gk104: fix chid bit mask Fix the channel id bit mask in FIFO schedule timeout error handling. FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000. FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff. Signed-off-by: Xia Yang <xiay@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>