| /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include "skeleton64.dtsi" |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,camcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,gpucc-sdm845.h> |
| #include <dt-bindings/clock/qcom,videocc-sdm845.h> |
| #include <dt-bindings/clock/qcom,cpucc-sdm845.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/regulator/qcom,rpmh-regulator.h> |
| |
| / { |
| model = "Qualcomm Technologies, Inc. SDM670"; |
| compatible = "qcom,sdm670"; |
| qcom,msm-id = <336 0x0>; |
| interrupt-parent = <&intc>; |
| |
| aliases { |
| ufshc1 = &ufshc_mem; /* Embedded UFS slot */ |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_0>; |
| L2_0: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| L3_0: l3-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x100000>; |
| cache-level = <3>; |
| }; |
| }; |
| L1_I_0: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_0: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_100>; |
| L2_100: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_100: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_100: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_200>; |
| L2_200: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_200: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_200: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_300>; |
| L2_300: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_300: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_300: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_400>; |
| L2_400: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_400: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_400: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_500>; |
| L2_500: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_500: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_500: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x600>; |
| enable-method = "psci"; |
| efficiency = <1740>; |
| cache-size = <0x10000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_600>; |
| L2_600: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x40000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_600: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x12000>; |
| }; |
| L1_D_600: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x12000>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x700>; |
| enable-method = "psci"; |
| efficiency = <1740>; |
| cache-size = <0x10000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_700>; |
| L2_700: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x40000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_700: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x12000>; |
| }; |
| L1_D_700: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x12000>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| |
| core4 { |
| cpu = <&CPU4>; |
| }; |
| |
| core5 { |
| cpu = <&CPU5>; |
| }; |
| }; |
| cluster1 { |
| core0 { |
| cpu = <&CPU6>; |
| }; |
| |
| core1 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| soc: soc { }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| removed_regions: removed_regions@85700000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x85700000 0 0x3800000>; |
| }; |
| |
| pil_camera_mem: camera_region@8ab00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x8ab00000 0 0x500000>; |
| }; |
| |
| pil_modem_mem: modem_region@8b000000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x8b000000 0 0x7e00000>; |
| }; |
| |
| pil_video_mem: pil_video_region@92e00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x92e00000 0 0x500000>; |
| }; |
| |
| pil_cdsp_mem: cdsp_regions@93300000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x93300000 0 0x600000>; |
| }; |
| |
| pil_mba_mem: pil_mba_region@0x93900000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x93900000 0 0x200000>; |
| }; |
| |
| pil_adsp_mem: pil_adsp_region@93b00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x93b00000 0 0x1e00000>; |
| }; |
| |
| pil_ipa_fw_mem: pil_ipa_fw_region@95900000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x95900000 0 0x10000>; |
| }; |
| |
| pil_ipa_gsi_mem: pil_ipa_gsi_region@95910000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x95910000 0 0x5000>; |
| }; |
| |
| pil_gpu_mem: pil_gpu_region@95915000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x95915000 0 0x1000>; |
| }; |
| |
| adsp_mem: adsp_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0xc00000>; |
| }; |
| |
| qseecom_mem: qseecom_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0x1400000>; |
| }; |
| |
| sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0x800000>; |
| }; |
| |
| secure_display_memory: secure_display_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0x5c00000>; |
| }; |
| |
| /* global autoconfigured region for contiguous allocations */ |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0x2000000>; |
| linux,cma-default; |
| }; |
| }; |
| }; |
| |
| #include "sdm670-ion.dtsi" |
| |
| #include "sdm670-qupv3.dtsi" |
| |
| &soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x20000>; |
| reg = <0x17a00000 0x10000>, /* GICD */ |
| <0x17a60000 0x100000>; /* GICR * 8 */ |
| interrupts = <1 9 4>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 1 0xf08>, |
| <1 2 0xf08>, |
| <1 3 0xf08>, |
| <1 0 0xf08>; |
| clock-frequency = <19200000>; |
| }; |
| |
| qcom,sps { |
| compatible = "qcom,msm_sps_4k"; |
| qcom,pipe-attr-ee; |
| }; |
| |
| timer@0x17c90000{ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x17c90000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@0x17ca0000 { |
| frame-number = <0>; |
| interrupts = <0 7 0x4>, |
| <0 6 0x4>; |
| reg = <0x17ca0000 0x1000>, |
| <0x17cb0000 0x1000>; |
| }; |
| |
| frame@17cc0000 { |
| frame-number = <1>; |
| interrupts = <0 8 0x4>; |
| reg = <0x17cc0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17cd0000 { |
| frame-number = <2>; |
| interrupts = <0 9 0x4>; |
| reg = <0x17cd0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17ce0000 { |
| frame-number = <3>; |
| interrupts = <0 10 0x4>; |
| reg = <0x17ce0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17cf0000 { |
| frame-number = <4>; |
| interrupts = <0 11 0x4>; |
| reg = <0x17cf0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17d00000 { |
| frame-number = <5>; |
| interrupts = <0 12 0x4>; |
| reg = <0x17d00000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17d10000 { |
| frame-number = <6>; |
| interrupts = <0 13 0x4>; |
| reg = <0x17d10000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| restart@10ac000 { |
| compatible = "qcom,pshold"; |
| reg = <0xC264000 0x4>, |
| <0x1fd3000 0x4>; |
| reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| }; |
| |
| clock_rpmh: qcom,rpmhclk { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "rpmh_clocks"; |
| #clock-cells = <1>; |
| }; |
| |
| clock_gcc: qcom,gcc@100000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "gcc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_videocc: qcom,videocc@ab00000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "videocc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_camcc: qcom,camcc@ad00000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "camcc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_dispcc: qcom,dispcc@af00000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "dispcc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_gpucc: qcom,gpucc@5090000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "gpucc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_gfx: qcom,gfxcc@5090000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "gfxcc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_cpucc: qcom,cpucc { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "cpucc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| wdog: qcom,wdt@17980000{ |
| compatible = "qcom,msm-watchdog"; |
| reg = <0x17980000 0x1000>; |
| reg-names = "wdt-base"; |
| interrupts = <0 3 0>, <0 4 0>; |
| qcom,bark-time = <11000>; |
| qcom,pet-time = <10000>; |
| qcom,ipi-ping; |
| qcom,wakeup-enable; |
| }; |
| |
| qcom,msm-rtb { |
| compatible = "qcom,msm-rtb"; |
| qcom,rtb-size = <0x100000>; |
| }; |
| |
| qcom,msm-imem@146bf000 { |
| compatible = "qcom,msm-imem"; |
| reg = <0x146bf000 0x1000>; |
| ranges = <0x0 0x146bf000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mem_dump_table@10 { |
| compatible = "qcom,msm-imem-mem_dump_table"; |
| reg = <0x10 8>; |
| }; |
| |
| restart_reason@65c { |
| compatible = "qcom,msm-imem-restart_reason"; |
| reg = <0x65c 4>; |
| }; |
| |
| pil@94c { |
| compatible = "qcom,msm-imem-pil"; |
| reg = <0x94c 200>; |
| }; |
| |
| kaslr_offset@6d0 { |
| compatible = "qcom,msm-imem-kaslr_offset"; |
| reg = <0x6d0 12>; |
| }; |
| }; |
| |
| cpuss_dump { |
| compatible = "qcom,cpuss-dump"; |
| qcom,l1_i_cache0 { |
| qcom,dump-node = <&L1_I_0>; |
| qcom,dump-id = <0x60>; |
| }; |
| qcom,l1_i_cache1 { |
| qcom,dump-node = <&L1_I_100>; |
| qcom,dump-id = <0x61>; |
| }; |
| qcom,l1_i_cache2 { |
| qcom,dump-node = <&L1_I_200>; |
| qcom,dump-id = <0x62>; |
| }; |
| qcom,l1_i_cache3 { |
| qcom,dump-node = <&L1_I_300>; |
| qcom,dump-id = <0x63>; |
| }; |
| qcom,l1_i_cache100 { |
| qcom,dump-node = <&L1_I_400>; |
| qcom,dump-id = <0x64>; |
| }; |
| qcom,l1_i_cache101 { |
| qcom,dump-node = <&L1_I_500>; |
| qcom,dump-id = <0x65>; |
| }; |
| qcom,l1_i_cache102 { |
| qcom,dump-node = <&L1_I_600>; |
| qcom,dump-id = <0x66>; |
| }; |
| qcom,l1_i_cache103 { |
| qcom,dump-node = <&L1_I_700>; |
| qcom,dump-id = <0x67>; |
| }; |
| qcom,l1_d_cache0 { |
| qcom,dump-node = <&L1_D_0>; |
| qcom,dump-id = <0x80>; |
| }; |
| qcom,l1_d_cache1 { |
| qcom,dump-node = <&L1_D_100>; |
| qcom,dump-id = <0x81>; |
| }; |
| qcom,l1_d_cache2 { |
| qcom,dump-node = <&L1_D_200>; |
| qcom,dump-id = <0x82>; |
| }; |
| qcom,l1_d_cache3 { |
| qcom,dump-node = <&L1_D_300>; |
| qcom,dump-id = <0x83>; |
| }; |
| qcom,l1_d_cache100 { |
| qcom,dump-node = <&L1_D_400>; |
| qcom,dump-id = <0x84>; |
| }; |
| qcom,l1_d_cache101 { |
| qcom,dump-node = <&L1_D_500>; |
| qcom,dump-id = <0x85>; |
| }; |
| qcom,l1_d_cache102 { |
| qcom,dump-node = <&L1_D_600>; |
| qcom,dump-id = <0x86>; |
| }; |
| qcom,l1_d_cache103 { |
| qcom,dump-node = <&L1_D_700>; |
| qcom,dump-id = <0x87>; |
| }; |
| qcom,llcc1_d_cache { |
| qcom,dump-node = <&LLCC_1>; |
| qcom,dump-id = <0x140>; |
| }; |
| qcom,llcc2_d_cache { |
| qcom,dump-node = <&LLCC_2>; |
| qcom,dump-id = <0x141>; |
| }; |
| }; |
| |
| kryo3xx-erp { |
| compatible = "arm,arm64-kryo3xx-cpu-erp"; |
| interrupts = <1 6 4>, |
| <1 7 4>, |
| <0 34 4>, |
| <0 35 4>; |
| |
| interrupt-names = "l1-l2-faultirq", |
| "l1-l2-errirq", |
| "l3-scu-errirq", |
| "l3-scu-faultirq"; |
| }; |
| |
| qcom,chd_sliver { |
| compatible = "qcom,core-hang-detect"; |
| label = "silver"; |
| qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058 |
| 0x17e30058 0x17e40058 0x17e50058>; |
| qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060 |
| 0x17e30060 0x17e40060 0x17e50060>; |
| }; |
| |
| qcom,chd_gold { |
| compatible = "qcom,core-hang-detect"; |
| label = "gold"; |
| qcom,threshold-arr = <0x17e60058 0x17e70058>; |
| qcom,config-arr = <0x17e60060 0x17e70060>; |
| }; |
| |
| qcom,ghd { |
| compatible = "qcom,gladiator-hang-detect-v2"; |
| qcom,threshold-arr = <0x1799041c 0x17990420>; |
| qcom,config-reg = <0x17990434>; |
| }; |
| |
| qcom,msm-gladiator-v3@17900000 { |
| compatible = "qcom,msm-gladiator-v3"; |
| reg = <0x17900000 0xd080>; |
| reg-names = "gladiator_base"; |
| interrupts = <0 17 0>; |
| }; |
| |
| qcom,llcc@1100000 { |
| compatible = "qcom,llcc-core", "syscon", "simple-mfd"; |
| reg = <0x1100000 0x250000>; |
| reg-names = "llcc_base"; |
| qcom,llcc-banks-off = <0x0 0x80000 >; |
| qcom,llcc-broadcast-off = <0x200000>; |
| |
| llcc: qcom,sdm670-llcc { |
| compatible = "qcom,sdm670-llcc"; |
| #cache-cells = <1>; |
| max-slices = <32>; |
| qcom,dump-size = <0x80000>; |
| }; |
| |
| qcom,llcc-erp { |
| compatible = "qcom,llcc-erp"; |
| interrupt-names = "ecc_irq"; |
| interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| qcom,llcc-amon { |
| compatible = "qcom,llcc-amon"; |
| }; |
| |
| LLCC_1: llcc_1_dcache { |
| qcom,dump-size = <0xd8000>; |
| }; |
| |
| LLCC_2: llcc_2_dcache { |
| qcom,dump-size = <0xd8000>; |
| }; |
| }; |
| |
| dcc: dcc_v2@10a2000 { |
| compatible = "qcom,dcc_v2"; |
| reg = <0x10a2000 0x1000>, |
| <0x10ae000 0x2000>; |
| reg-names = "dcc-base", "dcc-ram-base"; |
| }; |
| |
| spmi_bus: qcom,spmi@c440000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0xc440000 0x1100>, |
| <0xc600000 0x2000000>, |
| <0xe600000 0x100000>, |
| <0xe700000 0xa0000>, |
| <0xc40a000 0x26000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| cell-index = <0>; |
| }; |
| |
| ufsphy_mem: ufsphy_mem@1d87000 { |
| reg = <0x1d87000 0xe00>; /* PHY regs */ |
| reg-names = "phy_mem"; |
| #phy-cells = <0>; |
| |
| lanes-per-direction = <1>; |
| |
| clock-names = "ref_clk_src", |
| "ref_clk", |
| "ref_aux_clk"; |
| clocks = <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, |
| <&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>; |
| |
| status = "disabled"; |
| }; |
| |
| ufshc_mem: ufshc@1d84000 { |
| compatible = "qcom,ufshc"; |
| reg = <0x1d84000 0x3000>; |
| interrupts = <0 265 0>; |
| phys = <&ufsphy_mem>; |
| phy-names = "ufsphy"; |
| |
| lanes-per-direction = <1>; |
| dev-ref-clk-freq = <0>; /* 19.2 MHz */ |
| |
| clock-names = |
| "core_clk", |
| "bus_aggr_clk", |
| "iface_clk", |
| "core_clk_unipro", |
| "core_clk_ice", |
| "ref_clk", |
| "tx_lane0_sync_clk", |
| "rx_lane0_sync_clk"; |
| clocks = |
| <&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>, |
| <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK>, |
| <&clock_gcc GCC_UFS_PHY_AHB_CLK>, |
| <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>, |
| <&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>, |
| <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; |
| freq-table-hz = |
| <50000000 200000000>, |
| <0 0>, |
| <0 0>, |
| <37500000 150000000>, |
| <75000000 300000000>, |
| <0 0>, |
| <0 0>, |
| <0 0>; |
| |
| resets = <&clock_gcc GCC_UFS_PHY_BCR>; |
| reset-names = "core_reset"; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| #include "sdm670-pinctrl.dtsi" |
| #include "msm-arm-smmu-sdm670.dtsi" |
| #include "msm-gdsc-sdm845.dtsi" |
| |
| &usb30_prim_gdsc { |
| status = "ok"; |
| }; |
| |
| &ufs_phy_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_aggre_noc_mmu_tbu1_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_aggre_noc_mmu_tbu2_gdsc { |
| status = "ok"; |
| }; |
| |
| &bps_gdsc { |
| status = "ok"; |
| }; |
| |
| &ife_0_gdsc { |
| status = "ok"; |
| }; |
| |
| &ife_1_gdsc { |
| status = "ok"; |
| }; |
| |
| &ipe_0_gdsc { |
| status = "ok"; |
| }; |
| |
| &ipe_1_gdsc { |
| status = "ok"; |
| }; |
| |
| &titan_top_gdsc { |
| status = "ok"; |
| }; |
| |
| &mdss_core_gdsc { |
| status = "ok"; |
| }; |
| |
| &gpu_cx_gdsc { |
| status = "ok"; |
| }; |
| |
| &gpu_gx_gdsc { |
| clock-names = "core_root_clk"; |
| clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>; |
| qcom,force-enable-root-clk; |
| status = "ok"; |
| }; |
| |
| &vcodec0_gdsc { |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| &vcodec1_gdsc { |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| &venus_gdsc { |
| status = "ok"; |
| }; |
| |
| #include "pm660.dtsi" |
| #include "pm660l.dtsi" |
| #include "sdm670-regulator.dtsi" |