Merge "drivers: thermal: cpu-cooling: unisolate CPU after hotplug"
diff --git a/Documentation/devicetree/bindings/arm/msm/msm_bus_adhoc.txt b/Documentation/devicetree/bindings/arm/msm/msm_bus_adhoc.txt
index 6bf6a57..8aeaf77 100644
--- a/Documentation/devicetree/bindings/arm/msm/msm_bus_adhoc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/msm_bus_adhoc.txt
@@ -121,6 +121,20 @@
cannot connect to either directly or via any number of
intermediate nodes.
qcom,agg-ports: The number of aggregation ports on the bus.
+qcom,node-qos-bcms: Optional property to target specific BCMs to toggle during QoS configuration,
+ this is to ensure QoS register space is clocked and accessible. Array is
+ defined as follows: BCM node ID, VoteX, VoteY. The vectors must be defined in
+ sets of the three values aforementioned.
+qcom,prio: Default fixed priority for bus master.
+qcom,qos-lim-params: Array containing QoS limiter configurations defined as: Bandwidth, Saturation.
+ Must define "qcom,qos-lim-en" for these settings to take effect.
+qcom,qos-lim-en: Boolean to enable limiter settings, default is disabled.
+qcom,qos-reg-params: Array containing QoS regulator configurations defined as: Low Priority, High
+ Priority, Bandwidth, Saturation. Must define "qcom,qos-reg-regmode" for these
+ settings to take effect.
+qcom,qos-reg-mode: Array containing QoS regulator mode enablement: Read Enable, Write Enable,
+ default is disabled.
+qcom,forwarding: Boolean indicate Urgent Forwarding enablement.
The following properties are optional as collecting data via coresight might
and are present on child nodes that represent NOC devices. The documentation
@@ -172,6 +186,12 @@
<&clock_gcc clk_q1_clk>;
q0-clk-supply = <&gdsc_q0_clk>;
};
+ qcom,node-qos-bcms = <0x7011 0 1>;
+ qcom,prio = 1;
+ qcom,qos-lim-params = <1000 1000>;
+ qcom,qos-lim-en:
+ qcom,qos-reg-params = <1 2 1000 1000>;
+ qcom,qos-reg-mode = <1 1>;
};
mm_int_bimc: mm-int-bimc {
diff --git a/Documentation/devicetree/bindings/usb/msm-phy.txt b/Documentation/devicetree/bindings/usb/msm-phy.txt
index e508a4f..a9480be 100644
--- a/Documentation/devicetree/bindings/usb/msm-phy.txt
+++ b/Documentation/devicetree/bindings/usb/msm-phy.txt
@@ -1,5 +1,39 @@
MSM USB PHY transceivers
+HSUSB PHY
+
+Required properties:
+ - compatible: Should be "qcom,usb-hsphy-snps-femto"
+ - reg: Address and length of the register set for the device
+ Required regs are:
+ "hsusb_phy_base" : the base register for the PHY
+ - <supply-name>-supply: phandle to the regulator device tree node
+ Required "supply-name" examples are:
+ "vdd" : vdd supply for HSPHY digital circuit operation
+ "vdda18" : 1.8v supply for HSPHY
+ "vdda33" : 3.3v supply for HSPHY
+ - clocks: a list of phandles to the PHY clocks. Use as per
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
+ property. "ref_clk_src" is a mandatory clock.
+ - qcom,vdd-voltage-level: This property must be a list of three integer
+ values (no, min, max) where each value represents either a voltage in
+ microvolts or a value corresponding to voltage corner
+ - resets: reset specifier pair consists of phandle for the reset controller
+ and reset lines used by this controller.
+ - reset-names: reset signal name strings sorted in the same order as the resets
+ property.
+
+Example:
+ hsphy@f9200000 {
+ compatible = "qcom,usb-hsphy-snps-femto";
+ reg = <0xff1000 0x400>;
+ vdd-supply = <&pm8841_s2_corner>;
+ vdda18-supply = <&pm8941_l6>;
+ vdda33-supply = <&pm8941_l24>;
+ qcom,vdd-voltage-level = <0 872000 872000>;
+ };
+
SSUSB-QMP PHY
Required properties:
@@ -140,6 +174,7 @@
- qcom,hold-reset: Indicates that hold QUSB PHY into reset state.
- qcom,phy-clk-scheme: Should be one of "cml" or "cmos" if ref_clk_addr is provided.
- qcom,major-rev: provide major revision number to differentiate power up sequence. default is 2.0
+ - qcom,phy-auto-resume-offset: Provides phy auto-resume register offset.
Example:
qusb_phy: qusb@f9b39000 {
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills-rumi.dts b/arch/arm/boot/dts/qcom/sdxpoorwills-rumi.dts
index fc4ff37..b3103cd 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills-rumi.dts
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills-rumi.dts
@@ -36,3 +36,35 @@
&gdsc_pcie {
compatible = "regulator-fixed";
};
+
+&usb {
+ /delete-property/ qcom,usb-dbm;
+ qcom,charging-disabled;
+ dwc3@a600000 {
+ usb-phy = <&usb2_phy>, <&usb_nop_phy>;
+ maximum-speed = "high-speed";
+ };
+};
+
+&usb2_phy {
+ reg = <0xff1000 0x1000>,
+ <0x0a60cd00 0x40>;
+ reg-names = "hsusb_phy_base",
+ "emu_phy_base";
+ qcom,emu-init-seq = <0x19 0x404
+ 0x20 0x414
+ 0x79 0x410
+ 0x00 0x418
+ 0x99 0x404
+ 0x04 0x408
+ 0xd9 0x404>;
+
+ qcom,emu-dcm-reset-seq = <0x100000 0x20
+ 0x0 0x20
+ 0x1e0 0x20
+ 0x5 0x14>;
+};
+
+&usb3_qmp_phy {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills-usb.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills-usb.dtsi
new file mode 100644
index 0000000..be2b63e
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills-usb.dtsi
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,gcc-sdxpoorwills.h>
+
+&soc {
+ /* USB port for DWC3 controller */
+ usb: ssusb@a600000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0x0a600000 0xf8c00>;
+ reg-names = "core_base";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts = <0 131 0>, <0 130 0>, <0 59 0>;
+ interrupt-names = "hs_phy_irq", "pwr_event_irq", "ss_phy_irq";
+
+ USB3_GDSC-supply = <&gdsc_usb30>;
+ qcom,usb-dbm = <&dbm_1p5>;
+ qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
+ qcom,num-gsi-evt-buffs = <0x3>;
+
+ clocks = <&clock_gcc GCC_USB30_MASTER_CLK>,
+ <&clock_gcc GCC_SYS_NOC_USB3_CLK>,
+ <&clock_gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&clock_gcc GCC_USB30_SLEEP_CLK>,
+ <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>;
+
+ clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
+ "cfg_ahb_clk", "xo";
+
+ qcom,core-clk-rate = <133333333>;
+ qcom,core-clk-rate-hs = <66666667>;
+
+ resets = <&clock_gcc GCC_USB30_BCR>;
+ reset-names = "core_reset";
+
+ dwc3@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0a600000 0xcd00>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 133 0>;
+ usb-phy = <&usb2_phy>, <&usb3_qmp_phy>;
+ tx-fifo-resize;
+ linux,sysdev_is_parent;
+ snps,disable-clk-gating;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ };
+ };
+
+ /* USB port for High Speed PHY */
+ usb2_phy: hsphy@ff1000 {
+ compatible = "qcom,usb-hsphy-snps-femto";
+ reg = <0xff1000 0x400>;
+ reg-names = "hsusb_phy_base";
+
+ vdd-supply = <&pmxpoorwills_l4>;
+ vdda18-supply = <&pmxpoorwills_l5>;
+ vdda33-supply = <&pmxpoorwills_l10>;
+ qcom,vdd-voltage-level = <0 872000 872000>;
+ clocks = <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+ clock-names = "ref_clk_src", "cfg_ahb_clk";
+
+ resets = <&clock_gcc GCC_QUSB2PHY_BCR>;
+ reset-names = "phy_reset";
+ };
+
+ dbm_1p5: dbm@a6f8000 {
+ compatible = "qcom,usb-dbm-1p5";
+ reg = <0xa6f8000 0x400>;
+ qcom,reset-ep-after-lpm-resume;
+ };
+
+ usb_nop_phy: usb_nop_phy {
+ compatible = "usb-nop-xceiv";
+ };
+
+ /* USB port for Super Speed PHY */
+ usb3_qmp_phy: ssphy@ff0000 {
+ compatible = "qcom,usb-ssphy-qmp-v2";
+ reg = <0xff0000 0x1000>;
+ reg-names = "qmp_phy_base";
+
+ vdd-supply = <&pmxpoorwills_l4>;
+ core-supply = <&pmxpoorwills_l1>;
+ qcom,vdd-voltage-level = <0 872000 872000>;
+ qcom,vbus-valid-override;
+ qcom,qmp-phy-init-seq =
+ /* <reg_offset, value, delay> */
+ <0x048 0x07 0x00 /* QSERDES_COM_PLL_IVCO */
+ 0x080 0x14 0x00 /* QSERDES_COM_SYSCLK_EN_SEL */
+ 0x034 0x04 0x00 /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
+ 0x138 0x30 0x00 /* QSERDES_COM_CLK_SELECT */
+ 0x03c 0x02 0x00 /* QSERDES_COM_SYS_CLK_CTRL */
+ 0x08c 0x08 0x00 /* QSERDES_COM_RESETSM_CNTRL2 */
+ 0x15c 0x06 0x00 /* QSERDES_COM_CMN_CONFIG */
+ 0x164 0x01 0x00 /* QSERDES_COM_SVS_MODE_CLK_SEL */
+ 0x13c 0x80 0x00 /* QSERDES_COM_HSCLK_SEL */
+ 0x0b0 0x82 0x00 /* QSERDES_COM_DEC_START_MODE0 */
+ 0x0b8 0xab 0x00 /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
+ 0x0bc 0xea 0x00 /* QSERDES_COM_DIV_FRAC_START2_MODE0 */
+ 0x0c0 0x02 0x00 /* QSERDES_COM_DIV_FRAC_START3_MODE0 */
+ 0x060 0x06 0x00 /* QSERDES_COM_CP_CTRL_MODE0 */
+ 0x068 0x16 0x00 /* QSERDES_COM_PLL_RCTRL_MODE0 */
+ 0x070 0x36 0x00 /* QSERDES_COM_PLL_CCTRL_MODE0 */
+ 0x0dc 0x00 0x00 /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
+ 0x0d8 0x3f 0x00 /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
+ 0x0f8 0x01 0x00 /* QSERDES_COM_VCO_TUNE2_MODE0 */
+ 0x0f4 0xc9 0x00 /* QSERDES_COM_VCO_TUNE1_MODE0 */
+ 0x148 0x0a 0x00 /* QSERDES_COM_CORECLK_DIV_MODE0 */
+ 0x0a0 0x00 0x00 /* QSERDES_COM_LOCK_CMP3_MODE0 */
+ 0x09c 0x34 0x00 /* QSERDES_COM_LOCK_CMP2_MODE0 */
+ 0x098 0x15 0x00 /* QSERDES_COM_LOCK_CMP1_MODE0 */
+ 0x090 0x04 0x00 /* QSERDES_COM_LOCK_CMP_EN */
+ 0x154 0x00 0x00 /* QSERDES_COM_CORE_CLK_EN */
+ 0x094 0x00 0x00 /* QSERDES_COM_LOCK_CMP_CFG */
+ 0x0f0 0x00 0x00 /* QSERDES_COM_VCO_TUNE_MAP */
+ 0x040 0x0a 0x00 /* QSERDES_COM_SYSCLK_BUF_ENABLE */
+ 0x0d0 0x80 0x00 /* QSERDES_COM_INTEGLOOP_INITVAL */
+ 0x010 0x01 0x00 /* QSERDES_COM_SSC_EN_CENTER */
+ 0x01c 0x31 0x00 /* QSERDES_COM_SSC_PER1 */
+ 0x020 0x01 0x00 /* QSERDES_COM_SSC_PER2 */
+ 0x014 0x00 0x00 /* QSERDES_COM_SSC_ADJ_PER1 */
+ 0x018 0x00 0x00 /* QSERDES_COM_SSC_ADJ_PER2 */
+ 0x024 0x85 0x00 /* QSERDES_COM_SSC_STEP_SIZE1 */
+ 0x028 0x07 0x00 /* QSERDES_COM_SSC_STEP_SIZE2 */
+ 0x4c0 0x0c 0x00 /* QSERDES_RX_VGA_CAL_CNTRL2 */
+ 0x564 0x50 0x00 /* QSERDES_RX_RX_MODE_00 */
+ 0x430 0x0b 0x00 /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
+ 0x4d4 0x0e 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
+ 0x4d8 0x4e 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
+ 0x4dc 0x18 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
+ 0x4f8 0x77 0x00 /* RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
+ 0x4fc 0x80 0x00 /* RX_RX_OFFSET_ADAPTOR_CNTRL2 */
+ 0x504 0x03 0x00 /* QSERDES_RX_SIGDET_CNTRL */
+ 0x50c 0x1c 0x00 /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
+ 0x434 0x75 0x00 /* RX_UCDR_SO_SATURATION_AND_ENABLE */
+ 0x444 0x80 0x00 /* QSERDES_RX_UCDR_PI_CONTROLS */
+ 0x408 0x0a 0x00 /* QSERDES_RX_UCDR_FO_GAIN */
+ 0x40c 0x06 0x00 /* QSERDES_RX_UCDR_SO_GAIN */
+ 0x500 0x00 0x00 /* QSERDES_RX_SIGDET_ENABLES */
+ 0x260 0x10 0x00 /* QSERDES_TX_HIGHZ_DRVR_EN */
+ 0x2a4 0x12 0x00 /* QSERDES_TX_RCV_DETECT_LVL_2 */
+ 0x28c 0xc6 0x00 /* QSERDES_TX_LANE_MODE_1 */
+ 0x248 0x09 0x00 /* TX_RES_CODE_LANE_OFFSET_RX */
+ 0x244 0x0d 0x00 /* TX_RES_CODE_LANE_OFFSET_TX */
+ 0x8c8 0x83 0x00 /* USB3_UNI_PCS_FLL_CNTRL2 */
+ 0x8cc 0x09 0x00 /* USB3_UNI_PCS_FLL_CNT_VAL_L */
+ 0x8d0 0xa2 0x00 /* USB3_UNI_PCS_FLL_CNT_VAL_H_TOL */
+ 0x8d4 0x40 0x00 /* USB3_UNI_PCS_FLL_MAN_CODE */
+ 0x8c4 0x02 0x00 /* USB3_UNI_PCS_FLL_CNTRL1 */
+ 0x864 0x1b 0x00 /* USB3_UNI_PCS_POWER_STATE_CONFIG2 */
+ 0x80c 0x9f 0x00 /* USB3_UNI_PCS_TXMGN_V0 */
+ 0x810 0x9f 0x00 /* USB3_UNI_PCS_TXMGN_V1 */
+ 0x814 0xb5 0x00 /* USB3_UNI_PCS_TXMGN_V2 */
+ 0x818 0x4c 0x00 /* USB3_UNI_PCS_TXMGN_V3 */
+ 0x81c 0x64 0x00 /* USB3_UNI_PCS_TXMGN_V4 */
+ 0x820 0x6a 0x00 /* USB3_UNI_PCS_TXMGN_LS */
+ 0x824 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V0 */
+ 0x828 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V0 */
+ 0x82c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V1 */
+ 0x830 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V1 */
+ 0x834 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V2 */
+ 0x838 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V2 */
+ 0x83c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V3 */
+ 0x840 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V3 */
+ 0x844 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V4 */
+ 0x848 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V4 */
+ 0x84c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_LS */
+ 0x850 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_LS */
+ 0x85c 0x02 0x00 /* USB3_UNI_PCS_RATE_SLEW_CNTRL */
+ 0x8a0 0x04 0x00 /* PCS_PWRUP_RESET_DLY_TIME_AUXCLK */
+ 0x88c 0x44 0x00 /* USB3_UNI_PCS_TSYNC_RSYNC_TIME */
+ 0x880 0xd1 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG1 */
+ 0x884 0x1f 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG2 */
+ 0x888 0x47 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG3 */
+ 0x870 0xe7 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L */
+ 0x874 0x03 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H */
+ 0x878 0x40 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_U3_L */
+ 0x87c 0x00 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_U3_H */
+ 0x9d8 0xba 0x00 /* USB3_UNI_PCS_RX_SIGDET_LVL */
+ 0x8b8 0x75 0x00 /* RXEQTRAINING_WAIT_TIME */
+ 0x8b0 0x86 0x00 /* PCS_LFPS_TX_ECSTART_EQTLOCK */
+ 0x8bc 0x13 0x00 /* PCS_RXEQTRAINING_RUN_TIME */
+ 0xa0c 0x21 0x00 /* USB3_UNI_PCS_REFGEN_REQ_CONFIG1 */
+ 0xa10 0x60 0x00 /* USB3_UNI_PCS_REFGEN_REQ_CONFIG2 */
+ 0xffffffff 0xffffffff 0x00>;
+
+ qcom,qmp-phy-reg-offset =
+ <0x974 /* USB3_UNI_PCS_PCS_STATUS */
+ 0x8d8 /* USB3_UNI_PCS_AUTONOMOUS_MODE_CTRL */
+ 0x8dc /* USB3_UNI_PCS_LFPS_RXTERM_IRQ_CLEAR */
+ 0x804 /* USB3_UNI_PCS_POWER_DOWN_CONTROL */
+ 0x800 /* USB3_UNI_PCS_SW_RESET */
+ 0x808>; /* USB3_UNI_PCS_START_CONTROL */
+
+ clocks = <&clock_gcc GCC_USB3_PHY_AUX_CLK>,
+ <&clock_gcc GCC_USB3_PHY_PIPE_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+
+ clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
+ "cfg_ahb_clk";
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
index 961adc9..a2a3231 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
@@ -180,6 +180,38 @@
reg = <0x00137004 0x4>;
status = "ok";
};
+
+ qcom,msm-imem@8600000 {
+ compatible = "qcom,msm-imem";
+ reg = <0x8600000 0x1000>; /* Address and size of IMEM */
+ ranges = <0x0 0x8600000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 8>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 32>;
+ };
+ };
+
+ restart@4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0x4ab000 0x4>,
+ <0x193d100 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
};
#include "sdxpoorwills-regulator.dtsi"
+#include "sdxpoorwills-usb.dtsi"
diff --git a/arch/arm/configs/sdxpoorwills-perf_defconfig b/arch/arm/configs/sdxpoorwills-perf_defconfig
index 40289a8..1674c11 100644
--- a/arch/arm/configs/sdxpoorwills-perf_defconfig
+++ b/arch/arm/configs/sdxpoorwills-perf_defconfig
@@ -156,6 +156,7 @@
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
+CONFIG_MTD_MSM_QPIC_NAND=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
@@ -207,6 +208,8 @@
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_QCOM=y
+CONFIG_QCOM_DLOAD_MODE=y
CONFIG_POWER_SUPPLY=y
CONFIG_THERMAL=y
CONFIG_REGULATOR=y
@@ -240,11 +243,20 @@
CONFIG_USB_STORAGE_KARMA=y
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_MSM=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_MSM_SSPHY_QMP=y
+CONFIG_MSM_HSUSB_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_USB_CONFIGFS_F_DIAG=y
+CONFIG_USB_CONFIGFS_F_CDEV=y
+CONFIG_USB_CONFIGFS_F_GSI=y
CONFIG_MMC=y
CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_MMC_BLOCK_MINORS=32
diff --git a/arch/arm/configs/sdxpoorwills_defconfig b/arch/arm/configs/sdxpoorwills_defconfig
index d91f5f6..38a531f 100644
--- a/arch/arm/configs/sdxpoorwills_defconfig
+++ b/arch/arm/configs/sdxpoorwills_defconfig
@@ -148,6 +148,7 @@
CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
+CONFIG_MTD_MSM_QPIC_NAND=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
@@ -200,6 +201,8 @@
CONFIG_SLIMBUS=y
CONFIG_PINCTRL_SDXPOORWILLS=y
CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_QCOM=y
+CONFIG_QCOM_DLOAD_MODE=y
CONFIG_POWER_SUPPLY=y
CONFIG_THERMAL=y
CONFIG_MSM_CDC_PINCTRL=y
@@ -236,11 +239,21 @@
CONFIG_USB_STORAGE_KARMA=y
CONFIG_USB_STORAGE_CYPRESS_ATACB=y
CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_MSM=y
CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_MSM_SSPHY_QMP=y
+CONFIG_MSM_HSUSB_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DEBUG_FILES=y
CONFIG_USB_GADGET_DEBUG_FS=y
CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_USB_CONFIGFS_F_DIAG=y
+CONFIG_USB_CONFIGFS_F_CDEV=y
+CONFIG_USB_CONFIGFS_F_GSI=y
CONFIG_MMC=y
CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_MMC_BLOCK_MINORS=32
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index 92b7237..fe76010 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -170,6 +170,7 @@
{
__save_stack_trace(tsk, trace, 1);
}
+EXPORT_SYMBOL(save_stack_trace_tsk);
void save_stack_trace(struct stack_trace *trace)
{
diff --git a/arch/arm64/boot/dts/qcom/sdm845-bus.dtsi b/arch/arm64/boot/dts/qcom/sdm845-bus.dtsi
index e26f888..b33b525 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-bus.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-bus.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/msm/msm-bus-ids.h>
#include <dt-bindings/soc/qcom,tcs-mbox.h>
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
&soc {
ad_hoc_bus: ad-hoc-bus {
@@ -355,7 +356,8 @@
label = "fab-aggre1_noc";
qcom,fab-dev;
qcom,base-name = "aggre1_noc-base";
- qcom,bypass-qos-prg;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <16384>;
qcom,bus-type = <1>;
clocks = <>;
};
@@ -365,7 +367,8 @@
label = "fab-aggre2_noc";
qcom,fab-dev;
qcom,base-name = "aggre2_noc-base";
- qcom,bypass-qos-prg;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <16384>;
qcom,bus-type = <1>;
clocks = <>;
};
@@ -432,7 +435,8 @@
label = "fab-mem_noc";
qcom,fab-dev;
qcom,base-name = "mem_noc-base";
- qcom,bypass-qos-prg;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <65536>;
qcom,bus-type = <1>;
clocks = <>;
};
@@ -442,7 +446,8 @@
label = "fab-mmss_noc";
qcom,fab-dev;
qcom,base-name = "mmss_noc-base";
- qcom,bypass-qos-prg;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <36864>;
qcom,bus-type = <1>;
clocks = <>;
};
@@ -452,7 +457,8 @@
label = "fab-system_noc";
qcom,fab-dev;
qcom,base-name = "system_noc-base";
- qcom,bypass-qos-prg;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <36864>;
qcom,bus-type = <1>;
clocks = <>;
};
@@ -471,6 +477,8 @@
label = "fab-mem_noc_display";
qcom,fab-dev;
qcom,base-name = "mem_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <65536>;
qcom,bypass-qos-prg;
qcom,bus-type = <1>;
clocks = <>;
@@ -524,6 +532,8 @@
qcom,qport = <1>;
qcom,connections = <&slv_qns_a1noc_snoc>;
qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <1>;
};
mas_xm_sdc4: mas-xm-sdc4 {
@@ -534,6 +544,8 @@
qcom,qport = <2>;
qcom,connections = <&slv_qns_a1noc_snoc>;
qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <1>;
};
mas_xm_ufs_card: mas-xm-ufs-card {
@@ -544,6 +556,8 @@
qcom,qport = <3>;
qcom,connections = <&slv_qns_a1noc_snoc>;
qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
};
mas_xm_ufs_mem: mas-xm-ufs-mem {
@@ -554,6 +568,8 @@
qcom,qport = <4>;
qcom,connections = <&slv_qns_a1noc_snoc>;
qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
};
mas_qhm_a2noc_cfg: mas-qhm-a2noc-cfg {
@@ -592,6 +608,8 @@
qcom,qport = <0>;
qcom,connections = <&slv_qns_a2noc_snoc>;
qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <1>;
};
mas_qxm_crypto: mas-qxm-crypto {
@@ -603,6 +621,8 @@
qcom,connections = <&slv_qns_a2noc_snoc>;
qcom,bus-dev = <&fab_aggre2_noc>;
qcom,bcms = <&bcm_ce0>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
};
mas_qxm_ipa: mas-qxm-ipa {
@@ -613,6 +633,7 @@
qcom,qport = <2>;
qcom,connections = <&slv_qns_a2noc_snoc>;
qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,prio = <2>;
};
mas_xm_pcie3_1: mas-xm-pcie3-1 {
@@ -623,6 +644,8 @@
qcom,qport = <6>;
qcom,connections = <&slv_qns_pcie_snoc>;
qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
};
mas_xm_pcie_0: mas-xm-pcie-0 {
@@ -632,7 +655,9 @@
qcom,agg-ports = <1>;
qcom,qport = <5>;
qcom,connections = <&slv_qns_pcie_snoc>;
- qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
};
mas_xm_qdss_etr: mas-xm-qdss-etr {
@@ -643,6 +668,8 @@
qcom,qport = <7>;
qcom,connections = <&slv_qns_a2noc_snoc>;
qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
};
mas_xm_usb3_0: mas-xm-usb3-0 {
@@ -653,6 +680,7 @@
qcom,qport = <10>;
qcom,connections = <&slv_qns_a2noc_snoc>;
qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,prio = <2>;
};
mas_xm_usb3_1: mas-xm-usb3-1 {
@@ -663,6 +691,7 @@
qcom,qport = <11>;
qcom,connections = <&slv_qns_a2noc_snoc>;
qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,prio = <2>;
};
mas_qxm_camnoc_hf0_uncomp: mas-qxm-camnoc-hf0-uncomp {
@@ -825,12 +854,12 @@
qcom,bus-dev = <&fab_gladiator_noc>;
};
- mas_ipa_core: mas-ipa-core {
+ mas_ipa_core_master: mas-ipa-core-master {
cell-id = <MSM_BUS_MASTER_IPA_CORE>;
- label = "mas-ipa-core";
- qcom,buswidth = <1>;
+ label = "mas-ipa-core-master";
+ qcom,buswidth = <8>;
qcom,agg-ports = <1>;
- qcom,connections = <&slv_ipa_core>;
+ qcom,connections = <&slv_ipa_core_slave>;
qcom,bus-dev = <&fab_ipa_virt>;
};
@@ -853,6 +882,8 @@
&slv_qns_memnoc_snoc>;
qcom,bus-dev = <&fab_mem_noc>;
qcom,bcms = <&bcm_sh3>;
+ qcom,ap-owned;
+ qcom,prio = <6>;
};
mas_qhm_memnoc_cfg: mas-qhm-memnoc-cfg {
@@ -874,6 +905,8 @@
qcom,connections = <&slv_qns_llcc>;
qcom,bus-dev = <&fab_mem_noc>;
qcom,bcms = <&bcm_sh5>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
};
mas_qnm_mnoc_hf: mas-qnm-mnoc-hf {
@@ -884,6 +917,10 @@
qcom,qport = <4 5>;
qcom,connections = <&slv_qns_apps_io &slv_qns_llcc>;
qcom,bus-dev = <&fab_mem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qnm_mnoc_sf: mas-qnm-mnoc-sf {
@@ -895,6 +932,10 @@
qcom,connections = <&slv_qns_apps_io
&slv_qns_llcc &slv_qns_memnoc_snoc>;
qcom,bus-dev = <&fab_mem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qnm_snoc_gc: mas-qnm-snoc-gc {
@@ -905,6 +946,9 @@
qcom,qport = <8>;
qcom,connections = <&slv_qns_llcc>;
qcom,bus-dev = <&fab_mem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
};
mas_qnm_snoc_sf: mas-qnm-snoc-sf {
@@ -915,6 +959,9 @@
qcom,qport = <9>;
qcom,connections = <&slv_qns_apps_io &slv_qns_llcc>;
qcom,bus-dev = <&fab_mem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
};
mas_qxm_gpu: mas-qxm-gpu {
@@ -926,7 +973,8 @@
qcom,connections = <&slv_qns_apps_io
&slv_qns_llcc &slv_qns_memnoc_snoc>;
qcom,bus-dev = <&fab_mem_noc>;
- qcom,bcms = <&bcm_sh4>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
};
mas_qhm_mnoc_cfg: mas-qhm-mnoc-cfg {
@@ -947,6 +995,10 @@
qcom,connections = <&slv_qns_mem_noc_hf>;
qcom,bus-dev = <&fab_mmss_noc>;
qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qxm_camnoc_hf1: mas-qxm-camnoc-hf1 {
@@ -958,6 +1010,10 @@
qcom,connections = <&slv_qns_mem_noc_hf>;
qcom,bus-dev = <&fab_mmss_noc>;
qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qxm_camnoc_sf: mas-qxm-camnoc-sf {
@@ -969,6 +1025,10 @@
qcom,connections = <&slv_qns2_mem_noc>;
qcom,bus-dev = <&fab_mmss_noc>;
qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qxm_mdp0: mas-qxm-mdp0 {
@@ -980,6 +1040,10 @@
qcom,connections = <&slv_qns_mem_noc_hf>;
qcom,bus-dev = <&fab_mmss_noc>;
qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qxm_mdp1: mas-qxm-mdp1 {
@@ -991,6 +1055,10 @@
qcom,connections = <&slv_qns_mem_noc_hf>;
qcom,bus-dev = <&fab_mmss_noc>;
qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qxm_rot: mas-qxm-rot {
@@ -1002,6 +1070,10 @@
qcom,connections = <&slv_qns2_mem_noc>;
qcom,bus-dev = <&fab_mmss_noc>;
qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qxm_venus0: mas-qxm-venus0 {
@@ -1013,6 +1085,10 @@
qcom,connections = <&slv_qns2_mem_noc>;
qcom,bus-dev = <&fab_mmss_noc>;
qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qxm_venus1: mas-qxm-venus1 {
@@ -1024,6 +1100,10 @@
qcom,connections = <&slv_qns2_mem_noc>;
qcom,bus-dev = <&fab_mmss_noc>;
qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qxm_venus_arm9: mas-qxm-venus-arm9 {
@@ -1035,6 +1115,10 @@
qcom,connections = <&slv_qns2_mem_noc>;
qcom,bus-dev = <&fab_mmss_noc>;
qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
};
mas_qhm_snoc_cfg: mas-qhm-snoc-cfg {
@@ -1120,6 +1204,8 @@
qcom,connections = <&slv_qxs_imem &slv_qns_memnoc_gc>;
qcom,bus-dev = <&fab_system_noc>;
qcom,bcms = <&bcm_sn4>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
};
mas_alc: mas-alc {
@@ -1687,10 +1773,10 @@
qcom,bus-dev = <&fab_gladiator_noc>;
};
- slv_ipa_core:slv-ipa-core {
- cell-id = <MSM_BUS_SLAVE_IPA>;
- label = "slv-ipa-core";
- qcom,buswidth = <1>;
+ slv_ipa_core_slave:slv-ipa-core-slave {
+ cell-id = <MSM_BUS_SLAVE_IPA_CORE>;
+ label = "slv-ipa-core-slave";
+ qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_ipa_virt>;
qcom,bcms = <&bcm_ip0>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-usb.dtsi b/arch/arm64/boot/dts/qcom/sdm845-usb.dtsi
index df6ffad..53cb27e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-usb.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-usb.dtsi
@@ -141,6 +141,8 @@
0x00 0x23c /* CHG_CTRL2 */
0x22 0x210>; /* PWR_CTRL1 */
+ qcom,phy-auto-resume-offset = <0x254>;
+
phy_type= "utmi";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 83f1166..1eaeb59 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1771,9 +1771,8 @@
interrupts = <0 494 1>;
vdd_cx-supply = <&pm8998_l27_level>;
- vdd_px-supply = <&pm8998_lvs2>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
- qcom,proxy-reg-names = "vdd_cx", "vdd_px";
+ qcom,proxy-reg-names = "vdd_cx";
qcom,keep-proxy-regs-on;
clocks = <&clock_rpmh RPMH_CXO_CLK>;
diff --git a/arch/arm64/configs/sdm845-perf_defconfig b/arch/arm64/configs/sdm845-perf_defconfig
index 18b0a3b..8a5b17d 100644
--- a/arch/arm64/configs/sdm845-perf_defconfig
+++ b/arch/arm64/configs/sdm845-perf_defconfig
@@ -246,9 +246,12 @@
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_QCOM=y
CONFIG_SCSI_UFS_QCOM_ICE=y
+CONFIG_SCSI_UFSHCD_CMD_LOGGING=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
+CONFIG_DM_DEBUG=y
CONFIG_DM_CRYPT=y
+CONFIG_DM_REQ_CRYPT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
@@ -366,6 +369,7 @@
CONFIG_UHID=y
CONFIG_HID_APPLE=y
CONFIG_HID_MICROSOFT=y
+CONFIG_HID_PLANTRONICS=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_XHCI_HCD=y
diff --git a/arch/arm64/configs/sdm845_defconfig b/arch/arm64/configs/sdm845_defconfig
index 1f1b5b4..e70963a 100644
--- a/arch/arm64/configs/sdm845_defconfig
+++ b/arch/arm64/configs/sdm845_defconfig
@@ -259,7 +259,9 @@
CONFIG_SCSI_UFSHCD_CMD_LOGGING=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
+CONFIG_DM_DEBUG=y
CONFIG_DM_CRYPT=y
+CONFIG_DM_REQ_CRYPT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
@@ -374,6 +376,7 @@
CONFIG_UHID=y
CONFIG_HID_APPLE=y
CONFIG_HID_MICROSOFT=y
+CONFIG_HID_PLANTRONICS=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
@@ -601,6 +604,7 @@
CONFIG_DEBUG_LIST=y
CONFIG_FAULT_INJECTION=y
CONFIG_FAIL_PAGE_ALLOC=y
+CONFIG_UFS_FAULT_INJECTION=y
CONFIG_FAULT_INJECTION_DEBUG_FS=y
CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
CONFIG_IPC_LOGGING=y
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index fe8f94a..fc1a286 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -225,18 +225,12 @@
static void show_extra_register_data(struct pt_regs *regs, int nbytes)
{
mm_segment_t fs;
- unsigned int i;
fs = get_fs();
set_fs(KERNEL_DS);
show_data(regs->pc - nbytes, nbytes * 2, "PC");
show_data(regs->regs[30] - nbytes, nbytes * 2, "LR");
show_data(regs->sp - nbytes, nbytes * 2, "SP");
- for (i = 0; i < 30; i++) {
- char name[4];
- snprintf(name, sizeof(name), "X%u", i);
- show_data(regs->regs[i] - nbytes, nbytes * 2, name);
- }
set_fs(fs);
}
diff --git a/arch/arm64/kernel/stacktrace.c b/arch/arm64/kernel/stacktrace.c
index c2efddf..bedf97d 100644
--- a/arch/arm64/kernel/stacktrace.c
+++ b/arch/arm64/kernel/stacktrace.c
@@ -203,6 +203,7 @@
if (trace->nr_entries < trace->max_entries)
trace->entries[trace->nr_entries++] = ULONG_MAX;
}
+EXPORT_SYMBOL(save_stack_trace_tsk);
void save_stack_trace(struct stack_trace *trace)
{
diff --git a/block/blk-core.c b/block/blk-core.c
index 710c93b..d8fba67 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -1438,6 +1438,9 @@
/* this is a bio leak */
WARN_ON(req->bio != NULL);
+ /* this is a bio leak if the bio is not tagged with BIO_DONTFREE */
+ WARN_ON(req->bio && !bio_flagged(req->bio, BIO_DONTFREE));
+
/*
* Request may not have originated from ll_rw_blk. if not,
* it didn't come out of our reserved rq pools
@@ -2619,6 +2622,15 @@
blk_account_io_completion(req, nr_bytes);
total_bytes = 0;
+
+ /*
+ * Check for this if flagged, Req based dm needs to perform
+ * post processing, hence dont end bios or request.DM
+ * layer takes care.
+ */
+ if (bio_flagged(req->bio, BIO_DONTFREE))
+ return false;
+
while (req->bio) {
struct bio *bio = req->bio;
unsigned bio_bytes = min(bio->bi_iter.bi_size, nr_bytes);
diff --git a/block/blk-merge.c b/block/blk-merge.c
index 2642e5f..abde370 100644
--- a/block/blk-merge.c
+++ b/block/blk-merge.c
@@ -492,6 +492,64 @@
}
EXPORT_SYMBOL(blk_rq_map_sg);
+/*
+ * map a request to scatterlist without combining PHY CONT
+ * blocks, return number of sg entries setup. Caller
+ * must make sure sg can hold rq->nr_phys_segments entries
+ */
+int blk_rq_map_sg_no_cluster(struct request_queue *q, struct request *rq,
+ struct scatterlist *sglist)
+{
+ struct bio_vec bvec, bvprv = { NULL };
+ struct req_iterator iter;
+ struct scatterlist *sg;
+ int nsegs, cluster = 0;
+
+ nsegs = 0;
+
+ /*
+ * for each bio in rq
+ */
+ sg = NULL;
+ rq_for_each_segment(bvec, rq, iter) {
+ __blk_segment_map_sg(q, &bvec, sglist, &bvprv, &sg,
+ &nsegs, &cluster);
+ } /* segments in rq */
+
+
+ if (!sg)
+ return nsegs;
+
+ if (unlikely(rq->cmd_flags & REQ_COPY_USER) &&
+ (blk_rq_bytes(rq) & q->dma_pad_mask)) {
+ unsigned int pad_len =
+ (q->dma_pad_mask & ~blk_rq_bytes(rq)) + 1;
+
+ sg->length += pad_len;
+ rq->extra_len += pad_len;
+ }
+
+ if (q->dma_drain_size && q->dma_drain_needed(rq)) {
+ if (rq->cmd_flags & REQ_OP_WRITE)
+ memset(q->dma_drain_buffer, 0, q->dma_drain_size);
+
+ sg->page_link &= ~0x02;
+ sg = sg_next(sg);
+ sg_set_page(sg, virt_to_page(q->dma_drain_buffer),
+ q->dma_drain_size,
+ ((unsigned long)q->dma_drain_buffer) &
+ (PAGE_SIZE - 1));
+ nsegs++;
+ rq->extra_len += q->dma_drain_size;
+ }
+
+ if (sg)
+ sg_mark_end(sg);
+
+ return nsegs;
+}
+EXPORT_SYMBOL(blk_rq_map_sg_no_cluster);
+
static inline int ll_new_hw_segment(struct request_queue *q,
struct request *req,
struct bio *bio)
diff --git a/block/blk.h b/block/blk.h
index 74444c4..ae07666 100644
--- a/block/blk.h
+++ b/block/blk.h
@@ -207,7 +207,6 @@
int attempt_front_merge(struct request_queue *q, struct request *rq);
int blk_attempt_req_merge(struct request_queue *q, struct request *rq,
struct request *next);
-void blk_recalc_rq_segments(struct request *rq);
void blk_rq_set_mixed_merge(struct request *rq);
bool blk_rq_merge_ok(struct request *rq, struct bio *bio);
int blk_try_merge(struct request *rq, struct bio *bio);
diff --git a/drivers/base/topology.c b/drivers/base/topology.c
index df3c97c..d6ec1c5 100644
--- a/drivers/base/topology.c
+++ b/drivers/base/topology.c
@@ -118,51 +118,19 @@
return sysfs_create_group(&dev->kobj, &topology_attr_group);
}
-static void topology_remove_dev(unsigned int cpu)
+static int topology_remove_dev(unsigned int cpu)
{
struct device *dev = get_cpu_device(cpu);
sysfs_remove_group(&dev->kobj, &topology_attr_group);
-}
-
-static int topology_cpu_callback(struct notifier_block *nfb,
- unsigned long action, void *hcpu)
-{
- unsigned int cpu = (unsigned long)hcpu;
- int rc = 0;
-
- switch (action) {
- case CPU_UP_PREPARE:
- case CPU_UP_PREPARE_FROZEN:
- rc = topology_add_dev(cpu);
- break;
- case CPU_UP_CANCELED:
- case CPU_UP_CANCELED_FROZEN:
- case CPU_DEAD:
- case CPU_DEAD_FROZEN:
- topology_remove_dev(cpu);
- break;
- }
- return notifier_from_errno(rc);
+ return 0;
}
static int topology_sysfs_init(void)
{
- int cpu;
- int rc = 0;
-
- cpu_notifier_register_begin();
-
- for_each_online_cpu(cpu) {
- rc = topology_add_dev(cpu);
- if (rc)
- goto out;
- }
- __hotcpu_notifier(topology_cpu_callback, 0);
-
-out:
- cpu_notifier_register_done();
- return rc;
+ return cpuhp_setup_state(CPUHP_TOPOLOGY_PREPARE,
+ "base/topology:prepare", topology_add_dev,
+ topology_remove_dev);
}
device_initcall(topology_sysfs_init);
diff --git a/drivers/char/diag/diag_masks.c b/drivers/char/diag/diag_masks.c
index c4d378e..b5a594a 100644
--- a/drivers/char/diag/diag_masks.c
+++ b/drivers/char/diag/diag_masks.c
@@ -60,7 +60,8 @@
{ .ssid_first = MSG_SSID_21, .ssid_last = MSG_SSID_21_LAST },
{ .ssid_first = MSG_SSID_22, .ssid_last = MSG_SSID_22_LAST },
{ .ssid_first = MSG_SSID_23, .ssid_last = MSG_SSID_23_LAST },
- { .ssid_first = MSG_SSID_24, .ssid_last = MSG_SSID_24_LAST }
+ { .ssid_first = MSG_SSID_24, .ssid_last = MSG_SSID_24_LAST },
+ { .ssid_first = MSG_SSID_25, .ssid_last = MSG_SSID_25_LAST }
};
static int diag_apps_responds(void)
diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
index 9ccef91..86e148d 100644
--- a/drivers/clk/qcom/camcc-sdm845.c
+++ b/drivers/clk/qcom/camcc-sdm845.c
@@ -1928,22 +1928,11 @@
};
static const struct qcom_reset_map cam_cc_sdm845_resets[] = {
- [TITAN_CAM_CC_BPS_BCR] = { 0x6000 },
- [TITAN_CAM_CC_CAMNOC_BCR] = { 0xb120 },
[TITAN_CAM_CC_CCI_BCR] = { 0xb0d4 },
[TITAN_CAM_CC_CPAS_BCR] = { 0xb118 },
[TITAN_CAM_CC_CSI0PHY_BCR] = { 0x5000 },
[TITAN_CAM_CC_CSI1PHY_BCR] = { 0x5024 },
[TITAN_CAM_CC_CSI2PHY_BCR] = { 0x5048 },
- [TITAN_CAM_CC_FD_BCR] = { 0xb0ac },
- [TITAN_CAM_CC_ICP_BCR] = { 0xb074 },
- [TITAN_CAM_CC_IFE_0_BCR] = { 0x9000 },
- [TITAN_CAM_CC_IFE_1_BCR] = { 0xa000 },
- [TITAN_CAM_CC_IFE_LITE_BCR] = { 0xb000 },
- [TITAN_CAM_CC_IPE_0_BCR] = { 0x7000 },
- [TITAN_CAM_CC_IPE_1_BCR] = { 0x8000 },
- [TITAN_CAM_CC_JPEG_BCR] = { 0xb048 },
- [TITAN_CAM_CC_LRME_BCR] = { 0xb0f4 },
[TITAN_CAM_CC_MCLK0_BCR] = { 0x4000 },
[TITAN_CAM_CC_MCLK1_BCR] = { 0x4020 },
[TITAN_CAM_CC_MCLK2_BCR] = { 0x4040 },
diff --git a/drivers/clk/qcom/clk-regmap-mux-div.c b/drivers/clk/qcom/clk-regmap-mux-div.c
index 9593aef..942a68e 100644
--- a/drivers/clk/qcom/clk-regmap-mux-div.c
+++ b/drivers/clk/qcom/clk-regmap-mux-div.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Linaro Limited
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014, 2017, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -64,20 +64,26 @@
return -EBUSY;
}
-static void __mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
+int mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
u32 *div)
{
+ int ret = 0;
u32 val, __div, __src;
const char *name = clk_hw_get_name(&md->clkr.hw);
- regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
+ ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
+ if (ret)
+ return ret;
if (val & CMD_RCGR_DIRTY_CFG) {
pr_err("%s: RCG configuration is pending\n", name);
- return;
+ return -EBUSY;
}
- regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
+ ret = regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
+ if (ret)
+ return ret;
+
__src = (val >> md->src_shift);
__src &= BIT(md->src_width) - 1;
*src = __src;
@@ -85,6 +91,8 @@
__div = (val >> md->hid_shift);
__div &= BIT(md->hid_width) - 1;
*div = __div;
+
+ return ret;
}
static int mux_div_enable(struct clk_hw *hw)
@@ -181,7 +189,7 @@
const char *name = clk_hw_get_name(hw);
u32 i, div, src = 0;
- __mux_div_get_src_div(md, &src, &div);
+ mux_div_get_src_div(md, &src, &div);
for (i = 0; i < clk_hw_get_num_parents(hw); i++)
if (src == md->parent_map[i].cfg)
@@ -222,7 +230,7 @@
int i, num_parents = clk_hw_get_num_parents(hw);
const char *name = clk_hw_get_name(hw);
- __mux_div_get_src_div(md, &src, &div);
+ mux_div_get_src_div(md, &src, &div);
for (i = 0; i < num_parents; i++)
if (src == md->parent_map[i].cfg) {
struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
diff --git a/drivers/clk/qcom/clk-regmap-mux-div.h b/drivers/clk/qcom/clk-regmap-mux-div.h
index 6fac5c5..63a696a 100644
--- a/drivers/clk/qcom/clk-regmap-mux-div.h
+++ b/drivers/clk/qcom/clk-regmap-mux-div.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Linaro Limited
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014, 2017, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -61,5 +61,6 @@
extern const struct clk_ops clk_regmap_mux_div_ops;
int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div);
+int mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src, u32 *div);
#endif
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
index 6acab9f..d6ecf12 100644
--- a/drivers/clk/qcom/dispcc-sdm845.c
+++ b/drivers/clk/qcom/dispcc-sdm845.c
@@ -992,8 +992,6 @@
};
static const struct qcom_reset_map disp_cc_sdm845_resets[] = {
- [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
- [DISP_CC_MDSS_GCC_CLOCKS_BCR] = { 0x4000 },
[DISP_CC_MDSS_RSCC_BCR] = { 0x5000 },
};
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 13de253..cd47e14 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -1240,6 +1240,8 @@
static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
.halt_reg = 0x82028,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x82028,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x82028,
.enable_mask = BIT(0),
@@ -1275,6 +1277,8 @@
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x82024,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x82024,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x82024,
.enable_mask = BIT(0),
@@ -1346,6 +1350,8 @@
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x38004,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(10),
@@ -1359,6 +1365,8 @@
static struct clk_branch gcc_camera_ahb_clk = {
.halt_reg = 0xb008,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb008,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb008,
.enable_mask = BIT(0),
@@ -1398,6 +1406,8 @@
static struct clk_branch gcc_ce1_ahb_clk = {
.halt_reg = 0x4100c,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x4100c,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(3),
@@ -1504,6 +1514,8 @@
static struct clk_branch gcc_cpuss_gnoc_clk = {
.halt_reg = 0x48004,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x48004,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(22),
@@ -1548,6 +1560,8 @@
static struct clk_branch gcc_disp_ahb_clk = {
.halt_reg = 0xb00c,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb00c,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb00c,
.enable_mask = BIT(0),
@@ -1675,6 +1689,8 @@
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x71004,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x71004,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71004,
.enable_mask = BIT(0),
@@ -1774,6 +1790,8 @@
static struct clk_branch gcc_mss_cfg_ahb_clk = {
.halt_reg = 0x8a000,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x8a000,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8a000,
.enable_mask = BIT(0),
@@ -1799,6 +1817,8 @@
static struct clk_branch gcc_mss_mfab_axis_clk = {
.halt_reg = 0x8a004,
.halt_check = BRANCH_VOTED,
+ .hwcg_reg = 0x8a004,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8a004,
.enable_mask = BIT(0),
@@ -1856,6 +1876,8 @@
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x6b018,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(2),
@@ -1907,6 +1929,8 @@
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b010,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x6b010,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(0),
@@ -1951,6 +1975,8 @@
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0x8d018,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x8d018,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(28),
@@ -2002,6 +2028,8 @@
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0x8d010,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x8d010,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(26),
@@ -2082,6 +2110,8 @@
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x33004,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
@@ -2108,6 +2138,8 @@
static struct clk_branch gcc_prng_ahb_clk = {
.halt_reg = 0x34004,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x34004,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52004,
.enable_mask = BIT(13),
@@ -2121,6 +2153,8 @@
static struct clk_branch gcc_qmip_camera_ahb_clk = {
.halt_reg = 0xb014,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb014,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb014,
.enable_mask = BIT(0),
@@ -2134,6 +2168,8 @@
static struct clk_branch gcc_qmip_disp_ahb_clk = {
.halt_reg = 0xb018,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb018,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb018,
.enable_mask = BIT(0),
@@ -2147,6 +2183,8 @@
static struct clk_branch gcc_qmip_video_ahb_clk = {
.halt_reg = 0xb010,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb010,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb010,
.enable_mask = BIT(0),
@@ -2461,6 +2499,8 @@
static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
.halt_reg = 0x17008,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x17008,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(7),
@@ -2487,6 +2527,8 @@
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x18010,
.halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x18010,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x5200c,
.enable_mask = BIT(21),
@@ -2624,6 +2666,8 @@
static struct clk_branch gcc_ufs_card_ahb_clk = {
.halt_reg = 0x75010,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x75010,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75010,
.enable_mask = BIT(0),
@@ -2637,6 +2681,8 @@
static struct clk_branch gcc_ufs_card_axi_clk = {
.halt_reg = 0x7500c,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x7500c,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7500c,
.enable_mask = BIT(0),
@@ -2685,6 +2731,8 @@
static struct clk_branch gcc_ufs_card_ice_core_clk = {
.halt_reg = 0x75058,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x75058,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75058,
.enable_mask = BIT(0),
@@ -2720,6 +2768,8 @@
static struct clk_branch gcc_ufs_card_phy_aux_clk = {
.halt_reg = 0x7508c,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x7508c,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7508c,
.enable_mask = BIT(0),
@@ -2791,6 +2841,8 @@
static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.halt_reg = 0x75054,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x75054,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x75054,
.enable_mask = BIT(0),
@@ -2839,6 +2891,8 @@
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77010,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77010,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77010,
.enable_mask = BIT(0),
@@ -2852,6 +2906,8 @@
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x7700c,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x7700c,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7700c,
.enable_mask = BIT(0),
@@ -2887,6 +2943,8 @@
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x77058,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77058,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77058,
.enable_mask = BIT(0),
@@ -2922,6 +2980,8 @@
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x7708c,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x7708c,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7708c,
.enable_mask = BIT(0),
@@ -2993,6 +3053,8 @@
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x77054,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x77054,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77054,
.enable_mask = BIT(0),
@@ -3248,6 +3310,8 @@
static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
.halt_reg = 0x6a004,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x6a004,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0x6a004,
.enable_mask = BIT(0),
@@ -3261,6 +3325,8 @@
static struct clk_branch gcc_video_ahb_clk = {
.halt_reg = 0xb004,
.halt_check = BRANCH_HALT,
+ .hwcg_reg = 0xb004,
+ .hwcg_bit = 1,
.clkr = {
.enable_reg = 0xb004,
.enable_mask = BIT(0),
@@ -3500,7 +3566,6 @@
};
static const struct qcom_reset_map gcc_sdm845_resets[] = {
- [GCC_GPU_BCR] = { 0x71000 },
[GCC_MMSS_BCR] = { 0xb000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_1_BCR] = { 0x8d000 },
diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c
index 14a9cff..362ea0b 100644
--- a/drivers/clk/qcom/videocc-sdm845.c
+++ b/drivers/clk/qcom/videocc-sdm845.c
@@ -311,13 +311,6 @@
[VIDEO_PLL0] = &video_pll0.clkr,
};
-static const struct qcom_reset_map video_cc_sdm845_resets[] = {
- [VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
- [VIDEO_CC_VCODEC0_BCR] = { 0x870 },
- [VIDEO_CC_VCODEC1_BCR] = { 0x8b0 },
- [VIDEO_CC_VENUS_BCR] = { 0x810 },
-};
-
static const struct regmap_config video_cc_sdm845_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -330,8 +323,6 @@
.config = &video_cc_sdm845_regmap_config,
.clks = video_cc_sdm845_clocks,
.num_clks = ARRAY_SIZE(video_cc_sdm845_clocks),
- .resets = video_cc_sdm845_resets,
- .num_resets = ARRAY_SIZE(video_cc_sdm845_resets),
};
static const struct of_device_id video_cc_sdm845_match_table[] = {
diff --git a/drivers/crypto/msm/qcrypto.c b/drivers/crypto/msm/qcrypto.c
index 0f0da4f..b979fb9 100644
--- a/drivers/crypto/msm/qcrypto.c
+++ b/drivers/crypto/msm/qcrypto.c
@@ -4289,7 +4289,7 @@
};
EXPORT_SYMBOL(qcrypto_cipher_set_device);
-int qcrypto_cipher_set_device_hw(struct ablkcipher_request *req, u32 dev,
+int qcrypto_cipher_set_device_hw(struct skcipher_request *req, u32 dev,
u32 hw_inst)
{
struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
@@ -4335,7 +4335,7 @@
};
EXPORT_SYMBOL(qcrypto_ahash_set_device);
-int qcrypto_cipher_set_flag(struct ablkcipher_request *req, unsigned int flags)
+int qcrypto_cipher_set_flag(struct skcipher_request *req, unsigned int flags)
{
struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
struct crypto_priv *cp = ctx->cp;
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 954a2fa..706398db2 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -21,7 +21,6 @@
#include "dp_ctrl.h"
#define DP_KHZ_TO_HZ 1000
-#define DP_CRYPTO_CLK_RATE_KHZ 180000
#define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
#define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
@@ -1034,8 +1033,6 @@
dp_ctrl_set_clock_rate(ctrl, "ctrl_link_clk",
drm_dp_bw_code_to_link_rate(ctrl->link->link_rate));
- dp_ctrl_set_clock_rate(ctrl, "ctrl_crypto_clk", DP_CRYPTO_CLK_RATE_KHZ);
-
dp_ctrl_set_clock_rate(ctrl, "ctrl_pixel_clk", ctrl->pixel_rate);
ret = ctrl->power->clk_enable(ctrl->power, DP_CTRL_PM, true);
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c
index 722c436..e81bbb3 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -494,8 +494,7 @@
ctrl_clk_index++;
if (!strcmp(clk_name, "ctrl_link_clk") ||
- !strcmp(clk_name, "ctrl_pixel_clk") ||
- !strcmp(clk_name, "ctrl_crypto_clk"))
+ !strcmp(clk_name, "ctrl_pixel_clk"))
clk->type = DSS_CLK_PCLK;
else
clk->type = DSS_CLK_AHB;
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
index da7a7c0..4788f3b 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
@@ -31,6 +31,8 @@
#include "dsi_pwr.h"
#include "dsi_catalog.h"
+#include "sde_dbg.h"
+
#define DSI_CTRL_DEFAULT_LABEL "MDSS DSI CTRL"
#define DSI_CTRL_TX_TO_MS 200
@@ -199,6 +201,7 @@
{
int rc = 0;
struct dentry *dir, *state_file, *reg_dump;
+ char dbg_name[DSI_DEBUG_NAME_LEN];
dir = debugfs_create_dir(dsi_ctrl->name, parent);
if (IS_ERR_OR_NULL(dir)) {
@@ -233,6 +236,11 @@
}
dsi_ctrl->debugfs_root = dir;
+
+ snprintf(dbg_name, DSI_DEBUG_NAME_LEN, "dsi%d_ctrl",
+ dsi_ctrl->cell_index);
+ sde_dbg_reg_register_base(dbg_name, dsi_ctrl->hw.base,
+ msm_iomap_size(dsi_ctrl->pdev, "dsi_ctrl"));
error_remove_dir:
debugfs_remove(dir);
error:
@@ -1296,8 +1304,7 @@
dsi_ctrl->pdev = pdev;
platform_set_drvdata(pdev, dsi_ctrl);
-
- pr_debug("Probe successful for %s\n", dsi_ctrl->name);
+ pr_info("Probe successful for %s\n", dsi_ctrl->name);
return 0;
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
index cf36315..77da9b4 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
@@ -36,6 +36,7 @@
value;\
})
+#define DSI_DEBUG_NAME_LEN 32
/**
* enum dsi_pixel_format - DSI pixel formats
* @DSI_PIXEL_FORMAT_RGB565:
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
index a1a0e57..a91dba8 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
@@ -29,6 +29,8 @@
#include "dsi_pwr.h"
#include "dsi_catalog.h"
+#include "sde_dbg.h"
+
#define DSI_PHY_DEFAULT_LABEL "MDSS PHY CTRL"
struct dsi_phy_list_item {
@@ -547,6 +549,11 @@
*/
int dsi_phy_drv_init(struct msm_dsi_phy *dsi_phy)
{
+ char dbg_name[DSI_DEBUG_NAME_LEN];
+
+ snprintf(dbg_name, DSI_DEBUG_NAME_LEN, "dsi%d_phy", dsi_phy->index);
+ sde_dbg_reg_register_base(dbg_name, dsi_phy->hw.base,
+ msm_iomap_size(dsi_phy->pdev, "dsi_phy"));
return 0;
}
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index d4a270e..f7d5d02 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -229,6 +229,24 @@
return ptr;
}
+unsigned long msm_iomap_size(struct platform_device *pdev, const char *name)
+{
+ struct resource *res;
+
+ if (name)
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+ else
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+ if (!res) {
+ dev_err(&pdev->dev, "failed to get memory resource: %s\n",
+ name);
+ return 0;
+ }
+
+ return resource_size(res);
+}
+
void msm_iounmap(struct platform_device *pdev, void __iomem *addr)
{
devm_iounmap(&pdev->dev, addr);
@@ -389,10 +407,11 @@
priv->vram.paddr, attrs);
}
+ component_unbind_all(dev, ddev);
+
sde_dbg_destroy();
debugfs_remove_recursive(priv->debug_root);
- component_unbind_all(dev, ddev);
sde_power_client_destroy(&priv->phandle, priv->pclient);
sde_power_resource_deinit(pdev, &priv->phandle);
@@ -586,6 +605,15 @@
goto power_client_fail;
}
+ dbg_power_ctrl.handle = &priv->phandle;
+ dbg_power_ctrl.client = priv->pclient;
+ dbg_power_ctrl.enable_fn = msm_power_enable_wrapper;
+ ret = sde_dbg_init(&pdev->dev, &dbg_power_ctrl);
+ if (ret) {
+ dev_err(dev, "failed to init sde dbg: %d\n", ret);
+ goto dbg_init_fail;
+ }
+
/* Bind all our sub-components: */
ret = msm_component_bind_all(dev, ddev);
if (ret)
@@ -595,15 +623,6 @@
if (ret)
goto fail;
- dbg_power_ctrl.handle = &priv->phandle;
- dbg_power_ctrl.client = priv->pclient;
- dbg_power_ctrl.enable_fn = msm_power_enable_wrapper;
- ret = sde_dbg_init(&pdev->dev, &dbg_power_ctrl);
- if (ret) {
- dev_err(dev, "failed to init sde dbg: %d\n", ret);
- goto fail;
- }
-
switch (get_mdp_ver(pdev)) {
case KMS_MDP4:
kms = mdp4_kms_init(ddev);
@@ -757,6 +776,8 @@
msm_drm_uninit(dev);
return ret;
bind_fail:
+ sde_dbg_destroy();
+dbg_init_fail:
sde_power_client_destroy(&priv->phandle, priv->pclient);
power_client_fail:
sde_power_resource_deinit(pdev, &priv->phandle);
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index fdf9b1f..86fec8b 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -774,6 +774,7 @@
void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
const char *dbgname);
+unsigned long msm_iomap_size(struct platform_device *pdev, const char *name);
void msm_iounmap(struct platform_device *dev, void __iomem *addr);
void msm_writel(u32 data, void __iomem *addr);
u32 msm_readl(const void __iomem *addr);
diff --git a/drivers/gpu/drm/msm/msm_prop.c b/drivers/gpu/drm/msm/msm_prop.c
index 663781f..f2996dd 100644
--- a/drivers/gpu/drm/msm/msm_prop.c
+++ b/drivers/gpu/drm/msm/msm_prop.c
@@ -371,6 +371,18 @@
return rc;
}
+int msm_property_set_dirty(struct msm_property_info *info, int property_idx)
+{
+ if (!info) {
+ DRM_ERROR("invalid property info\n");
+ return -EINVAL;
+ }
+ mutex_lock(&info->property_lock);
+ _msm_property_set_dirty_no_lock(info, property_idx);
+ mutex_unlock(&info->property_lock);
+ return 0;
+}
+
int msm_property_atomic_set(struct msm_property_info *info,
uint64_t *property_values,
struct drm_property_blob **property_blobs,
diff --git a/drivers/gpu/drm/msm/msm_prop.h b/drivers/gpu/drm/msm/msm_prop.h
index dbe28bd..e54c796 100644
--- a/drivers/gpu/drm/msm/msm_prop.h
+++ b/drivers/gpu/drm/msm/msm_prop.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -266,6 +266,14 @@
struct drm_property *property);
/**
+ * msm_property_set_dirty - forcibly flag a property as dirty
+ * @info: Pointer to property info container struct
+ * @property_idx: Property index
+ * Returns: Zero on success
+ */
+int msm_property_set_dirty(struct msm_property_info *info, int property_idx);
+
+/**
* msm_property_atomic_set - helper function for atomic property set callback
* @info: Pointer to property info container struct
* @property_values: Pointer to property values cache array
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index 0b4dd82..09882cd 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -530,6 +530,7 @@
struct split_pipe_cfg cfg = { 0 };
struct sde_hw_mdp *hw_mdptop;
enum sde_rm_topology_name topology;
+ struct msm_display_info *disp_info;
if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
SDE_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
@@ -538,6 +539,10 @@
sde_enc = to_sde_encoder_virt(phys_enc->parent);
hw_mdptop = phys_enc->hw_mdptop;
+ disp_info = &sde_enc->disp_info;
+
+ if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
+ return;
/**
* disable split modes since encoder will be operating in as the only
@@ -1164,15 +1169,11 @@
struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
{
struct sde_encoder_virt *sde_enc;
- struct msm_display_info *disp_info;
if (!drm_enc)
return NULL;
-
sde_enc = to_sde_encoder_virt(drm_enc);
- disp_info = &sde_enc->disp_info;
-
- return disp_info->is_primary ? sde_enc->rsc_client : NULL;
+ return sde_enc->rsc_client;
}
static void _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
index bc1b1e7..9fd5992 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
@@ -1223,8 +1223,8 @@
};
struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
- void __iomem *addr,
- struct sde_mdss_cfg *catalog)
+ void __iomem *addr, struct sde_mdss_cfg *catalog,
+ bool is_virtual_pipe)
{
struct sde_hw_pipe *hw_pipe;
struct sde_sspp_cfg *cfg;
@@ -1256,12 +1256,13 @@
goto blk_init_error;
}
- sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
+ if (!is_virtual_pipe)
+ sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
hw_pipe->hw.blk_off,
hw_pipe->hw.blk_off + hw_pipe->hw.length,
hw_pipe->hw.xin_id);
- if (cfg->sblk->scaler_blk.len)
+ if (cfg->sblk->scaler_blk.len && !is_virtual_pipe)
sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
cfg->sblk->scaler_blk.name,
hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base,
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
index e4be055..8d14715 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
@@ -649,10 +649,11 @@
* @idx: Pipe index for which driver object is required
* @addr: Mapped register io address of MDP
* @catalog : Pointer to mdss catalog data
+ * @is_virtual_pipe: is this pipe virtual pipe
*/
struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx,
- void __iomem *addr,
- struct sde_mdss_cfg *catalog);
+ void __iomem *addr, struct sde_mdss_cfg *catalog,
+ bool is_virtual_pipe);
/**
* sde_hw_sspp_destroy(): Destroys SSPP driver context
diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c
index bda89cf..26125d8 100644
--- a/drivers/gpu/drm/msm/sde/sde_kms.c
+++ b/drivers/gpu/drm/msm/sde/sde_kms.c
@@ -1462,43 +1462,6 @@
return ret;
}
-static void __iomem *_sde_kms_ioremap(struct platform_device *pdev,
- const char *name, unsigned long *out_size)
-{
- struct resource *res;
- unsigned long size;
- void __iomem *ptr;
-
- if (out_size)
- *out_size = 0;
-
- if (name)
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
- else
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
- if (!res) {
- /* availability depends on platform */
- SDE_DEBUG("failed to get memory resource: %s\n", name);
- return ERR_PTR(-EINVAL);
- }
-
- size = resource_size(res);
-
- ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
- if (!ptr) {
- SDE_ERROR("failed to ioremap: %s\n", name);
- return ERR_PTR(-ENOMEM);
- }
-
- SDE_DEBUG("IO:region %s %p %08lx\n", name, ptr, size);
-
- if (out_size)
- *out_size = size;
-
- return ptr;
-}
-
static void sde_kms_handle_power_event(u32 event_type, void *usr)
{
struct sde_kms *sde_kms = usr;
@@ -1535,8 +1498,7 @@
goto end;
}
- sde_kms->mmio = _sde_kms_ioremap(dev->platformdev, "mdp_phys",
- &sde_kms->mmio_len);
+ sde_kms->mmio = msm_ioremap(dev->platformdev, "mdp_phys", "mdp_phys");
if (IS_ERR(sde_kms->mmio)) {
rc = PTR_ERR(sde_kms->mmio);
SDE_ERROR("mdp register memory map failed: %d\n", rc);
@@ -1544,32 +1506,36 @@
goto error;
}
DRM_INFO("mapped mdp address space @%p\n", sde_kms->mmio);
+ sde_kms->mmio_len = msm_iomap_size(dev->platformdev, "mdp_phys");
rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
sde_kms->mmio_len);
if (rc)
SDE_ERROR("dbg base register kms failed: %d\n", rc);
- sde_kms->vbif[VBIF_RT] = _sde_kms_ioremap(dev->platformdev, "vbif_phys",
- &sde_kms->vbif_len[VBIF_RT]);
+ sde_kms->vbif[VBIF_RT] = msm_ioremap(dev->platformdev, "vbif_phys",
+ "vbif_phys");
if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
SDE_ERROR("vbif register memory map failed: %d\n", rc);
sde_kms->vbif[VBIF_RT] = NULL;
goto error;
}
-
+ sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(dev->platformdev,
+ "vbif_phys");
rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
sde_kms->vbif_len[VBIF_RT]);
if (rc)
SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
- sde_kms->vbif[VBIF_NRT] = _sde_kms_ioremap(dev->platformdev,
- "vbif_nrt_phys", &sde_kms->vbif_len[VBIF_NRT]);
+ sde_kms->vbif[VBIF_NRT] = msm_ioremap(dev->platformdev, "vbif_nrt_phys",
+ "vbif_nrt_phys");
if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
sde_kms->vbif[VBIF_NRT] = NULL;
SDE_DEBUG("VBIF NRT is not defined");
} else {
+ sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(dev->platformdev,
+ "vbif_nrt_phys");
rc = sde_dbg_reg_register_base("vbif_nrt",
sde_kms->vbif[VBIF_NRT],
sde_kms->vbif_len[VBIF_NRT]);
@@ -1578,19 +1544,20 @@
rc);
}
- sde_kms->reg_dma = _sde_kms_ioremap(dev->platformdev, "regdma_phys",
- &sde_kms->reg_dma_len);
+ sde_kms->reg_dma = msm_ioremap(dev->platformdev, "regdma_phys",
+ "regdma_phys");
if (IS_ERR(sde_kms->reg_dma)) {
sde_kms->reg_dma = NULL;
SDE_DEBUG("REG_DMA is not defined");
} else {
+ sde_kms->reg_dma_len = msm_iomap_size(dev->platformdev,
+ "regdma_phys");
rc = sde_dbg_reg_register_base("vbif_nrt",
sde_kms->reg_dma,
sde_kms->reg_dma_len);
if (rc)
SDE_ERROR("dbg base register reg_dma failed: %d\n",
rc);
-
}
sde_kms->core_client = sde_power_client_create(&priv->phandle, "core");
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index 6b8a9b9..2a98af4 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -1623,7 +1623,12 @@
attached_pstate = to_sde_plane_state(attached_state);
attached_rstate = &attached_pstate->rot;
- if (attached_rstate->rot_hw != rstate->rot_hw)
+ if (attached_state->fb != state->fb)
+ continue;
+
+ if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) !=
+ sde_plane_get_property(attached_pstate,
+ PLANE_PROP_ROTATION))
continue;
found++;
@@ -1892,6 +1897,46 @@
}
/**
+ * _sde_plane_rot_get_fb - attempt to get previously allocated fb/fbo
+ * If an fb/fbo was already created, either from a previous frame or
+ * from another plane in the current commit cycle, attempt to reuse
+ * it for this commit cycle as well.
+ * @plane: Pointer to drm plane
+ * @cstate: Pointer to crtc state
+ * @rstate: Pointer to rotator plane state
+ */
+static void _sde_plane_rot_get_fb(struct drm_plane *plane,
+ struct drm_crtc_state *cstate,
+ struct sde_plane_rot_state *rstate)
+{
+ struct sde_kms_fbo *fbo;
+ struct drm_framebuffer *fb;
+
+ if (!plane || !cstate || !rstate)
+ return;
+
+ fbo = sde_crtc_res_get(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
+ (u64) &rstate->rot_hw->base);
+ fb = sde_crtc_res_get(cstate, SDE_CRTC_RES_ROT_OUT_FB,
+ (u64) &rstate->rot_hw->base);
+ if (fb && fbo) {
+ SDE_DEBUG("plane%d.%d get fb/fbo\n", plane->base.id,
+ rstate->sequence_id);
+ } else if (fbo) {
+ sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
+ (u64) &rstate->rot_hw->base);
+ fbo = NULL;
+ } else if (fb) {
+ sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FB,
+ (u64) &rstate->rot_hw->base);
+ fb = NULL;
+ }
+
+ rstate->out_fbo = fbo;
+ rstate->out_fb = fb;
+}
+
+/**
* sde_plane_rot_prepare_fb - prepare framebuffer of the new state
* for rotator (pre-sspp) stage
* @plane: Pointer to drm plane
@@ -1927,30 +1972,8 @@
sde_plane_rot_calc_cfg(plane, new_state);
/* check if stream buffer is already attached to rotator */
- if (sde_plane_enabled(new_state)) {
- struct sde_kms_fbo *fbo;
- struct drm_framebuffer *fb;
-
- fbo = sde_crtc_res_get(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
- (u64) &new_rstate->rot_hw->base);
- fb = sde_crtc_res_get(cstate, SDE_CRTC_RES_ROT_OUT_FB,
- (u64) &new_rstate->rot_hw->base);
- if (fb && fbo) {
- SDE_DEBUG("plane%d.%d get fb/fbo\n", plane->base.id,
- new_rstate->sequence_id);
- } else if (fbo) {
- sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FBO,
- (u64) &new_rstate->rot_hw->base);
- fbo = NULL;
- } else if (fb) {
- sde_crtc_res_put(cstate, SDE_CRTC_RES_ROT_OUT_FB,
- (u64) &new_rstate->rot_hw->base);
- fb = NULL;
- }
-
- new_rstate->out_fbo = fbo;
- new_rstate->out_fb = fb;
- }
+ if (sde_plane_enabled(new_state) && !new_rstate->out_fb)
+ _sde_plane_rot_get_fb(plane, cstate, new_rstate);
/* release buffer if output format configuration changes */
if (new_rstate->out_fb &&
@@ -2199,6 +2222,10 @@
sde_plane_rot_calc_cfg(plane, state);
+ /* attempt to reuse stream buffer if already available */
+ if (sde_plane_enabled(state))
+ _sde_plane_rot_get_fb(plane, cstate, rstate);
+
ret = sde_plane_rot_submit_command(plane, state,
SDE_HW_ROT_CMD_VALIDATE);
@@ -2831,7 +2858,7 @@
"req %d/%d, fetch %d/%d, src %dx%d\n",
hor_req_pixels, vert_req_pixels,
hor_fetch_pixels, vert_fetch_pixels,
- src_w, src_h);
+ img_w, img_h);
return -EINVAL;
}
@@ -3537,7 +3564,7 @@
}
if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
- msm_property_install_volatile_range(
+ msm_property_install_range(
&psde->property_info, "scaler_v2",
0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
msm_property_install_blob(&psde->property_info,
@@ -3549,7 +3576,7 @@
"lut_sep", 0,
PLANE_PROP_SCALER_LUT_SEP);
} else if (psde->features & SDE_SSPP_SCALER) {
- msm_property_install_volatile_range(
+ msm_property_install_range(
&psde->property_info, "scaler_v1", 0x0,
0, ~0, 0, PLANE_PROP_SCALER_V1);
}
@@ -3754,6 +3781,9 @@
return;
}
+ /* force property to be dirty, even if the pointer didn't change */
+ msm_property_set_dirty(&psde->property_info, PLANE_PROP_SCALER_V1);
+
/* populate from user space */
pe = &(psde->pixel_ext);
memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
@@ -3817,6 +3847,9 @@
return;
}
+ /* force property to be dirty, even if the pointer didn't change */
+ msm_property_set_dirty(&psde->property_info, PLANE_PROP_SCALER_V2);
+
/* populate from user space */
pe = &(psde->pixel_ext);
memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
@@ -4460,7 +4493,8 @@
}
/* initialize underlying h/w driver */
- psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
+ psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog,
+ master_plane_id != 0);
if (IS_ERR(psde->pipe_hw)) {
SDE_ERROR("[%u]SSPP init failed\n", pipe);
ret = PTR_ERR(psde->pipe_hw);
diff --git a/drivers/gpu/drm/msm/sde_dbg.c b/drivers/gpu/drm/msm/sde_dbg.c
index a420ffb..bcd3eaa 100644
--- a/drivers/gpu/drm/msm/sde_dbg.c
+++ b/drivers/gpu/drm/msm/sde_dbg.c
@@ -160,6 +160,7 @@
* @enable_reg_dump: whether to dump registers into memory, kernel log, or both
* @dbgbus_sde: debug bus structure for the sde
* @dbgbus_vbif_rt: debug bus structure for the realtime vbif
+ * @dump_all: dump all entries in register dump
*/
static struct sde_dbg_base {
struct sde_dbg_evtlog *evtlog;
@@ -176,6 +177,7 @@
struct sde_dbg_sde_debug_bus dbgbus_sde;
struct sde_dbg_vbif_debug_bus dbgbus_vbif_rt;
+ bool dump_all;
} sde_dbg_base;
/* sde_dbg_base_evtlog - global pointer to main sde event log for macro use */
@@ -2427,18 +2429,22 @@
*/
static void _sde_dump_array(struct sde_dbg_reg_base *blk_arr[],
u32 len, bool do_panic, const char *name, bool dump_dbgbus_sde,
- bool dump_dbgbus_vbif_rt)
+ bool dump_dbgbus_vbif_rt, bool dump_all)
{
int i;
- for (i = 0; i < len; i++) {
- if (blk_arr[i] != NULL)
- _sde_dump_reg_by_ranges(blk_arr[i],
- sde_dbg_base.enable_reg_dump);
- }
-
sde_evtlog_dump_all(sde_dbg_base.evtlog);
+ if (dump_all || !blk_arr || !len) {
+ _sde_dump_reg_all();
+ } else {
+ for (i = 0; i < len; i++) {
+ if (blk_arr[i] != NULL)
+ _sde_dump_reg_by_ranges(blk_arr[i],
+ sde_dbg_base.enable_reg_dump);
+ }
+ }
+
if (dump_dbgbus_sde)
_sde_dbg_dump_sde_dbg_bus(&sde_dbg_base.dbgbus_sde);
@@ -2459,7 +2465,8 @@
ARRAY_SIZE(sde_dbg_base.req_dump_blks),
sde_dbg_base.work_panic, "evtlog_workitem",
sde_dbg_base.dbgbus_sde.cmn.include_in_deferred_work,
- sde_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work);
+ sde_dbg_base.dbgbus_vbif_rt.cmn.include_in_deferred_work,
+ sde_dbg_base.dump_all);
}
void sde_dbg_dump(bool queue_work, const char *name, ...)
@@ -2468,6 +2475,7 @@
bool do_panic = false;
bool dump_dbgbus_sde = false;
bool dump_dbgbus_vbif_rt = false;
+ bool dump_all = false;
va_list args;
char *blk_name = NULL;
struct sde_dbg_reg_base *blk_base = NULL;
@@ -2485,6 +2493,7 @@
memset(sde_dbg_base.req_dump_blks, 0,
sizeof(sde_dbg_base.req_dump_blks));
+ sde_dbg_base.dump_all = false;
va_start(args, name);
i = 0;
@@ -2507,6 +2516,9 @@
}
}
+ if (!strcmp(blk_name, "all"))
+ dump_all = true;
+
if (!strcmp(blk_name, "dbg_bus"))
dump_dbgbus_sde = true;
@@ -2528,7 +2540,7 @@
schedule_work(&sde_dbg_base.dump_work);
} else {
_sde_dump_array(blk_arr, blk_len, do_panic, name,
- dump_dbgbus_sde, dump_dbgbus_vbif_rt);
+ dump_dbgbus_sde, dump_dbgbus_vbif_rt, dump_all);
}
}
@@ -2577,15 +2589,8 @@
static ssize_t sde_evtlog_dump_write(struct file *file,
const char __user *user_buf, size_t count, loff_t *ppos)
{
- _sde_dump_reg_all();
-
- sde_evtlog_dump_all(sde_dbg_base.evtlog);
-
- _sde_dbg_dump_sde_dbg_bus(&sde_dbg_base.dbgbus_sde);
- _sde_dbg_dump_vbif_dbg_bus(&sde_dbg_base.dbgbus_vbif_rt);
-
- if (sde_dbg_base.panic_on_err)
- panic("sde");
+ _sde_dump_array(NULL, 0, sde_dbg_base.panic_on_err, "dump_debugfs",
+ true, true, true);
return count;
}
@@ -3030,6 +3035,26 @@
return 0;
}
+static void sde_dbg_reg_base_destroy(void)
+{
+ struct sde_dbg_reg_range *range_node, *range_tmp;
+ struct sde_dbg_reg_base *blk_base, *blk_tmp;
+ struct sde_dbg_base *dbg_base = &sde_dbg_base;
+
+ if (!dbg_base)
+ return;
+
+ list_for_each_entry_safe(blk_base, blk_tmp, &dbg_base->reg_base_list,
+ reg_base_head) {
+ list_for_each_entry_safe(range_node, range_tmp,
+ &blk_base->sub_range_list, head) {
+ list_del(&range_node->head);
+ kfree(range_node);
+ }
+ list_del(&blk_base->reg_base_head);
+ kfree(blk_base);
+ }
+}
/**
* sde_dbg_destroy - destroy sde debug facilities
*/
@@ -3039,6 +3064,7 @@
sde_dbg_base_evtlog = NULL;
sde_evtlog_destroy(sde_dbg_base.evtlog);
sde_dbg_base.evtlog = NULL;
+ sde_dbg_reg_base_destroy();
}
int sde_dbg_reg_register_base(const char *name, void __iomem *base,
diff --git a/drivers/gpu/drm/msm/sde_rsc.c b/drivers/gpu/drm/msm/sde_rsc.c
index 8447916..9730f0b 100644
--- a/drivers/gpu/drm/msm/sde_rsc.c
+++ b/drivers/gpu/drm/msm/sde_rsc.c
@@ -30,6 +30,9 @@
#include "sde_rsc_priv.h"
#include "sde_dbg.h"
+#define SDE_RSC_DRV_DBG_NAME "sde_rsc_drv"
+#define SDE_RSC_WRAPPER_DBG_NAME "sde_rsc_wrapper"
+
/* worst case time to execute the one tcs vote(sleep/wake) - ~1ms */
#define SINGLE_TCS_EXECUTION_TIME 1064000
@@ -668,8 +671,6 @@
{
int rc = 0;
struct sde_rsc_priv *rsc;
- bool amc_mode = false;
- enum rpmh_state state;
if (!caller_client) {
pr_err("invalid client for ab/ib vote\n");
@@ -683,11 +684,6 @@
if (!rsc)
return -EINVAL;
- if (caller_client != rsc->primary_client) {
- pr_err("only primary client can use sde rsc:: curr client name:%s\n",
- caller_client->name);
- return -EINVAL;
- }
pr_debug("client:%s ab:%llu ib:%llu\n",
caller_client->name, ab_vote, ib_vote);
@@ -696,16 +692,6 @@
if (rc)
goto clk_enable_fail;
- if (rsc->hw_ops.is_amc_mode)
- amc_mode = rsc->hw_ops.is_amc_mode(rsc);
-
- if (rsc->current_state == SDE_RSC_CMD_STATE)
- state = RPMH_WAKE_ONLY_STATE;
- else if (amc_mode)
- state = RPMH_ACTIVE_ONLY_STATE;
- else
- state = RPMH_AWAKE_STATE;
-
if (rsc->hw_ops.tcs_wait) {
rc = rsc->hw_ops.tcs_wait(rsc);
if (rc) {
@@ -1065,6 +1051,10 @@
rsc->master_drm = drm;
mutex_unlock(&rsc->client_lock);
+ sde_dbg_reg_register_base(SDE_RSC_DRV_DBG_NAME, rsc->drv_io.base,
+ rsc->drv_io.len);
+ sde_dbg_reg_register_base(SDE_RSC_WRAPPER_DBG_NAME,
+ rsc->wrapper_io.base, rsc->wrapper_io.len);
return 0;
}
diff --git a/drivers/gpu/msm/Makefile b/drivers/gpu/msm/Makefile
index f513207..0058226 100644
--- a/drivers/gpu/msm/Makefile
+++ b/drivers/gpu/msm/Makefile
@@ -38,6 +38,7 @@
adreno_a6xx_snapshot.o \
adreno_a4xx_preempt.o \
adreno_a5xx_preempt.o \
+ adreno_a6xx_preempt.o \
adreno_sysfs.o \
adreno.o \
adreno_cp_parser.o \
diff --git a/drivers/gpu/msm/a6xx_reg.h b/drivers/gpu/msm/a6xx_reg.h
index 58ef5ee..f4552b6 100644
--- a/drivers/gpu/msm/a6xx_reg.h
+++ b/drivers/gpu/msm/a6xx_reg.h
@@ -70,6 +70,15 @@
#define A6XX_CP_ADDR_MODE_CNTL 0x842
#define A6XX_CP_PROTECT_CNTL 0x84F
#define A6XX_CP_PROTECT_REG 0x850
+#define A6XX_CP_CONTEXT_SWITCH_CNTL 0x8A0
+#define A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x8A1
+#define A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x8A2
+#define A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x8A3
+#define A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x8A4
+#define A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x8A5
+#define A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x8A6
+#define A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x8A7
+#define A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x8A8
#define A6XX_CP_PERFCTR_CP_SEL_0 0x8D0
#define A6XX_CP_PERFCTR_CP_SEL_1 0x8D1
#define A6XX_CP_PERFCTR_CP_SEL_2 0x8D2
@@ -590,6 +599,7 @@
#define A6XX_RB_PERFCTR_CMP_SEL_1 0x8E2D
#define A6XX_RB_PERFCTR_CMP_SEL_2 0x8E2E
#define A6XX_RB_PERFCTR_CMP_SEL_3 0x8E2F
+#define A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x8E50
/* PC registers */
#define A6XX_PC_DBG_ECO_CNTL 0x9E00
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 7a6581c..c7e3ad7 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -845,11 +845,14 @@
unsigned int *cmds,
struct kgsl_context *context);
int (*preemption_yield_enable)(unsigned int *);
+ unsigned int (*preemption_set_marker)(unsigned int *cmds, int start);
unsigned int (*preemption_post_ibsubmit)(
struct adreno_device *adreno_dev,
unsigned int *cmds);
int (*preemption_init)(struct adreno_device *);
void (*preemption_schedule)(struct adreno_device *);
+ int (*preemption_context_init)(struct kgsl_context *);
+ void (*preemption_context_destroy)(struct kgsl_context *);
void (*enable_64bit)(struct adreno_device *);
void (*clk_set_options)(struct adreno_device *,
const char *, struct clk *, bool on);
diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c
index 3cbb68e..fb745ad 100644
--- a/drivers/gpu/msm/adreno_a6xx.c
+++ b/drivers/gpu/msm/adreno_a6xx.c
@@ -29,9 +29,6 @@
#include "kgsl_gmu.h"
#include "kgsl_trace.h"
-#define A6XX_CP_RB_CNTL_DEFAULT (((ilog2(4) << 8) & 0x1F00) | \
- (ilog2(KGSL_RB_DWORDS >> 1) & 0x3F))
-
#define MIN_HBB 13
#define A6XX_LLC_NUM_GPU_SCIDS 5
@@ -79,10 +76,10 @@
{A6XX_RBBM_CLOCK_HYST_SP1, 0x00000080},
{A6XX_RBBM_CLOCK_HYST_SP2, 0x00000080},
{A6XX_RBBM_CLOCK_HYST_SP3, 0x00000080},
- {A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
- {A6XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},
- {A6XX_RBBM_CLOCK_CNTL_TP2, 0x22222222},
- {A6XX_RBBM_CLOCK_CNTL_TP3, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+ {A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
+ {A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
+ {A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
{A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
{A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
@@ -482,6 +479,12 @@
if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_TWO_PASS_USE_WFI))
kgsl_regrmw(device, A6XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
+ /* Enable the GMEM save/restore feature for preemption */
+ if (adreno_is_preemption_enabled(adreno_dev))
+ kgsl_regwrite(device, A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE,
+ 0x1);
+
+ a6xx_preemption_start(adreno_dev);
a6xx_protect_init(adreno_dev);
}
@@ -612,6 +615,70 @@
}
/*
+ * Follow the ME_INIT sequence with a preemption yield to allow the GPU to move
+ * to a different ringbuffer, if desired
+ */
+static int _preemption_init(struct adreno_device *adreno_dev,
+ struct adreno_ringbuffer *rb, unsigned int *cmds,
+ struct kgsl_context *context)
+{
+ unsigned int *cmds_orig = cmds;
+
+ /* Turn CP protection OFF */
+ *cmds++ = cp_type7_packet(CP_SET_PROTECTED_MODE, 1);
+ *cmds++ = 0;
+
+ *cmds++ = cp_type7_packet(CP_SET_PSEUDO_REGISTER, 6);
+ *cmds++ = 1;
+ cmds += cp_gpuaddr(adreno_dev, cmds,
+ rb->preemption_desc.gpuaddr);
+
+ *cmds++ = 2;
+ cmds += cp_gpuaddr(adreno_dev, cmds, 0);
+
+ /* Turn CP protection ON */
+ *cmds++ = cp_type7_packet(CP_SET_PROTECTED_MODE, 1);
+ *cmds++ = 1;
+
+ *cmds++ = cp_type7_packet(CP_CONTEXT_SWITCH_YIELD, 4);
+ cmds += cp_gpuaddr(adreno_dev, cmds, 0x0);
+ *cmds++ = 0;
+ /* generate interrupt on preemption completion */
+ *cmds++ = 0;
+
+ return cmds - cmds_orig;
+}
+
+static int a6xx_post_start(struct adreno_device *adreno_dev)
+{
+ int ret;
+ unsigned int *cmds, *start;
+ struct adreno_ringbuffer *rb = adreno_dev->cur_rb;
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+
+ if (!adreno_is_preemption_enabled(adreno_dev))
+ return 0;
+
+ cmds = adreno_ringbuffer_allocspace(rb, 42);
+ if (IS_ERR(cmds)) {
+ KGSL_DRV_ERR(device, "error allocating preemption init cmds");
+ return PTR_ERR(cmds);
+ }
+ start = cmds;
+
+ cmds += _preemption_init(adreno_dev, rb, cmds, NULL);
+
+ rb->_wptr = rb->_wptr - (42 - (cmds - start));
+
+ ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000);
+ if (ret)
+ adreno_spin_idle_debug(adreno_dev,
+ "hw preemption initialization failed to idle\n");
+
+ return ret;
+}
+
+/*
* a6xx_rb_start() - Start the ringbuffer
* @adreno_dev: Pointer to adreno device
* @start_type: Warm or cold start
@@ -651,7 +718,11 @@
return ret;
/* GPU comes up in secured mode, make it unsecured by default */
- return adreno_set_unsecured_mode(adreno_dev, rb);
+ ret = adreno_set_unsecured_mode(adreno_dev, rb);
+ if (ret)
+ return ret;
+
+ return a6xx_post_start(adreno_dev);
}
static int _load_firmware(struct kgsl_device *device, const char *fwfile,
@@ -1345,6 +1416,8 @@
int ret, i;
switch (boot_state) {
+ case GMU_RESET:
+ /* fall through */
case GMU_COLD_BOOT:
/* Turn on the HM and SPTP head switches */
ret = a6xx_hm_sptprac_enable(device);
@@ -1360,6 +1433,10 @@
ret = a6xx_hm_sptprac_enable(device);
if (ret)
return ret;
+ } else if (boot_state == GMU_RESET) {
+ ret = a6xx_hm_sptprac_enable(device);
+ if (ret)
+ return ret;
} else {
ret = a6xx_rpmh_power_on_gpu(device);
if (ret)
@@ -1387,11 +1464,6 @@
if (ret)
return ret;
break;
- case GMU_RESET:
- /* Turn on the HM and SPTP head switches */
- ret = a6xx_hm_sptprac_enable(device);
- if (ret)
- return ret;
default:
break;
}
@@ -2086,7 +2158,7 @@
/* 6 - RBBM_ATB_ASYNC_OVERFLOW */
ADRENO_IRQ_CALLBACK(a6xx_err_callback),
ADRENO_IRQ_CALLBACK(NULL), /* 7 - GPC_ERR */
- ADRENO_IRQ_CALLBACK(NULL),/* 8 - CP_SW */
+ ADRENO_IRQ_CALLBACK(a6xx_preemption_callback),/* 8 - CP_SW */
ADRENO_IRQ_CALLBACK(a6xx_cp_hw_err_callback), /* 9 - CP_HW_ERROR */
ADRENO_IRQ_CALLBACK(NULL), /* 10 - CP_CCU_FLUSH_DEPTH_TS */
ADRENO_IRQ_CALLBACK(NULL), /* 11 - CP_CCU_FLUSH_COLOR_TS */
@@ -2580,6 +2652,11 @@
ADRENO_REG_DEFINE(ADRENO_REG_CP_IB2_BUFSZ, A6XX_CP_IB2_REM_SIZE),
ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_ADDR, A6XX_CP_ROQ_DBG_ADDR),
ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_DATA, A6XX_CP_ROQ_DBG_DATA),
+ ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT, A6XX_CP_CONTEXT_SWITCH_CNTL),
+ ADRENO_REG_DEFINE(ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_LO,
+ A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO),
+ ADRENO_REG_DEFINE(ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI,
+ A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI),
ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A6XX_RBBM_STATUS),
ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS3, A6XX_RBBM_STATUS3),
ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_CTL, A6XX_RBBM_PERFCTR_CNTL),
@@ -2693,4 +2770,11 @@
.iommu_fault_block = a6xx_iommu_fault_block,
.reset = a6xx_reset,
.soft_reset = a6xx_soft_reset,
+ .preemption_pre_ibsubmit = a6xx_preemption_pre_ibsubmit,
+ .preemption_post_ibsubmit = a6xx_preemption_post_ibsubmit,
+ .preemption_init = a6xx_preemption_init,
+ .preemption_schedule = a6xx_preemption_schedule,
+ .preemption_set_marker = a6xx_preemption_set_marker,
+ .preemption_context_init = a6xx_preemption_context_init,
+ .preemption_context_destroy = a6xx_preemption_context_destroy,
};
diff --git a/drivers/gpu/msm/adreno_a6xx.h b/drivers/gpu/msm/adreno_a6xx.h
index 4b96f56..ddf89d6 100644
--- a/drivers/gpu/msm/adreno_a6xx.h
+++ b/drivers/gpu/msm/adreno_a6xx.h
@@ -23,10 +23,93 @@
#define CP_CLUSTER_SP_PS 0x4
#define CP_CLUSTER_PS 0x5
+/**
+ * struct a6xx_cp_preemption_record - CP context record for
+ * preemption.
+ * @magic: (00) Value at this offset must be equal to
+ * A6XX_CP_CTXRECORD_MAGIC_REF.
+ * @info: (04) Type of record. Written non-zero (usually) by CP.
+ * we must set to zero for all ringbuffers.
+ * @errno: (08) Error code. Initialize this to A6XX_CP_CTXRECORD_ERROR_NONE.
+ * CP will update to another value if a preemption error occurs.
+ * @data: (12) DATA field in YIELD and SET_MARKER packets.
+ * Written by CP when switching out. Not used on switch-in. Initialized to 0.
+ * @cntl: (16) RB_CNTL, saved and restored by CP. We must initialize this.
+ * @rptr: (20) RB_RPTR, saved and restored by CP. We must initialize this.
+ * @wptr: (24) RB_WPTR, saved and restored by CP. We must initialize this.
+ * @_pad28: (28) Reserved/padding.
+ * @rptr_addr: (32) RB_RPTR_ADDR_LO|HI saved and restored. We must initialize.
+ * rbase: (40) RB_BASE_LO|HI saved and restored.
+ * counter: (48) Pointer to preemption counter.
+ */
+struct a6xx_cp_preemption_record {
+ uint32_t magic;
+ uint32_t info;
+ uint32_t errno;
+ uint32_t data;
+ uint32_t cntl;
+ uint32_t rptr;
+ uint32_t wptr;
+ uint32_t _pad28;
+ uint64_t rptr_addr;
+ uint64_t rbase;
+ uint64_t counter;
+};
+
+/**
+ * struct a6xx_cp_smmu_info - CP preemption SMMU info.
+ * @magic: (00) The value at this offset must be equal to
+ * A6XX_CP_SMMU_INFO_MAGIC_REF.
+ * @_pad4: (04) Reserved/padding
+ * @ttbr0: (08) Base address of the page table for the
+ * incoming context.
+ * @context_idr: (16) Context Identification Register value.
+ */
+struct a6xx_cp_smmu_info {
+ uint32_t magic;
+ uint32_t _pad4;
+ uint64_t ttbr0;
+ uint32_t asid;
+ uint32_t context_idr;
+};
+
+#define A6XX_CP_SMMU_INFO_MAGIC_REF 0x3618CDA3UL
+
+#define A6XX_CP_CTXRECORD_MAGIC_REF 0xAE399D6EUL
+/* Size of each CP preemption record */
+#define A6XX_CP_CTXRECORD_SIZE_IN_BYTES (2112 * 1024)
+/* Size of the preemption counter block (in bytes) */
+#define A6XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE (16 * 4)
+/* Size of the user context record block (in bytes) */
+#define A6XX_CP_CTXRECORD_USER_RESTORE_SIZE (192 * 1024)
+/* Size of the performance counter save/restore block (in bytes) */
+#define A6XX_CP_PERFCOUNTER_SAVE_RESTORE_SIZE (4 * 1024)
+
+#define A6XX_CP_RB_CNTL_DEFAULT (((ilog2(4) << 8) & 0x1F00) | \
+ (ilog2(KGSL_RB_DWORDS >> 1) & 0x3F))
+
+/* Preemption functions */
+void a6xx_preemption_trigger(struct adreno_device *adreno_dev);
+void a6xx_preemption_schedule(struct adreno_device *adreno_dev);
+void a6xx_preemption_start(struct adreno_device *adreno_dev);
+int a6xx_preemption_init(struct adreno_device *adreno_dev);
+
+unsigned int a6xx_preemption_post_ibsubmit(struct adreno_device *adreno_dev,
+ unsigned int *cmds);
+unsigned int a6xx_preemption_pre_ibsubmit(struct adreno_device *adreno_dev,
+ struct adreno_ringbuffer *rb,
+ unsigned int *cmds, struct kgsl_context *context);
+
+unsigned int a6xx_preemption_set_marker(unsigned int *cmds, int start);
+
+void a6xx_preemption_callback(struct adreno_device *adreno_dev, int bit);
+
+int a6xx_preemption_context_init(struct kgsl_context *context);
+
+void a6xx_preemption_context_destroy(struct kgsl_context *context);
void a6xx_snapshot(struct adreno_device *adreno_dev,
struct kgsl_snapshot *snapshot);
void a6xx_crashdump_init(struct adreno_device *adreno_dev);
-
#endif
diff --git a/drivers/gpu/msm/adreno_a6xx_preempt.c b/drivers/gpu/msm/adreno_a6xx_preempt.c
new file mode 100644
index 0000000..00325e5
--- /dev/null
+++ b/drivers/gpu/msm/adreno_a6xx_preempt.c
@@ -0,0 +1,654 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "adreno.h"
+#include "adreno_a6xx.h"
+#include "a6xx_reg.h"
+#include "adreno_trace.h"
+#include "adreno_pm4types.h"
+
+#define PREEMPT_RECORD(_field) \
+ offsetof(struct a6xx_cp_preemption_record, _field)
+
+#define PREEMPT_SMMU_RECORD(_field) \
+ offsetof(struct a6xx_cp_smmu_info, _field)
+
+enum {
+ SET_PSEUDO_REGISTER_SAVE_REGISTER_SMMU_INFO = 0,
+ SET_PSEUDO_REGISTER_SAVE_REGISTER_PRIV_NON_SECURE_SAVE_ADDR,
+ SET_PSEUDO_REGISTER_SAVE_REGISTER_PRIV_SECURE_SAVE_ADDR,
+ SET_PSEUDO_REGISTER_SAVE_REGISTER_NON_PRIV_SAVE_ADDR,
+ SET_PSEUDO_REGISTER_SAVE_REGISTER_COUNTER,
+};
+
+static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer)
+{
+ struct adreno_ringbuffer *rb = adreno_dev->cur_rb;
+ unsigned int wptr;
+ unsigned long flags;
+
+ spin_lock_irqsave(&rb->preempt_lock, flags);
+
+ adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_WPTR, &wptr);
+
+ if (wptr != rb->wptr) {
+ adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_WPTR,
+ rb->wptr);
+ /*
+ * In case something got submitted while preemption was on
+ * going, reset the timer.
+ */
+ reset_timer = true;
+ }
+
+ if (reset_timer)
+ rb->dispatch_q.expires = jiffies +
+ msecs_to_jiffies(adreno_drawobj_timeout);
+
+ spin_unlock_irqrestore(&rb->preempt_lock, flags);
+}
+
+static inline bool adreno_move_preempt_state(struct adreno_device *adreno_dev,
+ enum adreno_preempt_states old, enum adreno_preempt_states new)
+{
+ return (atomic_cmpxchg(&adreno_dev->preempt.state, old, new) == old);
+}
+
+static void _a6xx_preemption_done(struct adreno_device *adreno_dev)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+ unsigned int status;
+
+ /*
+ * In the very unlikely case that the power is off, do nothing - the
+ * state will be reset on power up and everybody will be happy
+ */
+
+ if (!kgsl_state_is_awake(device))
+ return;
+
+ adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT, &status);
+
+ if (status & 0x1) {
+ KGSL_DRV_ERR(device,
+ "Preemption not complete: status=%X cur=%d R/W=%X/%X next=%d R/W=%X/%X\n",
+ status, adreno_dev->cur_rb->id,
+ adreno_get_rptr(adreno_dev->cur_rb),
+ adreno_dev->cur_rb->wptr, adreno_dev->next_rb->id,
+ adreno_get_rptr(adreno_dev->next_rb),
+ adreno_dev->next_rb->wptr);
+
+ /* Set a fault and restart */
+ adreno_set_gpu_fault(adreno_dev, ADRENO_PREEMPT_FAULT);
+ adreno_dispatcher_schedule(device);
+
+ return;
+ }
+
+ del_timer_sync(&adreno_dev->preempt.timer);
+
+ trace_adreno_preempt_done(adreno_dev->cur_rb, adreno_dev->next_rb);
+
+ /* Clean up all the bits */
+ adreno_dev->prev_rb = adreno_dev->cur_rb;
+ adreno_dev->cur_rb = adreno_dev->next_rb;
+ adreno_dev->next_rb = NULL;
+
+ /* Update the wptr for the new command queue */
+ _update_wptr(adreno_dev, true);
+
+ /* Update the dispatcher timer for the new command queue */
+ mod_timer(&adreno_dev->dispatcher.timer,
+ adreno_dev->cur_rb->dispatch_q.expires);
+
+ /* Clear the preempt state */
+ adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
+}
+
+static void _a6xx_preemption_fault(struct adreno_device *adreno_dev)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+ unsigned int status;
+
+ /*
+ * If the power is on check the preemption status one more time - if it
+ * was successful then just transition to the complete state
+ */
+ if (kgsl_state_is_awake(device)) {
+ adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT, &status);
+
+ if (status == 0) {
+ adreno_set_preempt_state(adreno_dev,
+ ADRENO_PREEMPT_COMPLETE);
+
+ adreno_dispatcher_schedule(device);
+ return;
+ }
+ }
+
+ KGSL_DRV_ERR(device,
+ "Preemption timed out: cur=%d R/W=%X/%X, next=%d R/W=%X/%X\n",
+ adreno_dev->cur_rb->id,
+ adreno_get_rptr(adreno_dev->cur_rb), adreno_dev->cur_rb->wptr,
+ adreno_dev->next_rb->id,
+ adreno_get_rptr(adreno_dev->next_rb),
+ adreno_dev->next_rb->wptr);
+
+ adreno_set_gpu_fault(adreno_dev, ADRENO_PREEMPT_FAULT);
+ adreno_dispatcher_schedule(device);
+}
+
+static void _a6xx_preemption_worker(struct work_struct *work)
+{
+ struct adreno_preemption *preempt = container_of(work,
+ struct adreno_preemption, work);
+ struct adreno_device *adreno_dev = container_of(preempt,
+ struct adreno_device, preempt);
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+
+ /* Need to take the mutex to make sure that the power stays on */
+ mutex_lock(&device->mutex);
+
+ if (adreno_in_preempt_state(adreno_dev, ADRENO_PREEMPT_FAULTED))
+ _a6xx_preemption_fault(adreno_dev);
+
+ mutex_unlock(&device->mutex);
+}
+
+static void _a6xx_preemption_timer(unsigned long data)
+{
+ struct adreno_device *adreno_dev = (struct adreno_device *) data;
+
+ /* We should only be here from a triggered state */
+ if (!adreno_move_preempt_state(adreno_dev,
+ ADRENO_PREEMPT_TRIGGERED, ADRENO_PREEMPT_FAULTED))
+ return;
+
+ /* Schedule the worker to take care of the details */
+ queue_work(system_unbound_wq, &adreno_dev->preempt.work);
+}
+
+/* Find the highest priority active ringbuffer */
+static struct adreno_ringbuffer *a6xx_next_ringbuffer(
+ struct adreno_device *adreno_dev)
+{
+ struct adreno_ringbuffer *rb;
+ unsigned long flags;
+ unsigned int i;
+
+ FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
+ bool empty;
+
+ spin_lock_irqsave(&rb->preempt_lock, flags);
+ empty = adreno_rb_empty(rb);
+ spin_unlock_irqrestore(&rb->preempt_lock, flags);
+
+ if (empty == false)
+ return rb;
+ }
+
+ return NULL;
+}
+
+void a6xx_preemption_trigger(struct adreno_device *adreno_dev)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+ struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);
+ struct adreno_ringbuffer *next;
+ uint64_t ttbr0;
+ unsigned int contextidr;
+ unsigned long flags;
+ uint32_t preempt_level = 0, usesgmem = 1, skipsaverestore = 0;
+
+ /* Put ourselves into a possible trigger state */
+ if (!adreno_move_preempt_state(adreno_dev,
+ ADRENO_PREEMPT_NONE, ADRENO_PREEMPT_START))
+ return;
+
+ /* Get the next ringbuffer to preempt in */
+ next = a6xx_next_ringbuffer(adreno_dev);
+
+ /*
+ * Nothing to do if every ringbuffer is empty or if the current
+ * ringbuffer is the only active one
+ */
+ if (next == NULL || next == adreno_dev->cur_rb) {
+ /*
+ * Update any critical things that might have been skipped while
+ * we were looking for a new ringbuffer
+ */
+
+ if (next != NULL) {
+ _update_wptr(adreno_dev, false);
+
+ mod_timer(&adreno_dev->dispatcher.timer,
+ adreno_dev->cur_rb->dispatch_q.expires);
+ }
+
+ adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
+ return;
+ }
+
+ /* Turn off the dispatcher timer */
+ del_timer(&adreno_dev->dispatcher.timer);
+
+ /*
+ * This is the most critical section - we need to take care not to race
+ * until we have programmed the CP for the switch
+ */
+
+ spin_lock_irqsave(&next->preempt_lock, flags);
+
+ /*
+ * Get the pagetable from the pagetable info.
+ * The pagetable_desc is allocated and mapped at probe time, and
+ * preemption_desc at init time, so no need to check if
+ * sharedmem accesses to these memdescs succeed.
+ */
+ kgsl_sharedmem_readq(&next->pagetable_desc, &ttbr0,
+ PT_INFO_OFFSET(ttbr0));
+ kgsl_sharedmem_readl(&next->pagetable_desc, &contextidr,
+ PT_INFO_OFFSET(contextidr));
+
+ kgsl_sharedmem_writel(device, &next->preemption_desc,
+ PREEMPT_RECORD(wptr), next->wptr);
+
+ spin_unlock_irqrestore(&next->preempt_lock, flags);
+
+ /* And write it to the smmu info */
+ kgsl_sharedmem_writeq(device, &iommu->smmu_info,
+ PREEMPT_SMMU_RECORD(ttbr0), ttbr0);
+ kgsl_sharedmem_writel(device, &iommu->smmu_info,
+ PREEMPT_SMMU_RECORD(context_idr), contextidr);
+
+ kgsl_regwrite(device,
+ A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO,
+ lower_32_bits(next->preemption_desc.gpuaddr));
+ kgsl_regwrite(device,
+ A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI,
+ upper_32_bits(next->preemption_desc.gpuaddr));
+
+ if (next->drawctxt_active) {
+ struct kgsl_context *context = &next->drawctxt_active->base;
+ uint64_t gpuaddr = context->user_ctxt_record->memdesc.gpuaddr;
+
+ kgsl_regwrite(device,
+ A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO,
+ lower_32_bits(gpuaddr));
+ kgsl_regwrite(device,
+ A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI,
+ upper_32_bits(gpuaddr));
+ }
+
+ adreno_dev->next_rb = next;
+
+ /* Start the timer to detect a stuck preemption */
+ mod_timer(&adreno_dev->preempt.timer,
+ jiffies + msecs_to_jiffies(ADRENO_PREEMPT_TIMEOUT));
+
+ trace_adreno_preempt_trigger(adreno_dev->cur_rb, adreno_dev->next_rb);
+
+ adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_TRIGGERED);
+
+ /* Trigger the preemption */
+ adreno_writereg(adreno_dev, ADRENO_REG_CP_PREEMPT,
+ ((preempt_level << 6) & 0xC0) |
+ ((skipsaverestore << 9) & 0x200) |
+ ((usesgmem << 8) & 0x100) | 0x1);
+}
+
+void a6xx_preemption_callback(struct adreno_device *adreno_dev, int bit)
+{
+ unsigned int status;
+
+ if (!adreno_move_preempt_state(adreno_dev,
+ ADRENO_PREEMPT_TRIGGERED, ADRENO_PREEMPT_PENDING))
+ return;
+
+ adreno_readreg(adreno_dev, ADRENO_REG_CP_PREEMPT, &status);
+
+ if (status & 0x1) {
+ KGSL_DRV_ERR(KGSL_DEVICE(adreno_dev),
+ "preempt interrupt with non-zero status: %X\n", status);
+
+ /*
+ * Under the assumption that this is a race between the
+ * interrupt and the register, schedule the worker to clean up.
+ * If the status still hasn't resolved itself by the time we get
+ * there then we have to assume something bad happened
+ */
+ adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_COMPLETE);
+ adreno_dispatcher_schedule(KGSL_DEVICE(adreno_dev));
+ return;
+ }
+
+ del_timer(&adreno_dev->preempt.timer);
+
+ trace_adreno_preempt_done(adreno_dev->cur_rb,
+ adreno_dev->next_rb);
+
+ adreno_dev->prev_rb = adreno_dev->cur_rb;
+ adreno_dev->cur_rb = adreno_dev->next_rb;
+ adreno_dev->next_rb = NULL;
+
+ /* Update the wptr if it changed while preemption was ongoing */
+ _update_wptr(adreno_dev, true);
+
+ /* Update the dispatcher timer for the new command queue */
+ mod_timer(&adreno_dev->dispatcher.timer,
+ adreno_dev->cur_rb->dispatch_q.expires);
+
+ adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
+
+ a6xx_preemption_trigger(adreno_dev);
+}
+
+void a6xx_preemption_schedule(struct adreno_device *adreno_dev)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+
+ if (!adreno_is_preemption_enabled(adreno_dev))
+ return;
+
+ mutex_lock(&device->mutex);
+
+ if (adreno_in_preempt_state(adreno_dev, ADRENO_PREEMPT_COMPLETE))
+ _a6xx_preemption_done(adreno_dev);
+
+ a6xx_preemption_trigger(adreno_dev);
+
+ mutex_unlock(&device->mutex);
+}
+
+unsigned int a6xx_preemption_set_marker(unsigned int *cmds, int start)
+{
+ *cmds++ = cp_type7_packet(CP_SET_MARKER, 1);
+
+ /*
+ * Indicate the beginning and end of the IB1 list with a SET_MARKER.
+ * Among other things, this will implicitly enable and disable
+ * preemption respectively.
+ */
+ if (start)
+ *cmds++ = 0xD;
+ else
+ *cmds++ = 0xE;
+
+ return 2;
+}
+
+unsigned int a6xx_preemption_pre_ibsubmit(
+ struct adreno_device *adreno_dev,
+ struct adreno_ringbuffer *rb,
+ unsigned int *cmds, struct kgsl_context *context)
+{
+ unsigned int *cmds_orig = cmds;
+
+ if (context)
+ *cmds++ = cp_type7_packet(CP_SET_PSEUDO_REGISTER, 15);
+ else
+ *cmds++ = cp_type7_packet(CP_SET_PSEUDO_REGISTER, 12);
+
+ /* NULL SMMU_INFO buffer - we track in KMD */
+ *cmds++ = SET_PSEUDO_REGISTER_SAVE_REGISTER_SMMU_INFO;
+ cmds += cp_gpuaddr(adreno_dev, cmds, 0x0);
+
+ *cmds++ = SET_PSEUDO_REGISTER_SAVE_REGISTER_PRIV_NON_SECURE_SAVE_ADDR;
+ cmds += cp_gpuaddr(adreno_dev, cmds, rb->preemption_desc.gpuaddr);
+
+ *cmds++ = SET_PSEUDO_REGISTER_SAVE_REGISTER_PRIV_SECURE_SAVE_ADDR;
+ cmds += cp_gpuaddr(adreno_dev, cmds, 0);
+
+ if (context) {
+ uint64_t gpuaddr = context->user_ctxt_record->memdesc.gpuaddr;
+
+ *cmds++ = SET_PSEUDO_REGISTER_SAVE_REGISTER_NON_PRIV_SAVE_ADDR;
+ cmds += cp_gpuaddr(adreno_dev, cmds, gpuaddr);
+ }
+
+ /*
+ * There is no need to specify this address when we are about to
+ * trigger preemption. This is because CP internally stores this
+ * address specified here in the CP_SET_PSEUDO_REGISTER payload to
+ * the context record and thus knows from where to restore
+ * the saved perfcounters for the new ringbuffer.
+ */
+ *cmds++ = SET_PSEUDO_REGISTER_SAVE_REGISTER_COUNTER;
+ cmds += cp_gpuaddr(adreno_dev, cmds,
+ rb->perfcounter_save_restore_desc.gpuaddr);
+
+ return (unsigned int) (cmds - cmds_orig);
+}
+
+unsigned int a6xx_preemption_post_ibsubmit(struct adreno_device *adreno_dev,
+ unsigned int *cmds)
+{
+ unsigned int *cmds_orig = cmds;
+
+ *cmds++ = cp_type7_packet(CP_CONTEXT_SWITCH_YIELD, 4);
+ cmds += cp_gpuaddr(adreno_dev, cmds, 0x0);
+ *cmds++ = 1;
+ *cmds++ = 0;
+
+ return (unsigned int) (cmds - cmds_orig);
+}
+
+void a6xx_preemption_start(struct adreno_device *adreno_dev)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+ struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);
+ struct adreno_ringbuffer *rb;
+ unsigned int i;
+
+ if (!adreno_is_preemption_enabled(adreno_dev))
+ return;
+
+ /* Force the state to be clear */
+ adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
+
+ /* smmu_info is allocated and mapped in a6xx_preemption_iommu_init */
+ kgsl_sharedmem_writel(device, &iommu->smmu_info,
+ PREEMPT_SMMU_RECORD(magic), A6XX_CP_SMMU_INFO_MAGIC_REF);
+ kgsl_sharedmem_writeq(device, &iommu->smmu_info,
+ PREEMPT_SMMU_RECORD(ttbr0), MMU_DEFAULT_TTBR0(device));
+
+ /* The CP doesn't use the asid record, so poison it */
+ kgsl_sharedmem_writel(device, &iommu->smmu_info,
+ PREEMPT_SMMU_RECORD(asid), 0xDECAFBAD);
+ kgsl_sharedmem_writel(device, &iommu->smmu_info,
+ PREEMPT_SMMU_RECORD(context_idr),
+ MMU_DEFAULT_CONTEXTIDR(device));
+
+ adreno_writereg64(adreno_dev,
+ ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_LO,
+ ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI,
+ iommu->smmu_info.gpuaddr);
+
+ FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
+ /*
+ * preemption_desc is allocated and mapped at init time,
+ * so no need to check sharedmem_writel return value
+ */
+ kgsl_sharedmem_writel(device, &rb->preemption_desc,
+ PREEMPT_RECORD(rptr), 0);
+ kgsl_sharedmem_writel(device, &rb->preemption_desc,
+ PREEMPT_RECORD(wptr), 0);
+
+ adreno_ringbuffer_set_pagetable(rb,
+ device->mmu.defaultpagetable);
+ }
+}
+
+static int a6xx_preemption_ringbuffer_init(struct adreno_device *adreno_dev,
+ struct adreno_ringbuffer *rb, uint64_t counteraddr)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+ int ret;
+
+ ret = kgsl_allocate_global(device, &rb->preemption_desc,
+ A6XX_CP_CTXRECORD_SIZE_IN_BYTES, 0, KGSL_MEMDESC_PRIVILEGED,
+ "preemption_desc");
+ if (ret)
+ return ret;
+
+ ret = kgsl_allocate_global(device, &rb->perfcounter_save_restore_desc,
+ A6XX_CP_PERFCOUNTER_SAVE_RESTORE_SIZE, 0,
+ KGSL_MEMDESC_PRIVILEGED, "perfcounter_save_restore_desc");
+ if (ret)
+ return ret;
+
+ kgsl_sharedmem_writel(device, &rb->preemption_desc,
+ PREEMPT_RECORD(magic), A6XX_CP_CTXRECORD_MAGIC_REF);
+ kgsl_sharedmem_writel(device, &rb->preemption_desc,
+ PREEMPT_RECORD(info), 0);
+ kgsl_sharedmem_writel(device, &rb->preemption_desc,
+ PREEMPT_RECORD(data), 0);
+ kgsl_sharedmem_writel(device, &rb->preemption_desc,
+ PREEMPT_RECORD(cntl), A6XX_CP_RB_CNTL_DEFAULT);
+ kgsl_sharedmem_writel(device, &rb->preemption_desc,
+ PREEMPT_RECORD(rptr), 0);
+ kgsl_sharedmem_writel(device, &rb->preemption_desc,
+ PREEMPT_RECORD(wptr), 0);
+ kgsl_sharedmem_writeq(device, &rb->preemption_desc,
+ PREEMPT_RECORD(rptr_addr), SCRATCH_RPTR_GPU_ADDR(device,
+ rb->id));
+ kgsl_sharedmem_writeq(device, &rb->preemption_desc,
+ PREEMPT_RECORD(rbase), rb->buffer_desc.gpuaddr);
+ kgsl_sharedmem_writeq(device, &rb->preemption_desc,
+ PREEMPT_RECORD(counter), counteraddr);
+
+ return 0;
+}
+
+#ifdef CONFIG_QCOM_KGSL_IOMMU
+static int a6xx_preemption_iommu_init(struct adreno_device *adreno_dev)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+ struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);
+
+ /* Allocate mem for storing preemption smmu record */
+ return kgsl_allocate_global(device, &iommu->smmu_info, PAGE_SIZE,
+ KGSL_MEMFLAGS_GPUREADONLY, KGSL_MEMDESC_PRIVILEGED,
+ "smmu_info");
+}
+
+static void a6xx_preemption_iommu_close(struct adreno_device *adreno_dev)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+ struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);
+
+ kgsl_free_global(device, &iommu->smmu_info);
+}
+#else
+static int a6xx_preemption_iommu_init(struct adreno_device *adreno_dev)
+{
+ return -ENODEV;
+}
+
+static void a6xx_preemption_iommu_close(struct adreno_device *adreno_dev)
+{
+}
+#endif
+
+static void a6xx_preemption_close(struct kgsl_device *device)
+{
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+ struct adreno_preemption *preempt = &adreno_dev->preempt;
+ struct adreno_ringbuffer *rb;
+ unsigned int i;
+
+ del_timer(&preempt->timer);
+ kgsl_free_global(device, &preempt->counters);
+ a6xx_preemption_iommu_close(adreno_dev);
+
+ FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
+ kgsl_free_global(device, &rb->preemption_desc);
+ kgsl_free_global(device, &rb->perfcounter_save_restore_desc);
+ }
+}
+
+int a6xx_preemption_init(struct adreno_device *adreno_dev)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+ struct adreno_preemption *preempt = &adreno_dev->preempt;
+ struct adreno_ringbuffer *rb;
+ int ret;
+ unsigned int i;
+ uint64_t addr;
+
+ /* We are dependent on IOMMU to make preemption go on the CP side */
+ if (kgsl_mmu_get_mmutype(device) != KGSL_MMU_TYPE_IOMMU)
+ return -ENODEV;
+
+ INIT_WORK(&preempt->work, _a6xx_preemption_worker);
+
+ setup_timer(&preempt->timer, _a6xx_preemption_timer,
+ (unsigned long) adreno_dev);
+
+ /* Allocate mem for storing preemption counters */
+ ret = kgsl_allocate_global(device, &preempt->counters,
+ adreno_dev->num_ringbuffers *
+ A6XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE, 0, 0,
+ "preemption_counters");
+ if (ret)
+ goto err;
+
+ addr = preempt->counters.gpuaddr;
+
+ /* Allocate mem for storing preemption switch record */
+ FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
+ ret = a6xx_preemption_ringbuffer_init(adreno_dev, rb, addr);
+ if (ret)
+ goto err;
+
+ addr += A6XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE;
+ }
+
+ ret = a6xx_preemption_iommu_init(adreno_dev);
+
+err:
+ if (ret)
+ a6xx_preemption_close(device);
+
+ return ret;
+}
+
+void a6xx_preemption_context_destroy(struct kgsl_context *context)
+{
+ struct kgsl_device *device = context->device;
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+
+ if (!adreno_is_preemption_enabled(adreno_dev))
+ return;
+
+ gpumem_free_entry(context->user_ctxt_record);
+}
+
+int a6xx_preemption_context_init(struct kgsl_context *context)
+{
+ struct kgsl_device *device = context->device;
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+
+ if (!adreno_is_preemption_enabled(adreno_dev))
+ return 0;
+
+ context->user_ctxt_record = gpumem_alloc_entry(context->dev_priv,
+ A6XX_CP_CTXRECORD_USER_RESTORE_SIZE, 0);
+ if (IS_ERR(context->user_ctxt_record)) {
+ int ret = PTR_ERR(context->user_ctxt_record);
+
+ context->user_ctxt_record = NULL;
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/msm/adreno_drawctxt.c b/drivers/gpu/msm/adreno_drawctxt.c
index f217822..c6df7bb 100644
--- a/drivers/gpu/msm/adreno_drawctxt.c
+++ b/drivers/gpu/msm/adreno_drawctxt.c
@@ -341,6 +341,7 @@
struct adreno_context *drawctxt;
struct kgsl_device *device = dev_priv->device;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+ struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
int ret;
unsigned int local;
@@ -421,6 +422,16 @@
return ERR_PTR(ret);
}
+ if (gpudev->preemption_context_init) {
+ ret = gpudev->preemption_context_init(&drawctxt->base);
+ if (ret != 0) {
+ kgsl_context_detach(&drawctxt->base);
+ kgsl_context_put(&drawctxt->base);
+ kfree(drawctxt);
+ return ERR_PTR(ret);
+ }
+ }
+
kgsl_sharedmem_writel(device, &device->memstore,
KGSL_MEMSTORE_OFFSET(drawctxt->base.id, soptimestamp),
0);
@@ -545,10 +556,18 @@
void adreno_drawctxt_destroy(struct kgsl_context *context)
{
struct adreno_context *drawctxt;
+ struct adreno_device *adreno_dev;
+ struct adreno_gpudev *gpudev;
if (context == NULL)
return;
+ adreno_dev = ADRENO_DEVICE(context->device);
+ gpudev = ADRENO_GPU_DEVICE(adreno_dev);
+
+ if (gpudev->preemption_context_destroy)
+ gpudev->preemption_context_destroy(context);
+
drawctxt = ADRENO_CONTEXT(context);
debugfs_remove_recursive(drawctxt->debug_root);
kfree(drawctxt);
diff --git a/drivers/gpu/msm/adreno_iommu.c b/drivers/gpu/msm/adreno_iommu.c
index 80a04bc..1a2f8ff 100644
--- a/drivers/gpu/msm/adreno_iommu.c
+++ b/drivers/gpu/msm/adreno_iommu.c
@@ -574,6 +574,40 @@
return cmds - cmds_orig;
}
+static unsigned int _adreno_iommu_set_pt_v2_a6xx(struct kgsl_device *device,
+ unsigned int *cmds_orig,
+ u64 ttbr0, u32 contextidr,
+ struct adreno_ringbuffer *rb,
+ unsigned int cb_num)
+{
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+ unsigned int *cmds = cmds_orig;
+
+ cmds += _adreno_iommu_add_idle_cmds(adreno_dev, cmds);
+ cmds += cp_wait_for_me(adreno_dev, cmds);
+
+ /* CP switches the pagetable and flushes the Caches */
+ *cmds++ = cp_packet(adreno_dev, CP_SMMU_TABLE_UPDATE, 4);
+ *cmds++ = lower_32_bits(ttbr0);
+ *cmds++ = upper_32_bits(ttbr0);
+ *cmds++ = contextidr;
+ *cmds++ = cb_num;
+
+ *cmds++ = cp_mem_packet(adreno_dev, CP_MEM_WRITE, 4, 1);
+ cmds += cp_gpuaddr(adreno_dev, cmds, (rb->pagetable_desc.gpuaddr +
+ PT_INFO_OFFSET(ttbr0)));
+ *cmds++ = lower_32_bits(ttbr0);
+ *cmds++ = upper_32_bits(ttbr0);
+ *cmds++ = contextidr;
+
+ /* release all commands with wait_for_me */
+ cmds += cp_wait_for_me(adreno_dev, cmds);
+
+ cmds += _adreno_iommu_add_idle_cmds(adreno_dev, cmds);
+
+ return cmds - cmds_orig;
+}
+
/**
* adreno_iommu_set_pt_generate_cmds() - Generate commands to change pagetable
* @rb: The RB pointer in which these commaands are to be submitted
@@ -588,6 +622,7 @@
struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);
+ struct kgsl_iommu_context *ctx = &iommu->ctx[KGSL_IOMMU_CONTEXT_USER];
u64 ttbr0;
u32 contextidr;
unsigned int *cmds_orig = cmds;
@@ -601,7 +636,11 @@
iommu->setstate.gpuaddr + KGSL_IOMMU_SETSTATE_NOP_OFFSET);
if (iommu->version >= 2) {
- if (adreno_is_a5xx(adreno_dev) || adreno_is_a6xx(adreno_dev))
+ if (adreno_is_a6xx(adreno_dev))
+ cmds += _adreno_iommu_set_pt_v2_a6xx(device, cmds,
+ ttbr0, contextidr, rb,
+ ctx->cb_num);
+ else if (adreno_is_a5xx(adreno_dev))
cmds += _adreno_iommu_set_pt_v2_a5xx(device, cmds,
ttbr0, contextidr, rb);
else if (adreno_is_a4xx(adreno_dev))
diff --git a/drivers/gpu/msm/adreno_pm4types.h b/drivers/gpu/msm/adreno_pm4types.h
index fceceda..2a330b4 100644
--- a/drivers/gpu/msm/adreno_pm4types.h
+++ b/drivers/gpu/msm/adreno_pm4types.h
@@ -55,6 +55,12 @@
/* switches SMMU pagetable, used on a5xx only */
#define CP_SMMU_TABLE_UPDATE 0x53
+/* Set internal CP registers, used to indicate context save data addresses */
+#define CP_SET_PSEUDO_REGISTER 0x56
+
+/* Tell CP the current operation mode, indicates save and restore procedure */
+#define CP_SET_MARKER 0x65
+
/* register read/modify/write */
#define CP_REG_RMW 0x21
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index bff1fda..15c68fb 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -864,9 +864,12 @@
dwords += 2;
}
- if (gpudev->preemption_yield_enable &&
- adreno_is_preemption_enabled(adreno_dev))
- dwords += 8;
+ if (adreno_is_preemption_enabled(adreno_dev)) {
+ if (gpudev->preemption_set_marker)
+ dwords += 4;
+ else if (gpudev->preemption_yield_enable)
+ dwords += 8;
+ }
link = kcalloc(dwords, sizeof(unsigned int), GFP_KERNEL);
if (!link) {
@@ -897,6 +900,10 @@
gpu_ticks_submitted));
}
+ if (gpudev->preemption_set_marker &&
+ adreno_is_preemption_enabled(adreno_dev))
+ cmds += gpudev->preemption_set_marker(cmds, 1);
+
if (numibs) {
list_for_each_entry(ib, &cmdobj->cmdlist, node) {
/*
@@ -918,9 +925,12 @@
}
}
- if (gpudev->preemption_yield_enable &&
- adreno_is_preemption_enabled(adreno_dev))
- cmds += gpudev->preemption_yield_enable(cmds);
+ if (adreno_is_preemption_enabled(adreno_dev)) {
+ if (gpudev->preemption_set_marker)
+ cmds += gpudev->preemption_set_marker(cmds, 0);
+ else if (gpudev->preemption_yield_enable)
+ cmds += gpudev->preemption_yield_enable(cmds);
+ }
if (kernel_profiling) {
cmds += _get_alwayson_counter(adreno_dev, cmds,
diff --git a/drivers/gpu/msm/adreno_ringbuffer.h b/drivers/gpu/msm/adreno_ringbuffer.h
index 63374af..72fc5bf3 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.h
+++ b/drivers/gpu/msm/adreno_ringbuffer.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2002,2007-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2002,2007-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -92,6 +92,8 @@
* @drawctxt_active: The last pagetable that this ringbuffer is set to
* @preemption_desc: The memory descriptor containing
* preemption info written/read by CP
+ * @perfcounter_save_restore_desc: Used by CP to save/restore the perfcounter
+ * values across preemption
* @pagetable_desc: Memory to hold information about the pagetables being used
* and the commands to switch pagetable on the RB
* @dispatch_q: The dispatcher side queue for this ringbuffer
@@ -118,6 +120,7 @@
struct kgsl_event_group events;
struct adreno_context *drawctxt_active;
struct kgsl_memdesc preemption_desc;
+ struct kgsl_memdesc perfcounter_save_restore_desc;
struct kgsl_memdesc pagetable_desc;
struct adreno_dispatcher_drawqueue dispatch_q;
wait_queue_head_t ts_expire_waitq;
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 6bd212d..7b8cdc2 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -245,8 +245,6 @@
}
EXPORT_SYMBOL(kgsl_readtimestamp);
-static long gpumem_free_entry(struct kgsl_mem_entry *entry);
-
/* Scheduled by kgsl_mem_entry_put_deferred() */
static void _deferred_put(struct work_struct *work)
{
@@ -608,7 +606,7 @@
* detached by checking the KGSL_CONTEXT_PRIV_DETACHED bit in
* context->priv.
*/
-static void kgsl_context_detach(struct kgsl_context *context)
+void kgsl_context_detach(struct kgsl_context *context)
{
struct kgsl_device *device;
@@ -1812,7 +1810,7 @@
return 0;
}
-static long gpumem_free_entry(struct kgsl_mem_entry *entry)
+long gpumem_free_entry(struct kgsl_mem_entry *entry)
{
pid_t ptname = 0;
@@ -3054,7 +3052,7 @@
/* The largest allowable alignment for a GPU object is 32MB */
#define KGSL_MAX_ALIGN (32 * SZ_1M)
-static struct kgsl_mem_entry *gpumem_alloc_entry(
+struct kgsl_mem_entry *gpumem_alloc_entry(
struct kgsl_device_private *dev_priv,
uint64_t size, uint64_t flags)
{
diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h
index 3f1c86e..c54e51e 100644
--- a/drivers/gpu/msm/kgsl.h
+++ b/drivers/gpu/msm/kgsl.h
@@ -445,6 +445,10 @@
int kgsl_suspend_driver(struct platform_device *pdev, pm_message_t state);
int kgsl_resume_driver(struct platform_device *pdev);
+struct kgsl_mem_entry *gpumem_alloc_entry(struct kgsl_device_private *dev_priv,
+ uint64_t size, uint64_t flags);
+long gpumem_free_entry(struct kgsl_mem_entry *entry);
+
static inline int kgsl_gpuaddr_in_memdesc(const struct kgsl_memdesc *memdesc,
uint64_t gpuaddr, uint64_t size)
{
diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h
index ca1f181..b621ada 100644
--- a/drivers/gpu/msm/kgsl_device.h
+++ b/drivers/gpu/msm/kgsl_device.h
@@ -378,6 +378,8 @@
* @pwr_constraint: power constraint from userspace for this context
* @fault_count: number of times gpu hanged in last _context_throttle_time ms
* @fault_time: time of the first gpu hang in last _context_throttle_time ms
+ * @user_ctxt_record: memory descriptor used by CP to save/restore VPC data
+ * across preemption
*/
struct kgsl_context {
struct kref refcount;
@@ -395,6 +397,7 @@
struct kgsl_pwr_constraint pwr_constraint;
unsigned int fault_count;
unsigned long fault_time;
+ struct kgsl_mem_entry *user_ctxt_record;
};
#define _context_comm(_c) \
@@ -689,6 +692,8 @@
void kgsl_events_init(void);
void kgsl_events_exit(void);
+void kgsl_context_detach(struct kgsl_context *context);
+
void kgsl_del_event_group(struct kgsl_event_group *group);
void kgsl_add_event_group(struct kgsl_event_group *group,
diff --git a/drivers/gpu/msm/kgsl_gmu.c b/drivers/gpu/msm/kgsl_gmu.c
index 2a6e7dd..324840d 100644
--- a/drivers/gpu/msm/kgsl_gmu.c
+++ b/drivers/gpu/msm/kgsl_gmu.c
@@ -1238,7 +1238,7 @@
return ret;
}
-#define CX_GDSC_TIMEOUT 10 /* ms */
+#define CX_GDSC_TIMEOUT 500 /* ms */
static int gmu_disable_gdsc(struct gmu_device *gmu)
{
int ret;
@@ -1264,7 +1264,7 @@
do {
if (!regulator_is_enabled(gmu->cx_gdsc))
return 0;
- udelay(100);
+ cond_resched();
} while (!(time_after(jiffies, t)));
@@ -1418,7 +1418,7 @@
gmu_irq_enable(device);
- ret = hfi_start(gmu, GMU_WARM_BOOT);
+ ret = hfi_start(gmu, GMU_COLD_BOOT);
if (ret)
goto error_gpu;
diff --git a/drivers/gpu/msm/kgsl_hfi.c b/drivers/gpu/msm/kgsl_hfi.c
index e91550a..067b276 100644
--- a/drivers/gpu/msm/kgsl_hfi.c
+++ b/drivers/gpu/msm/kgsl_hfi.c
@@ -188,9 +188,9 @@
msg->seqnum == rsp->ret_hdr.seqnum)
break;
}
- spin_unlock(&hfi->msglock);
if (msg == NULL) {
+ spin_unlock(&hfi->msglock);
dev_err(&gmu->pdev->dev,
"Cannot find receiver of ack msg with id=%d\n",
rsp->ret_hdr.id);
@@ -199,6 +199,7 @@
memcpy(&msg->results, (void *) rsp, rsp->hdr.size << 2);
complete(&msg->msg_complete);
+ spin_unlock(&hfi->msglock);
}
static void receive_err_msg(struct gmu_device *gmu, struct hfi_msg_rsp *rsp)
diff --git a/drivers/gpu/msm/kgsl_hfi.h b/drivers/gpu/msm/kgsl_hfi.h
index 83abec4..8eedbfa2 100644
--- a/drivers/gpu/msm/kgsl_hfi.h
+++ b/drivers/gpu/msm/kgsl_hfi.h
@@ -115,7 +115,7 @@
HFI_F2H_QPRI_DEBUG = 40,
};
-#define HFI_RSP_TIMEOUT 50 /* msec */
+#define HFI_RSP_TIMEOUT 100 /* msec */
#define HFI_H2F_CMD_IRQ_MASK BIT(0)
enum hfi_msg_type {
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index b3d02e6..73c0d71 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -1255,7 +1255,7 @@
ret = iommu_domain_get_attr(iommu_pt->domain,
DOMAIN_ATTR_CONTEXT_BANK, &cb_num);
if (ret) {
- KGSL_CORE_ERR("get DOMAIN_ATTR_PROCID failed: %d\n",
+ KGSL_CORE_ERR("get DOMAIN_ATTR_CONTEXT_BANK failed: %d\n",
ret);
goto done;
}
diff --git a/drivers/gpu/msm/kgsl_iommu.h b/drivers/gpu/msm/kgsl_iommu.h
index 6337a48..acf8ae4 100644
--- a/drivers/gpu/msm/kgsl_iommu.h
+++ b/drivers/gpu/msm/kgsl_iommu.h
@@ -23,7 +23,7 @@
* These defines control the address range for allocations that
* are mapped into all pagetables.
*/
-#define KGSL_IOMMU_GLOBAL_MEM_SIZE SZ_8M
+#define KGSL_IOMMU_GLOBAL_MEM_SIZE (20 * SZ_1M)
#define KGSL_IOMMU_GLOBAL_MEM_BASE 0xf8000000
#define KGSL_IOMMU_SECURE_SIZE SZ_256M
diff --git a/drivers/md/Kconfig b/drivers/md/Kconfig
index e7b8f49..89fc93b 100644
--- a/drivers/md/Kconfig
+++ b/drivers/md/Kconfig
@@ -277,6 +277,23 @@
If unsure, say N.
+config DM_REQ_CRYPT
+ tristate "Req Crypt target support"
+ depends on BLK_DEV_DM
+ select XTS
+ select CRYPTO_XTS
+ ---help---
+ This request based device-mapper target allows you to create a device that
+ transparently encrypts the data on it. You'll need to activate
+ the ciphers you're going to use in the cryptoapi configuration.
+ The DM REQ CRYPT operates on requests (bigger payloads) to utilize
+ crypto hardware better.
+
+ To compile this code as a module, choose M here: the module will
+ be called dm-req-crypt.
+
+ If unsure, say N.
+
config DM_SNAPSHOT
tristate "Snapshot target"
depends on BLK_DEV_DM
diff --git a/drivers/md/Makefile b/drivers/md/Makefile
index f26ce41..f14e2fc 100644
--- a/drivers/md/Makefile
+++ b/drivers/md/Makefile
@@ -59,6 +59,7 @@
obj-$(CONFIG_DM_CACHE_CLEANER) += dm-cache-cleaner.o
obj-$(CONFIG_DM_ERA) += dm-era.o
obj-$(CONFIG_DM_LOG_WRITES) += dm-log-writes.o
+obj-$(CONFIG_DM_REQ_CRYPT) += dm-req-crypt.o
obj-$(CONFIG_DM_ANDROID_VERITY) += dm-android-verity.o
ifeq ($(CONFIG_DM_UEVENT),y)
diff --git a/drivers/md/dm-req-crypt.c b/drivers/md/dm-req-crypt.c
new file mode 100644
index 0000000..3ffe7e5
--- /dev/null
+++ b/drivers/md/dm-req-crypt.c
@@ -0,0 +1,1364 @@
+/*
+ * DM request based crypto driver
+ *
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bio.h>
+#include <linux/blkdev.h>
+#include <linux/mempool.h>
+#include <linux/slab.h>
+#include <linux/crypto.h>
+#include <linux/qcrypto.h>
+#include <linux/workqueue.h>
+#include <linux/backing-dev.h>
+#include <linux/atomic.h>
+#include <linux/scatterlist.h>
+#include <linux/device-mapper.h>
+#include <linux/printk.h>
+
+#include <asm/page.h>
+#include <asm/unaligned.h>
+#include <crypto/skcipher.h>
+#include <crypto/internal/skcipher.h>
+#include <crypto/scatterwalk.h>
+#include <crypto/hash.h>
+#include <crypto/md5.h>
+#include <crypto/algapi.h>
+#include <crypto/ice.h>
+
+#define DM_MSG_PREFIX "req-crypt"
+
+#define MAX_SG_LIST 1024
+#define REQ_DM_512_KB (512*1024)
+#define MAX_ENCRYPTION_BUFFERS 1
+#define MIN_IOS 256
+#define MIN_POOL_PAGES 32
+#define KEY_SIZE_XTS 32
+#define AES_XTS_IV_LEN 16
+#define MAX_MSM_ICE_KEY_LUT_SIZE 32
+#define SECTOR_SIZE 512
+#define MIN_CRYPTO_TRANSFER_SIZE (4 * 1024)
+
+#define DM_REQ_CRYPT_ERROR -1
+#define DM_REQ_CRYPT_ERROR_AFTER_PAGE_MALLOC -2
+
+/*
+ * ENCRYPTION_MODE_CRYPTO means dm-req-crypt would invoke crypto operations
+ * for all of the requests. Crypto operations are performed by crypto engine
+ * plugged with Linux Kernel Crypto APIs
+ */
+#define DM_REQ_CRYPT_ENCRYPTION_MODE_CRYPTO 0
+/*
+ * ENCRYPTION_MODE_TRANSPARENT means dm-req-crypt would not invoke crypto
+ * operations for any of the requests. Data would be encrypted or decrypted
+ * using Inline Crypto Engine(ICE) embedded in storage hardware
+ */
+#define DM_REQ_CRYPT_ENCRYPTION_MODE_TRANSPARENT 1
+
+#define DM_REQ_CRYPT_QUEUE_SIZE 256
+
+struct req_crypt_result {
+ struct completion completion;
+ int err;
+};
+
+#define FDE_KEY_ID 0
+#define PFE_KEY_ID 1
+
+static struct dm_dev *dev;
+static struct kmem_cache *_req_crypt_io_pool;
+static struct kmem_cache *_req_dm_scatterlist_pool;
+static sector_t start_sector_orig;
+static struct workqueue_struct *req_crypt_queue;
+static struct workqueue_struct *req_crypt_split_io_queue;
+static mempool_t *req_io_pool;
+static mempool_t *req_page_pool;
+static mempool_t *req_scatterlist_pool;
+static bool is_fde_enabled;
+static struct crypto_skcipher *tfm;
+static unsigned int encryption_mode;
+static struct ice_crypto_setting *ice_settings;
+
+unsigned int num_engines;
+unsigned int num_engines_fde, fde_cursor;
+unsigned int num_engines_pfe, pfe_cursor;
+struct crypto_engine_entry *fde_eng, *pfe_eng;
+DEFINE_MUTEX(engine_list_mutex);
+
+struct req_dm_crypt_io {
+ struct ice_crypto_setting ice_settings;
+ struct work_struct work;
+ struct request *cloned_request;
+ int error;
+ atomic_t pending;
+ struct timespec start_time;
+ bool should_encrypt;
+ bool should_decrypt;
+ u32 key_id;
+};
+
+struct req_dm_split_req_io {
+ struct work_struct work;
+ struct scatterlist *req_split_sg_read;
+ struct req_crypt_result result;
+ struct crypto_engine_entry *engine;
+ u8 IV[AES_XTS_IV_LEN];
+ int size;
+ struct request *clone;
+};
+
+#ifdef CONFIG_FIPS_ENABLE
+static struct qcrypto_func_set dm_qcrypto_func;
+#else
+static struct qcrypto_func_set dm_qcrypto_func = {
+ qcrypto_cipher_set_device_hw,
+ qcrypto_cipher_set_flag,
+ qcrypto_get_num_engines,
+ qcrypto_get_engine_list
+};
+#endif
+static void req_crypt_cipher_complete
+ (struct crypto_async_request *req, int err);
+static void req_cryptd_split_req_queue_cb
+ (struct work_struct *work);
+static void req_cryptd_split_req_queue
+ (struct req_dm_split_req_io *io);
+static void req_crypt_split_io_complete
+ (struct req_crypt_result *res, int err);
+
+static bool req_crypt_should_encrypt(struct req_dm_crypt_io *req)
+{
+ int ret = 0;
+ bool should_encrypt = false;
+ struct bio *bio = NULL;
+ bool is_encrypted = false;
+ bool is_inplace = false;
+
+ if (!req || !req->cloned_request || !req->cloned_request->bio)
+ return false;
+
+ if (encryption_mode == DM_REQ_CRYPT_ENCRYPTION_MODE_TRANSPARENT)
+ return false;
+ bio = req->cloned_request->bio;
+
+ /* req->key_id = key_id; @todo support more than 1 pfe key */
+ if ((ret == 0) && (is_encrypted || is_inplace)) {
+ should_encrypt = true;
+ req->key_id = PFE_KEY_ID;
+ } else if (is_fde_enabled) {
+ should_encrypt = true;
+ req->key_id = FDE_KEY_ID;
+ }
+
+ return should_encrypt;
+}
+
+static bool req_crypt_should_deccrypt(struct req_dm_crypt_io *req)
+{
+ int ret = 0;
+ bool should_deccrypt = false;
+ struct bio *bio = NULL;
+ bool is_encrypted = false;
+ bool is_inplace = false;
+
+ if (!req || !req->cloned_request || !req->cloned_request->bio)
+ return false;
+ if (encryption_mode == DM_REQ_CRYPT_ENCRYPTION_MODE_TRANSPARENT)
+ return false;
+
+ bio = req->cloned_request->bio;
+
+ /* req->key_id = key_id; @todo support more than 1 pfe key */
+ if ((ret == 0) && (is_encrypted && !is_inplace)) {
+ should_deccrypt = true;
+ req->key_id = PFE_KEY_ID;
+ } else if (is_fde_enabled) {
+ should_deccrypt = true;
+ req->key_id = FDE_KEY_ID;
+ }
+
+ return should_deccrypt;
+}
+
+static void req_crypt_inc_pending(struct req_dm_crypt_io *io)
+{
+ atomic_inc(&io->pending);
+}
+
+static void req_crypt_dec_pending_encrypt(struct req_dm_crypt_io *io)
+{
+ int error = 0;
+ struct request *clone = NULL;
+
+ if (io) {
+ error = io->error;
+ if (io->cloned_request) {
+ clone = io->cloned_request;
+ } else {
+ DMERR("%s io->cloned_request is NULL\n",
+ __func__);
+ /*
+ * If Clone is NULL we cannot do anything,
+ * this should never happen
+ */
+ WARN_ON(1);
+ }
+ } else {
+ DMERR("%s io is NULL\n", __func__);
+ /*
+ * If Clone is NULL we cannot do anything,
+ * this should never happen
+ */
+ WARN_ON(1);
+ }
+
+ atomic_dec(&io->pending);
+
+ if (error < 0) {
+ dm_kill_unmapped_request(clone, error);
+ mempool_free(io, req_io_pool);
+ } else
+ dm_dispatch_request(clone);
+}
+
+static void req_crypt_dec_pending_decrypt(struct req_dm_crypt_io *io)
+{
+ int error = 0;
+ struct request *clone = NULL;
+
+ if (io) {
+ error = io->error;
+ if (io->cloned_request) {
+ clone = io->cloned_request;
+ } else {
+ DMERR("%s io->cloned_request is NULL\n",
+ __func__);
+ /*
+ * If Clone is NULL we cannot do anything,
+ * this should never happen
+ */
+ WARN_ON(1);
+ }
+ } else {
+ DMERR("%s io is NULL\n",
+ __func__);
+ /*
+ * If Clone is NULL we cannot do anything,
+ * this should never happen
+ */
+ WARN_ON(1);
+ }
+
+ /* Should never get here if io or Clone is NULL */
+ dm_end_request(clone, error);
+ atomic_dec(&io->pending);
+ mempool_free(io, req_io_pool);
+}
+
+/*
+ * The callback that will be called by the worker queue to perform Decryption
+ * for reads and use the dm function to complete the bios and requests.
+ */
+static void req_cryptd_crypt_read_convert(struct req_dm_crypt_io *io)
+{
+ struct request *clone = NULL;
+ int error = DM_REQ_CRYPT_ERROR;
+ int total_sg_len = 0, total_bytes_in_req = 0, temp_size = 0, i = 0;
+ struct scatterlist *sg = NULL;
+ struct scatterlist *req_sg_read = NULL;
+
+ unsigned int engine_list_total = 0;
+ struct crypto_engine_entry *curr_engine_list = NULL;
+ bool split_transfers = 0;
+ sector_t tempiv;
+ struct req_dm_split_req_io *split_io = NULL;
+
+ if (io) {
+ error = io->error;
+ if (io->cloned_request) {
+ clone = io->cloned_request;
+ } else {
+ DMERR("%s io->cloned_request is NULL\n",
+ __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ goto submit_request;
+ }
+ } else {
+ DMERR("%s io is NULL\n",
+ __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ goto submit_request;
+ }
+
+ req_crypt_inc_pending(io);
+
+ mutex_lock(&engine_list_mutex);
+
+ engine_list_total = (io->key_id == FDE_KEY_ID ? num_engines_fde :
+ (io->key_id == PFE_KEY_ID ?
+ num_engines_pfe : 0));
+
+ curr_engine_list = (io->key_id == FDE_KEY_ID ? fde_eng :
+ (io->key_id == PFE_KEY_ID ?
+ pfe_eng : NULL));
+
+ mutex_unlock(&engine_list_mutex);
+
+ req_sg_read = (struct scatterlist *)mempool_alloc(req_scatterlist_pool,
+ GFP_KERNEL);
+ if (!req_sg_read) {
+ DMERR("%s req_sg_read allocation failed\n",
+ __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+ memset(req_sg_read, 0, sizeof(struct scatterlist) * MAX_SG_LIST);
+
+ total_sg_len = blk_rq_map_sg_no_cluster(clone->q, clone, req_sg_read);
+ if ((total_sg_len <= 0) || (total_sg_len > MAX_SG_LIST)) {
+ DMERR("%s Request Error%d", __func__, total_sg_len);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+
+ total_bytes_in_req = clone->__data_len;
+ if (total_bytes_in_req > REQ_DM_512_KB) {
+ DMERR("%s total_bytes_in_req > 512 MB %d",
+ __func__, total_bytes_in_req);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+
+
+ if ((clone->__data_len >= (MIN_CRYPTO_TRANSFER_SIZE *
+ engine_list_total))
+ && (engine_list_total > 1))
+ split_transfers = 1;
+
+ if (split_transfers) {
+ split_io = kzalloc(sizeof(struct req_dm_split_req_io)
+ * engine_list_total, GFP_KERNEL);
+ if (!split_io) {
+ DMERR("%s split_io allocation failed\n", __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+
+ split_io[0].req_split_sg_read = sg = req_sg_read;
+ split_io[engine_list_total - 1].size = total_bytes_in_req;
+ for (i = 0; i < (engine_list_total); i++) {
+ while ((sg) && i < (engine_list_total - 1)) {
+ split_io[i].size += sg->length;
+ split_io[engine_list_total - 1].size -=
+ sg->length;
+ if (split_io[i].size >=
+ (total_bytes_in_req /
+ engine_list_total)) {
+ split_io[i + 1].req_split_sg_read =
+ sg_next(sg);
+ sg_mark_end(sg);
+ break;
+ }
+ sg = sg_next(sg);
+ }
+ split_io[i].engine = &curr_engine_list[i];
+ init_completion(&split_io[i].result.completion);
+ memset(&split_io[i].IV, 0, AES_XTS_IV_LEN);
+ tempiv = clone->__sector + (temp_size / SECTOR_SIZE);
+ memcpy(&split_io[i].IV, &tempiv, sizeof(sector_t));
+ temp_size += split_io[i].size;
+ split_io[i].clone = clone;
+ req_cryptd_split_req_queue(&split_io[i]);
+ }
+ } else {
+ split_io = kzalloc(sizeof(struct req_dm_split_req_io),
+ GFP_KERNEL);
+ if (!split_io) {
+ DMERR("%s split_io allocation failed\n", __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+ split_io->engine = &curr_engine_list[0];
+ init_completion(&split_io->result.completion);
+ memcpy(split_io->IV, &clone->__sector, sizeof(sector_t));
+ split_io->req_split_sg_read = req_sg_read;
+ split_io->size = total_bytes_in_req;
+ split_io->clone = clone;
+ req_cryptd_split_req_queue(split_io);
+ }
+
+ if (!split_transfers) {
+ wait_for_completion_interruptible(&split_io->result.completion);
+ if (split_io->result.err) {
+ DMERR("%s error = %d for request\n",
+ __func__, split_io->result.err);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+ } else {
+ for (i = 0; i < (engine_list_total); i++) {
+ wait_for_completion_interruptible(
+ &split_io[i].result.completion);
+ if (split_io[i].result.err) {
+ DMERR("%s error = %d for %dst request\n",
+ __func__, split_io[i].result.err, i);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+ }
+ }
+ error = 0;
+skcipher_req_alloc_failure:
+
+ mempool_free(req_sg_read, req_scatterlist_pool);
+ kfree(split_io);
+submit_request:
+ if (io)
+ io->error = error;
+ req_crypt_dec_pending_decrypt(io);
+}
+
+/*
+ * This callback is called by the worker queue to perform non-decrypt reads
+ * and use the dm function to complete the bios and requests.
+ */
+static void req_cryptd_crypt_read_plain(struct req_dm_crypt_io *io)
+{
+ struct request *clone = NULL;
+ int error = 0;
+
+ if (!io || !io->cloned_request) {
+ DMERR("%s io is invalid\n", __func__);
+ WARN_ON(1); /* should not happen */
+ }
+
+ clone = io->cloned_request;
+
+ dm_end_request(clone, error);
+ mempool_free(io, req_io_pool);
+}
+
+/*
+ * The callback that will be called by the worker queue to perform Encryption
+ * for writes and submit the request using the elevelator.
+ */
+static void req_cryptd_crypt_write_convert(struct req_dm_crypt_io *io)
+{
+ struct request *clone = NULL;
+ struct bio *bio_src = NULL;
+ unsigned int total_sg_len_req_in = 0, total_sg_len_req_out = 0,
+ total_bytes_in_req = 0, error = DM_MAPIO_REMAPPED, rc = 0;
+ struct req_iterator iter;
+ struct req_iterator iter1;
+ struct skcipher_request *req = NULL;
+ struct req_crypt_result result;
+ struct bio_vec bvec;
+ struct scatterlist *req_sg_in = NULL;
+ struct scatterlist *req_sg_out = NULL;
+ int copy_bio_sector_to_req = 0;
+ gfp_t gfp_mask = GFP_NOIO | __GFP_HIGHMEM;
+ struct page *page = NULL;
+ u8 IV[AES_XTS_IV_LEN];
+ int remaining_size = 0, err = 0;
+ struct crypto_engine_entry engine;
+ unsigned int engine_list_total = 0;
+ struct crypto_engine_entry *curr_engine_list = NULL;
+ unsigned int *engine_cursor = NULL;
+
+
+ if (io) {
+ if (io->cloned_request) {
+ clone = io->cloned_request;
+ } else {
+ DMERR("%s io->cloned_request is NULL\n",
+ __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ goto submit_request;
+ }
+ } else {
+ DMERR("%s io is NULL\n",
+ __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ goto submit_request;
+ }
+
+ req_crypt_inc_pending(io);
+
+ req = skcipher_request_alloc(tfm, GFP_KERNEL);
+ if (!req) {
+ DMERR("%s skcipher request allocation failed\n",
+ __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+
+ skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
+ req_crypt_cipher_complete, &result);
+
+ mutex_lock(&engine_list_mutex);
+ engine_list_total = (io->key_id == FDE_KEY_ID ? num_engines_fde :
+ (io->key_id == PFE_KEY_ID ?
+ num_engines_pfe : 0));
+
+ curr_engine_list = (io->key_id == FDE_KEY_ID ? fde_eng :
+ (io->key_id == PFE_KEY_ID ?
+ pfe_eng : NULL));
+
+ engine_cursor = (io->key_id == FDE_KEY_ID ? &fde_cursor :
+ (io->key_id == PFE_KEY_ID ? &pfe_cursor
+ : NULL));
+ if ((engine_list_total < 1) || (curr_engine_list == NULL) ||
+ (engine_cursor == NULL)) {
+ DMERR("%s Unknown Key ID!\n", __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ mutex_unlock(&engine_list_mutex);
+ goto skcipher_req_alloc_failure;
+ }
+
+ engine = curr_engine_list[*engine_cursor];
+ (*engine_cursor)++;
+ (*engine_cursor) %= engine_list_total;
+
+ err = (dm_qcrypto_func.cipher_set)(req, engine.ce_device,
+ engine.hw_instance);
+ if (err) {
+ DMERR("%s qcrypto_cipher_set_device_hw failed with err %d\n",
+ __func__, err);
+ mutex_unlock(&engine_list_mutex);
+ goto skcipher_req_alloc_failure;
+ }
+ mutex_unlock(&engine_list_mutex);
+
+ init_completion(&result.completion);
+
+ (dm_qcrypto_func.cipher_flag)(req,
+ QCRYPTO_CTX_USE_PIPE_KEY | QCRYPTO_CTX_XTS_DU_SIZE_512B);
+ crypto_skcipher_clear_flags(tfm, ~0);
+ crypto_skcipher_setkey(tfm, NULL, KEY_SIZE_XTS);
+
+ req_sg_in = (struct scatterlist *)mempool_alloc(req_scatterlist_pool,
+ GFP_KERNEL);
+ if (!req_sg_in) {
+ DMERR("%s req_sg_in allocation failed\n",
+ __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+ memset(req_sg_in, 0, sizeof(struct scatterlist) * MAX_SG_LIST);
+
+ req_sg_out = (struct scatterlist *)mempool_alloc(req_scatterlist_pool,
+ GFP_KERNEL);
+ if (!req_sg_out) {
+ DMERR("%s req_sg_out allocation failed\n",
+ __func__);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+ memset(req_sg_out, 0, sizeof(struct scatterlist) * MAX_SG_LIST);
+
+ total_sg_len_req_in = blk_rq_map_sg(clone->q, clone, req_sg_in);
+ if ((total_sg_len_req_in <= 0) ||
+ (total_sg_len_req_in > MAX_SG_LIST)) {
+ DMERR("%s Request Error%d", __func__, total_sg_len_req_in);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+
+ total_bytes_in_req = clone->__data_len;
+ if (total_bytes_in_req > REQ_DM_512_KB) {
+ DMERR("%s total_bytes_in_req > 512 MB %d",
+ __func__, total_bytes_in_req);
+ error = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+
+ rq_for_each_segment(bvec, clone, iter) {
+ if (bvec.bv_len > remaining_size) {
+ page = NULL;
+ while (page == NULL) {
+ page = mempool_alloc(req_page_pool, gfp_mask);
+ if (!page) {
+ DMERR("%s Crypt page alloc failed",
+ __func__);
+ congestion_wait(BLK_RW_ASYNC, HZ/100);
+ }
+ }
+
+ bvec.bv_page = page;
+ bvec.bv_offset = 0;
+ remaining_size = PAGE_SIZE - bvec.bv_len;
+ if (remaining_size < 0)
+ WARN_ON(1);
+ } else {
+ bvec.bv_page = page;
+ bvec.bv_offset = PAGE_SIZE - remaining_size;
+ remaining_size = remaining_size - bvec.bv_len;
+ }
+ }
+
+ total_sg_len_req_out = blk_rq_map_sg(clone->q, clone, req_sg_out);
+ if ((total_sg_len_req_out <= 0) ||
+ (total_sg_len_req_out > MAX_SG_LIST)) {
+ DMERR("%s Request Error %d", __func__, total_sg_len_req_out);
+ error = DM_REQ_CRYPT_ERROR_AFTER_PAGE_MALLOC;
+ goto skcipher_req_alloc_failure;
+ }
+
+ memset(IV, 0, AES_XTS_IV_LEN);
+ memcpy(IV, &clone->__sector, sizeof(sector_t));
+
+ skcipher_request_set_crypt(req, req_sg_in, req_sg_out,
+ total_bytes_in_req, (void *) IV);
+
+ rc = crypto_skcipher_encrypt(req);
+
+ switch (rc) {
+ case 0:
+ break;
+
+ case -EBUSY:
+ /*
+ * Lets make this synchronous request by waiting on
+ * in progress as well
+ */
+ case -EINPROGRESS:
+ wait_for_completion_interruptible(&result.completion);
+ if (result.err) {
+ DMERR("%s error = %d encrypting the request\n",
+ __func__, result.err);
+ error = DM_REQ_CRYPT_ERROR_AFTER_PAGE_MALLOC;
+ goto skcipher_req_alloc_failure;
+ }
+ break;
+
+ default:
+ error = DM_REQ_CRYPT_ERROR_AFTER_PAGE_MALLOC;
+ goto skcipher_req_alloc_failure;
+ }
+
+ __rq_for_each_bio(bio_src, clone) {
+ if (copy_bio_sector_to_req == 0)
+ copy_bio_sector_to_req++;
+ blk_queue_bounce(clone->q, &bio_src);
+ }
+
+ /*
+ * Recalculate the phy_segments as we allocate new pages
+ * This is used by storage driver to fill the sg list.
+ */
+ blk_recalc_rq_segments(clone);
+
+skcipher_req_alloc_failure:
+ if (req)
+ skcipher_request_free(req);
+
+ if (error == DM_REQ_CRYPT_ERROR_AFTER_PAGE_MALLOC) {
+ rq_for_each_segment(bvec, clone, iter1) {
+ if (bvec.bv_offset == 0) {
+ mempool_free(bvec.bv_page, req_page_pool);
+ bvec.bv_page = NULL;
+ } else
+ bvec.bv_page = NULL;
+ }
+ }
+
+ mempool_free(req_sg_in, req_scatterlist_pool);
+ mempool_free(req_sg_out, req_scatterlist_pool);
+submit_request:
+ if (io)
+ io->error = error;
+ req_crypt_dec_pending_encrypt(io);
+}
+
+/*
+ * This callback is called by the worker queue to perform non-encrypted writes
+ * and submit the request using the elevelator.
+ */
+static void req_cryptd_crypt_write_plain(struct req_dm_crypt_io *io)
+{
+ struct request *clone = NULL;
+
+ if (!io || !io->cloned_request) {
+ DMERR("%s io is invalid\n", __func__);
+ WARN_ON(1); /* should not happen */
+ }
+
+ clone = io->cloned_request;
+ io->error = 0;
+ dm_dispatch_request(clone);
+}
+
+/* Queue callback function that will get triggered */
+static void req_cryptd_crypt(struct work_struct *work)
+{
+ struct req_dm_crypt_io *io =
+ container_of(work, struct req_dm_crypt_io, work);
+
+ if (rq_data_dir(io->cloned_request) == WRITE) {
+ if (io->should_encrypt)
+ req_cryptd_crypt_write_convert(io);
+ else
+ req_cryptd_crypt_write_plain(io);
+ } else if (rq_data_dir(io->cloned_request) == READ) {
+ if (io->should_decrypt)
+ req_cryptd_crypt_read_convert(io);
+ else
+ req_cryptd_crypt_read_plain(io);
+ } else {
+ DMERR("%s received non-write request for Clone 0x%p\n",
+ __func__, io->cloned_request);
+ }
+}
+
+static void req_cryptd_split_req_queue_cb(struct work_struct *work)
+{
+ struct req_dm_split_req_io *io =
+ container_of(work, struct req_dm_split_req_io, work);
+ struct skcipher_request *req = NULL;
+ struct req_crypt_result result;
+ int err = 0;
+ struct crypto_engine_entry *engine = NULL;
+
+ if ((!io) || (!io->req_split_sg_read) || (!io->engine)) {
+ DMERR("%s Input invalid\n",
+ __func__);
+ err = DM_REQ_CRYPT_ERROR;
+ /* If io is not populated this should not be called */
+ WARN_ON(1);
+ }
+ req = skcipher_request_alloc(tfm, GFP_KERNEL);
+ if (!req) {
+ DMERR("%s skcipher request allocation failed\n", __func__);
+ err = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+
+ skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
+ req_crypt_cipher_complete, &result);
+
+ engine = io->engine;
+
+ err = (dm_qcrypto_func.cipher_set)(req, engine->ce_device,
+ engine->hw_instance);
+ if (err) {
+ DMERR("%s qcrypto_cipher_set_device_hw failed with err %d\n",
+ __func__, err);
+ goto skcipher_req_alloc_failure;
+ }
+ init_completion(&result.completion);
+ (dm_qcrypto_func.cipher_flag)(req,
+ QCRYPTO_CTX_USE_PIPE_KEY | QCRYPTO_CTX_XTS_DU_SIZE_512B);
+
+ crypto_skcipher_clear_flags(tfm, ~0);
+ crypto_skcipher_setkey(tfm, NULL, KEY_SIZE_XTS);
+
+ skcipher_request_set_crypt(req, io->req_split_sg_read,
+ io->req_split_sg_read, io->size, (void *) io->IV);
+
+ err = crypto_skcipher_decrypt(req);
+ switch (err) {
+ case 0:
+ break;
+
+ case -EBUSY:
+ /*
+ * Lets make this synchronous request by waiting on
+ * in progress as well
+ */
+ case -EINPROGRESS:
+ wait_for_completion_io(&result.completion);
+ if (result.err) {
+ DMERR("%s error = %d encrypting the request\n",
+ __func__, result.err);
+ err = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+ break;
+
+ default:
+ err = DM_REQ_CRYPT_ERROR;
+ goto skcipher_req_alloc_failure;
+ }
+ err = 0;
+skcipher_req_alloc_failure:
+ if (req)
+ skcipher_request_free(req);
+
+ req_crypt_split_io_complete(&io->result, err);
+}
+
+static void req_cryptd_split_req_queue(struct req_dm_split_req_io *io)
+{
+ INIT_WORK(&io->work, req_cryptd_split_req_queue_cb);
+ queue_work(req_crypt_split_io_queue, &io->work);
+}
+
+static void req_cryptd_queue_crypt(struct req_dm_crypt_io *io)
+{
+ INIT_WORK(&io->work, req_cryptd_crypt);
+ queue_work(req_crypt_queue, &io->work);
+}
+
+/*
+ * Cipher complete callback, this is triggered by the Linux crypto api once
+ * the operation is done. This signals the waiting thread that the crypto
+ * operation is complete.
+ */
+static void req_crypt_cipher_complete(struct crypto_async_request *req, int err)
+{
+ struct req_crypt_result *res = req->data;
+
+ if (err == -EINPROGRESS)
+ return;
+
+ res->err = err;
+ complete(&res->completion);
+}
+
+static void req_crypt_split_io_complete(struct req_crypt_result *res, int err)
+{
+ if (err == -EINPROGRESS)
+ return;
+
+ res->err = err;
+ complete(&res->completion);
+}
+/*
+ * If bio->bi_dev is a partition, remap the location
+ */
+static inline void req_crypt_blk_partition_remap(struct bio *bio)
+{
+ struct block_device *bdev = bio->bi_bdev;
+
+ if (bio_sectors(bio) && bdev != bdev->bd_contains) {
+ struct hd_struct *p = bdev->bd_part;
+ /*
+ * Check for integer overflow, should never happen.
+ */
+ if (p->start_sect > (UINT_MAX - bio->bi_iter.bi_sector))
+ WARN_ON(1);
+
+ bio->bi_iter.bi_sector += p->start_sect;
+ bio->bi_bdev = bdev->bd_contains;
+ }
+}
+
+/*
+ * The endio function is called from ksoftirqd context (atomic).
+ * For write operations the new pages created form the mempool
+ * is freed and returned. * For read operations, decryption is
+ * required, since this is called in a atomic * context, the
+ * request is sent to a worker queue to complete decryptiona and
+ * free the request once done.
+ */
+static int req_crypt_endio(struct dm_target *ti, struct request *clone,
+ int error, union map_info *map_context)
+{
+ int err = 0;
+ struct req_iterator iter1;
+ struct bio_vec bvec;
+ struct req_dm_crypt_io *req_io = map_context->ptr;
+
+ /* If it is for ICE, free up req_io and return */
+ if (encryption_mode == DM_REQ_CRYPT_ENCRYPTION_MODE_TRANSPARENT) {
+ mempool_free(req_io, req_io_pool);
+ err = error;
+ goto submit_request;
+ }
+
+ if (rq_data_dir(clone) == WRITE) {
+ rq_for_each_segment(bvec, clone, iter1) {
+ if (req_io->should_encrypt && bvec.bv_offset == 0) {
+ mempool_free(bvec.bv_page, req_page_pool);
+ bvec.bv_page = NULL;
+ } else
+ bvec.bv_page = NULL;
+ }
+ mempool_free(req_io, req_io_pool);
+ goto submit_request;
+ } else if (rq_data_dir(clone) == READ) {
+ req_io->error = error;
+ req_cryptd_queue_crypt(req_io);
+ err = DM_ENDIO_INCOMPLETE;
+ goto submit_request;
+ }
+
+submit_request:
+ return err;
+}
+
+/*
+ * This function is called with interrupts disabled
+ * The function remaps the clone for the underlying device.
+ * If it is a write request, it calls into the worker queue to
+ * encrypt the data
+ * and submit the request directly using the elevator
+ * For a read request no pre-processing is required the request
+ * is returned to dm once mapping is done
+ */
+static int req_crypt_map(struct dm_target *ti, struct request *clone,
+ union map_info *map_context)
+{
+ struct req_dm_crypt_io *req_io = NULL;
+ int error = DM_REQ_CRYPT_ERROR, copy_bio_sector_to_req = 0;
+ struct bio *bio_src = NULL;
+ gfp_t gfp_flag = GFP_KERNEL;
+
+ if (in_interrupt() || irqs_disabled())
+ gfp_flag = GFP_NOWAIT;
+
+ req_io = mempool_alloc(req_io_pool, gfp_flag);
+ if (!req_io) {
+ WARN_ON(1);
+ error = DM_REQ_CRYPT_ERROR;
+ goto submit_request;
+ }
+
+ /* Save the clone in the req_io, the callback to the worker
+ * queue will get the req_io
+ */
+ req_io->cloned_request = clone;
+ map_context->ptr = req_io;
+ atomic_set(&req_io->pending, 0);
+
+ if (rq_data_dir(clone) == WRITE)
+ req_io->should_encrypt = req_crypt_should_encrypt(req_io);
+ if (rq_data_dir(clone) == READ)
+ req_io->should_decrypt = req_crypt_should_deccrypt(req_io);
+
+ /* Get the queue of the underlying original device */
+ clone->q = bdev_get_queue(dev->bdev);
+ clone->rq_disk = dev->bdev->bd_disk;
+
+ __rq_for_each_bio(bio_src, clone) {
+ bio_src->bi_bdev = dev->bdev;
+ /* Currently the way req-dm works is that once the underlying
+ * device driver completes the request by calling into the
+ * block layer. The block layer completes the bios (clones) and
+ * then the cloned request. This is undesirable for req-dm-crypt
+ * hence added a flag BIO_DONTFREE, this flag will ensure that
+ * blk layer does not complete the cloned bios before completing
+ * the request. When the crypt endio is called, post-processing
+ * is done and then the dm layer will complete the bios (clones)
+ * and free them.
+ */
+ if (encryption_mode == DM_REQ_CRYPT_ENCRYPTION_MODE_TRANSPARENT)
+ bio_src->bi_flags |= 1 << BIO_INLINECRYPT;
+ else
+ bio_src->bi_flags |= 1 << BIO_DONTFREE;
+
+ /*
+ * If this device has partitions, remap block n
+ * of partition p to block n+start(p) of the disk.
+ */
+ req_crypt_blk_partition_remap(bio_src);
+ if (copy_bio_sector_to_req == 0) {
+ clone->__sector = bio_src->bi_iter.bi_sector;
+ copy_bio_sector_to_req++;
+ }
+ blk_queue_bounce(clone->q, &bio_src);
+ }
+
+ if (encryption_mode == DM_REQ_CRYPT_ENCRYPTION_MODE_TRANSPARENT) {
+ /* Set all crypto parameters for inline crypto engine */
+ memcpy(&req_io->ice_settings, ice_settings,
+ sizeof(struct ice_crypto_setting));
+ } else {
+ /* ICE checks for key_index which could be >= 0. If a chip has
+ * both ICE and GPCE and wanted to use GPCE, there could be
+ * issue. Storage driver send all requests to ICE driver. If
+ * it sees key_index as 0, it would assume it is for ICE while
+ * it is not. Hence set invalid key index by default.
+ */
+ req_io->ice_settings.key_index = -1;
+
+ }
+
+ if (rq_data_dir(clone) == READ ||
+ encryption_mode == DM_REQ_CRYPT_ENCRYPTION_MODE_TRANSPARENT) {
+ error = DM_MAPIO_REMAPPED;
+ goto submit_request;
+ } else if (rq_data_dir(clone) == WRITE) {
+ req_cryptd_queue_crypt(req_io);
+ error = DM_MAPIO_SUBMITTED;
+ goto submit_request;
+ }
+
+submit_request:
+ return error;
+
+}
+
+static void deconfigure_qcrypto(void)
+{
+ mempool_destroy(req_page_pool);
+ req_page_pool = NULL;
+
+ mempool_destroy(req_scatterlist_pool);
+ req_scatterlist_pool = NULL;
+
+ if (req_crypt_split_io_queue) {
+ destroy_workqueue(req_crypt_split_io_queue);
+ req_crypt_split_io_queue = NULL;
+ }
+ if (req_crypt_queue) {
+ destroy_workqueue(req_crypt_queue);
+ req_crypt_queue = NULL;
+ }
+
+ kmem_cache_destroy(_req_dm_scatterlist_pool);
+
+ mutex_lock(&engine_list_mutex);
+ kfree(pfe_eng);
+ pfe_eng = NULL;
+ kfree(fde_eng);
+ fde_eng = NULL;
+ mutex_unlock(&engine_list_mutex);
+
+ if (tfm) {
+ crypto_free_skcipher(tfm);
+ tfm = NULL;
+ }
+}
+
+static void req_crypt_dtr(struct dm_target *ti)
+{
+ DMDEBUG("dm-req-crypt Destructor.\n");
+
+ mempool_destroy(req_io_pool);
+ req_io_pool = NULL;
+
+ if (encryption_mode == DM_REQ_CRYPT_ENCRYPTION_MODE_TRANSPARENT) {
+ kfree(ice_settings);
+ ice_settings = NULL;
+ } else {
+ deconfigure_qcrypto();
+ }
+
+ kmem_cache_destroy(_req_crypt_io_pool);
+
+ if (dev) {
+ dm_put_device(ti, dev);
+ dev = NULL;
+ }
+}
+
+static int configure_qcrypto(void)
+{
+ struct crypto_engine_entry *eng_list = NULL;
+ struct block_device *bdev = NULL;
+ int err = DM_REQ_CRYPT_ERROR, i;
+ struct request_queue *q = NULL;
+
+ bdev = dev->bdev;
+ q = bdev_get_queue(bdev);
+ blk_queue_max_hw_sectors(q, DM_REQ_CRYPT_QUEUE_SIZE);
+
+ /* Allocate the crypto alloc blk cipher and keep the handle */
+ tfm = crypto_alloc_skcipher("qcom-xts(aes)", 0, 0);
+ if (IS_ERR(tfm)) {
+ DMERR("%s skcipher tfm allocation failed : error\n",
+ __func__);
+ tfm = NULL;
+ goto exit_err;
+ }
+
+ num_engines_fde = num_engines_pfe = 0;
+
+ mutex_lock(&engine_list_mutex);
+ num_engines = (dm_qcrypto_func.get_num_engines)();
+ if (!num_engines) {
+ DMERR(KERN_INFO "%s qcrypto_get_num_engines failed\n",
+ __func__);
+ err = DM_REQ_CRYPT_ERROR;
+ mutex_unlock(&engine_list_mutex);
+ goto exit_err;
+ }
+
+ eng_list = kcalloc(num_engines, sizeof(*eng_list), GFP_KERNEL);
+ if (eng_list == NULL) {
+ DMERR("%s engine list allocation failed\n", __func__);
+ err = DM_REQ_CRYPT_ERROR;
+ mutex_unlock(&engine_list_mutex);
+ goto exit_err;
+ }
+
+ (dm_qcrypto_func.get_engine_list)(num_engines, eng_list);
+
+ for (i = 0; i < num_engines; i++) {
+ if (eng_list[i].ce_device == FDE_KEY_ID)
+ num_engines_fde++;
+ if (eng_list[i].ce_device == PFE_KEY_ID)
+ num_engines_pfe++;
+ }
+
+ fde_eng = kcalloc(num_engines_fde, sizeof(*fde_eng), GFP_KERNEL);
+ if (fde_eng == NULL) {
+ DMERR("%s fde engine list allocation failed\n", __func__);
+ mutex_unlock(&engine_list_mutex);
+ goto exit_err;
+ }
+
+ pfe_eng = kcalloc(num_engines_pfe, sizeof(*pfe_eng), GFP_KERNEL);
+ if (pfe_eng == NULL) {
+ DMERR("%s pfe engine list allocation failed\n", __func__);
+ mutex_unlock(&engine_list_mutex);
+ goto exit_err;
+ }
+
+ fde_cursor = 0;
+ pfe_cursor = 0;
+
+ for (i = 0; i < num_engines; i++) {
+ if (eng_list[i].ce_device == FDE_KEY_ID)
+ fde_eng[fde_cursor++] = eng_list[i];
+ if (eng_list[i].ce_device == PFE_KEY_ID)
+ pfe_eng[pfe_cursor++] = eng_list[i];
+ }
+
+ fde_cursor = 0;
+ pfe_cursor = 0;
+ mutex_unlock(&engine_list_mutex);
+
+ _req_dm_scatterlist_pool = kmem_cache_create("req_dm_scatterlist",
+ sizeof(struct scatterlist) * MAX_SG_LIST,
+ __alignof__(struct scatterlist), 0, NULL);
+ if (!_req_dm_scatterlist_pool)
+ goto exit_err;
+
+ req_crypt_queue = alloc_workqueue("req_cryptd",
+ WQ_UNBOUND |
+ WQ_CPU_INTENSIVE |
+ WQ_MEM_RECLAIM,
+ 0);
+ if (!req_crypt_queue) {
+ DMERR("%s req_crypt_queue not allocated\n", __func__);
+ goto exit_err;
+ }
+
+ req_crypt_split_io_queue = alloc_workqueue("req_crypt_split",
+ WQ_UNBOUND |
+ WQ_CPU_INTENSIVE |
+ WQ_MEM_RECLAIM,
+ 0);
+ if (!req_crypt_split_io_queue) {
+ DMERR("%s req_crypt_split_io_queue not allocated\n", __func__);
+ goto exit_err;
+ }
+ req_scatterlist_pool = mempool_create_slab_pool(MIN_IOS,
+ _req_dm_scatterlist_pool);
+ if (!req_scatterlist_pool) {
+ DMERR("%s req_scatterlist_pool is not allocated\n", __func__);
+ err = -ENOMEM;
+ goto exit_err;
+ }
+
+ req_page_pool = mempool_create_page_pool(MIN_POOL_PAGES, 0);
+ if (!req_page_pool) {
+ DMERR("%s req_page_pool not allocated\n", __func__);
+ goto exit_err;
+ }
+
+ err = 0;
+
+exit_err:
+ kfree(eng_list);
+ return err;
+}
+
+/*
+ * Construct an encryption mapping:
+ * <cipher> <key> <iv_offset> <dev_path> <start>
+ */
+static int req_crypt_ctr(struct dm_target *ti, unsigned int argc, char **argv)
+{
+ int err = DM_REQ_CRYPT_ERROR;
+ unsigned long long tmpll;
+ char dummy;
+ int ret;
+
+ DMDEBUG("dm-req-crypt Constructor.\n");
+
+ if (argc < 5) {
+ DMERR(" %s Not enough args\n", __func__);
+ err = DM_REQ_CRYPT_ERROR;
+ goto ctr_exit;
+ }
+
+ if (argv[3]) {
+ if (dm_get_device(ti, argv[3],
+ dm_table_get_mode(ti->table), &dev)) {
+ DMERR(" %s Device Lookup failed\n", __func__);
+ err = DM_REQ_CRYPT_ERROR;
+ goto ctr_exit;
+ }
+ } else {
+ DMERR(" %s Arg[3] invalid\n", __func__);
+ err = DM_REQ_CRYPT_ERROR;
+ goto ctr_exit;
+ }
+
+ if (argv[4]) {
+ if (sscanf(argv[4], "%llu%c", &tmpll, &dummy) != 1) {
+ DMERR("%s Invalid device sector\n", __func__);
+ err = DM_REQ_CRYPT_ERROR;
+ goto ctr_exit;
+ }
+ } else {
+ DMERR(" %s Arg[4] invalid\n", __func__);
+ err = DM_REQ_CRYPT_ERROR;
+ goto ctr_exit;
+ }
+ start_sector_orig = tmpll;
+
+ /* Allow backward compatible */
+ if (argc >= 6) {
+ if (argv[5]) {
+ if (!strcmp(argv[5], "fde_enabled"))
+ is_fde_enabled = true;
+ else
+ is_fde_enabled = false;
+ } else {
+ DMERR(" %s Arg[5] invalid\n", __func__);
+ err = DM_REQ_CRYPT_ERROR;
+ goto ctr_exit;
+ }
+ } else {
+ DMERR(" %s Arg[5] missing, set FDE enabled.\n", __func__);
+ is_fde_enabled = true; /* backward compatible */
+ }
+
+ _req_crypt_io_pool = KMEM_CACHE(req_dm_crypt_io, 0);
+ if (!_req_crypt_io_pool) {
+ err = DM_REQ_CRYPT_ERROR;
+ goto ctr_exit;
+ }
+
+ encryption_mode = DM_REQ_CRYPT_ENCRYPTION_MODE_CRYPTO;
+ if (argc >= 7 && argv[6]) {
+ if (!strcmp(argv[6], "ice"))
+ encryption_mode =
+ DM_REQ_CRYPT_ENCRYPTION_MODE_TRANSPARENT;
+ }
+
+ if (encryption_mode == DM_REQ_CRYPT_ENCRYPTION_MODE_TRANSPARENT) {
+ /* configure ICE settings */
+ ice_settings =
+ kzalloc(sizeof(struct ice_crypto_setting), GFP_KERNEL);
+ if (!ice_settings) {
+ err = -ENOMEM;
+ goto ctr_exit;
+ }
+ ice_settings->key_size = ICE_CRYPTO_KEY_SIZE_128;
+ ice_settings->algo_mode = ICE_CRYPTO_ALGO_MODE_AES_XTS;
+ ice_settings->key_mode = ICE_CRYPTO_USE_LUT_SW_KEY;
+ if (kstrtou16(argv[1], 0, &ice_settings->key_index) ||
+ ice_settings->key_index < 0 ||
+ ice_settings->key_index > MAX_MSM_ICE_KEY_LUT_SIZE) {
+ DMERR("%s Err: key index %d received for ICE\n",
+ __func__, ice_settings->key_index);
+ err = DM_REQ_CRYPT_ERROR;
+ goto ctr_exit;
+ }
+ } else {
+ ret = configure_qcrypto();
+ if (ret) {
+ DMERR("%s failed to configure qcrypto\n", __func__);
+ err = ret;
+ goto ctr_exit;
+ }
+ }
+
+ req_io_pool = mempool_create_slab_pool(MIN_IOS, _req_crypt_io_pool);
+ if (!req_io_pool) {
+ DMERR("%s req_io_pool not allocated\n", __func__);
+ err = -ENOMEM;
+ goto ctr_exit;
+ }
+
+ /*
+ * If underlying device supports flush/discard, mapped target
+ * should also allow it
+ */
+ ti->num_flush_bios = 1;
+ ti->num_discard_bios = 1;
+
+ err = 0;
+ DMINFO("%s: Mapping block_device %s to dm-req-crypt ok!\n",
+ __func__, argv[3]);
+ctr_exit:
+ if (err)
+ req_crypt_dtr(ti);
+
+ return err;
+}
+
+static int req_crypt_iterate_devices(struct dm_target *ti,
+ iterate_devices_callout_fn fn, void *data)
+{
+ return fn(ti, dev, start_sector_orig, ti->len, data);
+}
+void set_qcrypto_func_dm(void *dev,
+ void *flag,
+ void *engines,
+ void *engine_list)
+{
+ dm_qcrypto_func.cipher_set = dev;
+ dm_qcrypto_func.cipher_flag = flag;
+ dm_qcrypto_func.get_num_engines = engines;
+ dm_qcrypto_func.get_engine_list = engine_list;
+}
+EXPORT_SYMBOL(set_qcrypto_func_dm);
+
+static struct target_type req_crypt_target = {
+ .name = "req-crypt",
+ .version = {1, 0, 0},
+ .module = THIS_MODULE,
+ .ctr = req_crypt_ctr,
+ .dtr = req_crypt_dtr,
+ .map_rq = req_crypt_map,
+ .rq_end_io = req_crypt_endio,
+ .iterate_devices = req_crypt_iterate_devices,
+};
+
+static int __init req_dm_crypt_init(void)
+{
+ int r;
+
+
+ r = dm_register_target(&req_crypt_target);
+ if (r < 0) {
+ DMERR("register failed %d", r);
+ return r;
+ }
+
+ DMINFO("dm-req-crypt successfully initalized.\n");
+
+ return r;
+}
+
+static void __exit req_dm_crypt_exit(void)
+{
+ dm_unregister_target(&req_crypt_target);
+}
+
+module_init(req_dm_crypt_init);
+module_exit(req_dm_crypt_exit);
+
+MODULE_DESCRIPTION(DM_NAME " target for request based transparent encryption / decryption");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/md/dm-rq.c b/drivers/md/dm-rq.c
index ba7c4c6..bca4c0e 100644
--- a/drivers/md/dm-rq.c
+++ b/drivers/md/dm-rq.c
@@ -283,7 +283,7 @@
* Must be called without clone's queue lock held,
* see end_clone_request() for more details.
*/
-static void dm_end_request(struct request *clone, int error)
+void dm_end_request(struct request *clone, int error)
{
int rw = rq_data_dir(clone);
struct dm_rq_target_io *tio = clone->end_io_data;
@@ -464,7 +464,7 @@
* Target's rq_end_io() function isn't called.
* This may be used when the target's map_rq() or clone_and_map_rq() functions fail.
*/
-static void dm_kill_unmapped_request(struct request *rq, int error)
+void dm_kill_unmapped_request(struct request *rq, int error)
{
rq->cmd_flags |= REQ_FAILED;
dm_complete_request(rq, error);
@@ -512,6 +512,13 @@
dm_complete_request(rq, r);
}
+void dm_dispatch_request(struct request *rq)
+{
+ struct dm_rq_target_io *tio = tio_from_request(rq);
+
+ dm_dispatch_clone_request(tio->clone, rq);
+}
+
static int dm_rq_bio_constructor(struct bio *bio, struct bio *bio_orig,
void *data)
{
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
index b582934..aa6c522 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
@@ -2677,9 +2677,9 @@
static irqreturn_t sde_hw_rotator_regdmairq_handler(int irq, void *ptr)
{
struct sde_hw_rotator *rot = ptr;
- struct sde_hw_rotator_context *ctx;
+ struct sde_hw_rotator_context *ctx, *tmp;
irqreturn_t ret = IRQ_NONE;
- u32 isr;
+ u32 isr, isr_tmp;
u32 ts;
u32 q_id;
@@ -2716,18 +2716,28 @@
* Timestamp packet is not available in sbuf mode.
* Simulate timestamp update in the handler instead.
*/
- if (!list_empty(&rot->sbuf_ctx[q_id])) {
- ctx = list_first_entry_or_null(&rot->sbuf_ctx[q_id],
- struct sde_hw_rotator_context, list);
- if (ctx) {
+ if (list_empty(&rot->sbuf_ctx[q_id]))
+ goto skip_sbuf;
+
+ ctx = NULL;
+ isr_tmp = isr;
+ list_for_each_entry(tmp, &rot->sbuf_ctx[q_id], list) {
+ u32 mask;
+
+ mask = tmp->timestamp & 0x1 ? REGDMA_INT_1_MASK :
+ REGDMA_INT_0_MASK;
+ if (isr_tmp & mask) {
+ isr_tmp &= ~mask;
+ ctx = tmp;
ts = ctx->timestamp;
sde_hw_rotator_update_swts(rot, ctx, ts);
SDEROT_DBG("update swts:0x%X\n", ts);
- } else {
- SDEROT_ERR("invalid swts ctx\n");
}
+ SDEROT_EVTLOG(isr, tmp->timestamp);
}
-
+ if (ctx == NULL)
+ SDEROT_ERR("invalid swts ctx\n");
+skip_sbuf:
ctx = rot->rotCtx[q_id][ts & SDE_HW_ROT_REGDMA_SEG_MASK];
/*
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3_hwio.h b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3_hwio.h
index d2b81d5..2afd032 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3_hwio.h
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3_hwio.h
@@ -297,4 +297,8 @@
#define REGDMA_TIMESTAMP_REG ROT_SSPP_TPG_PATTERN_GEN_INIT_VAL
#define REGDMA_RESET_STATUS_REG ROT_SSPP_TPG_RGB_MAPPING
+#define REGDMA_INT_0_MASK 0x101
+#define REGDMA_INT_1_MASK 0x202
+#define REGDMA_INT_2_MASK 0x404
+
#endif /*_SDE_ROTATOR_R3_HWIO_H */
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 9ac6568..f300435 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -1718,8 +1718,6 @@
/* We couldn't get a response from the card. Give up. */
if (err) {
- if (card->err_in_sdr104)
- return ERR_RETRY;
/* Check if the card is removed */
if (mmc_detect_card_removed(card->host))
return ERR_NOMEDIUM;
@@ -2210,8 +2208,7 @@
brq->data.error == -ETIMEDOUT ||
brq->cmd.error == -EILSEQ ||
brq->cmd.error == -EIO ||
- brq->cmd.error == -ETIMEDOUT ||
- brq->sbc.error))
+ brq->cmd.error == -ETIMEDOUT))
card->err_in_sdr104 = true;
/*
@@ -4664,10 +4661,6 @@
static void mmc_blk_shutdown(struct mmc_card *card)
{
_mmc_blk_suspend(card, 1);
-
- /* send power off notification */
- if (mmc_card_mmc(card))
- mmc_send_pon(card);
}
#ifdef CONFIG_PM_SLEEP
diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
index 1c28cf8..e3696c5 100644
--- a/drivers/mmc/core/bus.c
+++ b/drivers/mmc/core/bus.c
@@ -167,6 +167,19 @@
if (mmc_bus_needs_resume(host))
return 0;
ret = host->bus_ops->suspend(host);
+
+ /*
+ * bus_ops->suspend may fail due to some reason
+ * In such cases if we return error to PM framework
+ * from here without calling pm_generic_resume then mmc
+ * request may get stuck since PM framework will assume
+ * that mmc bus is not suspended (because of error) and
+ * it won't call resume again.
+ *
+ * So in case of error call pm_generic_resume().
+ */
+ if (ret)
+ pm_generic_resume(dev);
return ret;
}
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 3910d2d..787779c 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -456,22 +456,6 @@
}
EXPORT_SYMBOL(mmc_clk_update_freq);
-void mmc_recovery_fallback_lower_speed(struct mmc_host *host)
-{
- if (!host->card)
- return;
-
- if (host->sdr104_wa && mmc_card_sd(host->card) &&
- (host->ios.timing == MMC_TIMING_UHS_SDR104) &&
- !host->card->sdr104_blocked) {
- pr_err("%s: %s: blocked SDR104, lower the bus-speed (SDR50 / DDR50)\n",
- mmc_hostname(host), __func__);
- mmc_host_clear_sdr104(host);
- mmc_hw_reset(host);
- host->card->sdr104_blocked = true;
- }
-}
-
static int mmc_devfreq_set_target(struct device *dev,
unsigned long *freq, u32 devfreq_flags)
{
@@ -523,9 +507,6 @@
if (abort)
goto out;
- if (mmc_card_sd(host->card) && host->card->sdr104_blocked)
- goto rel_host;
-
/*
* In case we were able to claim host there is no need to
* defer the frequency change. It will be done now
@@ -534,18 +515,15 @@
mmc_host_clk_hold(host);
err = mmc_clk_update_freq(host, *freq, clk_scaling->state);
- if (err && err != -EAGAIN) {
+ if (err && err != -EAGAIN)
pr_err("%s: clock scale to %lu failed with error %d\n",
mmc_hostname(host), *freq, err);
- mmc_recovery_fallback_lower_speed(host);
- } else {
+ else
pr_debug("%s: clock change to %lu finished successfully (%s)\n",
mmc_hostname(host), *freq, current->comm);
- }
mmc_host_clk_release(host);
-rel_host:
mmc_release_host(host);
out:
return err;
@@ -566,9 +544,6 @@
if (!host->clk_scaling.enable)
return;
- if (mmc_card_sd(host->card) && host->card->sdr104_blocked)
- return;
-
spin_lock_bh(&host->clk_scaling.lock);
if (host->clk_scaling.clk_scaling_in_progress ||
@@ -589,15 +564,13 @@
err = mmc_clk_update_freq(host, target_freq,
host->clk_scaling.state);
- if (err && err != -EAGAIN) {
+ if (err && err != -EAGAIN)
pr_err("%s: failed on deferred scale clocks (%d)\n",
mmc_hostname(host), err);
- mmc_recovery_fallback_lower_speed(host);
- } else {
+ else
pr_debug("%s: clocks were successfully scaled to %lu (%s)\n",
mmc_hostname(host),
target_freq, current->comm);
- }
host->clk_scaling.clk_scaling_in_progress = false;
atomic_dec(&host->clk_scaling.devfreq_abort);
}
@@ -1598,13 +1571,8 @@
}
}
if (!cmd->error || !cmd->retries ||
- mmc_card_removed(host->card)) {
- if (cmd->error && !cmd->retries &&
- cmd->opcode != MMC_SEND_STATUS &&
- cmd->opcode != MMC_SEND_TUNING_BLOCK)
- mmc_recovery_fallback_lower_speed(host);
+ mmc_card_removed(host->card))
break;
- }
mmc_retune_recheck(host);
@@ -2272,6 +2240,38 @@
EXPORT_SYMBOL(__mmc_claim_host);
/**
+ * mmc_try_claim_host - try exclusively to claim a host
+ * and keep trying for given time, with a gap of 10ms
+ * @host: mmc host to claim
+ * @dealy_ms: delay in ms
+ *
+ * Returns %1 if the host is claimed, %0 otherwise.
+ */
+int mmc_try_claim_host(struct mmc_host *host, unsigned int delay_ms)
+{
+ int claimed_host = 0;
+ unsigned long flags;
+ int retry_cnt = delay_ms/10;
+
+ do {
+ spin_lock_irqsave(&host->lock, flags);
+ if (!host->claimed || host->claimer == current) {
+ host->claimed = 1;
+ host->claimer = current;
+ host->claim_cnt += 1;
+ claimed_host = 1;
+ }
+ spin_unlock_irqrestore(&host->lock, flags);
+ if (!claimed_host)
+ mmc_delay(10);
+ } while (!claimed_host && retry_cnt--);
+ if (host->ops->enable && claimed_host && host->claim_cnt == 1)
+ host->ops->enable(host);
+ return claimed_host;
+}
+EXPORT_SYMBOL(mmc_try_claim_host);
+
+/**
* mmc_release_host - release a host
* @host: mmc host to release
*
@@ -4157,12 +4157,10 @@
*/
int mmc_cmdq_hw_reset(struct mmc_host *host)
{
- if (!host->bus_ops->power_restore)
- return -EOPNOTSUPP;
+ if (!host->bus_ops->reset)
+ return -EOPNOTSUPP;
- mmc_power_cycle(host, host->ocr_avail);
- mmc_select_voltage(host, host->card->ocr);
- return host->bus_ops->power_restore(host);
+ return host->bus_ops->reset(host);
}
EXPORT_SYMBOL(mmc_cmdq_hw_reset);
@@ -4259,18 +4257,12 @@
}
if (ret) {
- if (host->ops->get_cd && host->ops->get_cd(host)) {
- mmc_recovery_fallback_lower_speed(host);
- ret = 0;
- } else {
- mmc_card_set_removed(host->card);
- if (host->card->sdr104_blocked) {
- mmc_host_set_sdr104(host);
- host->card->sdr104_blocked = false;
- }
- pr_debug("%s: card remove detected\n",
- mmc_hostname(host));
+ mmc_card_set_removed(host->card);
+ if (host->card->sdr104_blocked) {
+ mmc_host_set_sdr104(host);
+ host->card->sdr104_blocked = false;
}
+ pr_debug("%s: card remove detected\n", mmc_hostname(host));
}
return ret;
diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
index 0c8ff86..d1a0235 100644
--- a/drivers/mmc/core/debugfs.c
+++ b/drivers/mmc/core/debugfs.c
@@ -354,6 +354,33 @@
DEFINE_SIMPLE_ATTRIBUTE(mmc_force_err_fops, NULL, mmc_force_err_set, "%llu\n");
+static int mmc_err_state_get(void *data, u64 *val)
+{
+ struct mmc_host *host = data;
+
+ if (!host)
+ return -EINVAL;
+
+ *val = host->err_occurred ? 1 : 0;
+
+ return 0;
+}
+
+static int mmc_err_state_clear(void *data, u64 val)
+{
+ struct mmc_host *host = data;
+
+ if (!host)
+ return -EINVAL;
+
+ host->err_occurred = false;
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(mmc_err_state, mmc_err_state_get,
+ mmc_err_state_clear, "%llu\n");
+
void mmc_add_host_debugfs(struct mmc_host *host)
{
struct dentry *root;
@@ -399,6 +426,10 @@
root, host, &mmc_ring_buffer_fops))
goto err_node;
#endif
+ if (!debugfs_create_file("err_state", S_IRUSR | S_IWUSR, root, host,
+ &mmc_err_state))
+ goto err_node;
+
#ifdef CONFIG_MMC_CLKGATE
if (!debugfs_create_u32("clk_delay", (S_IRUSR | S_IWUSR),
root, &host->clk_delay))
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 564b5c9..3184dcd 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -2610,7 +2610,7 @@
static int _mmc_suspend(struct mmc_host *host, bool is_suspend)
{
- int err = 0;
+ int err = 0, ret;
BUG_ON(!host);
BUG_ON(!host->card);
@@ -2619,6 +2619,8 @@
if (err) {
pr_err("%s: %s: fail to suspend clock scaling (%d)\n",
mmc_hostname(host), __func__, err);
+ if (host->card->cmdq_init)
+ wake_up(&host->cmdq_ctx.wait);
return err;
}
@@ -2643,12 +2645,12 @@
if (mmc_card_doing_bkops(host->card)) {
err = mmc_stop_bkops(host->card);
if (err)
- goto out;
+ goto out_err;
}
err = mmc_flush_cache(host->card);
if (err)
- goto out;
+ goto out_err;
if (mmc_can_sleepawake(host)) {
/*
@@ -2665,16 +2667,38 @@
err = mmc_deselect_cards(host);
}
- if (!err) {
- mmc_power_off(host);
- mmc_card_set_suspended(host->card);
+ if (err)
+ goto out_err;
+ mmc_power_off(host);
+ mmc_card_set_suspended(host->card);
+
+ goto out;
+
+out_err:
+ /*
+ * In case of err let's put controller back in cmdq mode and unhalt
+ * the controller.
+ * We expect cmdq_enable and unhalt won't return any error
+ * since it is anyway enabling few registers.
+ */
+ if (host->card->cmdq_init) {
+ mmc_host_clk_hold(host);
+ ret = host->cmdq_ops->enable(host);
+ if (ret)
+ pr_err("%s: %s: enabling CMDQ mode failed (%d)\n",
+ mmc_hostname(host), __func__, ret);
+ mmc_host_clk_release(host);
+ mmc_cmdq_halt(host, false);
}
+
out:
/* Kick CMDQ thread to process any requests came in while suspending */
if (host->card->cmdq_init)
wake_up(&host->cmdq_ctx.wait);
mmc_release_host(host);
+ if (err)
+ mmc_resume_clk_scaling(host);
return err;
}
@@ -2963,6 +2987,7 @@
static int mmc_reset(struct mmc_host *host)
{
struct mmc_card *card = host->card;
+ int ret;
/*
* In the case of recovery, we can't expect flushing the cache to work
@@ -2983,7 +3008,45 @@
/* Do a brute force power cycle */
mmc_power_cycle(host, card->ocr);
}
- return mmc_init_card(host, card->ocr, card);
+
+ /* Suspend clk scaling to avoid switching frequencies intermittently */
+
+ ret = mmc_suspend_clk_scaling(host);
+ if (ret) {
+ pr_err("%s: %s: fail to suspend clock scaling (%d)\n",
+ mmc_hostname(host), __func__, ret);
+ return ret;
+ }
+
+ ret = mmc_init_card(host, host->card->ocr, host->card);
+ if (ret) {
+ pr_err("%s: %s: mmc_init_card failed (%d)\n",
+ mmc_hostname(host), __func__, ret);
+ return ret;
+ }
+
+ ret = mmc_resume_clk_scaling(host);
+ if (ret)
+ pr_err("%s: %s: fail to resume clock scaling (%d)\n",
+ mmc_hostname(host), __func__, ret);
+
+ return ret;
+}
+
+static int mmc_shutdown(struct mmc_host *host)
+{
+ struct mmc_card *card = host->card;
+
+ /*
+ * Exit clock scaling so that it doesn't kick in after
+ * power off notification is sent
+ */
+ if (host->caps2 & MMC_CAP2_CLK_SCALE)
+ mmc_exit_clk_scaling(card->host);
+ /* send power off notification */
+ if (mmc_card_mmc(card))
+ mmc_send_pon(card);
+ return 0;
}
static const struct mmc_bus_ops mmc_ops = {
@@ -2996,6 +3059,7 @@
.alive = mmc_alive,
.change_bus_speed = mmc_change_bus_speed,
.reset = mmc_reset,
+ .shutdown = mmc_shutdown,
};
/*
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index 7112f9f..650f658 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -1185,7 +1185,17 @@
BUG_ON(!host);
BUG_ON(!host->card);
- mmc_get_card(host->card);
+ /*
+ * Try to acquire claim host. If failed to get the lock in 2 sec,
+ * just return; This is to ensure that when this call is invoked
+ * due to pm_suspend, not to block suspend for longer duration.
+ */
+ pm_runtime_get_sync(&host->card->dev);
+ if (!mmc_try_claim_host(host, 2000)) {
+ pm_runtime_mark_last_busy(&host->card->dev);
+ pm_runtime_put_autosuspend(&host->card->dev);
+ return;
+ }
/*
* Just check if our card has been removed.
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index caf8dd1..1d9cf34 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -3270,6 +3270,21 @@
pr_err("-------------------------\n");
}
+static void sdhci_msm_cache_debug_data(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = pltfm_host->priv;
+ struct sdhci_msm_debug_data *cached_data = &msm_host->cached_data;
+
+ memcpy(&cached_data->copy_mmc, msm_host->mmc,
+ sizeof(struct mmc_host));
+ if (msm_host->mmc->card)
+ memcpy(&cached_data->copy_card, msm_host->mmc->card,
+ sizeof(struct mmc_card));
+ memcpy(&cached_data->copy_host, host,
+ sizeof(struct sdhci_host));
+}
+
void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -3281,6 +3296,7 @@
u32 test_bus_val = 0;
u32 debug_reg[MAX_TEST_BUS] = {0};
+ sdhci_msm_cache_debug_data(host);
pr_info("----------- VENDOR REGISTER DUMP -----------\n");
if (host->cq_host)
sdhci_msm_cmdq_dump_debug_ram(host);
@@ -3814,8 +3830,8 @@
group->req.type = PM_QOS_REQ_AFFINE_CORES;
cpumask_copy(&group->req.cpus_affine,
&msm_host->pdata->pm_qos_data.cpu_group_map.mask[i]);
- /* For initialization phase, set the performance mode latency */
- group->latency = latency[i].latency[SDHCI_PERFORMANCE_MODE];
+ /* We set default latency here for all pm_qos cpu groups. */
+ group->latency = PM_QOS_DEFAULT_VALUE;
pm_qos_add_request(&group->req, PM_QOS_CPU_DMA_LATENCY,
group->latency);
pr_info("%s (): voted for group #%d (mask=0x%lx) latency=%d (0x%p)\n",
diff --git a/drivers/mmc/host/sdhci-msm.h b/drivers/mmc/host/sdhci-msm.h
index a7577d9..2b907e9 100644
--- a/drivers/mmc/host/sdhci-msm.h
+++ b/drivers/mmc/host/sdhci-msm.h
@@ -170,6 +170,12 @@
int state;
};
+struct sdhci_msm_debug_data {
+ struct mmc_host copy_mmc;
+ struct mmc_card copy_card;
+ struct sdhci_host copy_host;
+};
+
struct sdhci_msm_host {
struct platform_device *pdev;
void __iomem *core_mem; /* MSM SDCC mapped address */
@@ -185,6 +191,7 @@
atomic_t clks_on; /* Set if clocks are enabled */
struct sdhci_msm_pltfm_data *pdata;
struct mmc_host *mmc;
+ struct sdhci_msm_debug_data cached_data;
struct sdhci_pltfm_data sdhci_msm_pdata;
u32 curr_pwr_state;
u32 curr_io_level;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 4bb4c18..8fbcdae 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -148,6 +148,8 @@
readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
}
+ host->mmc->err_occurred = true;
+
if (host->ops->dump_vendor_regs)
host->ops->dump_vendor_regs(host);
sdhci_dump_state(host);
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c
index 771a1f9..361d7dd0 100644
--- a/drivers/pci/host/pci-msm.c
+++ b/drivers/pci/host/pci-msm.c
@@ -564,7 +564,7 @@
msm_pcie_dev_tbl[MAX_RC_NUM * MAX_DEVICE_NUM];
/* PCIe driver state */
-struct pcie_drv_sta {
+static struct pcie_drv_sta {
u32 rc_num;
struct mutex drv_lock;
} pcie_drv;
@@ -690,14 +690,14 @@
/* resources */
static const struct msm_pcie_res_info_t msm_pcie_res_info[MSM_PCIE_MAX_RES] = {
- {"parf", 0, 0},
- {"phy", 0, 0},
- {"dm_core", 0, 0},
- {"elbi", 0, 0},
- {"conf", 0, 0},
- {"io", 0, 0},
- {"bars", 0, 0},
- {"tcsr", 0, 0}
+ {"parf", NULL, NULL},
+ {"phy", NULL, NULL},
+ {"dm_core", NULL, NULL},
+ {"elbi", NULL, NULL},
+ {"conf", NULL, NULL},
+ {"io", NULL, NULL},
+ {"bars", NULL, NULL},
+ {"tcsr", NULL, NULL}
};
/* irqs */
@@ -763,14 +763,14 @@
}
#endif
-static inline void msm_pcie_write_reg(void *base, u32 offset, u32 value)
+static inline void msm_pcie_write_reg(void __iomem *base, u32 offset, u32 value)
{
writel_relaxed(value, base + offset);
/* ensure that changes propagated to the hardware */
wmb();
}
-static inline void msm_pcie_write_reg_field(void *base, u32 offset,
+static inline void msm_pcie_write_reg_field(void __iomem *base, u32 offset,
const u32 mask, u32 val)
{
u32 shift = find_first_bit((void *)&mask, 32);
@@ -976,7 +976,7 @@
int i, j;
u32 val = 0;
u32 *shadow;
- void *cfg = dev->conf;
+ void __iomem *cfg = dev->conf;
for (i = 0; i < MAX_DEVICE_NUM; i++) {
if (!rc && !dev->pcidev_table[i].bdf)
@@ -1764,7 +1764,7 @@
return count;
}
-const struct file_operations msm_pcie_cmd_debug_ops = {
+static const struct file_operations msm_pcie_cmd_debug_ops = {
.write = msm_pcie_cmd_debug,
};
@@ -1807,7 +1807,7 @@
return count;
}
-const struct file_operations msm_pcie_rc_sel_ops = {
+static const struct file_operations msm_pcie_rc_sel_ops = {
.write = msm_pcie_set_rc_sel,
};
@@ -1865,7 +1865,7 @@
return count;
}
-const struct file_operations msm_pcie_base_sel_ops = {
+static const struct file_operations msm_pcie_base_sel_ops = {
.write = msm_pcie_set_base_sel,
};
@@ -1911,7 +1911,7 @@
return count;
}
-const struct file_operations msm_pcie_linkdown_panic_ops = {
+static const struct file_operations msm_pcie_linkdown_panic_ops = {
.write = msm_pcie_set_linkdown_panic,
};
@@ -1938,7 +1938,7 @@
return count;
}
-const struct file_operations msm_pcie_wr_offset_ops = {
+static const struct file_operations msm_pcie_wr_offset_ops = {
.write = msm_pcie_set_wr_offset,
};
@@ -1965,7 +1965,7 @@
return count;
}
-const struct file_operations msm_pcie_wr_mask_ops = {
+static const struct file_operations msm_pcie_wr_mask_ops = {
.write = msm_pcie_set_wr_mask,
};
static ssize_t msm_pcie_set_wr_value(struct file *file,
@@ -1991,7 +1991,7 @@
return count;
}
-const struct file_operations msm_pcie_wr_value_ops = {
+static const struct file_operations msm_pcie_wr_value_ops = {
.write = msm_pcie_set_wr_value,
};
@@ -2035,7 +2035,7 @@
return count;
}
-const struct file_operations msm_pcie_boot_option_ops = {
+static const struct file_operations msm_pcie_boot_option_ops = {
.write = msm_pcie_set_boot_option,
};
@@ -2091,7 +2091,7 @@
return count;
}
-const struct file_operations msm_pcie_aer_enable_ops = {
+static const struct file_operations msm_pcie_aer_enable_ops = {
.write = msm_pcie_set_aer_enable,
};
@@ -2118,7 +2118,7 @@
return count;
}
-const struct file_operations msm_pcie_corr_counter_limit_ops = {
+static const struct file_operations msm_pcie_corr_counter_limit_ops = {
.write = msm_pcie_set_corr_counter_limit,
};
@@ -2127,14 +2127,14 @@
rc_sel_max = (0x1 << MAX_RC_NUM) - 1;
wr_mask = 0xffffffff;
- dent_msm_pcie = debugfs_create_dir("pci-msm", 0);
+ dent_msm_pcie = debugfs_create_dir("pci-msm", NULL);
if (IS_ERR(dent_msm_pcie)) {
pr_err("PCIe: fail to create the folder for debug_fs.\n");
return;
}
dfile_rc_sel = debugfs_create_file("rc_sel", 0664,
- dent_msm_pcie, 0,
+ dent_msm_pcie, NULL,
&msm_pcie_rc_sel_ops);
if (!dfile_rc_sel || IS_ERR(dfile_rc_sel)) {
pr_err("PCIe: fail to create the file for debug_fs rc_sel.\n");
@@ -2142,7 +2142,7 @@
}
dfile_case = debugfs_create_file("case", 0664,
- dent_msm_pcie, 0,
+ dent_msm_pcie, NULL,
&msm_pcie_cmd_debug_ops);
if (!dfile_case || IS_ERR(dfile_case)) {
pr_err("PCIe: fail to create the file for debug_fs case.\n");
@@ -2150,7 +2150,7 @@
}
dfile_base_sel = debugfs_create_file("base_sel", 0664,
- dent_msm_pcie, 0,
+ dent_msm_pcie, NULL,
&msm_pcie_base_sel_ops);
if (!dfile_base_sel || IS_ERR(dfile_base_sel)) {
pr_err("PCIe: fail to create the file for debug_fs base_sel.\n");
@@ -2158,7 +2158,7 @@
}
dfile_linkdown_panic = debugfs_create_file("linkdown_panic", 0644,
- dent_msm_pcie, 0,
+ dent_msm_pcie, NULL,
&msm_pcie_linkdown_panic_ops);
if (!dfile_linkdown_panic || IS_ERR(dfile_linkdown_panic)) {
pr_err("PCIe: fail to create the file for debug_fs linkdown_panic.\n");
@@ -2166,7 +2166,7 @@
}
dfile_wr_offset = debugfs_create_file("wr_offset", 0664,
- dent_msm_pcie, 0,
+ dent_msm_pcie, NULL,
&msm_pcie_wr_offset_ops);
if (!dfile_wr_offset || IS_ERR(dfile_wr_offset)) {
pr_err("PCIe: fail to create the file for debug_fs wr_offset.\n");
@@ -2174,7 +2174,7 @@
}
dfile_wr_mask = debugfs_create_file("wr_mask", 0664,
- dent_msm_pcie, 0,
+ dent_msm_pcie, NULL,
&msm_pcie_wr_mask_ops);
if (!dfile_wr_mask || IS_ERR(dfile_wr_mask)) {
pr_err("PCIe: fail to create the file for debug_fs wr_mask.\n");
@@ -2182,7 +2182,7 @@
}
dfile_wr_value = debugfs_create_file("wr_value", 0664,
- dent_msm_pcie, 0,
+ dent_msm_pcie, NULL,
&msm_pcie_wr_value_ops);
if (!dfile_wr_value || IS_ERR(dfile_wr_value)) {
pr_err("PCIe: fail to create the file for debug_fs wr_value.\n");
@@ -2190,7 +2190,7 @@
}
dfile_boot_option = debugfs_create_file("boot_option", 0664,
- dent_msm_pcie, 0,
+ dent_msm_pcie, NULL,
&msm_pcie_boot_option_ops);
if (!dfile_boot_option || IS_ERR(dfile_boot_option)) {
pr_err("PCIe: fail to create the file for debug_fs boot_option.\n");
@@ -2198,7 +2198,7 @@
}
dfile_aer_enable = debugfs_create_file("aer_enable", 0664,
- dent_msm_pcie, 0,
+ dent_msm_pcie, NULL,
&msm_pcie_aer_enable_ops);
if (!dfile_aer_enable || IS_ERR(dfile_aer_enable)) {
pr_err("PCIe: fail to create the file for debug_fs aer_enable.\n");
@@ -2206,7 +2206,7 @@
}
dfile_corr_counter_limit = debugfs_create_file("corr_counter_limit",
- 0664, dent_msm_pcie, 0,
+ 0664, dent_msm_pcie, NULL,
&msm_pcie_corr_counter_limit_ops);
if (!dfile_corr_counter_limit || IS_ERR(dfile_corr_counter_limit)) {
pr_err("PCIe: fail to create the file for debug_fs corr_counter_limit.\n");
@@ -2609,7 +2609,7 @@
gpio_free(dev->gpio[i].num);
}
-int msm_pcie_vreg_init(struct msm_pcie_dev_t *dev)
+static int msm_pcie_vreg_init(struct msm_pcie_dev_t *dev)
{
int i, rc = 0;
struct regulator *vreg;
@@ -3229,7 +3229,7 @@
}
}
-void msm_pcie_config_msi_controller(struct msm_pcie_dev_t *dev)
+static void msm_pcie_config_msi_controller(struct msm_pcie_dev_t *dev)
{
int i;
@@ -3638,7 +3638,7 @@
dev->dev_io_res = NULL;
}
-int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
+static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
{
int ret = 0;
uint32_t val;
@@ -3895,7 +3895,7 @@
return ret;
}
-void msm_pcie_disable(struct msm_pcie_dev_t *dev, u32 options)
+static void msm_pcie_disable(struct msm_pcie_dev_t *dev, u32 options)
{
PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx);
@@ -4721,7 +4721,7 @@
}
}
-void msm_pcie_destroy_irq(unsigned int irq, struct pci_dev *pdev)
+static void msm_pcie_destroy_irq(unsigned int irq, struct pci_dev *pdev)
{
int pos;
struct msi_desc *entry = irq_get_msi_desc(irq);
@@ -5093,7 +5093,7 @@
.map = msm_pcie_msi_map,
};
-int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev)
+static int32_t msm_pcie_irq_init(struct msm_pcie_dev_t *dev)
{
int rc;
int msi_start = 0;
@@ -5233,7 +5233,7 @@
return 0;
}
-void msm_pcie_irq_deinit(struct msm_pcie_dev_t *dev)
+static void msm_pcie_irq_deinit(struct msm_pcie_dev_t *dev)
{
PCIE_DBG(dev, "RC%d\n", dev->rc_idx);
@@ -5575,7 +5575,7 @@
msm_pcie_dev[rc_idx].pcidev_table[i].short_bdf = 0;
msm_pcie_dev[rc_idx].pcidev_table[i].sid = 0;
msm_pcie_dev[rc_idx].pcidev_table[i].domain = rc_idx;
- msm_pcie_dev[rc_idx].pcidev_table[i].conf_base = 0;
+ msm_pcie_dev[rc_idx].pcidev_table[i].conf_base = NULL;
msm_pcie_dev[rc_idx].pcidev_table[i].phy_address = 0;
msm_pcie_dev[rc_idx].pcidev_table[i].dev_ctrlstts_offset = 0;
msm_pcie_dev[rc_idx].pcidev_table[i].event_reg = NULL;
@@ -5725,7 +5725,7 @@
},
};
-int __init pcie_init(void)
+static int __init pcie_init(void)
{
int ret = 0, i;
char rc_name[MAX_RC_NAME_LEN];
@@ -5784,7 +5784,7 @@
msm_pcie_dev_tbl[i].short_bdf = 0;
msm_pcie_dev_tbl[i].sid = 0;
msm_pcie_dev_tbl[i].domain = -1;
- msm_pcie_dev_tbl[i].conf_base = 0;
+ msm_pcie_dev_tbl[i].conf_base = NULL;
msm_pcie_dev_tbl[i].phy_address = 0;
msm_pcie_dev_tbl[i].dev_ctrlstts_offset = 0;
msm_pcie_dev_tbl[i].event_reg = NULL;
@@ -5999,7 +5999,7 @@
return ret;
}
-void msm_pcie_fixup_resume(struct pci_dev *dev)
+static void msm_pcie_fixup_resume(struct pci_dev *dev)
{
int ret;
struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus);
@@ -6022,7 +6022,7 @@
DECLARE_PCI_FIXUP_RESUME(PCIE_VENDOR_ID_RCP, PCIE_DEVICE_ID_RCP,
msm_pcie_fixup_resume);
-void msm_pcie_fixup_resume_early(struct pci_dev *dev)
+static void msm_pcie_fixup_resume_early(struct pci_dev *dev)
{
int ret;
struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus);
diff --git a/drivers/platform/msm/gsi/gsi.c b/drivers/platform/msm/gsi/gsi.c
index 7fca7aa..9c133a8 100644
--- a/drivers/platform/msm/gsi/gsi.c
+++ b/drivers/platform/msm/gsi/gsi.c
@@ -1353,6 +1353,35 @@
}
EXPORT_SYMBOL(gsi_query_evt_ring_db_addr);
+int gsi_ring_evt_ring_db(unsigned long evt_ring_hdl, uint64_t value)
+{
+ struct gsi_evt_ctx *ctx;
+
+ if (!gsi_ctx) {
+ pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__);
+ return -GSI_STATUS_NODEV;
+ }
+
+ if (evt_ring_hdl >= gsi_ctx->max_ev) {
+ GSIERR("bad params evt_ring_hdl=%lu\n", evt_ring_hdl);
+ return -GSI_STATUS_INVALID_PARAMS;
+ }
+
+ ctx = &gsi_ctx->evtr[evt_ring_hdl];
+
+ if (ctx->state != GSI_EVT_RING_STATE_ALLOCATED) {
+ GSIERR("bad state %d\n",
+ gsi_ctx->evtr[evt_ring_hdl].state);
+ return -GSI_STATUS_UNSUPPORTED_OP;
+ }
+
+ ctx->ring.wp_local = value;
+ gsi_ring_evt_doorbell(ctx);
+
+ return GSI_STATUS_SUCCESS;
+}
+EXPORT_SYMBOL(gsi_ring_evt_ring_db);
+
int gsi_reset_evt_ring(unsigned long evt_ring_hdl)
{
uint32_t val;
diff --git a/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c b/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c
index a02247d..5aa39b6 100644
--- a/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c
+++ b/drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015, 2016 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015, 2017 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -1059,6 +1059,7 @@
IPA_MHI_ERR("Unexpected err evt: %d\n", notify->evt_id);
}
IPA_MHI_ERR("err_desc=0x%x\n", notify->err_desc);
+ ipa_assert();
}
static void ipa_mhi_gsi_ch_err_cb(struct gsi_chan_err_notify *notify)
@@ -1090,6 +1091,7 @@
IPA_MHI_ERR("Unexpected err evt: %d\n", notify->evt_id);
}
IPA_MHI_ERR("err_desc=0x%x\n", notify->err_desc);
+ ipa_assert();
}
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_debugfs.c b/drivers/platform/msm/ipa/ipa_v2/ipa_debugfs.c
index f935bab..e8710a6 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_debugfs.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_debugfs.c
@@ -80,6 +80,9 @@
__stringify(ECM_DISCONNECT),
__stringify(IPA_TETHERING_STATS_UPDATE_STATS),
__stringify(IPA_TETHERING_STATS_UPDATE_NETWORK_STATS),
+ __stringify(IPA_QUOTA_REACH),
+ __stringify(IPA_SSR_BEFORE_SHUTDOWN),
+ __stringify(IPA_SSR_AFTER_POWERUP),
};
const char *ipa_hdr_l2_type_name[] = {
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.h b/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.h
index 67dd031..4c504f1 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.h
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.h
@@ -147,6 +147,9 @@
int rmnet_ipa_query_tethering_stats(struct wan_ioctl_query_tether_stats *data,
bool reset);
+int rmnet_ipa_query_tethering_stats_all(
+ struct wan_ioctl_query_tether_stats_all *data);
+
int rmnet_ipa_reset_tethering_stats(struct wan_ioctl_reset_tether_stats *data);
int ipa_qmi_get_data_stats(struct ipa_get_data_stats_req_msg_v01 *req,
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c
index 4ef7e1f..4652fc8 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c
@@ -878,7 +878,7 @@
void ipa2_set_client(int index, enum ipacm_client_enum client, bool uplink)
{
- if (client >= IPACM_CLIENT_MAX || client < IPACM_CLIENT_USB) {
+ if (client > IPACM_CLIENT_MAX || client < IPACM_CLIENT_USB) {
IPAERR("Bad client number! client =%d\n", client);
} else if (index >= IPA_MAX_NUM_PIPES || index < 0) {
IPAERR("Bad pipe index! index =%d\n", index);
diff --git a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c
index bcd602c..29766fb 100644
--- a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c
@@ -2338,6 +2338,29 @@
.remove = ipa_wwan_remove,
};
+/**
+ * rmnet_ipa_send_ssr_notification(bool ssr_done) - send SSR notification
+ *
+ * This function sends the SSR notification before modem shutdown and
+ * after_powerup from SSR framework, to user-space module
+ */
+static void rmnet_ipa_send_ssr_notification(bool ssr_done)
+{
+ struct ipa_msg_meta msg_meta;
+ int rc;
+
+ memset(&msg_meta, 0, sizeof(struct ipa_msg_meta));
+ if (ssr_done)
+ msg_meta.msg_type = IPA_SSR_AFTER_POWERUP;
+ else
+ msg_meta.msg_type = IPA_SSR_BEFORE_SHUTDOWN;
+ rc = ipa_send_msg(&msg_meta, NULL, NULL);
+ if (rc) {
+ IPAWANERR("ipa_send_msg failed: %d\n", rc);
+ return;
+ }
+}
+
static int ssr_notifier_cb(struct notifier_block *this,
unsigned long code,
void *data)
@@ -2345,6 +2368,8 @@
if (ipa_rmnet_ctx.ipa_rmnet_ssr) {
if (code == SUBSYS_BEFORE_SHUTDOWN) {
pr_info("IPA received MPSS BEFORE_SHUTDOWN\n");
+ /* send SSR before-shutdown notification to IPACM */
+ rmnet_ipa_send_ssr_notification(false);
atomic_set(&is_ssr, 1);
ipa_q6_pre_shutdown_cleanup();
if (ipa_netdevs[0])
@@ -2520,6 +2545,26 @@
}
/**
+ * rmnet_ipa_send_quota_reach_ind() - send quota_reach notification from
+ * IPA Modem
+ * This function sends the quota_reach indication from the IPA Modem driver
+ * via QMI, to user-space module
+ */
+static void rmnet_ipa_send_quota_reach_ind(void)
+{
+ struct ipa_msg_meta msg_meta;
+ int rc;
+
+ memset(&msg_meta, 0, sizeof(struct ipa_msg_meta));
+ msg_meta.msg_type = IPA_QUOTA_REACH;
+ rc = ipa_send_msg(&msg_meta, NULL, NULL);
+ if (rc) {
+ IPAWANERR("ipa_send_msg failed: %d\n", rc);
+ return;
+ }
+}
+
+/**
* rmnet_ipa_poll_tethering_stats() - Tethering stats polling IOCTL handler
* @data - IOCTL data
*
@@ -2808,10 +2853,6 @@
kfree(req);
kfree(resp);
return rc;
- } else if (reset) {
- kfree(req);
- kfree(resp);
- return 0;
}
if (resp->dl_dst_pipe_stats_list_valid) {
@@ -2947,6 +2988,49 @@
return rc;
}
+int rmnet_ipa_query_tethering_stats_all(
+ struct wan_ioctl_query_tether_stats_all *data)
+{
+ struct wan_ioctl_query_tether_stats tether_stats;
+ enum ipa_upstream_type upstream_type;
+ int rc = 0;
+
+ memset(&tether_stats, 0, sizeof(struct wan_ioctl_query_tether_stats));
+ /* get IPA backhaul type */
+ upstream_type = find_upstream_type(data->upstreamIface);
+
+ if (upstream_type == IPA_UPSTEAM_MAX) {
+ IPAWANERR(" Wrong upstreamIface name %s\n",
+ data->upstreamIface);
+ } else if (upstream_type == IPA_UPSTEAM_WLAN) {
+ IPAWANDBG_LOW(" query wifi-backhaul stats\n");
+ rc = rmnet_ipa_query_tethering_stats_wifi(
+ &tether_stats, data->reset_stats);
+ if (rc) {
+ IPAWANERR("wlan WAN_IOC_QUERY_TETHER_STATS failed\n");
+ return rc;
+ }
+ data->tx_bytes = tether_stats.ipv4_tx_bytes
+ + tether_stats.ipv6_tx_bytes;
+ data->rx_bytes = tether_stats.ipv4_rx_bytes
+ + tether_stats.ipv6_rx_bytes;
+ } else {
+ IPAWANDBG_LOW(" query modem-backhaul stats\n");
+ tether_stats.ipa_client = data->ipa_client;
+ rc = rmnet_ipa_query_tethering_stats_modem(
+ &tether_stats, data->reset_stats);
+ if (rc) {
+ IPAWANERR("modem WAN_IOC_QUERY_TETHER_STATS failed\n");
+ return rc;
+ }
+ data->tx_bytes = tether_stats.ipv4_tx_bytes
+ + tether_stats.ipv6_tx_bytes;
+ data->rx_bytes = tether_stats.ipv4_rx_bytes
+ + tether_stats.ipv6_rx_bytes;
+ }
+ return rc;
+}
+
int rmnet_ipa_reset_tethering_stats(struct wan_ioctl_reset_tether_stats *data)
{
enum ipa_upstream_type upstream_type;
@@ -3048,6 +3132,8 @@
IPAWANERR("putting nlmsg: <%s> <%s> <%s>\n",
alert_msg, iface_name_l, iface_name_m);
kobject_uevent_env(&(ipa_netdevs[0]->dev.kobj), KOBJ_CHANGE, envp);
+
+ rmnet_ipa_send_quota_reach_ind();
}
/**
@@ -3072,6 +3158,9 @@
*/
ipa2_proxy_clk_unvote();
+ /* send SSR power-up notification to IPACM */
+ rmnet_ipa_send_ssr_notification(true);
+
/*
* It is required to recover the network stats after
* SSR recovery
diff --git a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa_fd_ioctl.c b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa_fd_ioctl.c
index 436cf21..793529d 100644
--- a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa_fd_ioctl.c
+++ b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa_fd_ioctl.c
@@ -47,6 +47,10 @@
#define WAN_IOC_QUERY_DL_FILTER_STATS32 _IOWR(WAN_IOC_MAGIC, \
WAN_IOCTL_QUERY_DL_FILTER_STATS, \
compat_uptr_t)
+#define WAN_IOC_QUERY_TETHER_STATS_ALL32 _IOWR(WAN_IOC_MAGIC, \
+ WAN_IOCTL_QUERY_TETHER_STATS_ALL, \
+ compat_uptr_t)
+
#endif
static unsigned int dev_num = 1;
@@ -242,6 +246,32 @@
}
break;
+ case WAN_IOC_QUERY_TETHER_STATS_ALL:
+ IPAWANDBG_LOW("got WAN_IOC_QUERY_TETHER_STATS_ALL :>>>\n");
+ pyld_sz = sizeof(struct wan_ioctl_query_tether_stats_all);
+ param = kzalloc(pyld_sz, GFP_KERNEL);
+ if (!param) {
+ retval = -ENOMEM;
+ break;
+ }
+ if (copy_from_user(param, (u8 *)arg, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+
+ if (rmnet_ipa_query_tethering_stats_all(
+ (struct wan_ioctl_query_tether_stats_all *)param)) {
+ IPAWANERR("WAN_IOC_QUERY_TETHER_STATS failed\n");
+ retval = -EFAULT;
+ break;
+ }
+
+ if (copy_to_user((u8 *)arg, param, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
case WAN_IOC_RESET_TETHER_STATS:
IPAWANDBG("device %s got WAN_IOC_RESET_TETHER_STATS :>>>\n",
DRIVER_NAME);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c
index 564397a..2d08767 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c
@@ -1058,8 +1058,21 @@
if (should_force_clear) {
result = ipa3_enable_force_clear(qmi_req_id, false,
source_pipe_bitmask);
- if (result)
- goto exit;
+ if (result) {
+ struct ipahal_ep_cfg_ctrl_scnd ep_ctrl_scnd = { 0 };
+
+ /*
+ * assuming here modem SSR\shutdown, AP can remove
+ * the delay in this case
+ */
+ IPAERR(
+ "failed to force clear %d, remove delay from SCND reg\n"
+ , result);
+ ep_ctrl_scnd.endp_delay = false;
+ ipahal_write_reg_n_fields(
+ IPA_ENDP_INIT_CTRL_SCND_n, clnt_hdl,
+ &ep_ctrl_scnd);
+ }
}
/* with force clear, wait for emptiness */
for (i = 0; i < IPA_POLL_FOR_EMPTINESS_NUM; i++) {
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c b/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
index 1634b1c..2a7b977 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c
@@ -61,6 +61,9 @@
__stringify(ECM_DISCONNECT),
__stringify(IPA_TETHERING_STATS_UPDATE_STATS),
__stringify(IPA_TETHERING_STATS_UPDATE_NETWORK_STATS),
+ __stringify(IPA_QUOTA_REACH),
+ __stringify(IPA_SSR_BEFORE_SHUTDOWN),
+ __stringify(IPA_SSR_AFTER_POWERUP),
};
const char *ipa3_hdr_l2_type_name[] = {
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c b/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c
index f66e3a3..0dd86fa 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c
@@ -255,6 +255,24 @@
ep->gsi_evt_ring_hdl = *params->cached_gsi_evt_ring_hdl;
}
+ if (params->ev_ctx_host->wp == params->ev_ctx_host->rbase) {
+ IPA_MHI_ERR("event ring wp is not updated. base=wp=0x%llx\n",
+ params->ev_ctx_host->wp);
+ goto fail_alloc_ch;
+ return res;
+ }
+
+ IPA_MHI_DBG("Ring event db: evt_ring_hdl=%lu host_wp=0x%llx\n",
+ ep->gsi_evt_ring_hdl, params->ev_ctx_host->wp);
+ res = gsi_ring_evt_ring_db(ep->gsi_evt_ring_hdl,
+ params->ev_ctx_host->wp);
+ if (res) {
+ IPA_MHI_ERR("fail to ring evt ring db %d. hdl=%lu wp=0x%llx\n",
+ res, ep->gsi_evt_ring_hdl, params->ev_ctx_host->wp);
+ goto fail_alloc_ch;
+ return res;
+ }
+
memset(&ch_props, 0, sizeof(ch_props));
ch_props.prot = GSI_CHAN_PROT_MHI;
ch_props.dir = IPA_CLIENT_IS_PROD(client) ?
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h
index 6cd82f8..d5d8503 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h
@@ -190,6 +190,9 @@
int rmnet_ipa3_query_tethering_stats(struct wan_ioctl_query_tether_stats *data,
bool reset);
+int rmnet_ipa3_query_tethering_stats_all(
+ struct wan_ioctl_query_tether_stats_all *data);
+
int rmnet_ipa3_reset_tethering_stats(struct wan_ioctl_reset_tether_stats *data);
int ipa3_qmi_get_data_stats(struct ipa_get_data_stats_req_msg_v01 *req,
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index dbe6cd6..0abe5fe 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -2200,7 +2200,7 @@
void ipa3_set_client(int index, enum ipacm_client_enum client, bool uplink)
{
- if (client >= IPACM_CLIENT_MAX || client < IPACM_CLIENT_USB) {
+ if (client > IPACM_CLIENT_MAX || client < IPACM_CLIENT_USB) {
IPAERR("Bad client number! client =%d\n", client);
} else if (index >= IPA3_MAX_NUM_PIPES || index < 0) {
IPAERR("Bad pipe index! index =%d\n", index);
diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
index f408f23..fcaabe3 100644
--- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
@@ -2442,6 +2442,29 @@
.remove = ipa3_wwan_remove,
};
+/**
+ * rmnet_ipa_send_ssr_notification(bool ssr_done) - send SSR notification
+ *
+ * This function sends the SSR notification before modem shutdown and
+ * after_powerup from SSR framework, to user-space module
+ */
+static void rmnet_ipa_send_ssr_notification(bool ssr_done)
+{
+ struct ipa_msg_meta msg_meta;
+ int rc;
+
+ memset(&msg_meta, 0, sizeof(struct ipa_msg_meta));
+ if (ssr_done)
+ msg_meta.msg_type = IPA_SSR_AFTER_POWERUP;
+ else
+ msg_meta.msg_type = IPA_SSR_BEFORE_SHUTDOWN;
+ rc = ipa_send_msg(&msg_meta, NULL, NULL);
+ if (rc) {
+ IPAWANERR("ipa_send_msg failed: %d\n", rc);
+ return;
+ }
+}
+
static int ipa3_ssr_notifier_cb(struct notifier_block *this,
unsigned long code,
void *data)
@@ -2452,6 +2475,8 @@
switch (code) {
case SUBSYS_BEFORE_SHUTDOWN:
IPAWANINFO("IPA received MPSS BEFORE_SHUTDOWN\n");
+ /* send SSR before-shutdown notification to IPACM */
+ rmnet_ipa_send_ssr_notification(false);
atomic_set(&rmnet_ipa3_ctx->is_ssr, 1);
ipa3_q6_pre_shutdown_cleanup();
if (IPA_NETDEV())
@@ -2628,6 +2653,26 @@
}
/**
+ * rmnet_ipa_send_quota_reach_ind() - send quota_reach notification from
+ * IPA Modem
+ * This function sends the quota_reach indication from the IPA Modem driver
+ * via QMI, to user-space module
+ */
+static void rmnet_ipa_send_quota_reach_ind(void)
+{
+ struct ipa_msg_meta msg_meta;
+ int rc;
+
+ memset(&msg_meta, 0, sizeof(struct ipa_msg_meta));
+ msg_meta.msg_type = IPA_QUOTA_REACH;
+ rc = ipa_send_msg(&msg_meta, NULL, NULL);
+ if (rc) {
+ IPAWANERR("ipa_send_msg failed: %d\n", rc);
+ return;
+ }
+}
+
+/**
* rmnet_ipa3_poll_tethering_stats() - Tethering stats polling IOCTL handler
* @data - IOCTL data
*
@@ -2908,7 +2953,7 @@
IPAWANERR("reset the pipe stats\n");
} else {
/* print tethered-client enum */
- IPAWANDBG_LOW("Tethered-client enum(%d)\n", data->ipa_client);
+ IPAWANDBG("Tethered-client enum(%d)\n", data->ipa_client);
}
rc = ipa3_qmi_get_data_stats(req, resp);
@@ -2917,10 +2962,6 @@
kfree(req);
kfree(resp);
return rc;
- } else if (reset) {
- kfree(req);
- kfree(resp);
- return 0;
}
if (resp->dl_dst_pipe_stats_list_valid) {
@@ -3058,6 +3099,49 @@
return rc;
}
+int rmnet_ipa3_query_tethering_stats_all(
+ struct wan_ioctl_query_tether_stats_all *data)
+{
+ struct wan_ioctl_query_tether_stats tether_stats;
+ enum ipa_upstream_type upstream_type;
+ int rc = 0;
+
+ memset(&tether_stats, 0, sizeof(struct wan_ioctl_query_tether_stats));
+ /* get IPA backhaul type */
+ upstream_type = find_upstream_type(data->upstreamIface);
+
+ if (upstream_type == IPA_UPSTEAM_MAX) {
+ IPAWANERR(" Wrong upstreamIface name %s\n",
+ data->upstreamIface);
+ } else if (upstream_type == IPA_UPSTEAM_WLAN) {
+ IPAWANDBG_LOW(" query wifi-backhaul stats\n");
+ rc = rmnet_ipa3_query_tethering_stats_wifi(
+ &tether_stats, data->reset_stats);
+ if (rc) {
+ IPAWANERR("wlan WAN_IOC_QUERY_TETHER_STATS failed\n");
+ return rc;
+ }
+ data->tx_bytes = tether_stats.ipv4_tx_bytes
+ + tether_stats.ipv6_tx_bytes;
+ data->rx_bytes = tether_stats.ipv4_rx_bytes
+ + tether_stats.ipv6_rx_bytes;
+ } else {
+ IPAWANDBG_LOW(" query modem-backhaul stats\n");
+ tether_stats.ipa_client = data->ipa_client;
+ rc = rmnet_ipa3_query_tethering_stats_modem(
+ &tether_stats, data->reset_stats);
+ if (rc) {
+ IPAWANERR("modem WAN_IOC_QUERY_TETHER_STATS failed\n");
+ return rc;
+ }
+ data->tx_bytes = tether_stats.ipv4_tx_bytes
+ + tether_stats.ipv6_tx_bytes;
+ data->rx_bytes = tether_stats.ipv4_rx_bytes
+ + tether_stats.ipv6_rx_bytes;
+ }
+ return rc;
+}
+
int rmnet_ipa3_reset_tethering_stats(struct wan_ioctl_reset_tether_stats *data)
{
enum ipa_upstream_type upstream_type;
@@ -3155,6 +3239,8 @@
alert_msg, iface_name_l, iface_name_m);
kobject_uevent_env(&(IPA_NETDEV()->dev.kobj),
KOBJ_CHANGE, envp);
+
+ rmnet_ipa_send_quota_reach_ind();
}
/**
@@ -3179,6 +3265,9 @@
*/
ipa3_proxy_clk_unvote();
+ /* send SSR power-up notification to IPACM */
+ rmnet_ipa_send_ssr_notification(true);
+
/*
* It is required to recover the network stats after
* SSR recovery
diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa_fd_ioctl.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa_fd_ioctl.c
index 3ef17f6..c7a6186 100644
--- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa_fd_ioctl.c
+++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa_fd_ioctl.c
@@ -47,6 +47,9 @@
#define WAN_IOC_QUERY_DL_FILTER_STATS32 _IOWR(WAN_IOC_MAGIC, \
WAN_IOCTL_QUERY_DL_FILTER_STATS, \
compat_uptr_t)
+#define WAN_IOC_QUERY_TETHER_STATS_ALL32 _IOWR(WAN_IOC_MAGIC, \
+ WAN_IOCTL_QUERY_TETHER_STATS_ALL, \
+ compat_uptr_t)
#endif
static unsigned int dev_num = 1;
@@ -265,6 +268,32 @@
}
break;
+ case WAN_IOC_QUERY_TETHER_STATS_ALL:
+ IPAWANDBG_LOW("got WAN_IOC_QUERY_TETHER_STATS_ALL :>>>\n");
+ pyld_sz = sizeof(struct wan_ioctl_query_tether_stats_all);
+ param = kzalloc(pyld_sz, GFP_KERNEL);
+ if (!param) {
+ retval = -ENOMEM;
+ break;
+ }
+ if (copy_from_user(param, (u8 __user *)arg, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+
+ if (rmnet_ipa3_query_tethering_stats_all(
+ (struct wan_ioctl_query_tether_stats_all *)param)) {
+ IPAWANERR("WAN_IOC_QUERY_TETHER_STATS failed\n");
+ retval = -EFAULT;
+ break;
+ }
+
+ if (copy_to_user((void __user *)arg, param, pyld_sz)) {
+ retval = -EFAULT;
+ break;
+ }
+ break;
+
case WAN_IOC_RESET_TETHER_STATS:
IPAWANDBG_LOW("device %s got WAN_IOC_RESET_TETHER_STATS :>>>\n",
DRIVER_NAME);
diff --git a/drivers/platform/msm/sps/sps.c b/drivers/platform/msm/sps/sps.c
index fbf8773..f9ba30e 100644
--- a/drivers/platform/msm/sps/sps.c
+++ b/drivers/platform/msm/sps/sps.c
@@ -67,6 +67,7 @@
static u32 debugfs_buf_size;
static u32 debugfs_buf_used;
static int wraparound;
+static struct mutex sps_debugfs_lock;
struct dentry *dent;
struct dentry *dfile_info;
@@ -85,6 +86,7 @@
/* record debug info for debugfs */
void sps_debugfs_record(const char *msg)
{
+ mutex_lock(&sps_debugfs_lock);
if (debugfs_record_enabled) {
if (debugfs_buf_used + MAX_MSG_LEN >= debugfs_buf_size) {
debugfs_buf_used = 0;
@@ -98,6 +100,7 @@
debugfs_buf_size - debugfs_buf_used,
"\n**** end line of sps log ****\n\n");
}
+ mutex_unlock(&sps_debugfs_lock);
}
/* read the recorded debug info to userspace */
@@ -107,6 +110,7 @@
int ret = 0;
int size;
+ mutex_lock(&sps_debugfs_lock);
if (debugfs_record_enabled) {
if (wraparound)
size = debugfs_buf_size - MAX_MSG_LEN;
@@ -116,6 +120,7 @@
ret = simple_read_from_buffer(ubuf, count, ppos,
debugfs_buf, size);
}
+ mutex_unlock(&sps_debugfs_lock);
return ret;
}
@@ -160,12 +165,14 @@
new_buf_size = buf_size_kb * SZ_1K;
+ mutex_lock(&sps_debugfs_lock);
if (debugfs_record_enabled) {
if (debugfs_buf_size == new_buf_size) {
/* need do nothing */
pr_info(
"sps:debugfs: input buffer size is the same as before.\n"
);
+ mutex_unlock(&sps_debugfs_lock);
return count;
}
/* release the current buffer */
@@ -183,12 +190,14 @@
if (!debugfs_buf) {
debugfs_buf_size = 0;
pr_err("sps:fail to allocate memory for debug_fs.\n");
+ mutex_unlock(&sps_debugfs_lock);
return -ENOMEM;
}
debugfs_buf_used = 0;
wraparound = false;
debugfs_record_enabled = true;
+ mutex_unlock(&sps_debugfs_lock);
return count;
}
@@ -237,6 +246,7 @@
return count;
}
+ mutex_lock(&sps_debugfs_lock);
if (((option == 0) || (option == 2)) &&
((logging_option == 1) || (logging_option == 3))) {
debugfs_record_enabled = false;
@@ -248,6 +258,7 @@
}
logging_option = option;
+ mutex_unlock(&sps_debugfs_lock);
return count;
}
@@ -595,6 +606,8 @@
goto bam_log_level_err;
}
+ mutex_init(&sps_debugfs_lock);
+
return;
bam_log_level_err:
diff --git a/drivers/platform/msm/sps/spsi.h b/drivers/platform/msm/sps/spsi.h
index 2e57f7d..0c1b8ea 100644
--- a/drivers/platform/msm/sps/spsi.h
+++ b/drivers/platform/msm/sps/spsi.h
@@ -145,11 +145,6 @@
pr_info(msg, ##args); \
} \
} while (0)
-#define SPS_DEBUGFS(msg, args...) do { \
- char buf[MAX_MSG_LEN]; \
- snprintf(buf, MAX_MSG_LEN, msg"\n", ##args); \
- sps_debugfs_record(buf); \
- } while (0)
#define SPS_ERR(dev, msg, args...) do { \
if (logging_option != 1) { \
if (unlikely(print_limit_option > 2)) \
@@ -157,8 +152,6 @@
else \
pr_err(msg, ##args); \
} \
- if (unlikely(debugfs_record_enabled)) \
- SPS_DEBUGFS(msg, ##args); \
SPS_IPC(3, dev, msg, args); \
} while (0)
#define SPS_INFO(dev, msg, args...) do { \
@@ -168,8 +161,6 @@
else \
pr_info(msg, ##args); \
} \
- if (unlikely(debugfs_record_enabled)) \
- SPS_DEBUGFS(msg, ##args); \
SPS_IPC(3, dev, msg, args); \
} while (0)
#define SPS_DBG(dev, msg, args...) do { \
@@ -181,8 +172,6 @@
pr_info(msg, ##args); \
} else \
pr_debug(msg, ##args); \
- if (unlikely(debugfs_record_enabled)) \
- SPS_DEBUGFS(msg, ##args); \
if (dev) { \
if ((dev)->ipc_loglevel <= 0) \
SPS_IPC(0, dev, msg, args); \
@@ -197,8 +186,6 @@
pr_info(msg, ##args); \
} else \
pr_debug(msg, ##args); \
- if (unlikely(debugfs_record_enabled)) \
- SPS_DEBUGFS(msg, ##args); \
if (dev) { \
if ((dev)->ipc_loglevel <= 1) \
SPS_IPC(1, dev, msg, args); \
@@ -213,8 +200,6 @@
pr_info(msg, ##args); \
} else \
pr_debug(msg, ##args); \
- if (unlikely(debugfs_record_enabled)) \
- SPS_DEBUGFS(msg, ##args); \
if (dev) { \
if ((dev)->ipc_loglevel <= 2) \
SPS_IPC(2, dev, msg, args); \
@@ -229,8 +214,6 @@
pr_info(msg, ##args); \
} else \
pr_debug(msg, ##args); \
- if (unlikely(debugfs_record_enabled)) \
- SPS_DEBUGFS(msg, ##args); \
if (dev) { \
if ((dev)->ipc_loglevel <= 3) \
SPS_IPC(3, dev, msg, args); \
diff --git a/drivers/power/supply/qcom/qpnp-fg-gen3.c b/drivers/power/supply/qcom/qpnp-fg-gen3.c
index 73d54c6..75e79bb 100644
--- a/drivers/power/supply/qcom/qpnp-fg-gen3.c
+++ b/drivers/power/supply/qcom/qpnp-fg-gen3.c
@@ -3083,6 +3083,7 @@
pval->intval);
return -EINVAL;
}
+ break;
case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
rc = fg_set_constant_chg_voltage(chip, pval->intval);
break;
diff --git a/drivers/scsi/ufs/ufs-qcom-ice.c b/drivers/scsi/ufs/ufs-qcom-ice.c
index 814d1dc..0c86263 100644
--- a/drivers/scsi/ufs/ufs-qcom-ice.c
+++ b/drivers/scsi/ufs/ufs-qcom-ice.c
@@ -394,8 +394,8 @@
}
+ memset(&ice_set, 0, sizeof(ice_set));
if (qcom_host->ice.vops->config_start) {
- memset(&ice_set, 0, sizeof(ice_set));
spin_lock_irqsave(
&qcom_host->ice_work_lock, flags);
diff --git a/drivers/soc/qcom/msm_bus/msm_bus_fabric_rpmh.c b/drivers/soc/qcom/msm_bus/msm_bus_fabric_rpmh.c
index 144b1a1..b331e74 100644
--- a/drivers/soc/qcom/msm_bus/msm_bus_fabric_rpmh.c
+++ b/drivers/soc/qcom/msm_bus/msm_bus_fabric_rpmh.c
@@ -272,6 +272,9 @@
int ret = 0;
bool valid = true;
+ if (!cmd)
+ return ret;
+
if (vec_a == 0 && vec_b == 0)
valid = false;
@@ -670,7 +673,30 @@
return ret;
}
+static void bcm_commit_single_req(struct msm_bus_node_device_type *cur_bcm,
+ uint64_t vec_a, uint64_t vec_b)
+{
+ struct msm_bus_node_device_type *cur_rsc = NULL;
+ struct rpmh_client *cur_mbox = NULL;
+ struct tcs_cmd *cmd_active = NULL;
+ if (!cur_bcm->node_info->num_rsc_devs)
+ return;
+
+ cmd_active = kzalloc(sizeof(struct tcs_cmd), GFP_KERNEL);
+
+ if (!cmd_active)
+ return;
+
+ cur_rsc = to_msm_bus_node(cur_bcm->node_info->rsc_devs[0]);
+ cur_mbox = cur_rsc->rscdev->mbox;
+
+ tcs_cmd_gen(cur_bcm, cmd_active, vec_a, vec_b, true);
+ rpmh_write_single(cur_mbox, RPMH_ACTIVE_ONLY_STATE,
+ cmd_active->addr, cmd_active->data);
+
+ kfree(cmd_active);
+}
void *msm_bus_realloc_devmem(struct device *dev, void *p, size_t old_size,
size_t new_size, gfp_t flags)
@@ -733,29 +759,22 @@
static int msm_bus_enable_node_qos_clk(struct msm_bus_node_device_type *node)
{
- struct msm_bus_node_device_type *bus_node = NULL;
int i;
int ret;
long rounded_rate;
- if (!node || (!to_msm_bus_node(node->node_info->bus_device))) {
- ret = -ENXIO;
- goto exit_enable_node_qos_clk;
- }
- bus_node = to_msm_bus_node(node->node_info->bus_device);
-
- for (i = 0; i < bus_node->num_node_qos_clks; i++) {
- if (!bus_node->node_qos_clks[i].enable_only_clk) {
+ for (i = 0; i < node->num_node_qos_clks; i++) {
+ if (!node->node_qos_clks[i].enable_only_clk) {
rounded_rate =
clk_round_rate(
- bus_node->node_qos_clks[i].clk, 1);
- ret = setrate_nodeclk(&bus_node->node_qos_clks[i],
+ node->node_qos_clks[i].clk, 1);
+ ret = setrate_nodeclk(&node->node_qos_clks[i],
rounded_rate);
if (ret)
MSM_BUS_DBG("%s: Failed set rate clk,node %d\n",
__func__, node->node_info->id);
}
- ret = enable_nodeclk(&bus_node->node_qos_clks[i],
+ ret = enable_nodeclk(&node->node_qos_clks[i],
node->node_info->bus_device);
if (ret) {
MSM_BUS_DBG("%s: Failed to set Qos Clks ret %d\n",
@@ -763,12 +782,85 @@
msm_bus_disable_node_qos_clk(node);
goto exit_enable_node_qos_clk;
}
-
}
exit_enable_node_qos_clk:
return ret;
}
+static int msm_bus_vote_qos_bcms(struct msm_bus_node_device_type *node)
+{
+ struct msm_bus_node_device_type *cur_dev = NULL;
+ struct msm_bus_node_device_type *cur_bcm = NULL;
+ int i;
+ struct device *dev = NULL;
+
+ if (!node || (!to_msm_bus_node(node->node_info->bus_device)))
+ return -ENXIO;
+
+ cur_dev = node;
+
+ for (i = 0; i < cur_dev->num_qos_bcms; i++) {
+ dev = bus_find_device(&msm_bus_type, NULL,
+ (void *) &cur_dev->qos_bcms[i].qos_bcm_id,
+ msm_bus_device_match_adhoc);
+
+ if (!dev) {
+ MSM_BUS_ERR("Can't find dev node for %d",
+ cur_dev->qos_bcms[i].qos_bcm_id);
+ return -ENODEV;
+ }
+
+ cur_bcm = to_msm_bus_node(dev);
+ if (cur_bcm->node_vec[ACTIVE_CTX].vec_a != 0 ||
+ cur_bcm->node_vec[ACTIVE_CTX].vec_b != 0 ||
+ cur_bcm->node_vec[DUAL_CTX].vec_a != 0 ||
+ cur_bcm->node_vec[DUAL_CTX].vec_b != 0)
+ return 0;
+
+ bcm_commit_single_req(cur_bcm,
+ cur_dev->qos_bcms[i].vec.vec_a,
+ cur_dev->qos_bcms[i].vec.vec_b);
+ }
+
+ return 0;
+}
+
+static int msm_bus_rm_vote_qos_bcms(struct msm_bus_node_device_type *node)
+{
+ struct msm_bus_node_device_type *cur_dev = NULL;
+ struct msm_bus_node_device_type *cur_bcm = NULL;
+ int i;
+ struct device *dev = NULL;
+
+ if (!node || (!to_msm_bus_node(node->node_info->bus_device)))
+ return -ENXIO;
+
+ cur_dev = node;
+
+ for (i = 0; i < cur_dev->num_qos_bcms; i++) {
+ dev = bus_find_device(&msm_bus_type, NULL,
+ (void *) &cur_dev->qos_bcms[i].qos_bcm_id,
+ msm_bus_device_match_adhoc);
+
+ if (!dev) {
+ MSM_BUS_ERR("Can't find dev node for %d",
+ cur_dev->qos_bcms[i].qos_bcm_id);
+ return -ENODEV;
+ }
+
+ cur_bcm = to_msm_bus_node(dev);
+ if (cur_bcm->node_vec[ACTIVE_CTX].vec_a != 0 ||
+ cur_bcm->node_vec[ACTIVE_CTX].vec_b != 0 ||
+ cur_bcm->node_vec[DUAL_CTX].vec_a != 0 ||
+ cur_bcm->node_vec[DUAL_CTX].vec_b != 0)
+ return 0;
+
+ bcm_commit_single_req(cur_bcm, 0, 0);
+ }
+
+ return 0;
+}
+
int msm_bus_enable_limiter(struct msm_bus_node_device_type *node_dev,
int enable, uint64_t lim_bw)
{
@@ -847,12 +939,11 @@
bus_node_info->fabdev->noc_ops.qos_init) {
int ret = 0;
- if (node_dev->ap_owned &&
- (node_dev->node_info->qos_params.mode) != -1) {
-
+ if (node_dev->ap_owned) {
if (bus_node_info->fabdev->bypass_qos_prg)
goto exit_init_qos;
+ ret = msm_bus_vote_qos_bcms(node_dev);
ret = msm_bus_enable_node_qos_clk(node_dev);
if (ret < 0) {
MSM_BUS_DBG("Can't Enable QoS clk %d\n",
@@ -868,6 +959,7 @@
bus_node_info->fabdev->qos_off,
bus_node_info->fabdev->qos_freq);
ret = msm_bus_disable_node_qos_clk(node_dev);
+ ret = msm_bus_rm_vote_qos_bcms(node_dev);
node_dev->node_info->defer_qos = false;
}
} else
@@ -1136,18 +1228,27 @@
node_info->is_fab_dev = pdata_node_info->is_fab_dev;
node_info->is_bcm_dev = pdata_node_info->is_bcm_dev;
node_info->is_rsc_dev = pdata_node_info->is_rsc_dev;
- node_info->qos_params.mode = pdata_node_info->qos_params.mode;
- node_info->qos_params.prio1 = pdata_node_info->qos_params.prio1;
- node_info->qos_params.prio0 = pdata_node_info->qos_params.prio0;
- node_info->qos_params.reg_prio1 = pdata_node_info->qos_params.reg_prio1;
- node_info->qos_params.reg_prio0 = pdata_node_info->qos_params.reg_prio0;
- node_info->qos_params.prio_lvl = pdata_node_info->qos_params.prio_lvl;
- node_info->qos_params.prio_rd = pdata_node_info->qos_params.prio_rd;
- node_info->qos_params.prio_wr = pdata_node_info->qos_params.prio_wr;
- node_info->qos_params.gp = pdata_node_info->qos_params.gp;
- node_info->qos_params.thmp = pdata_node_info->qos_params.thmp;
- node_info->qos_params.ws = pdata_node_info->qos_params.ws;
- node_info->qos_params.bw_buffer = pdata_node_info->qos_params.bw_buffer;
+ node_info->qos_params.prio_dflt = pdata_node_info->qos_params.prio_dflt;
+ node_info->qos_params.limiter.bw =
+ pdata_node_info->qos_params.limiter.bw;
+ node_info->qos_params.limiter.sat =
+ pdata_node_info->qos_params.limiter.sat;
+ node_info->qos_params.limiter_en =
+ pdata_node_info->qos_params.limiter_en;
+ node_info->qos_params.reg.low_prio =
+ pdata_node_info->qos_params.reg.low_prio;
+ node_info->qos_params.reg.hi_prio =
+ pdata_node_info->qos_params.reg.hi_prio;
+ node_info->qos_params.reg.bw =
+ pdata_node_info->qos_params.reg.bw;
+ node_info->qos_params.reg.sat =
+ pdata_node_info->qos_params.reg.sat;
+ node_info->qos_params.reg_mode.read =
+ pdata_node_info->qos_params.reg_mode.read;
+ node_info->qos_params.reg_mode.write =
+ pdata_node_info->qos_params.reg_mode.write;
+ node_info->qos_params.urg_fwd_en =
+ pdata_node_info->qos_params.urg_fwd_en;
node_info->agg_params.buswidth = pdata_node_info->agg_params.buswidth;
node_info->agg_params.agg_scheme =
pdata_node_info->agg_params.agg_scheme;
@@ -1299,7 +1400,7 @@
struct device *bus_dev = NULL;
struct msm_bus_node_device_type *bus_node = NULL;
struct msm_bus_node_info_type *node_info = NULL;
- int ret = 0;
+ int ret = 0, i = 0;
/**
* Init here so we can use devm calls
@@ -1328,6 +1429,23 @@
bus_node->node_info = node_info;
bus_node->ap_owned = pdata->ap_owned;
bus_node->dirty = false;
+ bus_node->num_qos_bcms = pdata->num_qos_bcms;
+ if (bus_node->num_qos_bcms) {
+ bus_node->qos_bcms = devm_kzalloc(bus_dev,
+ (sizeof(struct qos_bcm_type) *
+ bus_node->num_qos_bcms), GFP_KERNEL);
+ if (!bus_node->qos_bcms)
+ goto exit_device_init;
+ for (i = 0; i < bus_node->num_qos_bcms; i++) {
+ bus_node->qos_bcms[i].qos_bcm_id =
+ pdata->qos_bcms[i].qos_bcm_id;
+ bus_node->qos_bcms[i].vec.vec_a =
+ pdata->qos_bcms[i].vec.vec_a;
+ bus_node->qos_bcms[i].vec.vec_b =
+ pdata->qos_bcms[i].vec.vec_b;
+ }
+ }
+
bus_dev->of_node = pdata->of_node;
if (msm_bus_copy_node_info(pdata, bus_dev) < 0) {
diff --git a/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c b/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c
index c501e80..996c719 100644
--- a/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c
+++ b/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -32,15 +32,46 @@
#define NOC_QOS_REG_BASE(b, o) ((b) + (o))
-#define NOC_QOS_PRIORITYn_ADDR(b, o, n, d) \
+#define NOC_QOS_MAINCTL_LOWn_ADDR(b, o, n, d) \
(NOC_QOS_REG_BASE(b, o) + 0x8 + (d) * (n))
-enum noc_qos_id_priorityn {
- NOC_QOS_PRIORITYn_RMSK = 0x0000000f,
- NOC_QOS_PRIORITYn_MAXn = 32,
- NOC_QOS_PRIORITYn_P1_BMSK = 0xc,
- NOC_QOS_PRIORITYn_P1_SHFT = 0x2,
- NOC_QOS_PRIORITYn_P0_BMSK = 0x3,
- NOC_QOS_PRIORITYn_P0_SHFT = 0x0,
+enum noc_qos_id_mainctl_lown {
+ NOC_QOS_MCTL_DFLT_PRIOn_BMSK = 0x00000070,
+ NOC_QOS_MCTL_DFLT_PRIOn_SHFT = 0x4,
+ NOC_QOS_MCTL_URGFWD_ENn_BMSK = 0x00000008,
+ NOC_QOS_MCTL_URGFWD_ENn_SHFT = 0x3,
+ NOC_QOS_MCTL_LIMIT_ENn_BMSK = 0x00000001,
+ NOC_QOS_MCTL_LIMIT_ENn_SHFT = 0x0,
+};
+
+#define NOC_QOS_LIMITBWn_ADDR(b, o, n, d) \
+ (NOC_QOS_REG_BASE(b, o) + 0x18 + (d) * (n))
+enum noc_qos_id_limitbwn {
+ NOC_QOS_LIMITBW_BWn_BMSK = 0x000007FF,
+ NOC_QOS_LIMITBW_BWn_SHFT = 0x0,
+ NOC_QOS_LIMITBW_SATn_BMSK = 0x03FF0000,
+ NOC_QOS_LIMITBW_SATn_SHFT = 0x11,
+};
+
+#define NOC_QOS_REGUL0CTLn_ADDR(b, o, n, d) \
+ (NOC_QOS_REG_BASE(b, o) + 0x40 + (d) * (n))
+enum noc_qos_id_regul0ctln {
+ NOC_QOS_REGUL0CTL_HI_PRIOn_BMSK = 0x00007000,
+ NOC_QOS_REGUL0CTL_HI_PRIOn_SHFT = 0x8,
+ NOC_QOS_REGUL0CTL_LW_PRIOn_BMSK = 0x00000700,
+ NOC_QOS_REGUL0CTL_LW_PRIOn_SHFT = 0xC,
+ NOC_QOS_REGUL0CTL_WRENn_BMSK = 0x00000002,
+ NOC_QOS_REGUL0CTL_WRENn_SHFT = 0x1,
+ NOC_QOS_REGUL0CTL_RDENn_BMSK = 0x00000001,
+ NOC_QOS_REGUL0CTL_RDENn_SHFT = 0x0,
+};
+
+#define NOC_QOS_REGUL0BWn_ADDR(b, o, n, d) \
+ (NOC_QOS_REG_BASE(b, o) + 0x48 + (d) * (n))
+enum noc_qos_id_regul0bwbwn {
+ NOC_QOS_REGUL0BW_BWn_BMSK = 0x000007FF,
+ NOC_QOS_REGUL0BW_BWn_SHFT = 0x0,
+ NOC_QOS_REGUL0BW_SATn_BMSK = 0x03FF0000,
+ NOC_QOS_REGUL0BW_SATn_SHFT = 0x11,
};
#define NOC_QOS_MODEn_ADDR(b, o, n, d) \
@@ -100,14 +131,6 @@
/**
* Calculate the max BW in Bytes/s for a given time-base.
*/
-static uint32_t noc_bw_ceil(long int bw_field, uint32_t qos_freq_khz)
-{
- uint64_t bw_temp = 2 * qos_freq_khz * bw_field;
- uint32_t scale = 1000 * BW_SCALE;
-
- noc_div(&bw_temp, scale);
- return bw_temp * 1000000;
-}
#define MAX_BW(timebase) noc_bw_ceil(MAX_BW_FIELD, (timebase))
/**
@@ -129,190 +152,147 @@
}
#define MAX_WS(bw, timebase) noc_ws((bw), MAX_SAT_FIELD, (timebase))
-/* Calculate bandwidth field value for requested bandwidth */
-static uint32_t noc_bw_field(uint64_t bw_bps, uint32_t qos_freq_khz)
-{
- uint32_t bw_field = 0;
-
- if (bw_bps) {
- uint32_t rem;
- uint64_t bw_capped = min_t(uint64_t, bw_bps,
- MAX_BW(qos_freq_khz));
- uint64_t bwc = bw_capped * BW_SCALE;
- uint64_t qf = 2 * qos_freq_khz * 1000;
-
- rem = noc_div(&bwc, qf);
- bw_field = (uint32_t)max_t(unsigned long, bwc, MIN_BW_FIELD);
- bw_field = (uint32_t)min_t(unsigned long, bw_field,
- MAX_BW_FIELD);
- }
-
- MSM_BUS_DBG("NOC: bw_field: %u\n", bw_field);
- return bw_field;
-}
-
-static uint32_t noc_sat_field(uint64_t bw, uint32_t ws, uint32_t qos_freq)
-{
- uint32_t sat_field = 0;
-
- if (bw) {
- /* Limit to max bw and scale bw to 100 KB increments */
- uint64_t tbw, tscale;
- uint64_t bw_scaled = min_t(uint64_t, bw, MAX_BW(qos_freq));
- uint32_t rem = noc_div(&bw_scaled, 100000);
-
- /**
- * SATURATION =
- * (BW [MBps] * integration window [us] *
- * time base frequency [MHz]) / (256 * 16)
- */
- tbw = bw_scaled * ws * qos_freq;
- tscale = BW_SCALE * SAT_SCALE * 1000000LL;
- rem = noc_div(&tbw, tscale);
- sat_field = (uint32_t)max_t(unsigned long, tbw, MIN_SAT_FIELD);
- sat_field = (uint32_t)min_t(unsigned long, sat_field,
- MAX_SAT_FIELD);
- }
-
- MSM_BUS_DBG("NOC: sat_field: %d\n", sat_field);
- return sat_field;
-}
-
-static void noc_set_qos_mode(void __iomem *base, uint32_t qos_off,
- uint32_t mport, uint32_t qos_delta, uint8_t mode,
- uint8_t perm_mode)
-{
- if (mode < NOC_QOS_MODE_MAX &&
- ((1 << mode) & perm_mode)) {
- uint32_t reg_val;
-
- reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(base, qos_off,
- mport, qos_delta)) & NOC_QOS_MODEn_RMSK;
- writel_relaxed(((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK))) |
- (mode & NOC_QOS_MODEn_MODE_BMSK)),
- NOC_QOS_MODEn_ADDR(base, qos_off, mport, qos_delta));
- }
- /* Ensure qos mode is set before exiting */
- wmb();
-}
-
-static void noc_set_qos_priority(void __iomem *base, uint32_t qos_off,
+static void noc_set_qos_dflt_prio(void __iomem *base, uint32_t qos_off,
uint32_t mport, uint32_t qos_delta,
- struct msm_bus_noc_qos_priority *priority)
+ uint32_t prio)
{
uint32_t reg_val, val;
- reg_val = readl_relaxed(NOC_QOS_PRIORITYn_ADDR(base, qos_off, mport,
- qos_delta)) & NOC_QOS_PRIORITYn_RMSK;
- val = priority->p1 << NOC_QOS_PRIORITYn_P1_SHFT;
- writel_relaxed(((reg_val & (~(NOC_QOS_PRIORITYn_P1_BMSK))) |
- (val & NOC_QOS_PRIORITYn_P1_BMSK)),
- NOC_QOS_PRIORITYn_ADDR(base, qos_off, mport, qos_delta));
+ reg_val = readl_relaxed(NOC_QOS_MAINCTL_LOWn_ADDR(base, qos_off, mport,
+ qos_delta));
+ val = prio << NOC_QOS_MCTL_DFLT_PRIOn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_MCTL_DFLT_PRIOn_BMSK))) |
+ (val & NOC_QOS_MCTL_DFLT_PRIOn_BMSK)),
+ NOC_QOS_MAINCTL_LOWn_ADDR(base, qos_off, mport, qos_delta));
- reg_val = readl_relaxed(NOC_QOS_PRIORITYn_ADDR(base, qos_off, mport,
- qos_delta))
- & NOC_QOS_PRIORITYn_RMSK;
- writel_relaxed(((reg_val & (~(NOC_QOS_PRIORITYn_P0_BMSK))) |
- (priority->p0 & NOC_QOS_PRIORITYn_P0_BMSK)),
- NOC_QOS_PRIORITYn_ADDR(base, qos_off, mport, qos_delta));
/* Ensure qos priority is set before exiting */
wmb();
}
-static void msm_bus_noc_set_qos_bw(void __iomem *base, uint32_t qos_off,
- uint32_t qos_freq, uint32_t mport, uint32_t qos_delta,
- uint8_t perm_mode, struct msm_bus_noc_qos_bw *qbw)
+static void noc_set_qos_limiter(void __iomem *base, uint32_t qos_off,
+ uint32_t mport, uint32_t qos_delta,
+ struct msm_bus_noc_limiter *lim, uint32_t lim_en)
{
- uint32_t reg_val, val, mode;
+ uint32_t reg_val, val;
- if (!qos_freq) {
- MSM_BUS_DBG("Zero QoS Freq\n");
- return;
- }
+ reg_val = readl_relaxed(NOC_QOS_MAINCTL_LOWn_ADDR(base, qos_off, mport,
+ qos_delta));
- /* If Limiter or Regulator modes are not supported, bw not available*/
- if (perm_mode & (NOC_QOS_PERM_MODE_LIMITER |
- NOC_QOS_PERM_MODE_REGULATOR)) {
- uint32_t bw_val = noc_bw_field(qbw->bw, qos_freq);
- uint32_t sat_val = noc_sat_field(qbw->bw, qbw->ws,
- qos_freq);
+ writel_relaxed((reg_val & (~(NOC_QOS_MCTL_LIMIT_ENn_BMSK))),
+ NOC_QOS_MAINCTL_LOWn_ADDR(base, qos_off, mport, qos_delta));
- MSM_BUS_DBG("NOC: BW: perm_mode: %d bw_val: %d, sat_val: %d\n",
- perm_mode, bw_val, sat_val);
- /*
- * If in Limiter/Regulator mode, first go to fixed mode.
- * Clear QoS accumulator
- **/
- mode = readl_relaxed(NOC_QOS_MODEn_ADDR(base, qos_off,
- mport, qos_delta)) & NOC_QOS_MODEn_MODE_BMSK;
- if (mode == NOC_QOS_MODE_REGULATOR || mode ==
- NOC_QOS_MODE_LIMITER) {
- reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(
- base, qos_off, mport, qos_delta));
- val = NOC_QOS_MODE_FIXED;
- writel_relaxed((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK)))
- | (val & NOC_QOS_MODEn_MODE_BMSK),
- NOC_QOS_MODEn_ADDR(base, qos_off, mport,
- qos_delta));
- }
+ /* Ensure we disable limiter before config*/
+ wmb();
- reg_val = readl_relaxed(NOC_QOS_BWn_ADDR(base, qos_off, mport,
- qos_delta));
- val = bw_val << NOC_QOS_BWn_BW_SHFT;
- writel_relaxed(((reg_val & (~(NOC_QOS_BWn_BW_BMSK))) |
- (val & NOC_QOS_BWn_BW_BMSK)),
- NOC_QOS_BWn_ADDR(base, qos_off, mport, qos_delta));
+ reg_val = readl_relaxed(NOC_QOS_LIMITBWn_ADDR(base, qos_off, mport,
+ qos_delta));
+ val = lim->bw << NOC_QOS_LIMITBW_BWn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_LIMITBW_BWn_BMSK))) |
+ (val & NOC_QOS_LIMITBW_BWn_BMSK)),
+ NOC_QOS_LIMITBWn_ADDR(base, qos_off, mport, qos_delta));
- MSM_BUS_DBG("NOC: BW: Wrote value: 0x%x\n", ((reg_val &
- (~NOC_QOS_BWn_BW_BMSK)) | (val &
- NOC_QOS_BWn_BW_BMSK)));
+ reg_val = readl_relaxed(NOC_QOS_LIMITBWn_ADDR(base, qos_off, mport,
+ qos_delta));
+ val = lim->sat << NOC_QOS_LIMITBW_SATn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_LIMITBW_SATn_BMSK))) |
+ (val & NOC_QOS_LIMITBW_SATn_BMSK)),
+ NOC_QOS_LIMITBWn_ADDR(base, qos_off, mport, qos_delta));
- reg_val = readl_relaxed(NOC_QOS_SATn_ADDR(base, qos_off,
- mport, qos_delta));
- val = sat_val << NOC_QOS_SATn_SAT_SHFT;
- writel_relaxed(((reg_val & (~(NOC_QOS_SATn_SAT_BMSK))) |
- (val & NOC_QOS_SATn_SAT_BMSK)),
- NOC_QOS_SATn_ADDR(base, qos_off, mport, qos_delta));
+ /* Ensure qos limiter settings in place before possibly enabling */
+ wmb();
- MSM_BUS_DBG("NOC: SAT: Wrote value: 0x%x\n", ((reg_val &
- (~NOC_QOS_SATn_SAT_BMSK)) | (val &
- NOC_QOS_SATn_SAT_BMSK)));
+ reg_val = readl_relaxed(NOC_QOS_MAINCTL_LOWn_ADDR(base, qos_off, mport,
+ qos_delta));
+ val = lim_en << NOC_QOS_MCTL_LIMIT_ENn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_MCTL_LIMIT_ENn_BMSK))) |
+ (val & NOC_QOS_MCTL_LIMIT_ENn_BMSK)),
+ NOC_QOS_MAINCTL_LOWn_ADDR(base, qos_off, mport, qos_delta));
- /* Set mode back to what it was initially */
- reg_val = readl_relaxed(NOC_QOS_MODEn_ADDR(base, qos_off,
- mport, qos_delta));
- writel_relaxed((reg_val & (~(NOC_QOS_MODEn_MODE_BMSK)))
- | (mode & NOC_QOS_MODEn_MODE_BMSK),
- NOC_QOS_MODEn_ADDR(base, qos_off, mport, qos_delta));
- /* Ensure that all writes for bandwidth registers have
- * completed before returning
- */
- wmb();
- }
+ wmb();
}
-uint8_t msm_bus_noc_get_qos_mode(void __iomem *base, uint32_t qos_off,
- uint32_t mport, uint32_t qos_delta, uint32_t mode, uint32_t perm_mode)
+static void noc_set_qos_regulator(void __iomem *base, uint32_t qos_off,
+ uint32_t mport, uint32_t qos_delta,
+ struct msm_bus_noc_regulator *reg,
+ struct msm_bus_noc_regulator_mode *reg_mode)
{
- if (perm_mode == NOC_QOS_MODES_ALL_PERM)
- return readl_relaxed(NOC_QOS_MODEn_ADDR(base, qos_off,
- mport, qos_delta)) & NOC_QOS_MODEn_MODE_BMSK;
- else
- return 31 - __CLZ(mode &
- NOC_QOS_MODES_ALL_PERM);
+ uint32_t reg_val, val;
+
+ reg_val = readl_relaxed(NOC_QOS_REGUL0CTLn_ADDR(base, qos_off, mport,
+ qos_delta)) & (NOC_QOS_REGUL0CTL_WRENn_BMSK |
+ NOC_QOS_REGUL0CTL_RDENn_BMSK);
+
+ writel_relaxed((reg_val & (~(NOC_QOS_REGUL0CTL_WRENn_BMSK |
+ NOC_QOS_REGUL0CTL_RDENn_BMSK))),
+ NOC_QOS_REGUL0CTLn_ADDR(base, qos_off, mport, qos_delta));
+
+ /* Ensure qos regulator is disabled before configuring */
+ wmb();
+
+ reg_val = readl_relaxed(NOC_QOS_REGUL0CTLn_ADDR(base, qos_off, mport,
+ qos_delta)) & NOC_QOS_REGUL0CTL_HI_PRIOn_BMSK;
+ val = reg->hi_prio << NOC_QOS_REGUL0CTL_HI_PRIOn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_REGUL0CTL_HI_PRIOn_BMSK))) |
+ (val & NOC_QOS_REGUL0CTL_HI_PRIOn_BMSK)),
+ NOC_QOS_REGUL0CTLn_ADDR(base, qos_off, mport, qos_delta));
+
+ reg_val = readl_relaxed(NOC_QOS_REGUL0CTLn_ADDR(base, qos_off, mport,
+ qos_delta)) & NOC_QOS_REGUL0CTL_LW_PRIOn_BMSK;
+ val = reg->low_prio << NOC_QOS_REGUL0CTL_LW_PRIOn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_REGUL0CTL_LW_PRIOn_BMSK))) |
+ (val & NOC_QOS_REGUL0CTL_LW_PRIOn_BMSK)),
+ NOC_QOS_REGUL0CTLn_ADDR(base, qos_off, mport, qos_delta));
+
+ reg_val = readl_relaxed(NOC_QOS_REGUL0BWn_ADDR(base, qos_off, mport,
+ qos_delta)) & NOC_QOS_REGUL0BW_BWn_BMSK;
+ val = reg->bw << NOC_QOS_REGUL0BW_BWn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_REGUL0BW_BWn_BMSK))) |
+ (val & NOC_QOS_REGUL0BW_BWn_BMSK)),
+ NOC_QOS_REGUL0BWn_ADDR(base, qos_off, mport, qos_delta));
+
+ reg_val = readl_relaxed(NOC_QOS_REGUL0BWn_ADDR(base, qos_off, mport,
+ qos_delta)) & NOC_QOS_REGUL0BW_SATn_BMSK;
+ val = reg->sat << NOC_QOS_REGUL0BW_SATn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_REGUL0BW_SATn_BMSK))) |
+ (val & NOC_QOS_REGUL0BW_SATn_BMSK)),
+ NOC_QOS_REGUL0BWn_ADDR(base, qos_off, mport, qos_delta));
+
+ /* Ensure regulator is configured before possibly enabling */
+ wmb();
+
+ reg_val = readl_relaxed(NOC_QOS_REGUL0CTLn_ADDR(base, qos_off, mport,
+ qos_delta));
+ val = reg_mode->write << NOC_QOS_REGUL0CTL_WRENn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_REGUL0CTL_WRENn_BMSK))) |
+ (val & NOC_QOS_REGUL0CTL_WRENn_BMSK)),
+ NOC_QOS_REGUL0CTLn_ADDR(base, qos_off, mport, qos_delta));
+
+ reg_val = readl_relaxed(NOC_QOS_REGUL0CTLn_ADDR(base, qos_off, mport,
+ qos_delta));
+ val = reg_mode->read << NOC_QOS_REGUL0CTL_RDENn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_REGUL0CTL_RDENn_BMSK))) |
+ (val & NOC_QOS_REGUL0CTL_RDENn_BMSK)),
+ NOC_QOS_REGUL0CTLn_ADDR(base, qos_off, mport, qos_delta));
+
+ /* Ensure regulator is ready before exiting */
+ wmb();
}
-void msm_bus_noc_get_qos_priority(void __iomem *base, uint32_t qos_off,
- uint32_t mport, uint32_t qos_delta,
- struct msm_bus_noc_qos_priority *priority)
+static void noc_set_qos_forwarding(void __iomem *base, uint32_t qos_off,
+ uint32_t mport, uint32_t qos_delta,
+ bool urg_fwd_en)
{
- priority->p1 = (readl_relaxed(NOC_QOS_PRIORITYn_ADDR(base, qos_off,
- mport, qos_delta)) & NOC_QOS_PRIORITYn_P1_BMSK) >>
- NOC_QOS_PRIORITYn_P1_SHFT;
+ uint32_t reg_val, val;
- priority->p0 = (readl_relaxed(NOC_QOS_PRIORITYn_ADDR(base, qos_off,
- mport, qos_delta)) & NOC_QOS_PRIORITYn_P0_BMSK) >>
- NOC_QOS_PRIORITYn_P0_SHFT;
+ reg_val = readl_relaxed(NOC_QOS_MAINCTL_LOWn_ADDR(base, qos_off, mport,
+ qos_delta));
+ val = (urg_fwd_en ? 1:0) << NOC_QOS_MCTL_URGFWD_ENn_SHFT;
+ writel_relaxed(((reg_val & (~(NOC_QOS_MCTL_URGFWD_ENn_BMSK))) |
+ (val & NOC_QOS_MCTL_URGFWD_ENn_BMSK)),
+ NOC_QOS_MAINCTL_LOWn_ADDR(base, qos_off, mport, qos_delta));
+
+ /* Ensure qos priority is set before exiting */
+ wmb();
}
void msm_bus_noc_get_qos_bw(void __iomem *base, uint32_t qos_off,
@@ -336,28 +316,16 @@
}
}
-static bool msm_bus_noc_update_bw_reg(int mode)
-{
- bool ret = false;
-
- if ((mode == NOC_QOS_MODE_LIMITER) ||
- (mode == NOC_QOS_MODE_REGULATOR))
- ret = true;
-
- return ret;
-}
-
static int msm_bus_noc_qos_init(struct msm_bus_node_device_type *info,
void __iomem *qos_base,
uint32_t qos_off, uint32_t qos_delta,
uint32_t qos_freq)
{
- struct msm_bus_noc_qos_priority prio;
+ struct msm_bus_noc_qos_params *qos_params;
int ret = 0;
int i;
- prio.p1 = info->node_info->qos_params.prio1;
- prio.p0 = info->node_info->qos_params.prio0;
+ qos_params = &info->node_info->qos_params;
if (!info->node_info->qport) {
MSM_BUS_DBG("No QoS Ports to init\n");
@@ -366,224 +334,38 @@
}
for (i = 0; i < info->node_info->num_qports; i++) {
- if (info->node_info->qos_params.mode != NOC_QOS_MODE_BYPASS) {
- noc_set_qos_priority(qos_base, qos_off,
- info->node_info->qport[i], qos_delta,
- &prio);
-
- if (info->node_info->qos_params.mode !=
- NOC_QOS_MODE_FIXED) {
- struct msm_bus_noc_qos_bw qbw;
-
- qbw.ws = info->node_info->qos_params.ws;
- qbw.bw = 0;
- msm_bus_noc_set_qos_bw(qos_base, qos_off,
- qos_freq,
+ noc_set_qos_dflt_prio(qos_base, qos_off,
info->node_info->qport[i],
qos_delta,
- info->node_info->qos_params.mode,
- &qbw);
- }
- }
+ qos_params->prio_dflt);
- noc_set_qos_mode(qos_base, qos_off, info->node_info->qport[i],
- qos_delta, info->node_info->qos_params.mode,
- (1 << info->node_info->qos_params.mode));
+ noc_set_qos_limiter(qos_base, qos_off,
+ info->node_info->qport[i],
+ qos_delta,
+ &qos_params->limiter,
+ qos_params->limiter_en);
+
+ noc_set_qos_regulator(qos_base, qos_off,
+ info->node_info->qport[i],
+ qos_delta,
+ &qos_params->reg,
+ &qos_params->reg_mode);
+
+ noc_set_qos_forwarding(qos_base, qos_off,
+ info->node_info->qport[i],
+ qos_delta,
+ qos_params->urg_fwd_en);
}
err_qos_init:
return ret;
}
-static int msm_bus_noc_set_bw(struct msm_bus_node_device_type *dev,
- void __iomem *qos_base,
- uint32_t qos_off, uint32_t qos_delta,
- uint32_t qos_freq)
-{
- int ret = 0;
- uint64_t bw = 0;
- int i;
- struct msm_bus_node_info_type *info = dev->node_info;
-
- if (info && info->num_qports &&
- ((info->qos_params.mode == NOC_QOS_MODE_REGULATOR) ||
- (info->qos_params.mode ==
- NOC_QOS_MODE_LIMITER))) {
- struct msm_bus_noc_qos_bw qos_bw;
-
- bw = msm_bus_div64(info->num_qports,
- dev->node_bw[ACTIVE_CTX].sum_ab);
-
- for (i = 0; i < info->num_qports; i++) {
- if (!info->qport) {
- MSM_BUS_DBG("No qos ports to update!\n");
- break;
- }
-
- qos_bw.bw = bw;
- qos_bw.ws = info->qos_params.ws;
- msm_bus_noc_set_qos_bw(qos_base, qos_off, qos_freq,
- info->qport[i], qos_delta,
- (1 << info->qos_params.mode), &qos_bw);
- MSM_BUS_DBG("NOC: QoS: Update mas_bw: ws: %u\n",
- qos_bw.ws);
- }
- }
- return ret;
-}
-
-static int msm_bus_noc_set_lim_mode(struct msm_bus_node_device_type *info,
- void __iomem *qos_base, uint32_t qos_off,
- uint32_t qos_delta, uint32_t qos_freq,
- u64 lim_bw)
-{
- int i;
-
- if (info && info->node_info->num_qports) {
- struct msm_bus_noc_qos_bw qos_bw;
-
- if (lim_bw != info->node_info->lim_bw) {
- for (i = 0; i < info->node_info->num_qports; i++) {
- qos_bw.bw = lim_bw;
- qos_bw.ws = info->node_info->qos_params.ws;
- msm_bus_noc_set_qos_bw(qos_base,
- qos_off, qos_freq,
- info->node_info->qport[i], qos_delta,
- (1 << NOC_QOS_MODE_LIMITER), &qos_bw);
- }
- info->node_info->lim_bw = lim_bw;
- }
-
- for (i = 0; i < info->node_info->num_qports; i++) {
- noc_set_qos_mode(qos_base, qos_off,
- info->node_info->qport[i],
- qos_delta,
- NOC_QOS_MODE_LIMITER,
- (1 << NOC_QOS_MODE_LIMITER));
- }
- }
-
- return 0;
-}
-
-static int msm_bus_noc_set_reg_mode(struct msm_bus_node_device_type *info,
- void __iomem *qos_base, uint32_t qos_off,
- uint32_t qos_delta, uint32_t qos_freq,
- u64 lim_bw)
-{
- int i;
-
- if (info && info->node_info->num_qports) {
- struct msm_bus_noc_qos_priority prio;
- struct msm_bus_noc_qos_bw qos_bw;
-
- for (i = 0; i < info->node_info->num_qports; i++) {
- prio.p1 =
- info->node_info->qos_params.reg_prio1;
- prio.p0 =
- info->node_info->qos_params.reg_prio0;
- noc_set_qos_priority(qos_base, qos_off,
- info->node_info->qport[i],
- qos_delta,
- &prio);
- }
-
- if (lim_bw != info->node_info->lim_bw) {
- for (i = 0; i < info->node_info->num_qports; i++) {
- qos_bw.bw = lim_bw;
- qos_bw.ws = info->node_info->qos_params.ws;
- msm_bus_noc_set_qos_bw(qos_base, qos_off,
- qos_freq,
- info->node_info->qport[i], qos_delta,
- (1 << NOC_QOS_MODE_REGULATOR), &qos_bw);
- }
- info->node_info->lim_bw = lim_bw;
- }
-
- for (i = 0; i < info->node_info->num_qports; i++) {
- noc_set_qos_mode(qos_base, qos_off,
- info->node_info->qport[i],
- qos_delta,
- NOC_QOS_MODE_REGULATOR,
- (1 << NOC_QOS_MODE_REGULATOR));
- }
- }
- return 0;
-}
-
-static int msm_bus_noc_set_def_mode(struct msm_bus_node_device_type *info,
- void __iomem *qos_base, uint32_t qos_off,
- uint32_t qos_delta, uint32_t qos_freq,
- u64 lim_bw)
-{
- int i;
-
- for (i = 0; i < info->node_info->num_qports; i++) {
- if (info->node_info->qos_params.mode ==
- NOC_QOS_MODE_FIXED) {
- struct msm_bus_noc_qos_priority prio;
-
- prio.p1 =
- info->node_info->qos_params.prio1;
- prio.p0 =
- info->node_info->qos_params.prio0;
- noc_set_qos_priority(qos_base, qos_off,
- info->node_info->qport[i],
- qos_delta, &prio);
- }
- noc_set_qos_mode(qos_base, qos_off,
- info->node_info->qport[i],
- qos_delta,
- info->node_info->qos_params.mode,
- (1 << info->node_info->qos_params.mode));
- }
- return 0;
-}
-
-static int msm_bus_noc_limit_mport(struct msm_bus_node_device_type *info,
- void __iomem *qos_base, uint32_t qos_off,
- uint32_t qos_delta, uint32_t qos_freq,
- int enable_lim, u64 lim_bw)
-{
- int ret = 0;
-
- if (!(info && info->node_info->num_qports)) {
- MSM_BUS_ERR("Invalid Node info or no Qports to program");
- ret = -ENXIO;
- goto exit_limit_mport;
- }
-
- if (lim_bw) {
- switch (enable_lim) {
- case THROTTLE_REG:
- msm_bus_noc_set_reg_mode(info, qos_base, qos_off,
- qos_delta, qos_freq, lim_bw);
- break;
- case THROTTLE_ON:
- msm_bus_noc_set_lim_mode(info, qos_base, qos_off,
- qos_delta, qos_freq, lim_bw);
- break;
- default:
- msm_bus_noc_set_def_mode(info, qos_base, qos_off,
- qos_delta, qos_freq, lim_bw);
- break;
- }
- } else
- msm_bus_noc_set_def_mode(info, qos_base, qos_off,
- qos_delta, qos_freq, lim_bw);
-
-exit_limit_mport:
- return ret;
-}
-
int msm_bus_noc_set_ops(struct msm_bus_node_device_type *bus_dev)
{
if (!bus_dev)
return -ENODEV;
bus_dev->fabdev->noc_ops.qos_init = msm_bus_noc_qos_init;
- bus_dev->fabdev->noc_ops.set_bw = msm_bus_noc_set_bw;
- bus_dev->fabdev->noc_ops.limit_mport = msm_bus_noc_limit_mport;
- bus_dev->fabdev->noc_ops.update_bw_reg = msm_bus_noc_update_bw_reg;
return 0;
}
diff --git a/drivers/soc/qcom/msm_bus/msm_bus_of.c b/drivers/soc/qcom/msm_bus/msm_bus_of.c
index fd72ae6..34ba05f 100644
--- a/drivers/soc/qcom/msm_bus/msm_bus_of.c
+++ b/drivers/soc/qcom/msm_bus/msm_bus_of.c
@@ -113,9 +113,9 @@
int index = i * 2;
usecase_lat[i].fal_ns = (uint64_t)
- KBTOB(be32_to_cpu(vec_arr[index]));
+ be32_to_cpu(vec_arr[index]);
usecase_lat[i].idle_t_ns = (uint64_t)
- KBTOB(be32_to_cpu(vec_arr[index + 1]));
+ be32_to_cpu(vec_arr[index + 1]);
}
pdata->usecase_lat = usecase_lat;
diff --git a/drivers/soc/qcom/msm_bus/msm_bus_of_rpmh.c b/drivers/soc/qcom/msm_bus/msm_bus_of_rpmh.c
index 5710bca..42a6f58 100644
--- a/drivers/soc/qcom/msm_bus/msm_bus_of_rpmh.c
+++ b/drivers/soc/qcom/msm_bus/msm_bus_of_rpmh.c
@@ -31,31 +31,6 @@
#define DEFAULT_VRAIL_COMP 100
#define DEFAULT_AGG_SCHEME AGG_SCHEME_LEG
-static int get_qos_mode(struct platform_device *pdev,
- struct device_node *node, const char *qos_mode)
-{
- static char const *qos_names[] = {"fixed", "limiter",
- "bypass", "regulator"};
- int i = 0;
- int ret = -1;
-
- if (!qos_mode)
- goto exit_get_qos_mode;
-
- for (i = 0; i < ARRAY_SIZE(qos_names); i++) {
- if (!strcmp(qos_mode, qos_names[i]))
- break;
- }
- if (i == ARRAY_SIZE(qos_names))
- dev_err(&pdev->dev, "Cannot match mode qos %s using Bypass",
- qos_mode);
- else
- ret = i;
-
-exit_get_qos_mode:
- return ret;
-}
-
static int *get_arr(struct platform_device *pdev,
struct device_node *node, const char *prop,
int *nports)
@@ -210,7 +185,6 @@
fab_dev->qos_freq = DEFAULT_QOS_FREQ;
}
-
return fab_dev;
fab_dev_err:
@@ -224,54 +198,48 @@
struct platform_device * const pdev,
struct msm_bus_node_info_type *node_info)
{
- const char *qos_mode = NULL;
- unsigned int ret;
- unsigned int temp;
+ const uint32_t *vec_arr = NULL;
+ int len;
- ret = of_property_read_string(dev_node, "qcom,qos-mode", &qos_mode);
+ of_property_read_u32(dev_node, "qcom,prio",
+ &node_info->qos_params.prio_dflt);
- if (ret)
- node_info->qos_params.mode = -1;
- else
- node_info->qos_params.mode = get_qos_mode(pdev, dev_node,
- qos_mode);
+ vec_arr = of_get_property(dev_node, "qcom,lim-params", &len);
+ if (vec_arr != NULL && len == sizeof(uint32_t) * 2) {
+ node_info->qos_params.limiter.bw = be32_to_cpu(vec_arr[0]);
+ node_info->qos_params.limiter.sat = be32_to_cpu(vec_arr[1]);
+ } else {
+ node_info->qos_params.limiter.bw = 0;
+ node_info->qos_params.limiter.sat = 0;
+ }
- of_property_read_u32(dev_node, "qcom,prio-lvl",
- &node_info->qos_params.prio_lvl);
+ node_info->qos_params.limiter_en = of_property_read_bool(dev_node,
+ "qcom,lim-en");
- of_property_read_u32(dev_node, "qcom,prio1",
- &node_info->qos_params.prio1);
+ vec_arr = of_get_property(dev_node, "qcom,qos-reg-params", &len);
+ if (vec_arr != NULL && len == sizeof(uint32_t) * 4) {
+ node_info->qos_params.reg.low_prio = be32_to_cpu(vec_arr[0]);
+ node_info->qos_params.reg.hi_prio = be32_to_cpu(vec_arr[1]);
+ node_info->qos_params.reg.bw = be32_to_cpu(vec_arr[2]);
+ node_info->qos_params.reg.sat = be32_to_cpu(vec_arr[3]);
+ } else {
+ node_info->qos_params.reg.low_prio = 0;
+ node_info->qos_params.reg.hi_prio = 0;
+ node_info->qos_params.reg.bw = 0;
+ node_info->qos_params.reg.sat = 0;
+ }
- of_property_read_u32(dev_node, "qcom,prio0",
- &node_info->qos_params.prio0);
+ vec_arr = of_get_property(dev_node, "qcom,qos-reg-mode", &len);
+ if (vec_arr != NULL && len == sizeof(uint32_t) * 2) {
+ node_info->qos_params.reg_mode.read = be32_to_cpu(vec_arr[0]);
+ node_info->qos_params.reg_mode.write = be32_to_cpu(vec_arr[1]);
+ } else {
+ node_info->qos_params.reg_mode.read = 0;
+ node_info->qos_params.reg_mode.write = 0;
+ }
- of_property_read_u32(dev_node, "qcom,reg-prio1",
- &node_info->qos_params.reg_prio1);
-
- of_property_read_u32(dev_node, "qcom,reg-prio0",
- &node_info->qos_params.reg_prio0);
-
- of_property_read_u32(dev_node, "qcom,prio-rd",
- &node_info->qos_params.prio_rd);
-
- of_property_read_u32(dev_node, "qcom,prio-wr",
- &node_info->qos_params.prio_wr);
-
- of_property_read_u32(dev_node, "qcom,gp",
- &node_info->qos_params.gp);
-
- of_property_read_u32(dev_node, "qcom,thmp",
- &node_info->qos_params.thmp);
-
- of_property_read_u32(dev_node, "qcom,ws",
- &node_info->qos_params.ws);
-
- ret = of_property_read_u32(dev_node, "qcom,bw_buffer", &temp);
-
- if (ret)
- node_info->qos_params.bw_buffer = 0;
- else
- node_info->qos_params.bw_buffer = KBTOB(temp);
+ node_info->qos_params.urg_fwd_en = of_property_read_bool(dev_node,
+ "qcom,forwarding");
}
@@ -308,13 +276,9 @@
char gdsc_string[MAX_REG_NAME];
(*clk_arr)[idx].clk = of_clk_get_by_name(dev_node, clk_name);
+ if (IS_ERR_OR_NULL((*clk_arr)[idx].clk))
+ goto exit_of_parse_clk_array;
- if (IS_ERR_OR_NULL((*clk_arr)[idx].clk)) {
- dev_err(&pdev->dev,
- "Failed to get clk %s for bus%d ", clk_name,
- id);
- continue;
- }
if (strnstr(clk_name, "no-rate", strlen(clk_name)))
(*clk_arr)[idx].enable_only_clk = true;
@@ -532,6 +496,10 @@
{
bool enable_only;
bool setrate_only;
+ int num_elems = 0, num_bcms = 0, i = 0, ret = 0;
+ uint32_t *vec_arr = NULL;
+ struct qos_bcm_type *qos_bcms = NULL;
+ struct device_node *qos_clk_node = NULL;
node_device->node_info = get_node_info_data(dev_node, pdev);
if (IS_ERR_OR_NULL(node_device->node_info)) {
@@ -566,8 +534,6 @@
}
if (node_device->node_info->is_fab_dev) {
- struct device_node *qos_clk_node;
-
dev_dbg(&pdev->dev, "Dev %d\n", node_device->node_info->id);
if (!node_device->node_info->virt_dev) {
@@ -615,6 +581,48 @@
of_node_put(qos_clk_node);
}
} else {
+ num_elems = of_property_count_elems_of_size(dev_node,
+ "qcom,node-qos-bcms", sizeof(uint32_t));
+
+ if (num_elems > 0) {
+ if (num_elems % 3 != 0) {
+ pr_err("Error: Length-error on getting vectors\n");
+ return -ENODATA;
+ }
+
+ vec_arr = devm_kzalloc(&pdev->dev, (sizeof(uint32_t) *
+ num_elems), GFP_KERNEL);
+ if (!vec_arr)
+ return -ENOMEM;
+
+ ret = of_property_read_u32_array(dev_node,
+ "qcom,node-qos-bcms", vec_arr,
+ num_elems);
+ if (ret) {
+ pr_err("Error: problem reading qos-bcm vectors\n");
+ return ret;
+ }
+ num_bcms = num_elems / 3;
+ node_device->num_qos_bcms = num_bcms;
+
+ qos_bcms = devm_kzalloc(&pdev->dev,
+ (sizeof(struct qos_bcm_type) *
+ num_bcms), GFP_KERNEL);
+ if (!qos_bcms)
+ return -ENOMEM;
+
+ for (i = 0; i < num_bcms; i++) {
+ int index = i * 3;
+
+ qos_bcms[i].qos_bcm_id = vec_arr[index];
+ qos_bcms[i].vec.vec_a =
+ (uint64_t)KBTOB(vec_arr[index + 1]);
+ qos_bcms[i].vec.vec_b =
+ (uint64_t)KBTOB(vec_arr[index + 2]);
+ }
+ node_device->qos_bcms = qos_bcms;
+ }
+
enable_only = of_property_read_bool(dev_node,
"qcom,enable-only-clk");
node_device->clk[DUAL_CTX].enable_only_clk = enable_only;
@@ -632,6 +640,20 @@
setrate_only;
}
+ qos_clk_node = of_get_child_by_name(dev_node,
+ "qcom,node-qos-clks");
+
+ if (qos_clk_node) {
+ if (msm_bus_of_parse_clk_array(qos_clk_node, dev_node,
+ pdev,
+ &node_device->node_qos_clks,
+ &node_device->num_node_qos_clks,
+ node_device->node_info->id)) {
+ dev_dbg(&pdev->dev, "Bypass QoS programming");
+ node_device->fabdev->bypass_qos_prg = true;
+ }
+ of_node_put(qos_clk_node);
+ }
node_device->clk[DUAL_CTX].clk = of_clk_get_by_name(dev_node,
"node_clk");
diff --git a/drivers/soc/qcom/msm_bus/msm_bus_rpmh.h b/drivers/soc/qcom/msm_bus/msm_bus_rpmh.h
index cd5281a..17657e5 100644
--- a/drivers/soc/qcom/msm_bus/msm_bus_rpmh.h
+++ b/drivers/soc/qcom/msm_bus/msm_bus_rpmh.h
@@ -19,6 +19,7 @@
#include <linux/msm-bus.h>
#include <linux/msm_bus_rules.h>
#include "msm_bus_core.h"
+#include "msm_bus_noc.h"
#define VCD_MAX_CNT 16
@@ -75,6 +76,11 @@
uint64_t query_vec_b;
};
+struct qos_bcm_type {
+ int qos_bcm_id;
+ struct nodevector vec;
+};
+
struct msm_bus_rsc_device_type {
struct rpmh_client *mbox;
struct list_head bcm_clist[VCD_MAX_CNT];
@@ -106,19 +112,30 @@
bool bypass_qos_prg;
};
-struct qos_params_type {
- int mode;
- unsigned int prio_lvl;
- unsigned int prio_rd;
- unsigned int prio_wr;
- unsigned int prio1;
- unsigned int prio0;
- unsigned int reg_prio1;
- unsigned int reg_prio0;
- unsigned int gp;
- unsigned int thmp;
- unsigned int ws;
- u64 bw_buffer;
+struct msm_bus_noc_limiter {
+ uint32_t bw;
+ uint32_t sat;
+};
+
+struct msm_bus_noc_regulator {
+ uint32_t low_prio;
+ uint32_t hi_prio;
+ uint32_t bw;
+ uint32_t sat;
+};
+
+struct msm_bus_noc_regulator_mode {
+ uint32_t read;
+ uint32_t write;
+};
+
+struct msm_bus_noc_qos_params {
+ uint32_t prio_dflt;
+ struct msm_bus_noc_limiter limiter;
+ bool limiter_en;
+ struct msm_bus_noc_regulator reg;
+ struct msm_bus_noc_regulator_mode reg_mode;
+ bool urg_fwd_en;
};
struct node_util_levels_type {
@@ -143,7 +160,7 @@
int num_ports;
int num_qports;
int *qport;
- struct qos_params_type qos_params;
+ struct msm_bus_noc_qos_params qos_params;
unsigned int num_connections;
unsigned int num_blist;
unsigned int num_bcm_devs;
@@ -185,6 +202,8 @@
struct nodeclk bus_qos_clk;
uint32_t num_node_qos_clks;
struct nodeclk *node_qos_clks;
+ uint32_t num_qos_bcms;
+ struct qos_bcm_type *qos_bcms;
unsigned int ap_owned;
struct device_node *of_node;
struct device dev;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 009193c..b042152 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -590,6 +590,7 @@
* @dbg_ep_events: different events counter for endpoint
* @dbg_ep_events_diff: differential events counter for endpoint
* @dbg_ep_events_ts: timestamp for previous event counters
+ * @fifo_depth: allocated TXFIFO depth
*/
struct dwc3_ep {
struct usb_ep endpoint;
@@ -644,6 +645,7 @@
struct dwc3_ep_events dbg_ep_events;
struct dwc3_ep_events dbg_ep_events_diff;
struct timespec dbg_ep_events_ts;
+ int fifo_depth;
};
enum dwc3_phy {
@@ -905,7 +907,6 @@
* @pending_events: true when we have pending IRQs to be handled
* @needs_fifo_resize: not all users might want fifo resizing, flag it
* @pullups_connected: true when Run/Stop bit is set
- * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
* @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
* @start_config_issued: true when StartConfig command has been issued
* @three_stage_setup: set if we perform a three phase setup
@@ -947,6 +948,7 @@
* @vbus_draw: current to be drawn from USB
* @index: dwc3 instance's number
* @dwc_ipc_log_ctxt: dwc3 ipc log context
+ * @last_fifo_depth: total TXFIFO depth of all enabled USB IN/INT endpoints
* @imod_interval: set the interrupt moderation interval in 250ns
* increments or 0 to disable.
*/
@@ -1082,7 +1084,6 @@
unsigned pending_events:1;
unsigned needs_fifo_resize:1;
unsigned pullups_connected:1;
- unsigned resize_fifos:1;
unsigned setup_packet_pending:1;
unsigned three_stage_setup:1;
unsigned usb3_lpm_capable:1;
@@ -1142,6 +1143,7 @@
wait_queue_head_t wait_linkstate;
unsigned int index;
void *dwc_ipc_log_ctxt;
+ int last_fifo_depth;
struct dwc3_gadget_events dbg_gadget_events;
};
@@ -1297,7 +1299,7 @@
/* prototypes */
void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
-int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
+int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc, struct dwc3_ep *dep);
/* check whether we are on the DWC_usb3 core */
static inline bool dwc3_is_usb3(struct dwc3 *dwc)
diff --git a/drivers/usb/dwc3/debugfs.c b/drivers/usb/dwc3/debugfs.c
index a7105af..260092c 100644
--- a/drivers/usb/dwc3/debugfs.c
+++ b/drivers/usb/dwc3/debugfs.c
@@ -324,7 +324,7 @@
struct dwc3 *dwc = s->private;
unsigned long flags;
u32 mode = 0;
- char buf[32];
+ char buf[32] = {};
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
return -EFAULT;
@@ -404,7 +404,7 @@
struct dwc3 *dwc = s->private;
unsigned long flags;
u32 testmode = 0;
- char buf[32];
+ char buf[32] = {};
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
return -EFAULT;
@@ -511,7 +511,7 @@
struct dwc3 *dwc = s->private;
unsigned long flags;
enum dwc3_link_state state = 0;
- char buf[32];
+ char buf[32] = {};
if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
return -EFAULT;
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index 4660e31..a496468 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -868,8 +868,8 @@
* n + 1 TRBs as per GSI h/w requirement. n Xfer TRBs + 1
* LINK TRB.
*/
- ch_info->xfer_ring_len = (request->num_bufs + 1) * 0x10;
- last_trb_index = request->num_bufs + 1;
+ ch_info->xfer_ring_len = (request->num_bufs + 2) * 0x10;
+ last_trb_index = request->num_bufs + 2;
}
/* Store last 16 bits of LINK TRB address as per GSI hw requirement */
@@ -941,13 +941,13 @@
}
/*
-* Rings Doorbell for IN GSI Channel
+* Rings Doorbell for GSI Channel
*
* @usb_ep - pointer to usb_ep instance.
* @request - pointer to GSI request. This is used to pass in the
* address of the GSI doorbell obtained from IPA driver
*/
-static void gsi_ring_in_db(struct usb_ep *ep, struct usb_gsi_request *request)
+static void gsi_ring_db(struct usb_ep *ep, struct usb_gsi_request *request)
{
void __iomem *gsi_dbl_address_lsb;
void __iomem *gsi_dbl_address_msb;
@@ -955,10 +955,11 @@
u64 dbl_addr = *((u64 *)request->buf_base_addr);
u32 dbl_lo_addr = (dbl_addr & 0xFFFFFFFF);
u32 dbl_hi_addr = (dbl_addr >> 32);
- u32 num_trbs = (request->num_bufs * 2 + 2);
struct dwc3_ep *dep = to_dwc3_ep(ep);
struct dwc3 *dwc = dep->dwc;
struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent);
+ int num_trbs = (dep->direction) ? (2 * (request->num_bufs) + 2)
+ : (request->num_bufs + 2);
gsi_dbl_address_lsb = devm_ioremap_nocache(mdwc->dev,
dbl_lo_addr, sizeof(u32));
@@ -971,8 +972,8 @@
dev_dbg(mdwc->dev, "Failed to get GSI DBL address MSB\n");
offset = dwc3_trb_dma_offset(dep, &dep->trb_pool[num_trbs-1]);
- dev_dbg(mdwc->dev, "Writing link TRB addr: %pa to %p (%x)\n",
- &offset, gsi_dbl_address_lsb, dbl_lo_addr);
+ dev_dbg(mdwc->dev, "Writing link TRB addr: %pa to %p (%x) for ep:%s\n",
+ &offset, gsi_dbl_address_lsb, dbl_lo_addr, ep->name);
writel_relaxed(offset, gsi_dbl_address_lsb);
writel_relaxed(0, gsi_dbl_address_msb);
@@ -1042,7 +1043,7 @@
struct dwc3 *dwc = dep->dwc;
struct dwc3_trb *trb;
int num_trbs = (dep->direction) ? (2 * (req->num_bufs) + 2)
- : (req->num_bufs + 1);
+ : (req->num_bufs + 2);
dep->trb_dma_pool = dma_pool_create(ep->name, dwc->sysdev,
num_trbs * sizeof(struct dwc3_trb),
@@ -1103,26 +1104,43 @@
trb = &dep->trb_pool[i];
memset(trb, 0, sizeof(*trb));
- trb->bpl = lower_32_bits(buffer_addr);
- trb->bph = 0;
- trb->size = req->buf_len;
- trb->ctrl = DWC3_TRBCTL_NORMAL | DWC3_TRB_CTRL_IOC
- | DWC3_TRB_CTRL_CSP
- | DWC3_TRB_CTRL_ISP_IMI;
- buffer_addr += req->buf_len;
-
- /* Set up the Link TRB at the end */
- if (i == (num_trbs - 1)) {
+ /* Setup LINK TRB to start with TRB ring */
+ if (i == 0) {
trb->bpl = dwc3_trb_dma_offset(dep,
- &dep->trb_pool[0]);
+ &dep->trb_pool[1]);
+ trb->ctrl = DWC3_TRBCTL_LINK_TRB;
+ } else if (i == (num_trbs - 1)) {
+ /* Set up the Link TRB at the end */
+ trb->bpl = dwc3_trb_dma_offset(dep,
+ &dep->trb_pool[0]);
trb->bph = (1 << 23) | (1 << 21)
| (ep->ep_intr_num << 16);
- trb->size = 0;
trb->ctrl = DWC3_TRBCTL_LINK_TRB
| DWC3_TRB_CTRL_HWO;
+ } else {
+ trb->bpl = lower_32_bits(buffer_addr);
+ trb->size = req->buf_len;
+ buffer_addr += req->buf_len;
+ trb->ctrl = DWC3_TRBCTL_NORMAL
+ | DWC3_TRB_CTRL_IOC
+ | DWC3_TRB_CTRL_CSP
+ | DWC3_TRB_CTRL_ISP_IMI;
}
}
}
+
+ pr_debug("%s: Initialized TRB Ring for %s\n", __func__, dep->name);
+ trb = &dep->trb_pool[0];
+ if (trb) {
+ for (i = 0; i < num_trbs; i++) {
+ pr_debug("TRB(%d): ADDRESS:%lx bpl:%x bph:%x size:%x ctrl:%x\n",
+ i, (unsigned long)dwc3_trb_dma_offset(dep,
+ &dep->trb_pool[i]), trb->bpl, trb->bph,
+ trb->size, trb->ctrl);
+ trb++;
+ }
+ }
+
return 0;
}
@@ -1163,7 +1181,8 @@
struct dwc3_gadget_ep_cmd_params params;
const struct usb_endpoint_descriptor *desc = ep->desc;
const struct usb_ss_ep_comp_descriptor *comp_desc = ep->comp_desc;
- u32 reg;
+ u32 reg;
+ int ret;
memset(¶ms, 0x00, sizeof(params));
@@ -1211,6 +1230,10 @@
/* Set XferRsc Index for GSI EP */
if (!(dep->flags & DWC3_EP_ENABLED)) {
+ ret = dwc3_gadget_resize_tx_fifos(dwc, dep);
+ if (ret)
+ return;
+
memset(¶ms, 0x00, sizeof(params));
params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
dwc3_send_gadget_ep_cmd(dep,
@@ -1363,10 +1386,10 @@
ch_info = (struct gsi_channel_info *)op_data;
gsi_get_channel_info(ep, ch_info);
break;
- case GSI_EP_OP_RING_IN_DB:
+ case GSI_EP_OP_RING_DB:
request = (struct usb_gsi_request *)op_data;
- dev_dbg(mdwc->dev, "RING IN EP DB\n");
- gsi_ring_in_db(ep, request);
+ dbg_print(0xFF, "RING_DB", 0, ep->name);
+ gsi_ring_db(ep, request);
break;
case GSI_EP_OP_UPDATEXFER:
request = (struct usb_gsi_request *)op_data;
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index b062d58..ec9ffc1 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -588,8 +588,9 @@
{
enum usb_device_state state = dwc->gadget.state;
u32 cfg;
- int ret;
+ int ret, num;
u32 reg;
+ struct dwc3_ep *dep;
cfg = le16_to_cpu(ctrl->wValue);
@@ -598,6 +599,24 @@
return -EINVAL;
case USB_STATE_ADDRESS:
+ /* Read ep0IN related TXFIFO size */
+ dwc->last_fifo_depth = (dwc3_readl(dwc->regs,
+ DWC3_GTXFIFOSIZ(0)) & 0xFFFF);
+ /* Clear existing allocated TXFIFO for all IN eps except ep0 */
+ for (num = 0; num < dwc->num_in_eps; num++) {
+ dep = dwc->eps[(num << 1) | 1];
+ if (num) {
+ dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), 0);
+ dep->fifo_depth = 0;
+ } else {
+ dep->fifo_depth = dwc->last_fifo_depth;
+ }
+
+ dev_dbg(dwc->dev, "%s(): %s dep->fifo_depth:%x\n",
+ __func__, dep->name, dep->fifo_depth);
+ dbg_event(0xFF, "fifo_reset", dep->number);
+ }
+
ret = dwc3_ep0_delegate_req(dwc, ctrl);
/* if the cfg matches and the cfg is non zero */
if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
@@ -619,9 +638,6 @@
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
-
- dwc->resize_fifos = true;
- dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
}
break;
@@ -1080,12 +1096,6 @@
{
int ret;
- if (dwc->resize_fifos) {
- dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
- dwc3_gadget_resize_tx_fifos(dwc);
- dwc->resize_fifos = 0;
- }
-
ret = dwc3_ep0_start_control_status(dep);
if (WARN_ON_ONCE(ret))
dbg_event(dep->number, "ECTRLSTATUS", ret);
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 19b9cfb..7d8566f 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -195,88 +195,64 @@
*
* Unfortunately, due to many variables that's not always the case.
*/
-int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
+int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc, struct dwc3_ep *dep)
{
- int last_fifo_depth = 0;
- int ram1_depth;
- int fifo_size;
- int mdwidth;
- int num;
- int num_eps;
- int max_packet = 1024;
- struct usb_composite_dev *cdev = get_gadget_data(&dwc->gadget);
+ int fifo_size, mdwidth, max_packet = 1024;
+ int tmp, mult = 1;
- if (!(cdev && cdev->config) || !dwc->needs_fifo_resize)
+ if (!dwc->needs_fifo_resize)
return 0;
- num_eps = dwc->num_in_eps;
- ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
- mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+ /* resize IN endpoints excepts ep0 */
+ if (!usb_endpoint_dir_in(dep->endpoint.desc) ||
+ dep->endpoint.ep_num == 0)
+ return 0;
- /* MDWIDTH is represented in bits, we need it in bytes */
- mdwidth >>= 3;
- last_fifo_depth = (dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0)) & 0xFFFF);
- dev_dbg(dwc->dev, "%s: num eps:%d max_packet:%d last_fifo_depth:%04x\n",
- __func__, num_eps, max_packet, last_fifo_depth);
-
- /* Don't resize ep0IN TxFIFO, start with ep1IN only. */
- for (num = 1; num < num_eps; num++) {
- /* bit0 indicates direction; 1 means IN ep */
- struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
- int mult = 1;
- int tmp;
-
- tmp = max_packet + mdwidth;
- /*
- * Interfaces like MBIM or ECM is having multiple data
- * interfaces. SET_CONFIG() happens before set_alt with
- * data interface 1 which results into calling this API
- * before GSI endpoint enabled. This results no txfifo
- * resize with GSI endpoint causing low throughput. Hence
- * use mult as 3 for GSI IN endpoint always irrespective
- * USB speed.
- */
- if (dep->endpoint.ep_type == EP_TYPE_GSI ||
- dep->endpoint.endless)
- mult = 3;
-
- if (!(dep->flags & DWC3_EP_ENABLED)) {
- dev_dbg(dwc->dev, "ep%dIn not enabled", num);
- goto resize_fifo;
- }
-
- if (((dep->endpoint.maxburst > 1) &&
- usb_endpoint_xfer_bulk(dep->endpoint.desc))
- || usb_endpoint_xfer_isoc(dep->endpoint.desc))
- mult = 3;
-
-resize_fifo:
- tmp *= mult;
- tmp += mdwidth;
-
- fifo_size = DIV_ROUND_UP(tmp, mdwidth);
-
- fifo_size |= (last_fifo_depth << 16);
-
- dev_dbg(dwc->dev, "%s: Fifo Addr %04x Size %d",
- dep->name, last_fifo_depth, fifo_size & 0xffff);
-
- last_fifo_depth += (fifo_size & 0xffff);
- if (dwc->tx_fifo_size &&
- (last_fifo_depth >= dwc->tx_fifo_size)) {
- /*
- * Fifo size allocated exceeded available RAM size.
- * Hence return error.
- */
- dev_err(dwc->dev, "Fifosize(%d) > available RAM(%d)\n",
- last_fifo_depth, dwc->tx_fifo_size);
- return -ENOMEM;
- }
-
- dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
-
+ /* Don't resize already resized IN endpoint */
+ if (dep->fifo_depth) {
+ dev_dbg(dwc->dev, "%s fifo_depth:%d is already set\n",
+ dep->endpoint.name, dep->fifo_depth);
+ return 0;
}
+ mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+ /* MDWIDTH is represented in bits, we need it in bytes */
+ mdwidth >>= 3;
+
+ if (dep->endpoint.ep_type == EP_TYPE_GSI || dep->endpoint.endless)
+ mult = 3;
+
+ if (((dep->endpoint.maxburst > 1) &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc))
+ || usb_endpoint_xfer_isoc(dep->endpoint.desc))
+ mult = 3;
+
+ tmp = ((max_packet + mdwidth) * mult) + mdwidth;
+ fifo_size = DIV_ROUND_UP(tmp, mdwidth);
+ dep->fifo_depth = fifo_size;
+ fifo_size |= (dwc->last_fifo_depth << 16);
+ dwc->last_fifo_depth += (fifo_size & 0xffff);
+
+ dev_dbg(dwc->dev, "%s ep_num:%d last_fifo_depth:%04x fifo_depth:%d\n",
+ dep->endpoint.name, dep->endpoint.ep_num, dwc->last_fifo_depth,
+ dep->fifo_depth);
+
+ dbg_event(0xFF, "resize_fifo", dep->number);
+ dbg_event(0xFF, "fifo_depth", dep->fifo_depth);
+ /* Check fifo size allocation doesn't exceed available RAM size. */
+ if (dwc->tx_fifo_size &&
+ ((dwc->last_fifo_depth * mdwidth) >= dwc->tx_fifo_size)) {
+ dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
+ (dwc->last_fifo_depth * mdwidth), dwc->tx_fifo_size,
+ dep->endpoint.name, fifo_size);
+ dwc->last_fifo_depth -= (fifo_size & 0xffff);
+ dep->fifo_depth = 0;
+ WARN_ON(1);
+ return -ENOMEM;
+ }
+
+ dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->endpoint.ep_num),
+ fifo_size);
return 0;
}
@@ -691,6 +667,17 @@
dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
if (!(dep->flags & DWC3_EP_ENABLED)) {
+ dep->endpoint.desc = desc;
+ dep->comp_desc = comp_desc;
+ dep->type = usb_endpoint_type(desc);
+ ret = dwc3_gadget_resize_tx_fifos(dwc, dep);
+ if (ret) {
+ dep->endpoint.desc = NULL;
+ dep->comp_desc = NULL;
+ dep->type = 0;
+ return ret;
+ }
+
ret = dwc3_gadget_start_config(dwc, dep);
if (ret) {
dev_err(dwc->dev, "start_config() failed for %s\n",
@@ -710,9 +697,6 @@
struct dwc3_trb *trb_st_hw;
struct dwc3_trb *trb_link;
- dep->endpoint.desc = desc;
- dep->comp_desc = comp_desc;
- dep->type = usb_endpoint_type(desc);
dep->flags |= DWC3_EP_ENABLED;
reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
@@ -2987,9 +2971,6 @@
dwc3_stop_active_transfers(dwc);
dwc3_clear_stall_all_ep(dwc);
- /* bus reset issued due to missing status stage of a control transfer */
- dwc->resize_fifos = 0;
-
/* Reset device address to zero */
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
reg &= ~(DWC3_DCFG_DEVADDR_MASK);
diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c
index 308a49c..4df2dc6 100644
--- a/drivers/usb/gadget/function/f_gsi.c
+++ b/drivers/usb/gadget/function/f_gsi.c
@@ -40,6 +40,7 @@
static struct workqueue_struct *ipa_usb_wq;
+static void gsi_rndis_ipa_reset_trigger(struct gsi_data_port *d_port);
static void ipa_disconnect_handler(struct gsi_data_port *d_port);
static int gsi_ctrl_send_notification(struct f_gsi *gsi);
static int gsi_alloc_trb_buffer(struct f_gsi *gsi);
@@ -472,6 +473,7 @@
usb_gsi_ep_op(d_port->in_ep, (void *)&block_db,
GSI_EP_OP_SET_CLR_BLOCK_DBL);
+ /* GSI channel DBL address for USB IN endpoint */
dbl_register_addr = gsi->d_port.in_db_reg_phs_addr_msb;
dbl_register_addr = dbl_register_addr << 32;
dbl_register_addr =
@@ -481,11 +483,18 @@
req.buf_base_addr = &dbl_register_addr;
req.num_bufs = gsi->d_port.in_request.num_bufs;
- usb_gsi_ep_op(gsi->d_port.in_ep, &req, GSI_EP_OP_RING_IN_DB);
+ usb_gsi_ep_op(gsi->d_port.in_ep, &req, GSI_EP_OP_RING_DB);
if (gsi->d_port.out_ep) {
- usb_gsi_ep_op(gsi->d_port.out_ep, &gsi->d_port.out_request,
- GSI_EP_OP_UPDATEXFER);
+ /* GSI channel DBL address for USB OUT endpoint */
+ dbl_register_addr = gsi->d_port.out_db_reg_phs_addr_msb;
+ dbl_register_addr = dbl_register_addr << 32;
+ dbl_register_addr = dbl_register_addr |
+ gsi->d_port.out_db_reg_phs_addr_lsb;
+ /* use temp request to pass 64 bit dbl reg addr and num_bufs */
+ req.buf_base_addr = &dbl_register_addr;
+ req.num_bufs = gsi->d_port.out_request.num_bufs;
+ usb_gsi_ep_op(gsi->d_port.out_ep, &req, GSI_EP_OP_RING_DB);
}
}
@@ -503,14 +512,11 @@
*/
usb_gsi_ep_op(d_port->in_ep, (void *)&block_db,
GSI_EP_OP_SET_CLR_BLOCK_DBL);
- gsi->in_ep_desc_backup = gsi->d_port.in_ep->desc;
usb_gsi_ep_op(gsi->d_port.in_ep, NULL, GSI_EP_OP_DISABLE);
}
- if (gsi->d_port.out_ep) {
- gsi->out_ep_desc_backup = gsi->d_port.out_ep->desc;
+ if (gsi->d_port.out_ep)
usb_gsi_ep_op(gsi->d_port.out_ep, NULL, GSI_EP_OP_DISABLE);
- }
gsi->d_port.net_ready_trigger = false;
}
@@ -616,6 +622,7 @@
struct device *dev;
struct device *gad_dev;
struct f_gsi *gsi = d_port_to_gsi(d_port);
+ bool block_db;
event = read_event(d_port);
@@ -676,28 +683,6 @@
break;
}
- /*
- * Update desc and reconfigure USB GSI OUT and IN
- * endpoint for RNDIS Adaptor enable case.
- */
- if (d_port->out_ep && !d_port->out_ep->desc &&
- gsi->out_ep_desc_backup) {
- d_port->out_ep->desc = gsi->out_ep_desc_backup;
- d_port->out_ep->ep_intr_num = 1;
- log_event_dbg("%s: OUT ep_op_config", __func__);
- usb_gsi_ep_op(d_port->out_ep,
- &d_port->out_request, GSI_EP_OP_CONFIG);
- }
-
- if (d_port->in_ep && !d_port->in_ep->desc &&
- gsi->in_ep_desc_backup) {
- d_port->in_ep->desc = gsi->in_ep_desc_backup;
- d_port->in_ep->ep_intr_num = 2;
- log_event_dbg("%s: IN ep_op_config", __func__);
- usb_gsi_ep_op(d_port->in_ep,
- &d_port->in_request, GSI_EP_OP_CONFIG);
- }
-
ipa_connect_channels(d_port);
ipa_data_path_enable(d_port);
d_port->sm_state = STATE_CONNECTED;
@@ -759,7 +744,15 @@
if (event == EVT_HOST_NRDY) {
log_event_dbg("%s: ST_CON_HOST_NRDY\n",
__func__);
- ipa_disconnect_handler(d_port);
+ block_db = true;
+ /* stop USB ringing doorbell to GSI(OUT_EP) */
+ usb_gsi_ep_op(d_port->in_ep, (void *)&block_db,
+ GSI_EP_OP_SET_CLR_BLOCK_DBL);
+ gsi_rndis_ipa_reset_trigger(d_port);
+ usb_gsi_ep_op(d_port->in_ep, NULL,
+ GSI_EP_OP_ENDXFER);
+ usb_gsi_ep_op(d_port->out_ep, NULL,
+ GSI_EP_OP_ENDXFER);
}
ipa_disconnect_work_handler(d_port);
@@ -1385,6 +1378,17 @@
rndis_signal_connect(gsi->params);
}
+static void gsi_rndis_ipa_reset_trigger(struct gsi_data_port *d_port)
+{
+ unsigned long flags;
+ struct f_gsi *gsi = d_port_to_gsi(d_port);
+
+ log_event_dbg("%s: setting net_ready_trigger\n", __func__);
+ spin_lock_irqsave(&d_port->lock, flags);
+ d_port->net_ready_trigger = false;
+ spin_unlock_irqrestore(&d_port->lock, flags);
+}
+
void gsi_rndis_flow_ctrl_enable(bool enable, struct rndis_params *param)
{
struct f_gsi *gsi = param->v;
@@ -2618,7 +2622,7 @@
info.in_req_num_buf = num_in_bufs;
gsi->d_port.out_aggr_size = GSI_ECM_AGGR_SIZE;
info.out_req_buf_len = GSI_OUT_ECM_BUF_LEN;
- info.out_req_num_buf = GSI_ECM_NUM_OUT_BUFFERS;
+ info.out_req_num_buf = num_out_bufs;
info.notify_buf_len = GSI_CTRL_NOTIFY_BUFF_LEN;
/* export host's Ethernet address in CDC format */
diff --git a/drivers/usb/gadget/function/f_gsi.h b/drivers/usb/gadget/function/f_gsi.h
index 43aae8f..0fe3665 100644
--- a/drivers/usb/gadget/function/f_gsi.h
+++ b/drivers/usb/gadget/function/f_gsi.h
@@ -37,8 +37,7 @@
#define GSI_NUM_IN_BUFFERS 15
#define GSI_IN_BUFF_SIZE 2048
-#define GSI_NUM_OUT_BUFFERS 15
-#define GSI_ECM_NUM_OUT_BUFFERS 31
+#define GSI_NUM_OUT_BUFFERS 14
#define GSI_OUT_AGGR_SIZE 24576
#define GSI_IN_RNDIS_AGGR_SIZE 9216
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index d2c4876..b1b74ff 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -245,4 +245,13 @@
Synopsys DWC3 USB IPs on MSM SOCs. This driver expects to configure the
PHY with a dedicated register I/O memory region.
+config MSM_HSUSB_PHY
+ tristate "MSM HSUSB PHY Driver"
+ depends on ARCH_QCOM
+ select USB_PHY
+ help
+ Enable this to support the HSUSB PHY on MSM chips. This driver supports
+ the high-speed PHY which is usually paired with either the ChipIdea or
+ Synopsys DWC3 USB IPs on MSM SOCs. This driver expects to configure the
+ PHY with a dedicated register I/O memory region.
endmenu
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index ce98866..5b748a6 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -30,3 +30,4 @@
obj-$(CONFIG_KEYSTONE_USB_PHY) += phy-keystone.o
obj-$(CONFIG_USB_MSM_SSPHY_QMP) += phy-msm-ssusb-qmp.o
obj-$(CONFIG_MSM_QUSB_PHY) += phy-msm-qusb.o phy-msm-qusb-v2.o
+obj-$(CONFIG_MSM_HSUSB_PHY) += phy-msm-snps-hs.o
diff --git a/drivers/usb/phy/phy-msm-qusb-v2.c b/drivers/usb/phy/phy-msm-qusb-v2.c
index 4f0a455..1210188e 100644
--- a/drivers/usb/phy/phy-msm-qusb-v2.c
+++ b/drivers/usb/phy/phy-msm-qusb-v2.c
@@ -48,7 +48,6 @@
#define DPSE_INTERRUPT BIT(0)
#define QUSB2PHY_PORT_TUNE1 0x23c
-#define QUSB2PHY_TEST1 0x24C
#define QUSB2PHY_PLL_CORE_INPUT_OVERRIDE 0x0a8
#define CORE_PLL_RATE BIT(0)
@@ -94,6 +93,7 @@
int *qusb_phy_host_init_seq;
u32 tune_val;
+ u32 phy_auto_resume_offset;
int efuse_bit_pos;
int efuse_num_of_bits;
@@ -551,14 +551,15 @@
CORE_RESET | CORE_RESET_MUX,
qphy->base + QUSB2PHY_PLL_CORE_INPUT_OVERRIDE);
- /* enable phy auto-resume */
- writel_relaxed(0x91,
- qphy->base + QUSB2PHY_TEST1);
- /* flush the previous write before next write */
- wmb();
- writel_relaxed(0x90,
- qphy->base + QUSB2PHY_TEST1);
-
+ if (qphy->phy_auto_resume_offset) {
+ /* enable phy auto-resume */
+ writel_relaxed(0x91,
+ qphy->base + qphy->phy_auto_resume_offset);
+ /* flush the previous write before next write */
+ wmb();
+ writel_relaxed(0x90,
+ qphy->base + qphy->phy_auto_resume_offset);
+ }
dev_dbg(phy->dev, "%s: intr_mask = %x\n",
__func__, intr_mask);
@@ -916,6 +917,12 @@
return ret;
}
+ ret = of_property_read_u32(dev->of_node, "qcom,phy-auto-resume-offset",
+ &qphy->phy_auto_resume_offset);
+ if (ret)
+ dev_dbg(dev, "error reading qcom,phy-auto-resume-offset %d\n",
+ ret);
+
qphy->vdd = devm_regulator_get(dev, "vdd");
if (IS_ERR(qphy->vdd)) {
dev_err(dev, "unable to get vdd supply\n");
diff --git a/drivers/usb/phy/phy-msm-snps-hs.c b/drivers/usb/phy/phy-msm-snps-hs.c
new file mode 100644
index 0000000..2d18faf
--- /dev/null
+++ b/drivers/usb/phy/phy-msm-snps-hs.c
@@ -0,0 +1,646 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/usb/phy.h>
+#include <linux/reset.h>
+
+#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
+#define SLEEPM BIT(0)
+
+#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
+#define ATERESET BIT(0)
+#define POR BIT(1)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
+#define VATESTENB_MASK (0x3 << 0)
+#define RETENABLEN BIT(3)
+#define FSEL_MASK (0x7 << 4)
+#define FSEL_DEFAULT (0x3 << 4)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
+#define VBUSVLDEXTSEL0 BIT(4)
+#define PLLBTUNE BIT(5)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
+#define VREGBYPASS BIT(0)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
+#define VBUSVLDEXT0 BIT(0)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
+#define USB2_SUSPEND_N BIT(2)
+#define USB2_SUSPEND_N_SEL BIT(3)
+
+#define USB2_PHY_USB_PHY_HS_PHY_TEST0 (0x80)
+#define TESTDATAIN_MASK (0xff << 0)
+
+#define USB2_PHY_USB_PHY_HS_PHY_TEST1 (0x84)
+#define TESTDATAOUTSEL BIT(4)
+#define TOGGLE_2WR BIT(6)
+
+#define USB2_PHY_USB_PHY_CFG0 (0x94)
+#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
+
+#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
+#define REFCLK_SEL_MASK (0x3 << 0)
+#define REFCLK_SEL_DEFAULT (0x2 << 0)
+
+#define USB_HSPHY_3P3_VOL_MIN 3050000 /* uV */
+#define USB_HSPHY_3P3_VOL_MAX 3300000 /* uV */
+#define USB_HSPHY_3P3_HPM_LOAD 16000 /* uA */
+#define USB_HSPHY_3P3_VOL_FSHOST 3150000 /* uV */
+
+#define USB_HSPHY_1P8_VOL_MIN 1800000 /* uV */
+#define USB_HSPHY_1P8_VOL_MAX 1800000 /* uV */
+#define USB_HSPHY_1P8_HPM_LOAD 19000 /* uA */
+
+struct msm_hsphy {
+ struct usb_phy phy;
+ void __iomem *base;
+
+ struct clk *ref_clk_src;
+ struct clk *cfg_ahb_clk;
+ struct reset_control *phy_reset;
+
+ struct regulator *vdd;
+ struct regulator *vdda33;
+ struct regulator *vdda18;
+ int vdd_levels[3]; /* none, low, high */
+
+ bool clocks_enabled;
+ bool power_enabled;
+ bool suspended;
+ bool cable_connected;
+
+ /* emulation targets specific */
+ void __iomem *emu_phy_base;
+ int *emu_init_seq;
+ int emu_init_seq_len;
+ int *emu_dcm_reset_seq;
+ int emu_dcm_reset_seq_len;
+};
+
+static void msm_hsphy_enable_clocks(struct msm_hsphy *phy, bool on)
+{
+ dev_dbg(phy->phy.dev, "%s(): clocks_enabled:%d on:%d\n",
+ __func__, phy->clocks_enabled, on);
+
+ if (!phy->clocks_enabled && on) {
+ clk_prepare_enable(phy->ref_clk_src);
+
+ if (phy->cfg_ahb_clk)
+ clk_prepare_enable(phy->cfg_ahb_clk);
+
+ phy->clocks_enabled = true;
+ }
+
+ if (phy->clocks_enabled && !on) {
+ if (phy->cfg_ahb_clk)
+ clk_disable_unprepare(phy->cfg_ahb_clk);
+
+ clk_disable_unprepare(phy->ref_clk_src);
+ phy->clocks_enabled = false;
+ }
+
+}
+static int msm_hsphy_config_vdd(struct msm_hsphy *phy, int high)
+{
+ int min, ret;
+
+ min = high ? 1 : 0; /* low or none? */
+ ret = regulator_set_voltage(phy->vdd, phy->vdd_levels[min],
+ phy->vdd_levels[2]);
+ if (ret) {
+ dev_err(phy->phy.dev, "unable to set voltage for hsusb vdd\n");
+ return ret;
+ }
+
+ dev_dbg(phy->phy.dev, "%s: min_vol:%d max_vol:%d\n", __func__,
+ phy->vdd_levels[min], phy->vdd_levels[2]);
+
+ return ret;
+}
+
+static int msm_hsphy_enable_power(struct msm_hsphy *phy, bool on)
+{
+ int ret = 0;
+
+ dev_dbg(phy->phy.dev, "%s turn %s regulators. power_enabled:%d\n",
+ __func__, on ? "on" : "off", phy->power_enabled);
+
+ if (phy->power_enabled == on) {
+ dev_dbg(phy->phy.dev, "PHYs' regulators are already ON.\n");
+ return 0;
+ }
+
+ if (!on)
+ goto disable_vdda33;
+
+ ret = msm_hsphy_config_vdd(phy, true);
+ if (ret) {
+ dev_err(phy->phy.dev, "Unable to config VDD:%d\n",
+ ret);
+ goto err_vdd;
+ }
+
+ ret = regulator_enable(phy->vdd);
+ if (ret) {
+ dev_err(phy->phy.dev, "Unable to enable VDD\n");
+ goto unconfig_vdd;
+ }
+
+ ret = regulator_set_load(phy->vdda18, USB_HSPHY_1P8_HPM_LOAD);
+ if (ret < 0) {
+ dev_err(phy->phy.dev, "Unable to set HPM of vdda18:%d\n", ret);
+ goto disable_vdd;
+ }
+
+ ret = regulator_set_voltage(phy->vdda18, USB_HSPHY_1P8_VOL_MIN,
+ USB_HSPHY_1P8_VOL_MAX);
+ if (ret) {
+ dev_err(phy->phy.dev,
+ "Unable to set voltage for vdda18:%d\n", ret);
+ goto put_vdda18_lpm;
+ }
+
+ ret = regulator_enable(phy->vdda18);
+ if (ret) {
+ dev_err(phy->phy.dev, "Unable to enable vdda18:%d\n", ret);
+ goto unset_vdda18;
+ }
+
+ ret = regulator_set_load(phy->vdda33, USB_HSPHY_3P3_HPM_LOAD);
+ if (ret < 0) {
+ dev_err(phy->phy.dev, "Unable to set HPM of vdda33:%d\n", ret);
+ goto disable_vdda18;
+ }
+
+ ret = regulator_set_voltage(phy->vdda33, USB_HSPHY_3P3_VOL_MIN,
+ USB_HSPHY_3P3_VOL_MAX);
+ if (ret) {
+ dev_err(phy->phy.dev,
+ "Unable to set voltage for vdda33:%d\n", ret);
+ goto put_vdda33_lpm;
+ }
+
+ ret = regulator_enable(phy->vdda33);
+ if (ret) {
+ dev_err(phy->phy.dev, "Unable to enable vdda33:%d\n", ret);
+ goto unset_vdd33;
+ }
+
+ phy->power_enabled = true;
+
+ pr_debug("%s(): HSUSB PHY's regulators are turned ON.\n", __func__);
+ return ret;
+
+disable_vdda33:
+ ret = regulator_disable(phy->vdda33);
+ if (ret)
+ dev_err(phy->phy.dev, "Unable to disable vdda33:%d\n", ret);
+
+unset_vdd33:
+ ret = regulator_set_voltage(phy->vdda33, 0, USB_HSPHY_3P3_VOL_MAX);
+ if (ret)
+ dev_err(phy->phy.dev,
+ "Unable to set (0) voltage for vdda33:%d\n", ret);
+
+put_vdda33_lpm:
+ ret = regulator_set_load(phy->vdda33, 0);
+ if (ret < 0)
+ dev_err(phy->phy.dev, "Unable to set (0) HPM of vdda33\n");
+
+disable_vdda18:
+ ret = regulator_disable(phy->vdda18);
+ if (ret)
+ dev_err(phy->phy.dev, "Unable to disable vdda18:%d\n", ret);
+
+unset_vdda18:
+ ret = regulator_set_voltage(phy->vdda18, 0, USB_HSPHY_1P8_VOL_MAX);
+ if (ret)
+ dev_err(phy->phy.dev,
+ "Unable to set (0) voltage for vdda18:%d\n", ret);
+
+put_vdda18_lpm:
+ ret = regulator_set_load(phy->vdda18, 0);
+ if (ret < 0)
+ dev_err(phy->phy.dev, "Unable to set LPM of vdda18\n");
+
+disable_vdd:
+ if (ret)
+ dev_err(phy->phy.dev, "Unable to disable vdd:%d\n",
+ ret);
+
+unconfig_vdd:
+ ret = msm_hsphy_config_vdd(phy, false);
+ if (ret)
+ dev_err(phy->phy.dev, "Unable unconfig VDD:%d\n",
+ ret);
+err_vdd:
+ phy->power_enabled = false;
+ dev_dbg(phy->phy.dev, "HSUSB PHY's regulators are turned OFF.\n");
+ return ret;
+}
+
+static void msm_usb_write_readback(void __iomem *base, u32 offset,
+ const u32 mask, u32 val)
+{
+ u32 write_val, tmp = readl_relaxed(base + offset);
+
+ tmp &= ~mask; /* retain other bits */
+ write_val = tmp | val;
+
+ writel_relaxed(write_val, base + offset);
+
+ /* Read back to see if val was written */
+ tmp = readl_relaxed(base + offset);
+ tmp &= mask; /* clear other bits */
+
+ if (tmp != val)
+ pr_err("%s: write: %x to QSCRATCH: %x FAILED\n",
+ __func__, val, offset);
+}
+
+static void msm_hsphy_reset(struct msm_hsphy *phy)
+{
+ int ret;
+
+ ret = reset_control_assert(phy->phy_reset);
+ if (ret)
+ dev_err(phy->phy.dev, "%s: phy_reset assert failed\n",
+ __func__);
+ usleep_range(100, 150);
+
+ ret = reset_control_deassert(phy->phy_reset);
+ if (ret)
+ dev_err(phy->phy.dev, "%s: phy_reset deassert failed\n",
+ __func__);
+}
+
+static void hsusb_phy_write_seq(void __iomem *base, u32 *seq, int cnt,
+ unsigned long delay)
+{
+ int i;
+
+ pr_debug("Seq count:%d\n", cnt);
+ for (i = 0; i < cnt; i = i+2) {
+ pr_debug("write 0x%02x to 0x%02x\n", seq[i], seq[i+1]);
+ writel_relaxed(seq[i], base + seq[i+1]);
+ if (delay)
+ usleep_range(delay, (delay + 2000));
+ }
+}
+
+static int msm_hsphy_emu_init(struct usb_phy *uphy)
+{
+ struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
+ int ret;
+
+ dev_dbg(uphy->dev, "%s\n", __func__);
+
+ ret = msm_hsphy_enable_power(phy, true);
+ if (ret)
+ return ret;
+
+ msm_hsphy_enable_clocks(phy, true);
+ msm_hsphy_reset(phy);
+
+ if (phy->emu_init_seq) {
+ hsusb_phy_write_seq(phy->base,
+ phy->emu_init_seq,
+ phy->emu_init_seq_len, 10000);
+
+ /* Wait for 5ms as per QUSB2 RUMI sequence */
+ usleep_range(5000, 7000);
+
+ if (phy->emu_dcm_reset_seq)
+ hsusb_phy_write_seq(phy->emu_phy_base,
+ phy->emu_dcm_reset_seq,
+ phy->emu_dcm_reset_seq_len, 10000);
+ }
+
+ return 0;
+}
+
+static int msm_hsphy_init(struct usb_phy *uphy)
+{
+ struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
+ int ret;
+
+ dev_dbg(uphy->dev, "%s\n", __func__);
+
+ ret = msm_hsphy_enable_power(phy, true);
+ if (ret)
+ return ret;
+
+ msm_hsphy_enable_clocks(phy, true);
+ msm_hsphy_reset(phy);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_CFG0,
+ UTMI_PHY_CMN_CTRL_OVERRIDE_EN, UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
+ POR, POR);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
+ FSEL_MASK, 0);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
+ PLLBTUNE, PLLBTUNE);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,
+ REFCLK_SEL_MASK, REFCLK_SEL_DEFAULT);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
+ VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
+ VBUSVLDEXT0, VBUSVLDEXT0);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
+ VREGBYPASS, VREGBYPASS);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
+ ATERESET, ATERESET);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_TEST1,
+ TESTDATAOUTSEL, TESTDATAOUTSEL);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_TEST1,
+ TOGGLE_2WR, TOGGLE_2WR);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
+ VATESTENB_MASK, 0);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_TEST0,
+ TESTDATAIN_MASK, 0);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
+ USB2_SUSPEND_N_SEL, USB2_SUSPEND_N_SEL);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
+ USB2_SUSPEND_N, USB2_SUSPEND_N);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,
+ SLEEPM, SLEEPM);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
+ POR, 0);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
+ USB2_SUSPEND_N_SEL, 0);
+
+ msm_usb_write_readback(phy->base, USB2_PHY_USB_PHY_CFG0,
+ UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
+
+ return 0;
+}
+
+static int msm_hsphy_set_suspend(struct usb_phy *uphy, int suspend)
+{
+ return 0;
+}
+
+static int msm_hsphy_notify_connect(struct usb_phy *uphy,
+ enum usb_device_speed speed)
+{
+ struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
+
+ phy->cable_connected = true;
+
+ return 0;
+}
+
+static int msm_hsphy_notify_disconnect(struct usb_phy *uphy,
+ enum usb_device_speed speed)
+{
+ struct msm_hsphy *phy = container_of(uphy, struct msm_hsphy, phy);
+
+ phy->cable_connected = false;
+
+ return 0;
+}
+
+static int msm_hsphy_probe(struct platform_device *pdev)
+{
+ struct msm_hsphy *phy;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ int ret = 0, size = 0;
+
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy) {
+ ret = -ENOMEM;
+ goto err_ret;
+ }
+
+ phy->phy.dev = dev;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "hsusb_phy_base");
+ if (!res) {
+ dev_err(dev, "missing memory base resource\n");
+ ret = -ENODEV;
+ goto err_ret;
+ }
+
+ phy->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(phy->base)) {
+ dev_err(dev, "ioremap failed\n");
+ ret = -ENODEV;
+ goto err_ret;
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "emu_phy_base");
+ if (res) {
+ phy->emu_phy_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(phy->emu_phy_base)) {
+ dev_dbg(dev, "couldn't ioremap emu_phy_base\n");
+ phy->emu_phy_base = NULL;
+ }
+ }
+
+ /* ref_clk_src is needed irrespective of SE_CLK or DIFF_CLK usage */
+ phy->ref_clk_src = devm_clk_get(dev, "ref_clk_src");
+ if (IS_ERR(phy->ref_clk_src)) {
+ dev_dbg(dev, "clk get failed for ref_clk_src\n");
+ ret = PTR_ERR(phy->ref_clk_src);
+ return ret;
+ }
+
+ if (of_property_match_string(pdev->dev.of_node,
+ "clock-names", "cfg_ahb_clk") >= 0) {
+ phy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk");
+ if (IS_ERR(phy->cfg_ahb_clk)) {
+ ret = PTR_ERR(phy->cfg_ahb_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev,
+ "clk get failed for cfg_ahb_clk ret %d\n", ret);
+ return ret;
+ }
+ }
+
+ phy->phy_reset = devm_reset_control_get(dev, "phy_reset");
+ if (IS_ERR(phy->phy_reset))
+ return PTR_ERR(phy->phy_reset);
+
+ of_get_property(dev->of_node, "qcom,emu-init-seq", &size);
+ if (size) {
+ phy->emu_init_seq = devm_kzalloc(dev,
+ size, GFP_KERNEL);
+ if (phy->emu_init_seq) {
+ phy->emu_init_seq_len =
+ (size / sizeof(*phy->emu_init_seq));
+ if (phy->emu_init_seq_len % 2) {
+ dev_err(dev, "invalid emu_init_seq_len\n");
+ return -EINVAL;
+ }
+
+ of_property_read_u32_array(dev->of_node,
+ "qcom,emu-init-seq",
+ phy->emu_init_seq,
+ phy->emu_init_seq_len);
+ } else {
+ dev_dbg(dev,
+ "error allocating memory for emu_init_seq\n");
+ }
+ }
+
+ size = 0;
+ of_get_property(dev->of_node, "qcom,emu-dcm-reset-seq", &size);
+ if (size) {
+ phy->emu_dcm_reset_seq = devm_kzalloc(dev,
+ size, GFP_KERNEL);
+ if (phy->emu_dcm_reset_seq) {
+ phy->emu_dcm_reset_seq_len =
+ (size / sizeof(*phy->emu_dcm_reset_seq));
+ if (phy->emu_dcm_reset_seq_len % 2) {
+ dev_err(dev, "invalid emu_dcm_reset_seq_len\n");
+ return -EINVAL;
+ }
+
+ of_property_read_u32_array(dev->of_node,
+ "qcom,emu-dcm-reset-seq",
+ phy->emu_dcm_reset_seq,
+ phy->emu_dcm_reset_seq_len);
+ } else {
+ dev_dbg(dev,
+ "error allocating memory for emu_dcm_reset_seq\n");
+ }
+ }
+
+ ret = of_property_read_u32_array(dev->of_node, "qcom,vdd-voltage-level",
+ (u32 *) phy->vdd_levels,
+ ARRAY_SIZE(phy->vdd_levels));
+ if (ret) {
+ dev_err(dev, "error reading qcom,vdd-voltage-level property\n");
+ goto err_ret;
+ }
+
+
+ phy->vdd = devm_regulator_get(dev, "vdd");
+ if (IS_ERR(phy->vdd)) {
+ dev_err(dev, "unable to get vdd supply\n");
+ ret = PTR_ERR(phy->vdd);
+ goto err_ret;
+ }
+
+ phy->vdda33 = devm_regulator_get(dev, "vdda33");
+ if (IS_ERR(phy->vdda33)) {
+ dev_err(dev, "unable to get vdda33 supply\n");
+ ret = PTR_ERR(phy->vdda33);
+ goto err_ret;
+ }
+
+ phy->vdda18 = devm_regulator_get(dev, "vdda18");
+ if (IS_ERR(phy->vdda18)) {
+ dev_err(dev, "unable to get vdda18 supply\n");
+ ret = PTR_ERR(phy->vdda18);
+ goto err_ret;
+ }
+
+ platform_set_drvdata(pdev, phy);
+
+ if (phy->emu_init_seq)
+ phy->phy.init = msm_hsphy_emu_init;
+ else
+ phy->phy.init = msm_hsphy_init;
+ phy->phy.set_suspend = msm_hsphy_set_suspend;
+ phy->phy.notify_connect = msm_hsphy_notify_connect;
+ phy->phy.notify_disconnect = msm_hsphy_notify_disconnect;
+ phy->phy.type = USB_PHY_TYPE_USB2;
+
+ ret = usb_add_phy_dev(&phy->phy);
+ if (ret)
+ return ret;
+
+ return 0;
+
+err_ret:
+ return ret;
+}
+
+static int msm_hsphy_remove(struct platform_device *pdev)
+{
+ struct msm_hsphy *phy = platform_get_drvdata(pdev);
+
+ if (!phy)
+ return 0;
+
+ usb_remove_phy(&phy->phy);
+ clk_disable_unprepare(phy->ref_clk_src);
+
+ msm_hsphy_enable_clocks(phy, false);
+ msm_hsphy_enable_power(phy, false);
+
+ kfree(phy);
+
+ return 0;
+}
+
+static const struct of_device_id msm_usb_id_table[] = {
+ {
+ .compatible = "qcom,usb-hsphy-snps-femto",
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, msm_usb_id_table);
+
+static struct platform_driver msm_hsphy_driver = {
+ .probe = msm_hsphy_probe,
+ .remove = msm_hsphy_remove,
+ .driver = {
+ .name = "msm-usb-hsphy",
+ .of_match_table = of_match_ptr(msm_usb_id_table),
+ },
+};
+
+module_platform_driver(msm_hsphy_driver);
+
+MODULE_DESCRIPTION("MSM USB HS PHY driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h
index e16b69a..7218261 100644
--- a/include/dt-bindings/clock/qcom,camcc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,camcc-sdm845.h
@@ -102,26 +102,15 @@
#define CAM_CC_SOC_AHB_CLK 85
#define CAM_CC_SYS_TMR_CLK 86
-#define TITAN_CAM_CC_BPS_BCR 0
-#define TITAN_CAM_CC_CAMNOC_BCR 1
-#define TITAN_CAM_CC_CCI_BCR 2
-#define TITAN_CAM_CC_CPAS_BCR 3
-#define TITAN_CAM_CC_CSI0PHY_BCR 4
-#define TITAN_CAM_CC_CSI1PHY_BCR 5
-#define TITAN_CAM_CC_CSI2PHY_BCR 6
-#define TITAN_CAM_CC_FD_BCR 7
-#define TITAN_CAM_CC_ICP_BCR 8
-#define TITAN_CAM_CC_IFE_0_BCR 9
-#define TITAN_CAM_CC_IFE_1_BCR 10
-#define TITAN_CAM_CC_IFE_LITE_BCR 11
-#define TITAN_CAM_CC_IPE_0_BCR 12
-#define TITAN_CAM_CC_IPE_1_BCR 13
-#define TITAN_CAM_CC_JPEG_BCR 14
-#define TITAN_CAM_CC_LRME_BCR 15
-#define TITAN_CAM_CC_MCLK0_BCR 16
-#define TITAN_CAM_CC_MCLK1_BCR 17
-#define TITAN_CAM_CC_MCLK2_BCR 18
-#define TITAN_CAM_CC_MCLK3_BCR 19
-#define TITAN_CAM_CC_TITAN_TOP_BCR 20
+#define TITAN_CAM_CC_CCI_BCR 0
+#define TITAN_CAM_CC_CPAS_BCR 1
+#define TITAN_CAM_CC_CSI0PHY_BCR 2
+#define TITAN_CAM_CC_CSI1PHY_BCR 3
+#define TITAN_CAM_CC_CSI2PHY_BCR 4
+#define TITAN_CAM_CC_MCLK0_BCR 5
+#define TITAN_CAM_CC_MCLK1_BCR 6
+#define TITAN_CAM_CC_MCLK2_BCR 7
+#define TITAN_CAM_CC_MCLK3_BCR 8
+#define TITAN_CAM_CC_TITAN_TOP_BCR 9
#endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
index 91ea077..42bb59f 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
@@ -56,9 +56,6 @@
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 39
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 40
-#define DISP_CC_MDSS_CORE_BCR 0
-#define DISP_CC_MDSS_GCC_CLOCKS_BCR 1
-#define DISP_CC_MDSS_RSCC_BCR 2
-#define DISP_CC_MDSS_SPDM_BCR 3
+#define DISP_CC_MDSS_RSCC_BCR 0
#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
index f6f4bc3..678a885 100644
--- a/include/dt-bindings/clock/qcom,gcc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -204,34 +204,33 @@
/* GCC reset clocks */
-#define GCC_GPU_BCR 0
-#define GCC_MMSS_BCR 1
-#define GCC_PCIE_0_BCR 2
-#define GCC_PCIE_1_BCR 3
-#define GCC_PCIE_PHY_BCR 4
-#define GCC_PDM_BCR 5
-#define GCC_PRNG_BCR 6
-#define GCC_QUPV3_WRAPPER_0_BCR 7
-#define GCC_QUPV3_WRAPPER_1_BCR 8
-#define GCC_QUSB2PHY_PRIM_BCR 9
-#define GCC_QUSB2PHY_SEC_BCR 10
-#define GCC_SDCC2_BCR 11
-#define GCC_SDCC4_BCR 12
-#define GCC_TSIF_BCR 13
-#define GCC_UFS_CARD_BCR 14
-#define GCC_UFS_PHY_BCR 15
-#define GCC_USB30_PRIM_BCR 16
-#define GCC_USB30_SEC_BCR 17
-#define GCC_USB3_PHY_PRIM_BCR 18
-#define GCC_USB3PHY_PHY_PRIM_BCR 19
-#define GCC_USB3_DP_PHY_PRIM_BCR 20
-#define GCC_USB3_PHY_SEC_BCR 21
-#define GCC_USB3PHY_PHY_SEC_BCR 22
-#define GCC_USB3_DP_PHY_SEC_BCR 23
-#define GCC_USB_PHY_CFG_AHB2PHY_BCR 24
-#define GCC_PCIE_0_PHY_BCR 25
-#define GCC_PCIE_1_PHY_BCR 26
-#define GCC_SDCC1_BCR 27
+#define GCC_MMSS_BCR 0
+#define GCC_PCIE_0_BCR 1
+#define GCC_PCIE_1_BCR 2
+#define GCC_PCIE_PHY_BCR 3
+#define GCC_PDM_BCR 4
+#define GCC_PRNG_BCR 5
+#define GCC_QUPV3_WRAPPER_0_BCR 6
+#define GCC_QUPV3_WRAPPER_1_BCR 7
+#define GCC_QUSB2PHY_PRIM_BCR 8
+#define GCC_QUSB2PHY_SEC_BCR 9
+#define GCC_SDCC2_BCR 10
+#define GCC_SDCC4_BCR 11
+#define GCC_TSIF_BCR 12
+#define GCC_UFS_CARD_BCR 13
+#define GCC_UFS_PHY_BCR 14
+#define GCC_USB30_PRIM_BCR 15
+#define GCC_USB30_SEC_BCR 16
+#define GCC_USB3_PHY_PRIM_BCR 17
+#define GCC_USB3PHY_PHY_PRIM_BCR 18
+#define GCC_USB3_DP_PHY_PRIM_BCR 19
+#define GCC_USB3_PHY_SEC_BCR 20
+#define GCC_USB3PHY_PHY_SEC_BCR 21
+#define GCC_USB3_DP_PHY_SEC_BCR 22
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
+#define GCC_PCIE_0_PHY_BCR 24
+#define GCC_PCIE_1_PHY_BCR 25
+#define GCC_SDCC1_BCR 26
/* Dummy clocks for rate measurement */
#define MEASURE_ONLY_SNOC_CLK 0
diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h
index b362852d..21b5092 100644
--- a/include/dt-bindings/clock/qcom,videocc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -28,9 +28,4 @@
#define VIDEO_CC_VENUS_CTL_CORE_CLK 11
#define VIDEO_PLL0 12
-#define VIDEO_CC_INTERFACE_BCR 0
-#define VIDEO_CC_VCODEC0_BCR 1
-#define VIDEO_CC_VCODEC1_BCR 2
-#define VIDEO_CC_VENUS_BCR 3
-
#endif
diff --git a/include/dt-bindings/msm/msm-bus-ids.h b/include/dt-bindings/msm/msm-bus-ids.h
index 9d52d2e..8bd30d4 100644
--- a/include/dt-bindings/msm/msm-bus-ids.h
+++ b/include/dt-bindings/msm/msm-bus-ids.h
@@ -588,7 +588,7 @@
#define MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 774
#define MSM_BUS_SLAVE_SNOC_MEM_NOC_SF 775
#define MSM_BUS_SLAVE_MEM_NOC_SNOC 776
-#define MSM_BUS_SLAVE_IPA 777
+#define MSM_BUS_SLAVE_IPA_CORE 777
#define MSM_BUS_SLAVE_CAMNOC_UNCOMP 778
#define MSM_BUS_SLAVE_LAST 779
diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h
index 744ea4f..2b8b6e0 100644
--- a/include/linux/blk_types.h
+++ b/include/linux/blk_types.h
@@ -125,7 +125,15 @@
* BVEC_POOL_IDX()
*/
#define BIO_RESET_BITS 10
-#define BIO_INLINECRYPT 15
+
+
+/*
+ * Added for Req based dm which need to perform post processing. This flag
+ * ensures blk_update_request does not free the bios or request, this is done
+ * at the dm level
+ */
+#define BIO_DONTFREE 10
+#define BIO_INLINECRYPT 11
/*
* We support 6 different bvec pools, the last one is magic in that it
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index e47a7f7..fb910c6 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -816,6 +816,7 @@
extern int sg_scsi_ioctl(struct request_queue *, struct gendisk *, fmode_t,
struct scsi_ioctl_command __user *);
+extern void blk_recalc_rq_segments(struct request *rq);
extern int blk_queue_enter(struct request_queue *q, bool nowait);
extern void blk_queue_exit(struct request_queue *q);
extern void blk_start_queue(struct request_queue *q);
@@ -1031,6 +1032,8 @@
extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev);
extern int blk_rq_map_sg(struct request_queue *, struct request *, struct scatterlist *);
+extern int blk_rq_map_sg_no_cluster(struct request_queue *q, struct request *rq,
+ struct scatterlist *sglist);
extern void blk_dump_rq_flags(struct request *, char *);
extern long nr_blockdev_pages(void);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 7f395e3..9f93d18 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -50,6 +50,7 @@
CPUHP_ARM_SHMOBILE_SCU_PREPARE,
CPUHP_SH_SH3X_PREPARE,
CPUHP_BLK_MQ_PREPARE,
+ CPUHP_TOPOLOGY_PREPARE,
CPUHP_TIMERS_DEAD,
CPUHP_NOTF_ERR_INJ_PREPARE,
CPUHP_MIPS_SOC_PREPARE,
diff --git a/include/linux/device-mapper.h b/include/linux/device-mapper.h
index cf86f52..20e26d9 100644
--- a/include/linux/device-mapper.h
+++ b/include/linux/device-mapper.h
@@ -650,4 +650,12 @@
return (n << SECTOR_SHIFT);
}
+/*-----------------------------------------------------------------
+ * Helper for block layer and dm core operations
+ *-----------------------------------------------------------------
+ */
+void dm_dispatch_request(struct request *rq);
+void dm_kill_unmapped_request(struct request *rq, int error);
+void dm_end_request(struct request *clone, int error);
+
#endif /* _LINUX_DEVICE_MAPPER_H */
diff --git a/include/linux/diagchar.h b/include/linux/diagchar.h
index 3b5c7bf..1731c3a 100644
--- a/include/linux/diagchar.h
+++ b/include/linux/diagchar.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2008-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2008-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -144,11 +144,11 @@
/* This needs to be modified manually now, when we add
* a new RANGE of SSIDs to the msg_mask_tbl.
*/
-#define MSG_MASK_TBL_CNT 25
-#define APPS_EVENT_LAST_ID 0x0B14
+#define MSG_MASK_TBL_CNT 26
+#define APPS_EVENT_LAST_ID 0x0B3F
#define MSG_SSID_0 0
-#define MSG_SSID_0_LAST 118
+#define MSG_SSID_0_LAST 121
#define MSG_SSID_1 500
#define MSG_SSID_1_LAST 506
#define MSG_SSID_2 1000
@@ -160,11 +160,11 @@
#define MSG_SSID_5 4000
#define MSG_SSID_5_LAST 4010
#define MSG_SSID_6 4500
-#define MSG_SSID_6_LAST 4573
+#define MSG_SSID_6_LAST 4583
#define MSG_SSID_7 4600
#define MSG_SSID_7_LAST 4615
#define MSG_SSID_8 5000
-#define MSG_SSID_8_LAST 5032
+#define MSG_SSID_8_LAST 5033
#define MSG_SSID_9 5500
#define MSG_SSID_9_LAST 5516
#define MSG_SSID_10 6000
@@ -184,7 +184,7 @@
#define MSG_SSID_17 9000
#define MSG_SSID_17_LAST 9008
#define MSG_SSID_18 9500
-#define MSG_SSID_18_LAST 9510
+#define MSG_SSID_18_LAST 9521
#define MSG_SSID_19 10200
#define MSG_SSID_19_LAST 10210
#define MSG_SSID_20 10251
@@ -194,9 +194,11 @@
#define MSG_SSID_22 10350
#define MSG_SSID_22_LAST 10377
#define MSG_SSID_23 10400
-#define MSG_SSID_23_LAST 10415
-#define MSG_SSID_24 0xC000
-#define MSG_SSID_24_LAST 0xC063
+#define MSG_SSID_23_LAST 10416
+#define MSG_SSID_24 10500
+#define MSG_SSID_24_LAST 10505
+#define MSG_SSID_25 0xC000
+#define MSG_SSID_25_LAST 0xC063
static const uint32_t msg_bld_masks_0[] = {
MSG_LVL_LOW,
@@ -347,6 +349,9 @@
MSG_LVL_FATAL,
MSG_LVL_MED,
MSG_LVL_MED,
+ MSG_LVL_HIGH,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW|MSG_LVL_MED|MSG_LVL_HIGH|MSG_LVL_ERROR|MSG_LVL_FATAL,
MSG_LVL_HIGH
};
@@ -546,7 +551,8 @@
MSG_LVL_MED,
MSG_LVL_MED,
MSG_LVL_MED,
- MSG_LVL_MED
+ MSG_LVL_MED,
+ MSG_LVL_HIGH
};
static const uint32_t msg_bld_masks_9[] = {
@@ -863,13 +869,27 @@
MSG_LVL_LOW,
MSG_LVL_LOW,
MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW
+};
+
+static const uint32_t msg_bld_masks_24[] = {
+ MSG_LVL_HIGH,
+ MSG_LVL_HIGH,
+ MSG_LVL_HIGH,
+ MSG_LVL_HIGH,
+ MSG_LVL_HIGH,
+ MSG_LVL_HIGH
+};
+
+static const uint32_t msg_bld_masks_25[] = {
MSG_LVL_LOW
};
/* LOG CODES */
static const uint32_t log_code_last_tbl[] = {
0x0, /* EQUIP ID 0 */
- 0x1966, /* EQUIP ID 1 */
+ 0x1A11, /* EQUIP ID 1 */
0x0, /* EQUIP ID 2 */
0x0, /* EQUIP ID 3 */
0x4910, /* EQUIP ID 4 */
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 227b1e2..0f2e651 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -214,6 +214,7 @@
extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort);
extern void mmc_release_host(struct mmc_host *host);
+extern int mmc_try_claim_host(struct mmc_host *host, unsigned int delay);
extern void mmc_get_card(struct mmc_card *card);
extern void mmc_put_card(struct mmc_card *card);
@@ -232,7 +233,6 @@
bool lock_needed);
extern void mmc_cmdq_clk_scaling_stop_busy(struct mmc_host *host,
bool lock_needed, bool is_cmdq_dcmd);
-extern void mmc_recovery_fallback_lower_speed(struct mmc_host *host);
/**
* mmc_claim_host - exclusively claim a host
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index df841cf..9200069 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -559,6 +559,8 @@
struct dentry *debugfs_root;
+ bool err_occurred;
+
struct mmc_async_req *areq; /* active async req */
struct mmc_context_info context_info; /* async synchronization info */
diff --git a/include/linux/msm_gsi.h b/include/linux/msm_gsi.h
index 0c460a0..ebca446 100644
--- a/include/linux/msm_gsi.h
+++ b/include/linux/msm_gsi.h
@@ -752,6 +752,18 @@
uint32_t *db_addr_wp_lsb, uint32_t *db_addr_wp_msb);
/**
+ * gsi_ring_evt_ring_db - Peripheral should call this function for
+ * ringing the event ring doorbell with given value
+ *
+ * @evt_ring_hdl: Client handle previously obtained from
+ * gsi_alloc_evt_ring
+ * @value: The value to be used for ringing the doorbell
+ *
+ * @Return gsi_status
+ */
+int gsi_ring_evt_ring_db(unsigned long evt_ring_hdl, uint64_t value);
+
+/**
* gsi_reset_evt_ring - Peripheral should call this function to
* reset an event ring to recover from error state
*
@@ -1142,6 +1154,12 @@
return -GSI_STATUS_UNSUPPORTED_OP;
}
+static inline int gsi_ring_evt_ring_db(unsigned long evt_ring_hdl,
+ uint64_t value)
+{
+ return -GSI_STATUS_UNSUPPORTED_OP;
+}
+
static inline int gsi_reset_evt_ring(unsigned long evt_ring_hdl)
{
return -GSI_STATUS_UNSUPPORTED_OP;
diff --git a/include/linux/qcrypto.h b/include/linux/qcrypto.h
index 252464a..ff0e64c 100644
--- a/include/linux/qcrypto.h
+++ b/include/linux/qcrypto.h
@@ -15,6 +15,7 @@
#include <linux/crypto.h>
#include <crypto/hash.h>
+#include <crypto/skcipher.h>
#define QCRYPTO_CTX_KEY_MASK 0x000000ff
#define QCRYPTO_CTX_USE_HW_KEY 0x00000001
@@ -29,7 +30,7 @@
int qcrypto_ahash_set_device(struct ahash_request *req, unsigned int dev);
/*int qcrypto_aead_set_device(struct aead_request *req, unsigned int dev);*/
-int qcrypto_cipher_set_flag(struct ablkcipher_request *req, unsigned int flags);
+int qcrypto_cipher_set_flag(struct skcipher_request *req, unsigned int flags);
int qcrypto_ahash_set_flag(struct ahash_request *req, unsigned int flags);
/*int qcrypto_aead_set_flag(struct aead_request *req, unsigned int flags);*/
@@ -47,16 +48,16 @@
int qcrypto_get_num_engines(void);
void qcrypto_get_engine_list(size_t num_engines,
struct crypto_engine_entry *arr);
-int qcrypto_cipher_set_device_hw(struct ablkcipher_request *req,
+int qcrypto_cipher_set_device_hw(struct skcipher_request *req,
unsigned int fde_pfe,
unsigned int hw_inst);
struct qcrypto_func_set {
- int (*cipher_set)(struct ablkcipher_request *req,
+ int (*cipher_set)(struct skcipher_request *req,
unsigned int fde_pfe,
unsigned int hw_inst);
- int (*cipher_flag)(struct ablkcipher_request *req, unsigned int flags);
+ int (*cipher_flag)(struct skcipher_request *req, unsigned int flags);
int (*get_num_engines)(void);
void (*get_engine_list)(size_t num_engines,
struct crypto_engine_entry *arr);
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index fd09a1b..ddd8f4d 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -58,7 +58,7 @@
GSI_EP_OP_STORE_DBL_INFO,
GSI_EP_OP_ENABLE_GSI,
GSI_EP_OP_UPDATEXFER,
- GSI_EP_OP_RING_IN_DB,
+ GSI_EP_OP_RING_DB,
GSI_EP_OP_ENDXFER,
GSI_EP_OP_GET_CH_INFO,
GSI_EP_OP_GET_XFER_IDX,
diff --git a/include/uapi/linux/msm_ipa.h b/include/uapi/linux/msm_ipa.h
index 9773480..48cfe31 100644
--- a/include/uapi/linux/msm_ipa.h
+++ b/include/uapi/linux/msm_ipa.h
@@ -438,10 +438,20 @@
IPA_TETHERING_STATS_UPDATE_STATS = IPA_ECM_EVENT_MAX,
IPA_TETHERING_STATS_UPDATE_NETWORK_STATS,
IPA_TETHERING_STATS_EVENT_MAX,
- IPA_EVENT_MAX_NUM = IPA_TETHERING_STATS_EVENT_MAX
};
-#define IPA_EVENT_MAX ((int)IPA_EVENT_MAX_NUM)
+enum ipa_quota_event {
+ IPA_QUOTA_REACH = IPA_TETHERING_STATS_EVENT_MAX,
+ IPA_QUOTA_EVENT_MAX,
+};
+
+enum ipa_ssr_event {
+ IPA_SSR_BEFORE_SHUTDOWN = IPA_QUOTA_EVENT_MAX,
+ IPA_SSR_AFTER_POWERUP,
+ IPA_SSR_EVENT_MAX
+};
+
+#define IPA_EVENT_MAX_NUM ((int)IPA_SSR_EVENT_MAX)
/**
* enum ipa_rm_resource_name - IPA RM clients identification names
diff --git a/include/uapi/linux/rmnet_ipa_fd_ioctl.h b/include/uapi/linux/rmnet_ipa_fd_ioctl.h
index 228bfe8..f04ac49 100644
--- a/include/uapi/linux/rmnet_ipa_fd_ioctl.h
+++ b/include/uapi/linux/rmnet_ipa_fd_ioctl.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -32,6 +32,7 @@
#define WAN_IOCTL_RESET_TETHER_STATS 7
#define WAN_IOCTL_QUERY_DL_FILTER_STATS 8
#define WAN_IOCTL_ADD_FLT_RULE_EX 9
+#define WAN_IOCTL_QUERY_TETHER_STATS_ALL 10
/* User space may not have this defined. */
#ifndef IFNAMSIZ
@@ -99,6 +100,16 @@
uint64_t ipv6_rx_bytes;
};
+struct wan_ioctl_query_tether_stats_all {
+ /* Name of the upstream interface */
+ char upstreamIface[IFNAMSIZ];
+ /* enum of tether interface */
+ enum ipacm_client_enum ipa_client;
+ uint8_t reset_stats;
+ uint64_t tx_bytes;
+ uint64_t rx_bytes;
+};
+
struct wan_ioctl_reset_tether_stats {
/* Name of the upstream interface, not support now */
char upstreamIface[IFNAMSIZ];
@@ -155,4 +166,8 @@
WAN_IOCTL_ADD_FLT_RULE_EX, \
struct ipa_install_fltr_rule_req_ex_msg_v01 *)
+#define WAN_IOC_QUERY_TETHER_STATS_ALL _IOWR(WAN_IOC_MAGIC, \
+ WAN_IOCTL_QUERY_TETHER_STATS_ALL, \
+ struct wan_ioctl_query_tether_stats_all *)
+
#endif /* _RMNET_IPA_FD_IOCTL_H */
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 8ac83e5..78b72d5 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -463,6 +463,7 @@
for (; st->state > target; st->state--) {
ret = cpuhp_invoke_callback(cpu, st->state, false, NULL);
+ BUG_ON(ret && st->state < CPUHP_AP_IDLE_DEAD);
if (ret) {
st->target = prev_state;
undo_cpu_down(cpu, st);
@@ -494,6 +495,7 @@
if (ret) {
st->target = prev_state;
undo_cpu_up(cpu, st);
+ cpu_notify(CPU_UP_CANCELED, cpu);
break;
}
}
diff --git a/kernel/sched/boost.c b/kernel/sched/boost.c
index f5e87791..1a3309b 100644
--- a/kernel/sched/boost.c
+++ b/kernel/sched/boost.c
@@ -10,7 +10,6 @@
* GNU General Public License for more details.
*/
-#include <linux/jiffies.h>
#include "sched.h"
#include <linux/of.h>
#include <linux/sched/core_ctl.h>
@@ -140,7 +139,6 @@
case RESTRAINED_BOOST:
freq_aggr_threshold_backup =
update_freq_aggregate_threshold(1);
- mod_timer(&sched_grp_timer, jiffies + 1);
break;
default:
diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c
index c42380a..0a0e9aa 100644
--- a/kernel/sched/cpufreq_schedutil.c
+++ b/kernel/sched/cpufreq_schedutil.c
@@ -36,7 +36,6 @@
raw_spinlock_t update_lock; /* For shared policies */
u64 last_freq_update_time;
s64 freq_update_delay_ns;
- u64 hispeed_jmp_ts;
unsigned int next_freq;
unsigned int cached_raw_freq;
unsigned long hispeed_util;
@@ -216,11 +215,8 @@
HISPEED_LOAD,
100));
- if (is_hiload && !is_migration &&
- sg_policy->next_freq < sg_policy->tunables->hispeed_freq) {
+ if (is_hiload && !is_migration)
*util = max(*util, sg_policy->hispeed_util);
- sg_policy->hispeed_jmp_ts = sg_cpu->last_update;
- }
if (is_hiload && nl >= mult_frac(cpu_util, NL_RATIO, 100))
*util = *max;
diff --git a/kernel/sched/walt.c b/kernel/sched/walt.c
index e4bd0f4..50f889b 100644
--- a/kernel/sched/walt.c
+++ b/kernel/sched/walt.c
@@ -100,45 +100,6 @@
local_irq_restore(*flags);
}
-struct timer_list sched_grp_timer;
-static void sched_agg_grp_load(unsigned long data)
-{
- struct sched_cluster *cluster;
- unsigned long flags;
- int cpu;
-
- acquire_rq_locks_irqsave(cpu_possible_mask, &flags);
-
- for_each_sched_cluster(cluster) {
- u64 aggr_grp_load = 0;
-
- for_each_cpu(cpu, &cluster->cpus) {
- struct rq *rq = cpu_rq(cpu);
-
- if (rq->curr)
- update_task_ravg(rq->curr, rq, TASK_UPDATE,
- sched_ktime_clock(), 0);
- aggr_grp_load +=
- rq->grp_time.prev_runnable_sum;
- }
-
- cluster->aggr_grp_load = aggr_grp_load;
- }
-
- release_rq_locks_irqrestore(cpu_possible_mask, &flags);
-
- if (sched_boost() == RESTRAINED_BOOST)
- mod_timer(&sched_grp_timer, jiffies + 1);
-}
-
-static int __init setup_sched_grp_timer(void)
-{
- init_timer_deferrable(&sched_grp_timer);
- sched_grp_timer.function = sched_agg_grp_load;
- return 0;
-}
-late_initcall(setup_sched_grp_timer);
-
/* 1 -> use PELT based load stats, 0 -> use window-based load stats */
unsigned int __read_mostly walt_disabled = 0;
@@ -3058,6 +3019,8 @@
wc = sched_ktime_clock();
for_each_sched_cluster(cluster) {
+ u64 aggr_grp_load = 0;
+
raw_spin_lock(&cluster->load_lock);
for_each_cpu(cpu, &cluster->cpus) {
@@ -3066,14 +3029,19 @@
update_task_ravg(rq->curr, rq,
TASK_UPDATE, wc, 0);
account_load_subtractions(rq);
+ aggr_grp_load += rq->grp_time.prev_runnable_sum;
}
-
- cpufreq_update_util(rq, 0);
}
+ cluster->aggr_grp_load = aggr_grp_load;
+
raw_spin_unlock(&cluster->load_lock);
}
+ for_each_sched_cluster(cluster)
+ for_each_cpu(cpu, &cluster->cpus)
+ cpufreq_update_util(cpu_rq(cpu), 0);
+
for_each_cpu(cpu, cpu_possible_mask)
raw_spin_unlock(&cpu_rq(cpu)->lock);
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 22eff06..6878aa8 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -1724,6 +1724,20 @@
and to test how the mmc host driver handles retries from
the block device.
+config UFS_FAULT_INJECTION
+ bool "Fault-injection capability for UFS IO"
+ select DEBUG_FS
+ depends on FAULT_INJECTION && SCSI_UFSHCD
+ help
+ Provide fault-injection capability for UFS IO.
+ This will make the UFS host controller driver to randomly
+ abort ongoing commands in the host controller, update OCS
+ field according to the injected fatal error and can also
+ forcefully hang the command indefinitely till upper layer
+ timeout occurs. This is useful to test error handling in
+ the UFS contoller driver and test how the driver handles
+ the retries from block/SCSI mid layer.
+
config FAIL_FUTEX
bool "Fault-injection capability for futexes"
select DEBUG_FS
diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c
index c3bf5ff..9e7861a 100644
--- a/sound/usb/mixer.c
+++ b/sound/usb/mixer.c
@@ -1013,6 +1013,17 @@
cval->res = 384;
}
break;
+
+ case USB_ID(0x1130, 0x1620): /* Logitech Speakers S150 */
+ /* This audio device has 2 channels and it explicitly requires the
+ * host to send SET_CUR command on the volume control of both the
+ * channels. 7936 = 0x1F00 is the default value.
+ */
+ if (cval->channels == 2)
+ snd_usb_mixer_set_ctl_value(cval, UAC_SET_CUR,
+ (cval->control << 8) | 2, 7936);
+ break;
+
}
}