[MIPS] Fix loads of section missmatches
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 417bb3e..a1b48af 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -167,7 +167,7 @@
panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
}
-static volatile int daddi_ov __initdata = 0;
+static volatile int daddi_ov __cpuinitdata = 0;
asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
{
@@ -239,7 +239,7 @@
panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
}
-int daddiu_bug __initdata = -1;
+int daddiu_bug __cpuinitdata = -1;
static inline void check_daddiu(void)
{
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5861a43..89c3304 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -550,7 +550,7 @@
}
}
-static char unknown_isa[] __initdata = KERN_ERR \
+static char unknown_isa[] __cpuinitdata = KERN_ERR \
"Unsupported ISA type, c0.config0: %d.";
static inline unsigned int decode_config0(struct cpuinfo_mips *c)
@@ -656,7 +656,7 @@
return config3 & MIPS_CONF_M;
}
-static void __init decode_configs(struct cpuinfo_mips *c)
+static void __cpuinit decode_configs(struct cpuinfo_mips *c)
{
/* MIPS32 or MIPS64 compliant CPU. */
c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
@@ -814,7 +814,7 @@
/*
* Name a CPU
*/
-static __init const char *cpu_to_name(struct cpuinfo_mips *c)
+static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
{
const char *name = NULL;
@@ -896,7 +896,7 @@
return name;
}
-__init void cpu_probe(void)
+__cpuinit void cpu_probe(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
unsigned int cpu = smp_processor_id();
@@ -959,7 +959,7 @@
c->srsets = 1;
}
-__init void cpu_report(void)
+__cpuinit void cpu_report(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index a24fb79..3613645 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -195,7 +195,7 @@
j start_kernel
END(kernel_entry)
- __INIT
+ __CPUINIT
#ifdef CONFIG_SMP
/*
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 79cf7e9..984c0d0 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1306,7 +1306,7 @@
int cp0_perfcount_irq;
EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
-void __init per_cpu_trap_init(void)
+void __cpuinit per_cpu_trap_init(void)
{
unsigned int cpu = smp_processor_id();
unsigned int status_set = ST0_CU0;
@@ -1423,11 +1423,12 @@
flush_icache_range(ebase + offset, ebase + offset + size);
}
-static char panic_null_cerr[] __initdata =
+static char panic_null_cerr[] __cpuinitdata =
"Trying to set NULL cache error exception handler";
/* Install uncached CPU exception handler */
-void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size)
+void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
+ unsigned long size)
{
#ifdef CONFIG_32BIT
unsigned long uncached_ebase = KSEG1ADDR(ebase);
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index 27b012d..a6d1c77 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -36,7 +36,7 @@
* values, so we can avoid sharing the same stack area between a cached
* and the uncached mode.
*/
-unsigned long __init run_uncached(void *func)
+unsigned long __cpuinit run_uncached(void *func)
{
register long sp __asm__("$sp");
register long ret __asm__("$2");
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index f02ce63..b50e0fc 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -146,7 +146,7 @@
}
}
-unsigned int __init get_c0_compare_int(void)
+unsigned int __cpuinit get_c0_compare_int(void)
{
#ifdef MSC01E_INT_BASE
if (cpu_has_veic) {
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
index e39bbe9..881ecbc 100644
--- a/arch/mips/mipssim/sim_time.c
+++ b/arch/mips/mipssim/sim_time.c
@@ -83,7 +83,7 @@
}
-unsigned __init get_c0_compare_int(void)
+unsigned __cpuinit get_c0_compare_int(void)
{
#ifdef MSC01E_INT_BASE
if (cpu_has_veic) {
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 562abb7..76935e3 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -307,7 +307,7 @@
r3k_flush_dcache_range(start, start + size);
}
-void __init r3k_cache_init(void)
+void __cpuinit r3k_cache_init(void)
{
extern void build_clear_page(void);
extern void build_copy_page(void);
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 2c4f7e1..6496925 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -93,7 +93,7 @@
blast_dcache32_page(addr);
}
-static void __init r4k_blast_dcache_page_setup(void)
+static void __cpuinit r4k_blast_dcache_page_setup(void)
{
unsigned long dc_lsize = cpu_dcache_line_size();
@@ -107,7 +107,7 @@
static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
-static void __init r4k_blast_dcache_page_indexed_setup(void)
+static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
{
unsigned long dc_lsize = cpu_dcache_line_size();
@@ -121,7 +121,7 @@
static void (* r4k_blast_dcache)(void);
-static void __init r4k_blast_dcache_setup(void)
+static void __cpuinit r4k_blast_dcache_setup(void)
{
unsigned long dc_lsize = cpu_dcache_line_size();
@@ -206,7 +206,7 @@
static void (* r4k_blast_icache_page)(unsigned long addr);
-static void __init r4k_blast_icache_page_setup(void)
+static void __cpuinit r4k_blast_icache_page_setup(void)
{
unsigned long ic_lsize = cpu_icache_line_size();
@@ -223,7 +223,7 @@
static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
-static void __init r4k_blast_icache_page_indexed_setup(void)
+static void __cpuinit r4k_blast_icache_page_indexed_setup(void)
{
unsigned long ic_lsize = cpu_icache_line_size();
@@ -247,7 +247,7 @@
static void (* r4k_blast_icache)(void);
-static void __init r4k_blast_icache_setup(void)
+static void __cpuinit r4k_blast_icache_setup(void)
{
unsigned long ic_lsize = cpu_icache_line_size();
@@ -268,7 +268,7 @@
static void (* r4k_blast_scache_page)(unsigned long addr);
-static void __init r4k_blast_scache_page_setup(void)
+static void __cpuinit r4k_blast_scache_page_setup(void)
{
unsigned long sc_lsize = cpu_scache_line_size();
@@ -286,7 +286,7 @@
static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
-static void __init r4k_blast_scache_page_indexed_setup(void)
+static void __cpuinit r4k_blast_scache_page_indexed_setup(void)
{
unsigned long sc_lsize = cpu_scache_line_size();
@@ -304,7 +304,7 @@
static void (* r4k_blast_scache)(void);
-static void __init r4k_blast_scache_setup(void)
+static void __cpuinit r4k_blast_scache_setup(void)
{
unsigned long sc_lsize = cpu_scache_line_size();
@@ -691,11 +691,11 @@
}
}
-static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
+static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
};
-static void __init probe_pcache(void)
+static void __cpuinit probe_pcache(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
unsigned int config = read_c0_config();
@@ -1016,7 +1016,7 @@
* executes in KSEG1 space or else you will crash and burn badly. You have
* been warned.
*/
-static int __init probe_scache(void)
+static int __cpuinit probe_scache(void)
{
unsigned long flags, addr, begin, end, pow2;
unsigned int config = read_c0_config();
@@ -1095,7 +1095,7 @@
extern int rm7k_sc_init(void);
extern int mips_sc_init(void);
-static void __init setup_scache(void)
+static void __cpuinit setup_scache(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
unsigned int config = read_c0_config();
@@ -1206,7 +1206,7 @@
}
}
-static void __init coherency_setup(void)
+static void __cpuinit coherency_setup(void)
{
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
@@ -1238,7 +1238,7 @@
}
}
-void __init r4k_cache_init(void)
+void __cpuinit r4k_cache_init(void)
{
extern void build_clear_page(void);
extern void build_copy_page(void);
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 9ea121e..b09d569 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -329,7 +329,7 @@
}
}
-void __init tx39_cache_init(void)
+void __cpuinit tx39_cache_init(void)
{
extern void build_clear_page(void);
extern void build_copy_page(void);
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 6a24651..51ab1fa 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -127,9 +127,10 @@
}
}
-static char cache_panic[] __initdata = "Yeee, unsupported cache architecture.";
+static char cache_panic[] __cpuinitdata =
+ "Yeee, unsupported cache architecture.";
-void __init cpu_cache_init(void)
+void __devinit cpu_cache_init(void)
{
if (cpu_has_3k_cache) {
extern void __weak r3k_cache_init(void);
diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S
index e54a62f..2d08268 100644
--- a/arch/mips/mm/cex-sb1.S
+++ b/arch/mips/mm/cex-sb1.S
@@ -34,8 +34,6 @@
* is changed.
*/
- __INIT
-
.set mips64
.set noreorder
.set noat
@@ -51,6 +49,8 @@
* (0x170-0x17f) are used to preserve k0, k1, and ra.
*/
+ __CPUINIT
+
LEAF(except_vec2_sb1)
/*
* If this error is recoverable, we need to exit the handler
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index 9185fbf..455dedb 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -66,21 +66,21 @@
* with 64-bit kernels. The prefetch offsets have been experimentally tuned
* an Origin 200.
*/
-static int pref_offset_clear __initdata = 512;
-static int pref_offset_copy __initdata = 256;
+static int pref_offset_clear __cpuinitdata = 512;
+static int pref_offset_copy __cpuinitdata = 256;
-static unsigned int pref_src_mode __initdata;
-static unsigned int pref_dst_mode __initdata;
+static unsigned int pref_src_mode __cpuinitdata;
+static unsigned int pref_dst_mode __cpuinitdata;
-static int load_offset __initdata;
-static int store_offset __initdata;
+static int load_offset __cpuinitdata;
+static int store_offset __cpuinitdata;
-static unsigned int __initdata *dest, *epc;
+static unsigned int __cpuinitdata *dest, *epc;
static unsigned int instruction_pending;
static union mips_instruction delayed_mi;
-static void __init emit_instruction(union mips_instruction mi)
+static void __cpuinit emit_instruction(union mips_instruction mi)
{
if (instruction_pending)
*epc++ = delayed_mi.word;
@@ -222,7 +222,7 @@
emit_instruction(mi);
}
-static void __init __build_store_reg(int reg)
+static void __cpuinit __build_store_reg(int reg)
{
union mips_instruction mi;
unsigned int width;
@@ -339,7 +339,7 @@
flush_delay_slot_or_nop();
}
-void __init build_clear_page(void)
+void __cpuinit build_clear_page(void)
{
unsigned int loop_start;
unsigned long off;
@@ -442,7 +442,7 @@
pr_debug("\t.set pop\n");
}
-void __init build_copy_page(void)
+void __cpuinit build_copy_page(void)
{
unsigned int loop_start;
unsigned long off;
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index 89925ec..49e289d 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -293,10 +293,10 @@
EXPORT_SYMBOL(clear_page);
EXPORT_SYMBOL(copy_page);
-void __init build_clear_page(void)
+void __cpuinit build_clear_page(void)
{
}
-void __init build_copy_page(void)
+void __cpuinit build_copy_page(void)
{
}
diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c
index d236cf8..1f602a1 100644
--- a/arch/mips/mm/sc-ip22.c
+++ b/arch/mips/mm/sc-ip22.c
@@ -168,7 +168,7 @@
.bc_inv = indy_sc_wback_invalidate
};
-void __init indy_sc_init(void)
+void __cpuinit indy_sc_init(void)
{
if (indy_sc_probe()) {
indy_sc_enable();
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index c13170b..b55c2d1 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -100,7 +100,7 @@
return 1;
}
-int __init mips_sc_init(void)
+int __cpuinit mips_sc_init(void)
{
int found = mips_sc_probe();
if (found) {
@@ -109,4 +109,3 @@
}
return found;
}
-
diff --git a/arch/mips/mm/sc-r5k.c b/arch/mips/mm/sc-r5k.c
index d35b6c1..f330d38 100644
--- a/arch/mips/mm/sc-r5k.c
+++ b/arch/mips/mm/sc-r5k.c
@@ -99,7 +99,7 @@
.bc_inv = r5k_dma_cache_inv_sc
};
-void __init r5k_sc_init(void)
+void __cpuinit r5k_sc_init(void)
{
if (r5k_sc_probe()) {
r5k_sc_enable();
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index 31ec730..fc227f3 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -128,7 +128,7 @@
.bc_inv = rm7k_sc_inv
};
-void __init rm7k_sc_init(void)
+void __cpuinit rm7k_sc_init(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
unsigned int config = read_c0_config();
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index 7948e9a..a782549 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -281,7 +281,7 @@
}
}
-void __init tlb_init(void)
+void __cpuinit tlb_init(void)
{
local_flush_tlb_all();
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 2ad08fc..63065d6 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -388,7 +388,7 @@
* lifetime of the system
*/
-static int temp_tlb_entry __initdata;
+static int temp_tlb_entry __cpuinitdata;
__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask)
@@ -427,7 +427,7 @@
return ret;
}
-static void __init probe_tlb(unsigned long config)
+static void __cpuinit probe_tlb(unsigned long config)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
unsigned int reg;
@@ -455,7 +455,7 @@
c->tlbsize = ((reg >> 25) & 0x3f) + 1;
}
-static int __initdata ntlb = 0;
+static int __cpuinitdata ntlb = 0;
static int __init set_ntlb(char *str)
{
get_option(&str, &ntlb);
@@ -464,7 +464,7 @@
__setup("ntlb=", set_ntlb);
-void __init tlb_init(void)
+void __cpuinit tlb_init(void)
{
unsigned int config = read_c0_config();
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c
index bd8409d..4f01a3b 100644
--- a/arch/mips/mm/tlb-r8k.c
+++ b/arch/mips/mm/tlb-r8k.c
@@ -214,14 +214,14 @@
local_irq_restore(flags);
}
-static void __init probe_tlb(unsigned long config)
+static void __cpuinit probe_tlb(unsigned long config)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
c->tlbsize = 3 * 128; /* 3 sets each 128 entries */
}
-void __init tlb_init(void)
+void __cpuinit tlb_init(void)
{
unsigned int config = read_c0_config();
unsigned long status;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 218a6cc..3a93d4c 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -60,7 +60,7 @@
* why; it's not an issue caused by the core RTL.
*
*/
-static int __init m4kc_tlbp_war(void)
+static int __cpuinit m4kc_tlbp_war(void)
{
return (current_cpu_data.processor_id & 0xffff00) ==
(PRID_COMP_MIPS | PRID_IMP_4KC);
@@ -144,16 +144,16 @@
* We deliberately chose a buffer size of 128, so we won't scribble
* over anything important on overflow before we panic.
*/
-static u32 tlb_handler[128] __initdata;
+static u32 tlb_handler[128] __cpuinitdata;
/* simply assume worst case size for labels and relocs */
-static struct uasm_label labels[128] __initdata;
-static struct uasm_reloc relocs[128] __initdata;
+static struct uasm_label labels[128] __cpuinitdata;
+static struct uasm_reloc relocs[128] __cpuinitdata;
/*
* The R3000 TLB handler is simple.
*/
-static void __init build_r3000_tlb_refill_handler(void)
+static void __cpuinit build_r3000_tlb_refill_handler(void)
{
long pgdc = (long)pgd_current;
u32 *p;
@@ -197,7 +197,7 @@
* other one.To keep things simple, we first assume linear space,
* then we relocate it to the final handler layout as needed.
*/
-static u32 final_handler[64] __initdata;
+static u32 final_handler[64] __cpuinitdata;
/*
* Hazards
@@ -221,7 +221,7 @@
*
* As if we MIPS hackers wouldn't know how to nop pipelines happy ...
*/
-static void __init __maybe_unused build_tlb_probe_entry(u32 **p)
+static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
{
switch (current_cpu_type()) {
/* Found by experiment: R4600 v2.0 needs this, too. */
@@ -245,7 +245,7 @@
*/
enum tlb_write_entry { tlb_random, tlb_indexed };
-static void __init build_tlb_write_entry(u32 **p, struct uasm_label **l,
+static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
struct uasm_reloc **r,
enum tlb_write_entry wmode)
{
@@ -389,7 +389,7 @@
* TMP and PTR are scratch.
* TMP will be clobbered, PTR will hold the pmd entry.
*/
-static void __init
+static void __cpuinit
build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
unsigned int tmp, unsigned int ptr)
{
@@ -450,7 +450,7 @@
* BVADDR is the faulting address, PTR is scratch.
* PTR will hold the pgd for vmalloc.
*/
-static void __init
+static void __cpuinit
build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
unsigned int bvaddr, unsigned int ptr)
{
@@ -522,7 +522,7 @@
* TMP and PTR are scratch.
* TMP will be clobbered, PTR will hold the pgd entry.
*/
-static void __init __maybe_unused
+static void __cpuinit __maybe_unused
build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
{
long pgdc = (long)pgd_current;
@@ -557,7 +557,7 @@
#endif /* !CONFIG_64BIT */
-static void __init build_adjust_context(u32 **p, unsigned int ctx)
+static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
{
unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
@@ -583,7 +583,7 @@
uasm_i_andi(p, ctx, ctx, mask);
}
-static void __init build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
+static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
{
/*
* Bug workaround for the Nevada. It seems as if under certain
@@ -608,7 +608,7 @@
UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
}
-static void __init build_update_entries(u32 **p, unsigned int tmp,
+static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
unsigned int ptep)
{
/*
@@ -651,7 +651,7 @@
#endif
}
-static void __init build_r4000_tlb_refill_handler(void)
+static void __cpuinit build_r4000_tlb_refill_handler(void)
{
u32 *p = tlb_handler;
struct uasm_label *l = labels;
@@ -783,7 +783,7 @@
u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
-static void __init
+static void __cpuinit
iPTE_LW(u32 **p, struct uasm_label **l, unsigned int pte, unsigned int ptr)
{
#ifdef CONFIG_SMP
@@ -803,7 +803,7 @@
#endif
}
-static void __init
+static void __cpuinit
iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
unsigned int mode)
{
@@ -863,7 +863,7 @@
* the page table where this PTE is located, PTE will be re-loaded
* with it's original value.
*/
-static void __init
+static void __cpuinit
build_pte_present(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
unsigned int pte, unsigned int ptr, enum label_id lid)
{
@@ -874,7 +874,7 @@
}
/* Make PTE valid, store result in PTR. */
-static void __init
+static void __cpuinit
build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
unsigned int ptr)
{
@@ -887,7 +887,7 @@
* Check if PTE can be written to, if not branch to LABEL. Regardless
* restore PTE with value from PTR when done.
*/
-static void __init
+static void __cpuinit
build_pte_writable(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
unsigned int pte, unsigned int ptr, enum label_id lid)
{
@@ -900,7 +900,7 @@
/* Make PTE writable, update software status bits as well, then store
* at PTR.
*/
-static void __init
+static void __cpuinit
build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
unsigned int ptr)
{
@@ -914,7 +914,7 @@
* Check if PTE can be modified, if not branch to LABEL. Regardless
* restore PTE with value from PTR when done.
*/
-static void __init
+static void __cpuinit
build_pte_modifiable(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
unsigned int pte, unsigned int ptr, enum label_id lid)
{
@@ -931,7 +931,7 @@
* This places the pte into ENTRYLO0 and writes it with tlbwi.
* Then it returns.
*/
-static void __init
+static void __cpuinit
build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
{
uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
@@ -947,7 +947,7 @@
* may have the probe fail bit set as a result of a trap on a
* kseg2 access, i.e. without refill. Then it returns.
*/
-static void __init
+static void __cpuinit
build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
struct uasm_reloc **r, unsigned int pte,
unsigned int tmp)
@@ -965,7 +965,7 @@
uasm_i_rfe(p); /* branch delay */
}
-static void __init
+static void __cpuinit
build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
unsigned int ptr)
{
@@ -985,7 +985,7 @@
uasm_i_tlbp(p); /* load delay */
}
-static void __init build_r3000_tlb_load_handler(void)
+static void __cpuinit build_r3000_tlb_load_handler(void)
{
u32 *p = handle_tlbl;
struct uasm_label *l = labels;
@@ -1015,7 +1015,7 @@
dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
}
-static void __init build_r3000_tlb_store_handler(void)
+static void __cpuinit build_r3000_tlb_store_handler(void)
{
u32 *p = handle_tlbs;
struct uasm_label *l = labels;
@@ -1045,7 +1045,7 @@
dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
}
-static void __init build_r3000_tlb_modify_handler(void)
+static void __cpuinit build_r3000_tlb_modify_handler(void)
{
u32 *p = handle_tlbm;
struct uasm_label *l = labels;
@@ -1078,7 +1078,7 @@
/*
* R4000 style TLB load/store/modify handlers.
*/
-static void __init
+static void __cpuinit
build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
struct uasm_reloc **r, unsigned int pte,
unsigned int ptr)
@@ -1103,7 +1103,7 @@
build_tlb_probe_entry(p);
}
-static void __init
+static void __cpuinit
build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
struct uasm_reloc **r, unsigned int tmp,
unsigned int ptr)
@@ -1120,7 +1120,7 @@
#endif
}
-static void __init build_r4000_tlb_load_handler(void)
+static void __cpuinit build_r4000_tlb_load_handler(void)
{
u32 *p = handle_tlbl;
struct uasm_label *l = labels;
@@ -1160,7 +1160,7 @@
dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
}
-static void __init build_r4000_tlb_store_handler(void)
+static void __cpuinit build_r4000_tlb_store_handler(void)
{
u32 *p = handle_tlbs;
struct uasm_label *l = labels;
@@ -1191,7 +1191,7 @@
dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
}
-static void __init build_r4000_tlb_modify_handler(void)
+static void __cpuinit build_r4000_tlb_modify_handler(void)
{
u32 *p = handle_tlbm;
struct uasm_label *l = labels;
@@ -1223,7 +1223,7 @@
dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
}
-void __init build_tlb_refill_handler(void)
+void __cpuinit build_tlb_refill_handler(void)
{
/*
* The refill handler is generated per-CPU, multi-node systems
@@ -1269,7 +1269,7 @@
}
}
-void __init flush_tlb_handlers(void)
+void __cpuinit flush_tlb_handlers(void)
{
flush_icache_range((unsigned long)handle_tlbl,
(unsigned long)handle_tlbl + sizeof(handle_tlbl));
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index e3f74ed..1a6f770 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -82,7 +82,7 @@
| (e) << RE_SH \
| (f) << FUNC_SH)
-static struct insn insn_table[] __initdata = {
+static struct insn insn_table[] __cpuinitdata = {
{ insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
{ insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
@@ -135,7 +135,7 @@
#undef M
-static inline __init u32 build_rs(u32 arg)
+static inline __cpuinit u32 build_rs(u32 arg)
{
if (arg & ~RS_MASK)
printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -143,7 +143,7 @@
return (arg & RS_MASK) << RS_SH;
}
-static inline __init u32 build_rt(u32 arg)
+static inline __cpuinit u32 build_rt(u32 arg)
{
if (arg & ~RT_MASK)
printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -151,7 +151,7 @@
return (arg & RT_MASK) << RT_SH;
}
-static inline __init u32 build_rd(u32 arg)
+static inline __cpuinit u32 build_rd(u32 arg)
{
if (arg & ~RD_MASK)
printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -159,7 +159,7 @@
return (arg & RD_MASK) << RD_SH;
}
-static inline __init u32 build_re(u32 arg)
+static inline __cpuinit u32 build_re(u32 arg)
{
if (arg & ~RE_MASK)
printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -167,7 +167,7 @@
return (arg & RE_MASK) << RE_SH;
}
-static inline __init u32 build_simm(s32 arg)
+static inline __cpuinit u32 build_simm(s32 arg)
{
if (arg > 0x7fff || arg < -0x8000)
printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -175,7 +175,7 @@
return arg & 0xffff;
}
-static inline __init u32 build_uimm(u32 arg)
+static inline __cpuinit u32 build_uimm(u32 arg)
{
if (arg & ~IMM_MASK)
printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -183,7 +183,7 @@
return arg & IMM_MASK;
}
-static inline __init u32 build_bimm(s32 arg)
+static inline __cpuinit u32 build_bimm(s32 arg)
{
if (arg > 0x1ffff || arg < -0x20000)
printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -194,7 +194,7 @@
return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
}
-static inline __init u32 build_jimm(u32 arg)
+static inline __cpuinit u32 build_jimm(u32 arg)
{
if (arg & ~((JIMM_MASK) << 2))
printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -202,7 +202,7 @@
return (arg >> 2) & JIMM_MASK;
}
-static inline __init u32 build_func(u32 arg)
+static inline __cpuinit u32 build_func(u32 arg)
{
if (arg & ~FUNC_MASK)
printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -210,7 +210,7 @@
return arg & FUNC_MASK;
}
-static inline __init u32 build_set(u32 arg)
+static inline __cpuinit u32 build_set(u32 arg)
{
if (arg & ~SET_MASK)
printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -222,7 +222,7 @@
* The order of opcode arguments is implicitly left to right,
* starting with RS and ending with FUNC or IMM.
*/
-static void __init build_insn(u32 **buf, enum opcode opc, ...)
+static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
{
struct insn *ip = NULL;
unsigned int i;
@@ -375,14 +375,14 @@
I_u2u1u3(_xori)
/* Handle labels. */
-void __init uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
+void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
{
(*lab)->addr = addr;
(*lab)->lab = lid;
(*lab)++;
}
-int __init uasm_in_compat_space_p(long addr)
+int __cpuinit uasm_in_compat_space_p(long addr)
{
/* Is this address in 32bit compat space? */
#ifdef CONFIG_64BIT
@@ -392,7 +392,7 @@
#endif
}
-int __init uasm_rel_highest(long val)
+int __cpuinit uasm_rel_highest(long val)
{
#ifdef CONFIG_64BIT
return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
@@ -401,7 +401,7 @@
#endif
}
-int __init uasm_rel_higher(long val)
+int __cpuinit uasm_rel_higher(long val)
{
#ifdef CONFIG_64BIT
return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
@@ -410,17 +410,17 @@
#endif
}
-int __init uasm_rel_hi(long val)
+int __cpuinit uasm_rel_hi(long val)
{
return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
}
-int __init uasm_rel_lo(long val)
+int __cpuinit uasm_rel_lo(long val)
{
return ((val & 0xffff) ^ 0x8000) - 0x8000;
}
-void __init UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
+void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
{
if (!uasm_in_compat_space_p(addr)) {
uasm_i_lui(buf, rs, uasm_rel_highest(addr));
@@ -436,7 +436,7 @@
uasm_i_lui(buf, rs, uasm_rel_hi(addr));
}
-void __init UASM_i_LA(u32 **buf, unsigned int rs, long addr)
+void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
{
UASM_i_LA_mostly(buf, rs, addr);
if (uasm_rel_lo(addr)) {
@@ -448,7 +448,7 @@
}
/* Handle relocations. */
-void __init
+void __cpuinit
uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
{
(*rel)->addr = addr;
@@ -457,7 +457,7 @@
(*rel)++;
}
-static inline void __init
+static inline void __cpuinit
__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
{
long laddr = (long)lab->addr;
@@ -474,7 +474,7 @@
}
}
-void __init
+void __cpuinit
uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
{
struct uasm_label *l;
@@ -485,7 +485,7 @@
__resolve_relocs(rel, l);
}
-void __init
+void __cpuinit
uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
{
for (; rel->lab != UASM_LABEL_INVALID; rel++)
@@ -493,7 +493,7 @@
rel->addr += off;
}
-void __init
+void __cpuinit
uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
{
for (; lab->lab != UASM_LABEL_INVALID; lab++)
@@ -501,7 +501,7 @@
lab->addr += off;
}
-void __init
+void __cpuinit
uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
u32 *end, u32 *target)
{
@@ -513,7 +513,7 @@
uasm_move_labels(lab, first, end, off);
}
-int __init uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
+int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
{
for (; rel->lab != UASM_LABEL_INVALID; rel++) {
if (rel->addr == addr
@@ -526,49 +526,49 @@
}
/* Convenience functions for labeled branches. */
-void __init
+void __cpuinit
uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
uasm_r_mips_pc16(r, *p, lid);
uasm_i_bltz(p, reg, 0);
}
-void __init
+void __cpuinit
uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
{
uasm_r_mips_pc16(r, *p, lid);
uasm_i_b(p, 0);
}
-void __init
+void __cpuinit
uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
uasm_r_mips_pc16(r, *p, lid);
uasm_i_beqz(p, reg, 0);
}
-void __init
+void __cpuinit
uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
uasm_r_mips_pc16(r, *p, lid);
uasm_i_beqzl(p, reg, 0);
}
-void __init
+void __cpuinit
uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
uasm_r_mips_pc16(r, *p, lid);
uasm_i_bnez(p, reg, 0);
}
-void __init
+void __cpuinit
uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
uasm_r_mips_pc16(r, *p, lid);
uasm_i_bgezl(p, reg, 0);
}
-void __init
+void __cpuinit
uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
uasm_r_mips_pc16(r, *p, lid);
diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h
index a10fc11..fe0574f 100644
--- a/arch/mips/mm/uasm.h
+++ b/arch/mips/mm/uasm.h
@@ -11,38 +11,38 @@
#include <linux/types.h>
#define Ip_u1u2u3(op) \
-void __init \
+void __cpuinit \
uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
#define Ip_u2u1u3(op) \
-void __init \
+void __cpuinit \
uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
#define Ip_u3u1u2(op) \
-void __init \
+void __cpuinit \
uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
#define Ip_u1u2s3(op) \
-void __init \
+void __cpuinit \
uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
#define Ip_u2s3u1(op) \
-void __init \
+void __cpuinit \
uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
#define Ip_u2u1s3(op) \
-void __init \
+void __cpuinit \
uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
#define Ip_u1u2(op) \
-void __init uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
+void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
#define Ip_u1s2(op) \
-void __init uasm_i##op(u32 **buf, unsigned int a, signed int b)
+void __cpuinit uasm_i##op(u32 **buf, unsigned int a, signed int b)
-#define Ip_u1(op) void __init uasm_i##op(u32 **buf, unsigned int a)
+#define Ip_u1(op) void __cpuinit uasm_i##op(u32 **buf, unsigned int a)
-#define Ip_0(op) void __init uasm_i##op(u32 **buf)
+#define Ip_0(op) void __cpuinit uasm_i##op(u32 **buf)
Ip_u2u1s3(_addiu);
Ip_u3u1u2(_addu);
@@ -98,19 +98,19 @@
int lab;
};
-void __init uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
+void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
#ifdef CONFIG_64BIT
-int __init uasm_in_compat_space_p(long addr);
-int __init uasm_rel_highest(long val);
-int __init uasm_rel_higher(long val);
+int uasm_in_compat_space_p(long addr);
+int uasm_rel_highest(long val);
+int uasm_rel_higher(long val);
#endif
-int __init uasm_rel_hi(long val);
-int __init uasm_rel_lo(long val);
-void __init UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
-void __init UASM_i_LA(u32 **buf, unsigned int rs, long addr);
+int uasm_rel_hi(long val);
+int uasm_rel_lo(long val);
+void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
+void UASM_i_LA(u32 **buf, unsigned int rs, long addr);
#define UASM_L_LA(lb) \
-static inline void __init uasm_l##lb(struct uasm_label **lab, u32 *addr) \
+static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
{ \
uasm_build_label(lab, addr, label##lb); \
}
@@ -164,29 +164,19 @@
/* This is zero so we can use zeroed label arrays. */
#define UASM_LABEL_INVALID 0
-void __init uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid);
-void __init
-uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab);
-void __init
-uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off);
-void __init
-uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off);
-void __init
-uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
- u32 *end, u32 *target);
-int __init uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr);
+void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid);
+void uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab);
+void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off);
+void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off);
+void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
+ u32 *first, u32 *end, u32 *target);
+int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr);
/* Convenience functions for labeled branches. */
-void __init
-uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void __init uasm_il_b(u32 **p, struct uasm_reloc **r, int lid);
-void __init
-uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void __init
-uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void __init
-uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void __init
-uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void __init
-uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid);
+void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index a322543..bb64828 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -40,7 +40,7 @@
extern struct pci_ops bridge_pci_ops;
-int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid)
+int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
{
unsigned long offset = NODE_OFFSET(nasid);
struct bridge_controller *bc;
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index f9471d7..358ad62 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -260,7 +260,7 @@
}
}
-void pcibios_fixup_bus(struct pci_bus *bus)
+void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
/* Propagate hose info into the subordinate devices. */
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index a49e7c8..7093e7c 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -53,7 +53,7 @@
extern void xtalk_probe_node(cnodeid_t nid);
-static void __init per_hub_init(cnodeid_t cnode)
+static void __cpuinit per_hub_init(cnodeid_t cnode)
{
struct hub_data *hub = hub_data(cnode);
nasid_t nasid = COMPACT_TO_NASID_NODEID(cnode);
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 08d4536..25d3baf 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -285,7 +285,7 @@
set_c0_status(SRB_TIMOCLK);
}
-void __init hub_rtc_init(cnodeid_t cnode)
+void __cpuinit hub_rtc_init(cnodeid_t cnode)
{
/*
* We only need to initialize the current node.
diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
index fc82f34..6ae64e8 100644
--- a/arch/mips/sgi-ip27/ip27-xtalk.c
+++ b/arch/mips/sgi-ip27/ip27-xtalk.c
@@ -22,7 +22,7 @@
extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
-static int __init probe_one_port(nasid_t nasid, int widget, int masterwid)
+static int __cpuinit probe_one_port(nasid_t nasid, int widget, int masterwid)
{
widgetreg_t widget_id;
xwidget_part_num_t partnum;
@@ -46,7 +46,7 @@
return 0;
}
-static int __init xbow_probe(nasid_t nasid)
+static int __cpuinit xbow_probe(nasid_t nasid)
{
lboard_t *brd;
klxbow_t *xbow_p;
@@ -99,7 +99,7 @@
return 0;
}
-void __init xtalk_probe_node(cnodeid_t nid)
+void __cpuinit xtalk_probe_node(cnodeid_t nid)
{
volatile u64 hubreg;
nasid_t nasid;
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
index 4933b49..01e7ead 100644
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -93,7 +93,7 @@
clear_bit(PG_dcache_dirty, &(page)->flags)
/* Run kernel code uncached, useful for cache probing functions. */
-unsigned long __init run_uncached(void *func);
+unsigned long run_uncached(void *func);
extern void *kmap_coherent(struct page *page, unsigned long addr);
extern void kunmap_coherent(void);