[MIPS] Fix loads of section missmatches
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index 27b012d..a6d1c77 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -36,7 +36,7 @@
* values, so we can avoid sharing the same stack area between a cached
* and the uncached mode.
*/
-unsigned long __init run_uncached(void *func)
+unsigned long __cpuinit run_uncached(void *func)
{
register long sp __asm__("$sp");
register long ret __asm__("$2");