| * Qualcomm Technologies, Inc. MSM CSI Phy |
| |
| Required properties: |
| - cell-index: csi phy hardware core index |
| - compatible : |
| - "qcom,csiphy-v5.01" |
| - reg : offset and length of the register set for the device |
| for the csiphy operating in compatible mode. |
| reg-cam-base : offset of ceiphy in camera hw block |
| - reg-names : should specify relevant names to each reg property defined. |
| - interrupts : should contain the csiphy interrupt. |
| - interrupt-names : should specify relevant names to each interrupts |
| property defined. |
| - clock-names: name of the clocks required for the device |
| - clock-rates: clock rate in Hz |
| - 0 if appropriate clock is required but doesn't have to apply the rate |
| - clock-cntl-level: says what all different cloc level node has. |
| |
| Example: |
| |
| qcom,csiphy@ac65000 { |
| cell-index = <0>; |
| compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| reg = <0xac65000 0x200>; |
| reg-cam-base = <0x65000>; |
| reg-names = "csiphy"; |
| interrupts = <0 477 0>; |
| interrupt-names = "csiphy"; |
| clock-names = "camnoc_axi_clk", "soc_ahb_clk", |
| "slow_ahb_src_clk", "cpas_ahb_clk", |
| "cphy_rx_clk_src", "csiphy0_clk", |
| "csi0phytimer_clk_src", "csi0phytimer_clk", |
| "ife_0_csid_clk", "ife_0_csid_clk_src"; |
| clock-rates = |
| <0 0 80000000 0 320000000 0 269333333 0 0 384000000>; |
| clock-cntl-level = "turbo"; |
| regulator-names = "gdscr"; |
| status = "ok"; |
| }; |