clk: qcom: mdss: fix debug clock names for DSI PLL on msm8994
Fix the debug clock names to match with proper clocks for
msm8994. These clocks are part of 20nm PHY PLL configuration.
Change-Id: I709d6df80330702304b91d76ec2cad0a7f494c1e
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c
index 89342ff..5b6b4b9 100644
--- a/drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c
+++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c
@@ -129,7 +129,7 @@
.ops = &ndiv_ops,
.c = {
.parent = &dsi_vco_clk_8994.c,
- .dbg_name = "ndiv_clk",
+ .dbg_name = "ndiv_clk_8994",
.ops = &ndiv_clk_ops,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(ndiv_clk_8994.c),
@@ -144,7 +144,7 @@
},
.c = {
.parent = &ndiv_clk_8994.c,
- .dbg_name = "indirect_path_div2_clk",
+ .dbg_name = "indirect_path_div2_clk_8994",
.ops = &clk_ops_div,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(indirect_path_div2_clk_8994.c),
@@ -174,7 +174,7 @@
},
.c = {
.parent = &hr_oclk3_div_clk_8994.c,
- .dbg_name = "pixel_clk_src_8994",
+ .dbg_name = "pixel_clk_src",
.ops = &clk_ops_div,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(pixel_clk_src.c),
@@ -204,7 +204,7 @@
},
.c = {
.parent = &bypass_lp_div_mux_8994.c,
- .dbg_name = "fixed_hr_oclk2_div_clk",
+ .dbg_name = "fixed_hr_oclk2_div_clk_8994",
.ops = &byte_clk_src_ops,
CLK_INIT(fixed_hr_oclk2_div_clk_8994.c),
},
@@ -218,7 +218,7 @@
},
.c = {
.parent = &fixed_hr_oclk2_div_clk_8994.c,
- .dbg_name = "byte_clk_src_8994",
+ .dbg_name = "byte_clk_src",
.ops = &clk_ops_div,
CLK_INIT(byte_clk_src.c),
},