| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| &soc { |
| qcom,cam-req-mgr { |
| compatible = "qcom,cam-req-mgr"; |
| status = "ok"; |
| }; |
| |
| qcom,csiphy@ac65000 { |
| cell-index = <0>; |
| compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| reg = <0x0ac65000 0x1000>; |
| reg-names = "csiphy"; |
| interrupts = <0 477 0>; |
| interrupt-names = "csiphy"; |
| gdscr-supply = <&titan_top_gdsc>; |
| qcom,cam-vreg-name = "gdscr"; |
| qcom,csi-vdd-voltage = <1200000>; |
| qcom,mipi-csi-vdd-supply = <&pm8998_l26>; |
| clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| <&clock_camcc CAM_CC_CSIPHY0_CLK>, |
| <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, |
| <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, |
| <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, |
| <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>; |
| clock-names = "camnoc_axi_clk", |
| "soc_ahb_clk", |
| "slow_ahb_src_clk", |
| "cpas_ahb_clk", |
| "cphy_rx_clk_src", |
| "csiphy0_clk", |
| "csi0phytimer_clk_src", |
| "csi0phytimer_clk", |
| "ife_0_csid_clk", |
| "ife_0_csid_clk_src"; |
| qcom,clock-rates = |
| <0 0 80000000 0 320000000 0 269333333 0 0 384000000>; |
| status = "ok"; |
| }; |
| |
| qcom,csiphy@ac66000{ |
| cell-index = <1>; |
| compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| reg = <0xac66000 0x1000>; |
| reg-names = "csiphy"; |
| interrupts = <0 478 0>; |
| interrupt-names = "csiphy"; |
| gdscr-supply = <&titan_top_gdsc>; |
| qcom,cam-vreg-name = "gdscr"; |
| qcom,csi-vdd-voltage = <1200000>; |
| qcom,mipi-csi-vdd-supply = <&pm8998_l26>; |
| clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| <&clock_camcc CAM_CC_CSIPHY1_CLK>, |
| <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, |
| <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, |
| <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, |
| <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>; |
| clock-names = "camnoc_axi_clk", |
| "soc_ahb_clk", |
| "slow_ahb_src_clk", |
| "cpas_ahb_clk", |
| "cphy_rx_clk_src", |
| "csiphy1_clk", |
| "csi1phytimer_clk_src", |
| "csi1phytimer_clk", |
| "ife_1_csid_clk", |
| "ife_1_csid_clk_src"; |
| qcom,clock-rates = |
| <0 0 80000000 0 320000000 0 269333333 0 0 384000000>; |
| |
| status = "ok"; |
| }; |
| |
| qcom,csiphy@ac67000 { |
| cell-index = <2>; |
| compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| reg = <0xac67000 0x1000>; |
| reg-names = "csiphy"; |
| interrupts = <0 479 0>; |
| interrupt-names = "csiphy"; |
| gdscr-supply = <&titan_top_gdsc>; |
| qcom,cam-vreg-name = "gdscr"; |
| qcom,csi-vdd-voltage = <1200000>; |
| qcom,mipi-csi-vdd-supply = <&pm8998_l26>; |
| clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| <&clock_camcc CAM_CC_CSIPHY2_CLK>, |
| <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, |
| <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, |
| <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, |
| <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>; |
| clock-names = "camnoc_axi_clk", |
| "soc_ahb_clk", |
| "slow_ahb_src_clk", |
| "cpas_ahb_clk", |
| "cphy_rx_clk_src", |
| "csiphy2_clk", |
| "csi2phytimer_clk_src", |
| "csi2phytimer_clk", |
| "ife_lite_csid_clk", |
| "ife_lite_csid_clk_src"; |
| qcom,clock-rates = |
| <0 0 80000000 0 320000000 0 269333333 0 0 384000000>; |
| status = "ok"; |
| }; |
| |
| cci: qcom,cci@ac4a000 { |
| cell-index = <0>; |
| compatible = "qcom,cci"; |
| reg = <0xac4a000 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg-names = "cci"; |
| interrupts = <0 460 0>; |
| interrupt-names = "cci"; |
| status = "ok"; |
| gdscr-supply = <&titan_top_gdsc>; |
| qcom,cam-vreg-name = "gdscr"; |
| clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_CCI_CLK>, |
| <&clock_camcc CAM_CC_CCI_CLK_SRC>; |
| clock-names = "camnoc_axi_clk", |
| "soc_ahb_clk", |
| "slow_ahb_src_clk", |
| "cpas_ahb_clk", |
| "cci_clk", |
| "cci_clk_src"; |
| qcom,clock-rates = <0 0 80000000 0 0 37500000>; |
| pinctrl-names = "cci_default", "cci_suspend"; |
| pinctrl-0 = <&cci0_active &cci1_active>; |
| pinctrl-1 = <&cci0_suspend &cci1_suspend>; |
| gpios = <&tlmm 17 0>, |
| <&tlmm 18 0>, |
| <&tlmm 19 0>, |
| <&tlmm 20 0>; |
| qcom,gpio-tbl-num = <0 1 2 3>; |
| qcom,gpio-tbl-flags = <1 1 1 1>; |
| qcom,gpio-tbl-label = "CCI_I2C_DATA0", |
| "CCI_I2C_CLK0", |
| "CCI_I2C_DATA1", |
| "CCI_I2C_CLK1"; |
| |
| i2c_freq_100Khz: qcom,i2c_standard_mode { |
| qcom,hw-thigh = <201>; |
| qcom,hw-tlow = <174>; |
| qcom,hw-tsu-sto = <204>; |
| qcom,hw-tsu-sta = <231>; |
| qcom,hw-thd-dat = <22>; |
| qcom,hw-thd-sta = <162>; |
| qcom,hw-tbuf = <227>; |
| qcom,hw-scl-stretch-en = <0>; |
| qcom,hw-trdhld = <6>; |
| qcom,hw-tsp = <3>; |
| qcom,cci-clk-src = <37500000>; |
| status = "ok"; |
| }; |
| |
| i2c_freq_400Khz: qcom,i2c_fast_mode { |
| qcom,hw-thigh = <38>; |
| qcom,hw-tlow = <56>; |
| qcom,hw-tsu-sto = <40>; |
| qcom,hw-tsu-sta = <40>; |
| qcom,hw-thd-dat = <22>; |
| qcom,hw-thd-sta = <35>; |
| qcom,hw-tbuf = <62>; |
| qcom,hw-scl-stretch-en = <0>; |
| qcom,hw-trdhld = <6>; |
| qcom,hw-tsp = <3>; |
| qcom,cci-clk-src = <37500000>; |
| status = "ok"; |
| }; |
| |
| i2c_freq_custom: qcom,i2c_custom_mode { |
| qcom,hw-thigh = <38>; |
| qcom,hw-tlow = <56>; |
| qcom,hw-tsu-sto = <40>; |
| qcom,hw-tsu-sta = <40>; |
| qcom,hw-thd-dat = <22>; |
| qcom,hw-thd-sta = <35>; |
| qcom,hw-tbuf = <62>; |
| qcom,hw-scl-stretch-en = <1>; |
| qcom,hw-trdhld = <6>; |
| qcom,hw-tsp = <3>; |
| qcom,cci-clk-src = <37500000>; |
| status = "ok"; |
| }; |
| |
| i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { |
| qcom,hw-thigh = <16>; |
| qcom,hw-tlow = <22>; |
| qcom,hw-tsu-sto = <17>; |
| qcom,hw-tsu-sta = <18>; |
| qcom,hw-thd-dat = <16>; |
| qcom,hw-thd-sta = <15>; |
| qcom,hw-tbuf = <24>; |
| qcom,hw-scl-stretch-en = <0>; |
| qcom,hw-trdhld = <3>; |
| qcom,hw-tsp = <3>; |
| qcom,cci-clk-src = <37500000>; |
| status = "ok"; |
| }; |
| }; |
| |
| qcom,cam_smmu { |
| compatible = "qcom,msm-cam-smmu"; |
| status = "ok"; |
| |
| msm_cam_smmu_ife { |
| compatible = "qcom,msm-cam-smmu-cb"; |
| iommus = <&apps_smmu 0x808 0x0>, |
| <&apps_smmu 0x810 0x8>, |
| <&apps_smmu 0xc08 0x0>, |
| <&apps_smmu 0xc10 0x8>; |
| label = "ife"; |
| ife_iova_mem_map: iova-mem-map { |
| /* IO region is approximately 3.4 GB */ |
| iova-mem-region-io { |
| iova-region-name = "io"; |
| iova-region-start = <0x7400000>; |
| iova-region-len = <0xd8c00000>; |
| iova-region-id = <0x3>; |
| status = "ok"; |
| }; |
| }; |
| }; |
| |
| msm_cam_icp_fw { |
| compatible = "qcom,msm-cam-smmu-fw-dev"; |
| label="icp"; |
| memory-region = <&pil_camera_mem>; |
| }; |
| |
| msm_cam_smmu_icp { |
| compatible = "qcom,msm-cam-smmu-cb"; |
| iommus = <&apps_smmu 0x1078 0x2>, |
| <&apps_smmu 0x1020 0x8>, |
| <&apps_smmu 0x1040 0x8>, |
| <&apps_smmu 0x1030 0x0>, |
| <&apps_smmu 0x1050 0x0>; |
| label = "icp"; |
| icp_iova_mem_map: iova-mem-map { |
| iova-mem-region-firmware { |
| /* Firmware region is 5MB */ |
| iova-region-name = "firmware"; |
| iova-region-start = <0x0>; |
| iova-region-len = <0x500000>; |
| iova-region-id = <0x0>; |
| status = "ok"; |
| }; |
| |
| iova-mem-region-shared { |
| /* Shared region is 100MB long */ |
| iova-region-name = "shared"; |
| iova-region-start = <0x7400000>; |
| iova-region-len = <0x6400000>; |
| iova-region-id = <0x1>; |
| status = "ok"; |
| }; |
| |
| iova-mem-region-io { |
| /* IO region is approximately 3.3 GB */ |
| iova-region-name = "io"; |
| iova-region-start = <0xd800000>; |
| iova-region-len = <0xd2800000>; |
| iova-region-id = <0x3>; |
| status = "ok"; |
| }; |
| }; |
| }; |
| |
| msm_cam_smmu_cpas_cdm { |
| compatible = "qcom,msm-cam-smmu-cb"; |
| iommus = <&apps_smmu 0x1000 0x0>; |
| label = "cpas-cdm0"; |
| cpas_cdm_iova_mem_map: iova-mem-map { |
| iova-mem-region-io { |
| /* IO region is approximately 3.4 GB */ |
| iova-region-name = "io"; |
| iova-region-start = <0x7400000>; |
| iova-region-len = <0xd8c00000>; |
| iova-region-id = <0x3>; |
| status = "ok"; |
| }; |
| }; |
| }; |
| |
| msm_cam_smmu_secure { |
| compatible = "qcom,msm-cam-smmu-cb"; |
| iommus = <&apps_smmu 0x1001 0x0>; |
| label = "cam-secure"; |
| cam_secure_iova_mem_map: iova-mem-map { |
| /* Secure IO region is approximately 3.4 GB */ |
| iova-mem-region-io { |
| iova-region-name = "io"; |
| iova-region-start = <0x7400000>; |
| iova-region-len = <0xd8c00000>; |
| iova-region-id = <0x3>; |
| status = "ok"; |
| }; |
| }; |
| }; |
| }; |
| |
| qcom,cam-cpas@ac40000 { |
| cell-index = <0>; |
| compatible = "qcom,cam-cpas"; |
| label = "cpas"; |
| arch-compat = "cpas_top"; |
| status = "ok"; |
| reg-names = "cam_cpas_top", "cam_camnoc"; |
| reg = <0xac40000 0x1000>, |
| <0xac42000 0x5000>; |
| reg-cam-base = <0x40000 0x42000>; |
| interrupt-names = "cpas_camnoc"; |
| interrupts = <0 459 0>; |
| regulator-names = "camss-vdd"; |
| camss-vdd-supply = <&titan_top_gdsc>; |
| clock-names = "gcc_ahb_clk", |
| "gcc_axi_clk", |
| "soc_ahb_clk", |
| "cpas_ahb_clk", |
| "slow_ahb_clk_src", |
| "camnoc_axi_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
| src-clock-name = "slow_ahb_clk_src"; |
| clock-rates = <0 0 0 0 80000000 0>; |
| qcom,msm-bus,name = "cam_ahb"; |
| qcom,msm-bus,num-cases = <4>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <MSM_BUS_MASTER_AMPSS_M0 |
| MSM_BUS_SLAVE_CAMERA_CFG 0 0>, |
| <MSM_BUS_MASTER_AMPSS_M0 |
| MSM_BUS_SLAVE_CAMERA_CFG 0 300000>, |
| <MSM_BUS_MASTER_AMPSS_M0 |
| MSM_BUS_SLAVE_CAMERA_CFG 0 640000>, |
| <MSM_BUS_MASTER_AMPSS_M0 |
| MSM_BUS_SLAVE_CAMERA_CFG 0 640000>; |
| client-id-based; |
| client-names = |
| "csiphy0", "csiphy1", "csiphy2", "cci0", |
| "csid0", "csid1", "csid2", |
| "ife0", "ife1", "ife2", "ipe0", |
| "ipe1", "cam-cdm-intf0", "cpas-cdm0", "bps0", |
| "icp0", "jpeg-dma0", "jpeg0", "fd0"; |
| client-axi-port-names = |
| "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", |
| "cam_hf_1", "cam_hf_2", "cam_hf_2", |
| "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", |
| "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", |
| "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1"; |
| client-bus-camnoc-based; |
| qcom,axi-port-list { |
| qcom,axi-port1 { |
| qcom,axi-port-name = "cam_hf_1"; |
| qcom,axi-port-mnoc { |
| qcom,msm-bus,name = "cam_hf_1_mnoc"; |
| qcom,msm-bus-vector-dyn-vote; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <MSM_BUS_MASTER_CAMNOC_HF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| <MSM_BUS_MASTER_CAMNOC_HF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| }; |
| qcom,axi-port-camnoc { |
| qcom,msm-bus,name = "cam_hf_1_camnoc"; |
| qcom,msm-bus-vector-dyn-vote; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <MSM_BUS_MASTER_CAMNOC_HF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| <MSM_BUS_MASTER_CAMNOC_HF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| }; |
| }; |
| qcom,axi-port2 { |
| qcom,axi-port-name = "cam_hf_2"; |
| qcom,axi-port-mnoc { |
| qcom,msm-bus,name = "cam_hf_2_mnoc"; |
| qcom,msm-bus-vector-dyn-vote; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <MSM_BUS_MASTER_CAMNOC_HF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| <MSM_BUS_MASTER_CAMNOC_HF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| }; |
| qcom,axi-port-camnoc { |
| qcom,msm-bus,name = "cam_hf_1_camnoc"; |
| qcom,msm-bus-vector-dyn-vote; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <MSM_BUS_MASTER_CAMNOC_HF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| <MSM_BUS_MASTER_CAMNOC_HF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| }; |
| }; |
| qcom,axi-port3 { |
| qcom,axi-port-name = "cam_sf_1"; |
| qcom,axi-port-mnoc { |
| qcom,msm-bus,name = "cam_sf_1_mnoc"; |
| qcom,msm-bus-vector-dyn-vote; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <MSM_BUS_MASTER_CAMNOC_SF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| <MSM_BUS_MASTER_CAMNOC_SF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| }; |
| qcom,axi-port-camnoc { |
| qcom,msm-bus,name = "cam_sf_1_camnoc"; |
| qcom,msm-bus-vector-dyn-vote; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <MSM_BUS_MASTER_CAMNOC_SF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| <MSM_BUS_MASTER_CAMNOC_SF |
| MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| }; |
| }; |
| }; |
| }; |
| |
| qcom,cam-cdm-intf { |
| compatible = "qcom,cam-cdm-intf"; |
| cell-index = <0>; |
| label = "cam-cdm-intf"; |
| num-hw-cdm = <1>; |
| cdm-client-names = "vfe", |
| "jpeg-dma", |
| "jpeg", |
| "fd"; |
| status = "ok"; |
| }; |
| |
| qcom,cpas-cdm0@ac48000 { |
| cell-index = <0>; |
| compatible = "qcom,cam170-cpas-cdm0"; |
| label = "cpas-cdm"; |
| reg = <0xac48000 0x1000>; |
| reg-names = "cpas-cdm"; |
| reg-cam-base = <0x48000>; |
| interrupts = <0 461 0>; |
| interrupt-names = "cpas-cdm"; |
| regulator-names = "camss"; |
| camss-supply = <&titan_top_gdsc>; |
| clock-names = "gcc_camera_ahb", |
| "gcc_camera_axi", |
| "cam_cc_soc_ahb_clk", |
| "cam_cc_cpas_ahb_clk", |
| "cam_cc_camnoc_axi_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
| clock-rates = <0 0 0 0 0>; |
| cdm-client-names = "ife"; |
| status = "ok"; |
| }; |
| |
| qcom,cam-isp { |
| compatible = "qcom,cam-isp"; |
| arch-compat = "ife"; |
| status = "ok"; |
| }; |
| |
| qcom,csid0@acb3000 { |
| cell-index = <0>; |
| compatible = "qcom,csid170"; |
| reg-names = "csid"; |
| reg = <0xacb3000 0x1000>; |
| reg-cam-base = <0xb3000>; |
| interrupt-names = "csid"; |
| interrupts = <0 464 0>; |
| regulator-names = "camss", "ife0"; |
| camss-supply = <&titan_top_gdsc>; |
| ife0-supply = <&ife_0_gdsc>; |
| clock-names = "camera_ahb", |
| "camera_axi", |
| "soc_ahb_clk", |
| "cpas_ahb_clk", |
| "slow_ahb_clk_src", |
| "ife_csid_clk", |
| "ife_csid_clk_src", |
| "ife_cphy_rx_clk", |
| "cphy_rx_clk_src", |
| "ife_clk", |
| "ife_clk_src", |
| "camnoc_axi_clk", |
| "ife_axi_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, |
| <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, |
| <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_0_CLK>, |
| <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, |
| <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; |
| clock-rates = <0 0 0 0 0 0 500000000 0 0 0 60000000 0 0>; |
| src-clock-name = "ife_csid_clk_src"; |
| status = "ok"; |
| }; |
| |
| qcom,vfe0@acaf000 { |
| cell-index = <0>; |
| compatible = "qcom,vfe170"; |
| reg-names = "ife"; |
| reg = <0xacaf000 0x4000>; |
| reg-cam-base = <0xaf000>; |
| interrupt-names = "ife"; |
| interrupts = <0 465 0>; |
| regulator-names = "camss", "ife0"; |
| camss-supply = <&titan_top_gdsc>; |
| ife0-supply = <&ife_0_gdsc>; |
| clock-names = "camera_ahb", |
| "camera_axi", |
| "soc_ahb_clk", |
| "cpas_ahb_clk", |
| "slow_ahb_clk_src", |
| "ife_clk", |
| "ife_clk_src", |
| "camnoc_axi_clk", |
| "ife_axi_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_0_CLK>, |
| <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, |
| <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; |
| clock-rates = <0 0 0 0 0 0 600000000 0 0>; |
| src-clock-name = "ife_clk_src"; |
| clock-names-option = "ife_dsp_clk"; |
| clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; |
| clock-rates-option = <404000000>; |
| status = "ok"; |
| }; |
| |
| qcom,csid1@acba000 { |
| cell-index = <1>; |
| compatible = "qcom,csid170"; |
| reg-names = "csid"; |
| reg = <0xacba000 0x1000>; |
| reg-cam-base = <0xba000>; |
| interrupt-names = "csid"; |
| interrupts = <0 466 0>; |
| regulator-names = "camss", "ife1"; |
| camss-supply = <&titan_top_gdsc>; |
| ife1-supply = <&ife_1_gdsc>; |
| clock-names = "camera_ahb", |
| "camera_axi", |
| "soc_ahb_clk", |
| "cpas_ahb_clk", |
| "slow_ahb_clk_src", |
| "ife_csid_clk", |
| "ife_csid_clk_src", |
| "ife_cphy_rx_clk", |
| "cphy_rx_clk_src", |
| "ife_clk", |
| "ife_clk_src", |
| "camnoc_axi_clk", |
| "ife_axi_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, |
| <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, |
| <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_1_CLK>, |
| <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, |
| <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; |
| clock-rates = <0 0 0 0 0 0 500000000 0 0 0 60000000 0 0>; |
| src-clock-name = "ife_csid_clk_src"; |
| status = "ok"; |
| }; |
| |
| qcom,vfe1@acb6000 { |
| cell-index = <1>; |
| compatible = "qcom,vfe170"; |
| reg-names = "ife"; |
| reg = <0xacb6000 0x4000>; |
| reg-cam-base = <0xb6000>; |
| interrupt-names = "ife"; |
| interrupts = <0 467 0>; |
| regulator-names = "camss", "ife1"; |
| camss-supply = <&titan_top_gdsc>; |
| ife1-supply = <&ife_1_gdsc>; |
| clock-names = "camera_ahb", |
| "camera_axi", |
| "soc_ahb_clk", |
| "cpas_ahb_clk", |
| "slow_ahb_clk_src", |
| "ife_clk", |
| "ife_clk_src", |
| "camnoc_axi_clk", |
| "ife_axi_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_1_CLK>, |
| <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, |
| <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; |
| clock-rates = <0 0 0 0 0 0 600000000 0 0>; |
| src-clock-name = "ife_clk_src"; |
| clock-names-option = "ife_dsp_clk"; |
| clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; |
| clock-rates-option = <404000000>; |
| status = "ok"; |
| }; |
| |
| qcom,csid-lite@acc8000 { |
| cell-index = <2>; |
| compatible = "qcom,csid-lite170"; |
| reg-names = "csid-lite"; |
| reg = <0xacc8000 0x1000>; |
| reg-cam-base = <0xc8000>; |
| interrupt-names = "csid-lite"; |
| interrupts = <0 468 0>; |
| regulator-names = "camss"; |
| camss-supply = <&titan_top_gdsc>; |
| clock-names = "camera_ahb", |
| "camera_axi", |
| "soc_ahb_clk", |
| "cpas_ahb_clk", |
| "slow_ahb_clk_src", |
| "ife_csid_clk", |
| "ife_csid_clk_src", |
| "ife_cphy_rx_clk", |
| "cphy_rx_clk_src", |
| "ife_clk", |
| "ife_clk_src", |
| "camnoc_axi_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, |
| <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, |
| <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_LITE_CLK>, |
| <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, |
| <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
| clock-rates = <0 0 0 0 0 0 384000000 0 0 0 40400000 0>; |
| src-clock-name = "ife_csid_clk_src"; |
| status = "ok"; |
| }; |
| |
| qcom,vfe-lite@acc4000 { |
| cell-index = <2>; |
| compatible = "qcom,vfe-lite170"; |
| reg-names = "ife-lite"; |
| reg = <0xacc4000 0x4000>; |
| reg-cam-base = <0xc4000>; |
| interrupt-names = "ife-lite"; |
| interrupts = <0 469 0>; |
| regulator-names = "camss"; |
| camss-supply = <&titan_top_gdsc>; |
| clock-names = "camera_ahb", |
| "camera_axi", |
| "soc_ahb_clk", |
| "cpas_ahb_clk", |
| "slow_ahb_clk_src", |
| "ife_clk", |
| "ife_clk_src", |
| "camnoc_axi_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| <&clock_camcc CAM_CC_IFE_LITE_CLK>, |
| <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, |
| <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
| qcom,clock-rates = <0 0 0 0 0 0 404000000 0>; |
| src-clock-name = "ife_clk_src"; |
| status = "ok"; |
| }; |
| |
| qcom,cam-icp { |
| compatible = "qcom,cam-icp"; |
| compat-hw-name = "qcom,a5", |
| "qcom,ipe0", |
| "qcom,ipe1", |
| "qcom,bps"; |
| num-a5 = <1>; |
| num-ipe = <2>; |
| num-bps = <1>; |
| status = "ok"; |
| }; |
| |
| qcom,a5@ac00000 { |
| cell-index = <0>; |
| compatible = "qcom,cam_a5"; |
| reg = <0xac00000 0x6000>, |
| <0xac10000 0x8000>, |
| <0xac18000 0x3000>; |
| reg-names = "a5_qgic", "a5_sierra", "a5_csr"; |
| reg-cam-base = <0x00000 0x10000 0x18000>; |
| interrupts = <0 463 0>; |
| interrupt-names = "a5"; |
| regulator-names = "camss-vdd"; |
| camss-vdd-supply = <&titan_top_gdsc>; |
| clock-names = "gcc_cam_ahb_clk", |
| "gcc_cam_axi_clk", |
| "soc_ahb_clk", |
| "cpas_ahb_clk", |
| "camnoc_axi_clk", |
| "icp_apb_clk", |
| "icp_clk", |
| "icp_clk_src"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| <&clock_camcc CAM_CC_ICP_APB_CLK>, |
| <&clock_camcc CAM_CC_ICP_CLK>, |
| <&clock_camcc CAM_CC_ICP_CLK_SRC>; |
| |
| clock-rates = <0 0 0 80000000 0 0 0 600000000>; |
| fw_name = "CAMERA_ICP.elf"; |
| status = "ok"; |
| }; |
| |
| qcom,ipe0 { |
| cell-index = <0>; |
| compatible = "qcom,cam_ipe"; |
| regulator-names = "ipe0-vdd"; |
| ipe0-vdd-supply = <&ipe_0_gdsc>; |
| clock-names = "ipe_0_ahb_clk", |
| "ipe_0_areg_clk", |
| "ipe_0_axi_clk", |
| "ipe_0_clk", |
| "ipe_0_clk_src"; |
| clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, |
| <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, |
| <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, |
| <&clock_camcc CAM_CC_IPE_0_CLK>, |
| <&clock_camcc CAM_CC_IPE_0_CLK_SRC>; |
| |
| clock-rates = <80000000 400000000 0 0 600000000>; |
| status = "ok"; |
| }; |
| |
| qcom,ipe1 { |
| cell-index = <1>; |
| compatible = "qcom,cam_ipe"; |
| regulator-names = "ipe1-vdd"; |
| ipe1-vdd-supply = <&ipe_1_gdsc>; |
| clock-names = "ipe_1_ahb_clk", |
| "ipe_1_areg_clk", |
| "ipe_1_axi_clk", |
| "ipe_1_clk", |
| "ipe_1_clk_src"; |
| clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>, |
| <&clock_camcc CAM_CC_IPE_1_AREG_CLK>, |
| <&clock_camcc CAM_CC_IPE_1_AXI_CLK>, |
| <&clock_camcc CAM_CC_IPE_1_CLK>, |
| <&clock_camcc CAM_CC_IPE_1_CLK_SRC>; |
| |
| clock-rates = <80000000 400000000 0 0 600000000>; |
| status = "ok"; |
| }; |
| |
| qcom,bps { |
| cell-index = <0>; |
| compatible = "qcom,cam_bps"; |
| regulator-names = "bps-vdd"; |
| bps-vdd-supply = <&bps_gdsc>; |
| clock-names = "bps_ahb_clk", |
| "bps_areg_clk", |
| "bps_axi_clk", |
| "bps_clk", |
| "bps_clk_src"; |
| clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>, |
| <&clock_camcc CAM_CC_BPS_AREG_CLK>, |
| <&clock_camcc CAM_CC_BPS_AXI_CLK>, |
| <&clock_camcc CAM_CC_BPS_CLK>, |
| <&clock_camcc CAM_CC_BPS_CLK_SRC>; |
| |
| clock-rates = <80000000 400000000 0 0 600000000>; |
| status = "ok"; |
| }; |
| }; |