clk: qcom: clk-cpu-osm: Rework the MEM_ACC_LEVEL setting logic
The MEM_ACC_LEVEL settings that the OSM driver is currently
programming are off from those listed in the voltage plan.
Correct this.
Change-Id: I26c9907c4deb96dd84f57c84a3737b11996ccd04
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi b/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi
index 0ef6bfa..a154ffd 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi
@@ -537,6 +537,13 @@
< 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
< 2630400000 0x40541d89 0x00006e6e 0x2 30 >,
< 2707200000 0x40541e8d 0x00007171 0x2 31 >;
+
+ qcom,l3-memacc-level-vc-bin0 = <8 13>;
+
+ qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;
+
+ qcom,perfcl-memacc-level-vc-bin0 = <14 22>;
+ qcom,perfcl-memacc-level-vc-bin1 = <14 22>;
};
&clock_gcc {