| Qualcomm Application A7 CPU clock driver |
| ------------------------------------- |
| |
| It is the clock controller driver which provides higher frequency |
| clocks and allows A7 CPU frequency scaling on sdxpoorwills based platforms. |
| |
| Required properties: |
| - compatible : shall contain only one of the following: |
| "qcom,cpu-sdxpoorwills", |
| - clocks : Phandle to the clock device. |
| - clock-names: Names of the used clocks. |
| - qcom,a7cc-init-rate = Initial rate which needs to be set from cpu driver. |
| - reg : shall contain base register offset and size. |
| - reg-names : Names of the bases for the above registers. |
| - vdd_dig_ao-supply : The regulator powering the APSS PLL. |
| - cpu-vdd-supply : The regulator powering the APSS RCG. |
| - qcom,rcg-reg-offset : Register offset for APSS RCG. |
| - qcom,speedX-bin-vZ : A table of CPU frequency (Hz) to regulator voltage (uV) mapping. |
| Format: <freq uV> |
| This represents the max frequency possible for each possible |
| power configuration for a CPU that's binned as speed bin X, |
| speed bin revision Z. Speed bin values can be between [0-7] |
| and the version can be between [0-3]. |
| - #clock-cells : shall contain 1. |
| |
| Optional properties : |
| - reg-names: "efuse", |
| |
| Example: |
| clock_cpu: qcom,clock-a7@17808100 { |
| compatible = "qcom,cpu-sdxpoorwills"; |
| clocks = <&clock_rpmh RPMH_CXO_CLK_A>; |
| clock-names = "xo_ao"; |
| qcom,a7cc-init-rate = <1497600000>; |
| reg = <0x17808100 0x7F10>; |
| reg-names = "apcs_pll"; |
| |
| vdd_dig_ao-supply = <&pmxpoorwills_s5_level_ao>; |
| cpu-vdd-supply = <&pmxpoorwills_s5_level_ao>; |
| qcom,rcg-reg-offset = <0x7F08>; |
| qcom,speed0-bin-v0 = |
| < 0 RPMH_REGULATOR_LEVEL_OFF>, |
| < 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>, |
| < 576000000 RPMH_REGULATOR_LEVEL_SVS>, |
| < 1094400000 RPMH_REGULATOR_LEVEL_NOM>, |
| < 1497600000 RPMH_REGULATOR_LEVEL_TURBO>; |
| #clock-cells = <1>; |
| }; |