Documentation/devicetree/bindings/thermal/qcom-lmh-dcvs.txt

Limits Management Hardware - DCVS

The LMH-DCVS block is a hardware IP for every CPU cluster, to handle quick
changes in thermal limits. The hardware responds to thermal variation amongst
the CPUs in the cluster by requesting limits on the clock frequency and
voltage on the OSM hardware.

The LMH DCVS driver exports a virtual sensor that can be used to set the
thermal limits on the hardware. LMH DCVS driver can be a platform CPU Cooling
device, which registers with the CPU cooling device interface. All CPU device
nodes should reference the corresponding LMH DCVS hardware in device tree.
CPUs referencing the same LMH DCVS node will be associated with the
corresponding cooling device as related CPUs.

Properties:

- compatible:
	Usage: required
	Value type: <string>
	Definition: shall be "qcom,msm-hw-limits"
- interrupts:
	Usage: required
	Value type: <interrupt_type interrupt_number interrupt_trigger_type>
	Definition: Should specify interrupt information about the debug
			interrupt generated by the LMH DCVSh hardware. LMH
			DCVSh hardware will generate this interrupt whenever
			it makes a new cpu DCVS decision.
- qcom,affinity:
	Usage: Required
	Value type: <u32>
	Definition: Should specify the cluster affinity this hardware
			corresponds to.

Example:

	lmh_dcvs0: qcom,limits-dcvs@0 {
		compatible = "qcom,msm-hw-limits";
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		qcom,affinity = <0>;
	};

	CPU0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,armv8";
		reg = <0x0 0x0>;
		qcom,lmh-dcvs = <&lmh_dcvs0>;;
	};