| ========================================== |
| ARM processors cache binding description |
| ========================================== |
| |
| Device tree bindings for ARM processor caches adhere to the cache bindings |
| described in [3], in section 3.8 for multi-level and shared caches. |
| On ARM based systems most of the cache properties related to cache |
| geometry are probeable in HW, hence, unless otherwise stated, the properties |
| defined in ePAPR for multi-level and shared caches are to be considered |
| optional by default. |
| |
| On ARM, caches are either architected (directly controlled by the processor |
| through coprocessor instructions and tightly coupled with the processor |
| implementation) or unarchitected (controlled through a memory mapped |
| interface, implemented as a stand-alone IP external to the processor |
| implementation). |
| |
| This document provides the device tree bindings for ARM architected caches. |
| |
| - ARM architected cache node |
| |
| Description: must be a direct child of the cpu node. A system |
| can contain multiple architected cache nodes per cpu node, |
| linked through the next-level-cache phandle. The |
| next-level-cache property in the cpu node points to |
| the first level of architected cache for the CPU. |
| The next-level-cache property in architected cache nodes |
| points to the respective next level of caching in the |
| hierarchy. An architected cache node with an empty or |
| missing next-level-cache property represents the last |
| architected cache level for the CPU. |
| On ARM v7 and v8 architectures, the order in which cache |
| nodes are linked through the next-level-cache phandle must |
| follow the ordering specified in the processors CLIDR (v7) |
| and CLIDR_EL1 (v8) registers, as described in [1][2], |
| implying that a cache node pointed at by a |
| next-level-cache phandle must correspond to a level |
| defined in CLIDR (v7) and CLIDR_EL1 (v8) greater than the |
| one the cache node containing the next-level-cache |
| phandle corresponds to. |
| |
| Since on ARM most of the cache properties are probeable in HW the |
| properties described in [3] - section 3.8 multi-level and shared |
| caches - shall be considered optional, with the following properties |
| updates, specific for the ARM architected cache node. |
| |
| - compatible |
| Usage: Required |
| Value type: <string> |
| Definition: value shall be "arm,arch-cache". |
| |
| - interrupts |
| Usage: Optional |
| Value type: See definition |
| Definition: standard device tree property [3] that defines |
| the interrupt line associated with the cache. |
| The property can be accompanied by an |
| interrupt-names property, as described in [4]. |
| |
| - power-domain |
| Usage: Optional |
| Value type: phandle |
| Definition: A phandle and power domain specifier as defined by |
| bindings of power controller specified by the |
| phandle [5]. |
| |
| - qcom,dump-size |
| Usage: Optional |
| Value type: <integer> |
| Definition: The memory size needed to contain a copy of the |
| cache data and associated tag ram. |
| size = nways * nsets * (bytes per cache line + |
| bytes tag ram per line) |
| |
| Example(dual-cluster big.LITTLE system 32-bit) |
| |
| cpus { |
| #size-cells = <0>; |
| #address-cells = <1>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x0>; |
| next-level-cache = <&L1_0>; |
| |
| L1_0: l1-cache { |
| compatible = "arm,arch-cache"; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| L2_0: l2-cache { |
| compatible = "arm,arch-cache"; |
| }; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x1>; |
| next-level-cache = <&L1_1>; |
| |
| L1_1: l1-cache { |
| compatible = "arm,arch-cache"; |
| next-level-cache = <&L2_0>; |
| }; |
| }; |
| |
| cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x2>; |
| next-level-cache = <&L1_2>; |
| |
| L1_2: l1-cache { |
| compatible = "arm,arch-cache"; |
| next-level-cache = <&L2_0>; |
| }; |
| }; |
| |
| cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x3>; |
| next-level-cache = <&L1_3>; |
| |
| L1_3: l1-cache { |
| compatible = "arm,arch-cache"; |
| next-level-cache = <&L2_0>; |
| }; |
| }; |
| |
| cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x100>; |
| next-level-cache = <&L1_4>; |
| |
| L1_4: l1-cache { |
| compatible = "arm,arch-cache"; |
| next-level-cache = <&L2_1>; |
| }; |
| |
| L2_1: l2-cache { |
| compatible = "arm,arch-cache"; |
| }; |
| }; |
| |
| cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x101>; |
| next-level-cache = <&L1_5>; |
| |
| L1_5: l1-cache { |
| compatible = "arm,arch-cache"; |
| next-level-cache = <&L2_1>; |
| }; |
| }; |
| |
| cpu@102 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x102>; |
| next-level-cache = <&L1_6>; |
| |
| L1_6: l1-cache { |
| compatible = "arm,arch-cache"; |
| next-level-cache = <&L2_1>; |
| }; |
| }; |
| |
| cpu@103 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0x103>; |
| next-level-cache = <&L1_7>; |
| |
| L1_7: l1-cache { |
| compatible = "arm,arch-cache"; |
| next-level-cache = <&L2_1>; |
| }; |
| }; |
| }; |
| |
| [1] ARMv7-AR Reference Manual |
| http://infocenter.arm.com/help/index.jsp |
| [2] ARMv8-A Reference Manual |
| http://infocenter.arm.com/help/index.jsp |
| [3] ePAPR standard |
| https://www.power.org/documentation/epapr-version-1-1/ |
| [4] Kernel documentation - resource property bindings |
| Documentation/devicetree/bindings/resource-names.txt |
| [5] Kernel documentation - power domain bindings |
| Documentation/devicetree/bindings/power/power_domain.txt |