commit 4b058d07da56ad2d460ba91d2cdc3aa398b1c270
author Yuan Zhao <yzhao@codeaurora.org> Mon Jul 15 19:59:47 2019 +0800
committer Gerrit - the friendly Code Review server <code-review@localhost> Thu Jul 25 22:22:26 2019 -0700
tree 4058d6ebef6a7216172e0cbbc3cfd389705caef4
parent 93bc65b1457d229906e962be4a6e4cf3a3d9994c

ARM: dts: msm: Enable LT9611 for SDM845 RB3

RB3 used LT9611 external brdige for the primary
display. Enable LT9611 support.

Change-Id: I655aebd673c482571702849755018058c8b307de
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>

arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi
index a7a234a..86320c3 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi
@@ -893,6 +893,21 @@
 			};
 		};
 
+		ext_bridge_mux {
+			lt9611_pins: lt9611_pins {
+				mux {
+					pins = "gpio84", "gpio128", "gpio89";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio84", "gpio128", "gpio89";
+					bias-disable = <0>; /* no pull */
+					drive-strength = <8>;
+				};
+			};
+		};
+
 		sec_aux_pcm {
 			sec_aux_pcm_sleep: sec_aux_pcm_sleep {
 				mux {

arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
index 7735237..aa3976d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
@@ -527,6 +527,29 @@
 		ibb-supply = <&ibb_regulator>;
 	};
 
+	ext_dsi_bridge_display: qcom,dsi-display@19 {
+		compatible = "qcom,dsi-display";
+		label = "ext_dsi_bridge_display";
+		qcom,display-type = "primary";
+
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+		       <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
+		clock-names = "mux_byte_clk", "mux_pixel_clk";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				ext_dsi_out: endpoint {
+				};
+			};
+		};
+	};
+
 	sde_wb: qcom,wb-display@0 {
 		compatible = "qcom,wb-display";
 		cell-index = <0>;

arch/arm64/boot/dts/qcom/sdm845-v2.1-rb3.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-rb3.dtsi b/arch/arm64/boot/dts/qcom/sdm845-v2.1-rb3.dtsi
index e1159d3..cf84ecf 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-v2.1-rb3.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-rb3.dtsi
@@ -204,3 +204,96 @@
 &ipa_hw {
 	status="disabled";
 };
+
+&dsi_nt35597_truly_dsc_cmd_display {
+	/delete-property/ qcom,dsi-display-active;
+};
+
+&mdss_mdp {
+	bridges = <&lt9611>;
+};
+
+&soc {
+	lt9611_vcc_eldo: lt9611-gpio-regulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "lt9611_vcc_eldo";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-enable-ramp-delay = <233>;
+		gpio = <&tlmm 89 0>;
+		enable-active-high;
+	};
+};
+
+&qupv3_se10_i2c {
+	status = "ok";
+	lt9611: lt,lt9611@3b {
+		compatible = "lt,lt9611";
+		reg = <0x3b>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <84 0>;
+		interrupt-names = "lt_irq";
+		lt,irq-gpio = <&tlmm 84 0x0>;
+		lt,reset-gpio = <&tlmm 128 0x0>;
+		lt,non-pluggable;
+		lt,preferred-mode = "1920x1080";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&lt9611_pins>;
+
+		vdd-supply = <&lt9611_vcc_eldo>;
+		lt,supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			lt,supply-entry@0 {
+				reg = <0>;
+				lt,supply-name = "vdd";
+				lt,supply-min-voltage = <1800000>;
+				lt,supply-max-voltage = <1800000>;
+				lt,supply-enable-load = <200000>;
+				lt,supply-post-on-sleep = <150>;
+			};
+		};
+
+		lt,customize-modes {
+			lt,customize-mode-id@0 {
+				lt,mode-h-active = <1920>;
+				lt,mode-h-front-porch = <88>;
+				lt,mode-h-pulse-width = <44>;
+				lt,mode-h-back-porch = <148>;
+				lt,mode-h-active-high;
+				lt,mode-v-active = <1080>;
+				lt,mode-v-front-porch = <4>;
+				lt,mode-v-pulse-width = <5>;
+				lt,mode-v-back-porch = <36>;
+				lt,mode-v-active-high;
+				lt,mode-refresh-rate = <60>;
+				lt,mode-clock-in-khz = <148500>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				lt9611_in: endpoint {
+					remote-endpoint = <&ext_dsi_out>;
+				};
+			};
+		};
+	};
+};
+
+&ext_dsi_bridge_display {
+	qcom,dsi-display-active;
+	ports {
+		port@0 {
+			ext_dsi_out: endpoint {
+				remote-endpoint = <&lt9611_in>;
+			};
+		};
+	};
+};