| /dts-v1/; |
| |
| #include "tegra124.dtsi" |
| |
| / { |
| model = "NVIDIA Tegra124 Venice2"; |
| compatible = "nvidia,venice2", "nvidia,tegra124"; |
| |
| memory { |
| reg = <0x80000000 0x80000000>; |
| }; |
| |
| pinmux: pinmux@70000868 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinmux_default>; |
| |
| pinmux_default: common { |
| dap_mclk1_pw4 { |
| nvidia,pins = "dap_mclk1_pw4"; |
| nvidia,function = "extperiph1"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| dap1_din_pn1 { |
| nvidia,pins = "dap1_din_pn1", |
| "dap1_dout_pn2", |
| "dap1_fs_pn0", |
| "dap1_sclk_pn3"; |
| nvidia,function = "i2s0"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| }; |
| dap2_din_pa4 { |
| nvidia,pins = "dap2_din_pa4", |
| "dap2_dout_pa5", |
| "dap2_fs_pa2", |
| "dap2_sclk_pa3"; |
| nvidia,function = "i2s1"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| }; |
| dvfs_pwm_px0 { |
| nvidia,pins = "dvfs_pwm_px0"; |
| nvidia,function = "cldvfs"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| }; |
| dvfs_clk_px2 { |
| nvidia,pins = "dvfs_clk_px2"; |
| nvidia,function = "cldvfs"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| ulpi_clk_py0 { |
| nvidia,pins = "ulpi_clk_py0", |
| "ulpi_dir_py1", |
| "ulpi_nxt_py2", |
| "ulpi_stp_py3"; |
| nvidia,function = "spi1"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| cam_i2c_scl_pbb1 { |
| nvidia,pins = "cam_i2c_scl_pbb1", |
| "cam_i2c_sda_pbb2"; |
| nvidia,function = "i2c3"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| }; |
| gen2_i2c_scl_pt5 { |
| nvidia,pins = "gen2_i2c_scl_pt5", |
| "gen2_i2c_sda_pt6"; |
| nvidia,function = "i2c2"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| }; |
| pg4 { |
| nvidia,pins = "pg4", |
| "pg5", |
| "pg6", |
| "pg7", |
| "pi3"; |
| nvidia,function = "spi4"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| ph0 { |
| nvidia,pins = "ph0"; |
| nvidia,function = "pwm0"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| }; |
| ph1 { |
| nvidia,pins = "ph1"; |
| nvidia,function = "pwm1"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc1_clk_pz0 { |
| nvidia,pins = "sdmmc1_clk_pz0", |
| "sdmmc1_cmd_pz1", |
| "sdmmc1_dat0_py7", |
| "sdmmc1_dat1_py6", |
| "sdmmc1_dat2_py5", |
| "sdmmc1_dat3_py4"; |
| nvidia,function = "sdmmc1"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_clk_pa6 { |
| nvidia,pins = "sdmmc3_clk_pa6"; |
| nvidia,function = "sdmmc3"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_cmd_pa7 { |
| nvidia,pins = "sdmmc3_cmd_pa7", |
| "sdmmc3_dat0_pb7", |
| "sdmmc3_dat1_pb6", |
| "sdmmc3_dat2_pb5", |
| "sdmmc3_dat3_pb4", |
| "sdmmc3_clk_lb_out_pee4", |
| "sdmmc3_clk_lb_in_pee5"; |
| nvidia,function = "sdmmc3"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc4_clk_pcc4 { |
| nvidia,pins = "sdmmc4_clk_pcc4"; |
| nvidia,function = "sdmmc4"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc4_cmd_pt7 { |
| nvidia,pins = "sdmmc4_cmd_pt7", |
| "sdmmc4_dat0_paa0", |
| "sdmmc4_dat1_paa1", |
| "sdmmc4_dat2_paa2", |
| "sdmmc4_dat3_paa3", |
| "sdmmc4_dat4_paa4", |
| "sdmmc4_dat5_paa5", |
| "sdmmc4_dat6_paa6", |
| "sdmmc4_dat7_paa7"; |
| nvidia,function = "sdmmc4"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| pwr_i2c_scl_pz6 { |
| nvidia,pins = "pwr_i2c_scl_pz6", |
| "pwr_i2c_sda_pz7"; |
| nvidia,function = "i2cpwr"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| }; |
| jtag_rtck { |
| nvidia,pins = "jtag_rtck"; |
| nvidia,function = "rtck"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| clk_32k_in { |
| nvidia,pins = "clk_32k_in"; |
| nvidia,function = "clk"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| core_pwr_req { |
| nvidia,pins = "core_pwr_req"; |
| nvidia,function = "pwron"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| cpu_pwr_req { |
| nvidia,pins = "cpu_pwr_req"; |
| nvidia,function = "cpu"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| pwr_int_n { |
| nvidia,pins = "pwr_int_n"; |
| nvidia,function = "pmi"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| reset_out_n { |
| nvidia,pins = "reset_out_n"; |
| nvidia,function = "reset_out_n"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| clk3_out_pee0 { |
| nvidia,pins = "clk3_out_pee0"; |
| nvidia,function = "extperiph3"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| dap4_din_pp5 { |
| nvidia,pins = "dap4_din_pp5", |
| "dap4_dout_pp6", |
| "dap4_fs_pp4", |
| "dap4_sclk_pp7"; |
| nvidia,function = "i2s3"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| }; |
| gen1_i2c_sda_pc5 { |
| nvidia,pins = "gen1_i2c_sda_pc5", |
| "gen1_i2c_scl_pc4"; |
| nvidia,function = "i2c1"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| pu0 { |
| nvidia,pins = "pu0", |
| "pu1", |
| "pu2", |
| "pu3"; |
| nvidia,function = "uarta"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| uart2_cts_n_pj5 { |
| nvidia,pins = "uart2_cts_n_pj5", |
| "uart2_rts_n_pj6"; |
| nvidia,function = "uartb"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| uart2_rxd_pc3 { |
| nvidia,pins = "uart2_rxd_pc3", |
| "uart2_txd_pc2"; |
| nvidia,function = "irda"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| uart3_cts_n_pa1 { |
| nvidia,pins = "uart3_cts_n_pa1", |
| "uart3_rts_n_pc0", |
| "uart3_rxd_pw7", |
| "uart3_txd_pw6"; |
| nvidia,function = "uartc"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| hdmi_cec_pee3 { |
| nvidia,pins = "hdmi_cec_pee3"; |
| nvidia,function = "cec"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| }; |
| ddc_scl_pv4 { |
| nvidia,pins = "ddc_scl_pv4", |
| "ddc_sda_pv5"; |
| nvidia,function = "i2c4"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| usb_vbus_en0_pn4 { |
| nvidia,pins = "usb_vbus_en0_pn4"; |
| nvidia,function = "usb"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| usb_vbus_en1_pn5 { |
| nvidia,pins = "usb_vbus_en1_pn5"; |
| nvidia,function = "usb"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| drive_sdio1 { |
| nvidia,pins = "drive_sdio1"; |
| nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| nvidia,pull-down-strength = <32>; |
| nvidia,pull-up-strength = <42>; |
| nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| }; |
| drive_sdio3 { |
| nvidia,pins = "drive_sdio3"; |
| nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| nvidia,pull-down-strength = <20>; |
| nvidia,pull-up-strength = <36>; |
| nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| }; |
| drive_gma { |
| nvidia,pins = "drive_gma"; |
| nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| nvidia,pull-down-strength = <1>; |
| nvidia,pull-up-strength = <2>; |
| nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| nvidia,drive-type = <1>; |
| }; |
| }; |
| }; |
| |
| serial@70006000 { |
| status = "okay"; |
| }; |
| |
| pwm: pwm@7000a000 { |
| status = "okay"; |
| }; |
| |
| i2c@7000c000 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| |
| acodec: audio-codec@10 { |
| compatible = "maxim,max98090"; |
| reg = <0x10>; |
| interrupt-parent = <&gpio>; |
| interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; |
| }; |
| }; |
| |
| i2c@7000c400 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c@7000c500 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c@7000c700 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c@7000d000 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| pmc@7000e400 { |
| nvidia,invert-interrupt; |
| nvidia,suspend-mode = <1>; |
| nvidia,cpu-pwr-good-time = <500>; |
| nvidia,cpu-pwr-off-time = <300>; |
| nvidia,core-pwr-good-time = <641 3845>; |
| nvidia,core-pwr-off-time = <61036>; |
| nvidia,core-power-req-active-high; |
| nvidia,sys-clock-req-active-high; |
| }; |
| |
| sdhci@700b0400 { |
| cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
| power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| bus-width = <4>; |
| }; |
| |
| sdhci@700b0600 { |
| status = "okay"; |
| bus-width = <8>; |
| }; |
| |
| ahub@70300000 { |
| i2s@70301100 { |
| status = "okay"; |
| }; |
| }; |
| |
| clocks { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| clk32k_in: clock@0 { |
| compatible = "fixed-clock"; |
| reg=<0>; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| }; |
| }; |
| |
| sound { |
| compatible = "nvidia,tegra-audio-max98090-venice2", |
| "nvidia,tegra-audio-max98090"; |
| nvidia,model = "NVIDIA Tegra Venice2"; |
| |
| nvidia,audio-routing = |
| "Headphones", "HPR", |
| "Headphones", "HPL", |
| "Speakers", "SPKR", |
| "Speakers", "SPKL", |
| "Mic Jack", "MICBIAS", |
| "IN34", "Mic Jack"; |
| |
| nvidia,i2s-controller = <&tegra_i2s1>; |
| nvidia,audio-codec = <&acodec>; |
| |
| clocks = <&tegra_car TEGRA124_CLK_PLL_A>, |
| <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, |
| <&tegra_car TEGRA124_CLK_EXTERN1>; |
| clock-names = "pll_a", "pll_a_out0", "mclk"; |
| }; |
| }; |