| commit | 4bfe6b6876a036d26a960320f1ab0bbd752c19bf | [log] [tgz] |
|---|---|---|
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | Mon Nov 02 07:52:29 2009 +0000 |
| committer | Eric Anholt <eric@anholt.net> | Thu Nov 05 14:00:32 2009 -0800 |
| tree | a148753cbfea2eee98989d253b9ca572a7873023 | |
| parent | ba86bf8bfc1add5f515db8cf1d6042bb9396a299 [diff] |
drm/i915: Fix and cleanup DPLL calculation for Ironlake When the ideal error range can't be reached, this will safely use a most closed one. Clean up some dumb codes in DPLL function too. This fixes DPLL clock issue against one monitor at 1680x1050@60hz. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>