Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] vpe: Add missing "space"
[MIPS] Compliment va_start() with va_end().
[MIPS] IP22: Fix broken eeprom access by using __raw_readl/__raw_writel
[MIPS] IP22: Fix broken EISA interrupt setup by switching to generic i8259
[MIPS] 64-bit Sibyte kernels need DMA32.
[MIPS] Only build r4k clocksource for systems that work ok with it.
[MIPS] Handle R4000/R4400 mfc0 from count register.
[MIPS] Fix possible hang in LL/SC futex loops.
[MIPS] Fix context DSP context / TLS pointer switching bug for new threads.
[MIPS] IP32: More interrupt renumbering fixes.
[MIPS] time: MIPSsim's plat_time_init doesn't need to be irq safe.
[MIPS] time: Fix negated condition in cevt-r4k driver.
[MIPS] Fix pcspeaker build.
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2f2ce0c..455bd1f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -22,6 +22,7 @@
config BASLER_EXCITE
bool "Basler eXcite smart camera"
select CEVT_R4K
+ select CSRC_R4K
select DMA_COHERENT
select HW_HAS_PCI
select IRQ_CPU
@@ -49,6 +50,7 @@
config BCM47XX
bool "BCM47XX based boards"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
@@ -66,6 +68,7 @@
config MIPS_COBALT
bool "Cobalt Server"
select CEVT_R4K
+ select CSRC_R4K
select CEVT_GT641XX
select DMA_NONCOHERENT
select HW_HAS_PCI
@@ -85,6 +88,7 @@
bool "DECstations"
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select NO_IOPORT
select IRQ_CPU
@@ -117,6 +121,7 @@
select ARC32
select ARCH_MAY_HAVE_PC_FDC
select CEVT_R4K
+ select CSRC_R4K
select GENERIC_ISA_DMA
select IRQ_CPU
select I8253
@@ -137,6 +142,7 @@
config LASAT
bool "LASAT Networks platforms"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select HW_HAS_PCI
@@ -154,6 +160,7 @@
bool "Lemote Fulong mini-PC"
select ARCH_SPARSEMEM_ENABLE
select CEVT_R4K
+ select CSRC_R4K
select SYS_HAS_CPU_LOONGSON2
select DMA_NONCOHERENT
select BOOT_ELF32
@@ -179,6 +186,7 @@
bool "MIPS Atlas board"
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select IRQ_CPU
@@ -210,6 +218,7 @@
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select IRQ_CPU
@@ -241,6 +250,7 @@
config MIPS_SEAD
bool "MIPS SEAD board"
select CEVT_R4K
+ select CSRC_R4K
select IRQ_CPU
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
@@ -260,6 +270,7 @@
config MIPS_SIM
bool 'MIPS simulator (MIPSsim)'
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select SYS_HAS_EARLY_PRINTK
select IRQ_CPU
@@ -278,6 +289,7 @@
config MARKEINS
bool "NEC EMMA2RH Mark-eins"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
@@ -293,6 +305,7 @@
config MACH_VR41XX
bool "NEC VR4100 series based machines"
select CEVT_R4K
+ select CSRC_R4K
select SYS_HAS_CPU_VR41XX
select GENERIC_HARDIRQS_NO__DO_IRQ
@@ -330,6 +343,7 @@
config PMC_YOSEMITE
bool "PMC-Sierra Yosemite eval board"
select CEVT_R4K
+ select CSRC_R4K
select DMA_COHERENT
select HW_HAS_PCI
select IRQ_CPU
@@ -351,6 +365,7 @@
config QEMU
bool "Qemu"
select CEVT_R4K
+ select CSRC_R4K
select DMA_COHERENT
select GENERIC_ISA_DMA
select HAVE_STD_PC_SERIAL_PORT
@@ -382,9 +397,11 @@
select ARC32
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_EISA
select I8253
+ select I8259
select IP22_CPU_SCACHE
select IRQ_CPU
select GENERIC_ISA_DMA_SUPPORT_BROKEN
@@ -427,6 +444,7 @@
select ARC32
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
@@ -498,6 +516,7 @@
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_KGDB
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select ZONE_DMA32 if 64BIT
config SIBYTE_LITTLESUR
bool "Sibyte BCM91250C2-LittleSur"
@@ -548,6 +567,7 @@
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
+ select ZONE_DMA32 if 64BIT
config SNI_RM
bool "SNI RM200/300/400"
@@ -556,6 +576,7 @@
select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select GENERIC_ISA_DMA
select HW_HAS_EISA
@@ -599,6 +620,7 @@
config TOSHIBA_RBTX4927
bool "Toshiba RBTX49[23]7 board"
select CEVT_R4K
+ select CSRC_R4K
select CEVT_TXX9
select DMA_NONCOHERENT
select HAS_TXX9_SERIAL
@@ -621,6 +643,7 @@
config TOSHIBA_RBTX4938
bool "Toshiba RBTX4938 board"
select CEVT_R4K
+ select CSRC_R4K
select CEVT_TXX9
select DMA_NONCOHERENT
select HAS_TXX9_SERIAL
@@ -642,6 +665,7 @@
config WR_PPMC
bool "Wind River PPMC board"
select CEVT_R4K
+ select CSRC_R4K
select IRQ_CPU
select BOOT_ELF32
select DMA_NONCOHERENT
@@ -752,6 +776,9 @@
config CSRC_BCM1480
bool
+config CSRC_R4K
+ bool
+
config CSRC_SB1250
bool
@@ -1640,6 +1667,9 @@
or have huge holes in the physical address space for other reasons.
See <file:Documentation/vm/numa> for more.
+config ARCH_POPULATES_NODE_MAP
+ def_bool y
+
config ARCH_SPARSEMEM_ENABLE
bool
select SPARSEMEM_STATIC
@@ -1945,6 +1975,9 @@
config PCSPEAKER
bool
+config ZONE_DMA32
+ bool
+
source "drivers/pcmcia/Kconfig"
source "drivers/pci/hotplug/Kconfig"
diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig
index b36cec58..05d1354 100644
--- a/arch/mips/au1000/Kconfig
+++ b/arch/mips/au1000/Kconfig
@@ -138,6 +138,7 @@
bool
select 64BIT_PHYS_ADDR
select CEVT_R4K
+ select CSRC_R4K
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index b551535..ffa0836 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -14,6 +14,7 @@
obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
+obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
@@ -43,6 +44,7 @@
obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_SMP_UP) += smp-up.o
obj-$(CONFIG_MIPS_MT) += mips-mt.o
obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index bab935a..24a2d90 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -219,7 +219,7 @@
return 1;
}
-void __cpuinit mips_clockevent_init(void)
+int __cpuinit mips_clockevent_init(void)
{
uint64_t mips_freq = mips_hpt_frequency;
unsigned int cpu = smp_processor_id();
@@ -227,7 +227,7 @@
unsigned int irq;
if (!cpu_has_counter || !mips_hpt_frequency)
- return;
+ return -ENXIO;
#ifdef CONFIG_MIPS_MT_SMTC
setup_smtc_dummy_clockevent_device();
@@ -237,11 +237,11 @@
* device.
*/
if (cpu)
- return;
+ return 0;
#endif
if (!c0_compare_int_usable())
- return;
+ return -ENXIO;
/*
* With vectored interrupts things are getting platform specific.
@@ -276,8 +276,8 @@
clockevents_register_device(cd);
- if (!cp0_timer_irq_installed)
- return;
+ if (cp0_timer_irq_installed)
+ return 0;
cp0_timer_irq_installed = 1;
@@ -287,4 +287,6 @@
#else
setup_irq(irq, &c0_compare_irqaction);
#endif
+
+ return 0;
}
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
new file mode 100644
index 0000000..74c5c62
--- /dev/null
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -0,0 +1,29 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 by Ralf Baechle
+ */
+
+static cycle_t c0_hpt_read(void)
+{
+ return read_c0_count();
+}
+
+static struct clocksource clocksource_mips = {
+ .name = "MIPS",
+ .read = c0_hpt_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init init_mips_clocksource(void)
+{
+ /* Calclate a somewhat reasonable rating value */
+ clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
+
+ clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+
+ clocksource_register(&clocksource_mips);
+}
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index a06a27d..7f6ddcb 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -269,7 +269,7 @@
static void __init bootmem_init(void)
{
- unsigned long reserved_end;
+ unsigned long init_begin, reserved_end;
unsigned long mapstart = ~0UL;
unsigned long bootmap_size;
int i;
@@ -342,6 +342,35 @@
*/
bootmap_size = init_bootmem_node(NODE_DATA(0), mapstart,
min_low_pfn, max_low_pfn);
+
+
+ init_begin = PFN_UP(__pa_symbol(&__init_begin));
+ for (i = 0; i < boot_mem_map.nr_map; i++) {
+ unsigned long start, end;
+
+ start = PFN_UP(boot_mem_map.map[i].addr);
+ end = PFN_DOWN(boot_mem_map.map[i].addr
+ + boot_mem_map.map[i].size);
+
+ if (start <= init_begin)
+ start = init_begin;
+ if (start >= end)
+ continue;
+
+#ifndef CONFIG_HIGHMEM
+ if (end > max_low_pfn)
+ end = max_low_pfn;
+
+ /*
+ * ... finally, is the area going away?
+ */
+ if (end <= start)
+ continue;
+#endif
+
+ add_active_range(0, start, end);
+ }
+
/*
* Register fully available low RAM pages with the bootmem allocator.
*/
diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c
new file mode 100644
index 0000000..ead6c30
--- /dev/null
+++ b/arch/mips/kernel/smp-up.c
@@ -0,0 +1,67 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ * Symmetric Uniprocessor (TM) Support
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+/*
+ * Send inter-processor interrupt
+ */
+void up_send_ipi_single(int cpu, unsigned int action)
+{
+ panic(KERN_ERR "%s called", __func__);
+}
+
+static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action)
+{
+ panic(KERN_ERR "%s called", __func__);
+}
+
+/*
+ * After we've done initial boot, this function is called to allow the
+ * board code to clean up state, if needed
+ */
+void __cpuinit up_init_secondary(void)
+{
+}
+
+void __cpuinit up_smp_finish(void)
+{
+}
+
+/* Hook for after all CPUs are online */
+void up_cpus_done(void)
+{
+}
+
+/*
+ * Firmware CPU startup hook
+ */
+void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle)
+{
+}
+
+void __init up_smp_setup(void)
+{
+}
+
+void __init up_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+struct plat_smp_ops up_smp_ops = {
+ .send_ipi_single = up_send_ipi_single,
+ .send_ipi_mask = up_send_ipi_mask,
+ .init_secondary = up_init_secondary,
+ .smp_finish = up_smp_finish,
+ .cpus_done = up_cpus_done,
+ .boot_secondary = up_boot_secondary,
+ .smp_setup = up_smp_setup,
+ .prepare_cpus = up_prepare_cpus,
+};
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 3284b9b..5207542 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -50,14 +50,6 @@
return rtc_mips_set_mmss(now.tv_sec);
}
-/*
- * High precision timer functions for a R4k-compatible timer.
- */
-static cycle_t c0_hpt_read(void)
-{
- return read_c0_count();
-}
-
int (*mips_timer_state)(void);
int null_perf_irq(void)
@@ -84,55 +76,6 @@
unsigned int mips_hpt_frequency;
-static struct clocksource clocksource_mips = {
- .name = "MIPS",
- .read = c0_hpt_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static unsigned int __init calibrate_hpt(void)
-{
- cycle_t frequency, hpt_start, hpt_end, hpt_count, hz;
-
- const int loops = HZ / 10;
- int log_2_loops = 0;
- int i;
-
- /*
- * We want to calibrate for 0.1s, but to avoid a 64-bit
- * division we round the number of loops up to the nearest
- * power of 2.
- */
- while (loops > 1 << log_2_loops)
- log_2_loops++;
- i = 1 << log_2_loops;
-
- /*
- * Wait for a rising edge of the timer interrupt.
- */
- while (mips_timer_state());
- while (!mips_timer_state());
-
- /*
- * Now see how many high precision timer ticks happen
- * during the calculated number of periods between timer
- * interrupts.
- */
- hpt_start = clocksource_mips.read();
- do {
- while (mips_timer_state());
- while (!mips_timer_state());
- } while (--i);
- hpt_end = clocksource_mips.read();
-
- hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask;
- hz = HZ;
- frequency = hpt_count * hz;
-
- return frequency >> log_2_loops;
-}
-
void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
{
u64 temp;
@@ -166,16 +109,6 @@
cd->mult = (u32) temp;
}
-static void __init init_mips_clocksource(void)
-{
- /* Calclate a somewhat reasonable rating value */
- clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
-
- clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
-
- clocksource_register(&clocksource_mips);
-}
-
void __init __weak plat_time_init(void)
{
}
@@ -194,21 +127,42 @@
BUG();
}
+static __init int cpu_has_mfc0_count_bug(void)
+{
+ switch (current_cpu_type()) {
+ case CPU_R4000PC:
+ case CPU_R4000SC:
+ case CPU_R4000MC:
+ /*
+ * V3.0 is documented as suffering from the mfc0 from count bug.
+ * Afaik this is the last version of the R4000. Later versions
+ * were marketed as R4400.
+ */
+ return 1;
+
+ case CPU_R4400PC:
+ case CPU_R4400SC:
+ case CPU_R4400MC:
+ /*
+ * The published errata for the R4400 upto 3.0 say the CPU
+ * has the mfc0 from count bug.
+ */
+ if ((current_cpu_data.processor_id & 0xff) <= 0x30)
+ return 1;
+
+ /*
+ * I don't have erratas for newer R4400 so be paranoid.
+ */
+ return 1;
+ }
+
+ return 0;
+}
+
void __init time_init(void)
{
plat_time_init();
- if (cpu_has_counter && (mips_hpt_frequency || mips_timer_state)) {
- /* We know counter frequency. Or we can get it. */
- if (!mips_hpt_frequency)
- mips_hpt_frequency = calibrate_hpt();
-
- /* Report the high precision timer rate for a reference. */
- printk("Using %u.%03u MHz high precision timer.\n",
- ((mips_hpt_frequency + 500) / 1000) / 1000,
- ((mips_hpt_frequency + 500) / 1000) % 1000);
+ if (mips_clockevent_init() || !cpu_has_mfc0_count_bug())
init_mips_clocksource();
- }
-
- mips_clockevent_init();
}
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 38bd33f..c06eb81 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -470,7 +470,7 @@
*/
if (v != l->value) {
printk(KERN_DEBUG "VPE loader: "
- "apply_r_mips_lo16/hi16: "
+ "apply_r_mips_lo16/hi16: \t"
"inconsistent value information\n");
return -ENOEXEC;
}
@@ -629,7 +629,7 @@
break;
case SHN_MIPS_SCOMMON:
- printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON"
+ printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON "
"symbol <%s> st_shndx %d\n", strtab + sym[i].st_name,
sym[i].st_shndx);
// .sbss section
diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c
index 946aee3..cb1b682 100644
--- a/arch/mips/math-emu/ieee754.c
+++ b/arch/mips/math-emu/ieee754.c
@@ -108,6 +108,7 @@
ax.rv.si = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
+ va_end(ax.ap);
return ax.rv.si;
}
@@ -122,5 +123,6 @@
ax.rv.di = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
+ va_end(ax.ap);
return ax.rv.di;
}
diff --git a/arch/mips/math-emu/ieee754dp.c b/arch/mips/math-emu/ieee754dp.c
index 3e214aa..6d2d89f 100644
--- a/arch/mips/math-emu/ieee754dp.c
+++ b/arch/mips/math-emu/ieee754dp.c
@@ -57,6 +57,7 @@
ax.rv.dp = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
+ va_end(ax.ap);
return ax.rv.dp;
}
@@ -83,6 +84,7 @@
ax.rv.dp = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
+ va_end(ax.ap);
return ax.rv.dp;
}
diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c
index adda851..4635340 100644
--- a/arch/mips/math-emu/ieee754sp.c
+++ b/arch/mips/math-emu/ieee754sp.c
@@ -58,6 +58,7 @@
ax.rv.sp = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
+ va_end(ax.ap);
return ax.rv.sp;
}
@@ -84,6 +85,7 @@
ax.rv.sp = r;
va_start(ax.ap, op);
ieee754_xcpt(&ax);
+ va_end(ax.ap);
return ax.rv.sp;
}
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
index bfaafa3..e39bbe9 100644
--- a/arch/mips/mipssim/sim_time.c
+++ b/arch/mips/mipssim/sim_time.c
@@ -101,9 +101,7 @@
void __init plat_time_init(void)
{
- unsigned int est_freq, flags;
-
- local_irq_save(flags);
+ unsigned int est_freq;
/* Set Data mode - binary. */
CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
@@ -114,6 +112,4 @@
(est_freq % 1000000) * 100 / 1000000);
cpu_khz = est_freq / 1000;
-
- local_irq_restore(flags);
}
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 33519ce..ae76795 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -40,16 +40,38 @@
current_cpu_type() == CPU_R12000);
}
+static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
+{
+ /* ignore region specifiers */
+ gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
+
+#ifdef CONFIG_ZONE_DMA32
+ if (dev == NULL)
+ gfp |= __GFP_DMA;
+ else if (dev->coherent_dma_mask < DMA_BIT_MASK(24))
+ gfp |= __GFP_DMA;
+ else
+#endif
+#ifdef CONFIG_ZONE_DMA32
+ if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
+ gfp |= __GFP_DMA32;
+ else
+#endif
+ ;
+
+ /* Don't invoke OOM killer */
+ gfp |= __GFP_NORETRY;
+
+ return gfp;
+}
+
void *dma_alloc_noncoherent(struct device *dev, size_t size,
dma_addr_t * dma_handle, gfp_t gfp)
{
void *ret;
- /* ignore region specifiers */
- gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
+ gfp = massage_gfp_flags(dev, gfp);
- if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
- gfp |= GFP_DMA;
ret = (void *) __get_free_pages(gfp, get_order(size));
if (ret != NULL) {
@@ -67,11 +89,8 @@
{
void *ret;
- /* ignore region specifiers */
- gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
+ gfp = massage_gfp_flags(dev, gfp);
- if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
- gfp |= GFP_DMA;
ret = (void *) __get_free_pages(gfp, get_order(size));
if (ret) {
@@ -343,7 +362,7 @@
* so we can't guarantee allocations that must be
* within a tighter range than GFP_DMA..
*/
- if (mask < 0x00ffffff)
+ if (mask < DMA_BIT_MASK(24))
return 0;
return 1;
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index ec3b9e9..480dec0 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -347,11 +347,8 @@
void __init paging_init(void)
{
- unsigned long zones_size[MAX_NR_ZONES] = { 0, };
-#ifndef CONFIG_FLATMEM
- unsigned long zholes_size[MAX_NR_ZONES] = { 0, };
- unsigned long i, j, pfn;
-#endif
+ unsigned long max_zone_pfns[MAX_NR_ZONES];
+ unsigned long lastpfn;
pagetable_init();
@@ -361,35 +358,27 @@
kmap_coherent_init();
#ifdef CONFIG_ZONE_DMA
- if (min_low_pfn < MAX_DMA_PFN && MAX_DMA_PFN <= max_low_pfn) {
- zones_size[ZONE_DMA] = MAX_DMA_PFN - min_low_pfn;
- zones_size[ZONE_NORMAL] = max_low_pfn - MAX_DMA_PFN;
- } else if (max_low_pfn < MAX_DMA_PFN)
- zones_size[ZONE_DMA] = max_low_pfn - min_low_pfn;
- else
+ max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
#endif
- zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn;
-
+#ifdef CONFIG_ZONE_DMA32
+ max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
+#endif
+ max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
+ lastpfn = max_low_pfn;
#ifdef CONFIG_HIGHMEM
- zones_size[ZONE_HIGHMEM] = highend_pfn - highstart_pfn;
+ max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
+ lastpfn = highend_pfn;
- if (cpu_has_dc_aliases && zones_size[ZONE_HIGHMEM]) {
+ if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
printk(KERN_WARNING "This processor doesn't support highmem."
- " %ldk highmem ignored\n", zones_size[ZONE_HIGHMEM]);
- zones_size[ZONE_HIGHMEM] = 0;
+ " %ldk highmem ignored\n",
+ (highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
+ max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
+ lastpfn = max_low_pfn;
}
#endif
-#ifdef CONFIG_FLATMEM
- free_area_init(zones_size);
-#else
- pfn = min_low_pfn;
- for (i = 0; i < MAX_NR_ZONES; i++)
- for (j = 0; j < zones_size[i]; j++, pfn++)
- if (!page_is_ram(pfn))
- zholes_size[i]++;
- free_area_init_node(0, NODE_DATA(0), zones_size, 0, zholes_size);
-#endif
+ free_area_init_nodes(max_zone_pfns);
}
static struct kcore_list kcore_mem, kcore_vmalloc;
diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig
index 6b293ce..90261b8 100644
--- a/arch/mips/pmc-sierra/Kconfig
+++ b/arch/mips/pmc-sierra/Kconfig
@@ -5,12 +5,14 @@
config PMC_MSP4200_EVAL
bool "PMC-Sierra MSP4200 Eval Board"
select CEVT_R4K
+ select CSRC_R4K
select IRQ_MSP_SLP
select HW_HAS_PCI
config PMC_MSP4200_GW
bool "PMC-Sierra MSP4200 VoIP Gateway"
select CEVT_R4K
+ select CSRC_R4K
select IRQ_MSP_SLP
select HW_HAS_PCI
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 26854fb..1617241 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -36,6 +36,7 @@
#include <asm/sgi/ioc.h>
#include <asm/sgi/mc.h>
#include <asm/sgi/ip22.h>
+#include <asm/i8259.h>
/* I2 has four EISA slots. */
#define IP22_EISA_MAX_SLOTS 4
@@ -93,126 +94,11 @@
return IRQ_NONE;
}
-static void enable_eisa1_irq(unsigned int irq)
-{
- u8 mask;
-
- mask = inb(EISA_INT1_MASK);
- mask &= ~((u8) (1 << irq));
- outb(mask, EISA_INT1_MASK);
-}
-
-static unsigned int startup_eisa1_irq(unsigned int irq)
-{
- u8 edge;
-
- /* Only use edge interrupts for EISA */
-
- edge = inb(EISA_INT1_EDGE_LEVEL);
- edge &= ~((u8) (1 << irq));
- outb(edge, EISA_INT1_EDGE_LEVEL);
-
- enable_eisa1_irq(irq);
- return 0;
-}
-
-static void disable_eisa1_irq(unsigned int irq)
-{
- u8 mask;
-
- mask = inb(EISA_INT1_MASK);
- mask |= ((u8) (1 << irq));
- outb(mask, EISA_INT1_MASK);
-}
-
-static void mask_and_ack_eisa1_irq(unsigned int irq)
-{
- disable_eisa1_irq(irq);
-
- outb(0x20, EISA_INT1_CTRL);
-}
-
-static void end_eisa1_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- enable_eisa1_irq(irq);
-}
-
-static struct irq_chip ip22_eisa1_irq_type = {
- .name = "IP22 EISA",
- .startup = startup_eisa1_irq,
- .ack = mask_and_ack_eisa1_irq,
- .mask = disable_eisa1_irq,
- .mask_ack = mask_and_ack_eisa1_irq,
- .unmask = enable_eisa1_irq,
- .end = end_eisa1_irq,
-};
-
-static void enable_eisa2_irq(unsigned int irq)
-{
- u8 mask;
-
- mask = inb(EISA_INT2_MASK);
- mask &= ~((u8) (1 << (irq - 8)));
- outb(mask, EISA_INT2_MASK);
-}
-
-static unsigned int startup_eisa2_irq(unsigned int irq)
-{
- u8 edge;
-
- /* Only use edge interrupts for EISA */
-
- edge = inb(EISA_INT2_EDGE_LEVEL);
- edge &= ~((u8) (1 << (irq - 8)));
- outb(edge, EISA_INT2_EDGE_LEVEL);
-
- enable_eisa2_irq(irq);
- return 0;
-}
-
-static void disable_eisa2_irq(unsigned int irq)
-{
- u8 mask;
-
- mask = inb(EISA_INT2_MASK);
- mask |= ((u8) (1 << (irq - 8)));
- outb(mask, EISA_INT2_MASK);
-}
-
-static void mask_and_ack_eisa2_irq(unsigned int irq)
-{
- disable_eisa2_irq(irq);
-
- outb(0x20, EISA_INT2_CTRL);
-}
-
-static void end_eisa2_irq(unsigned int irq)
-{
- if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
- enable_eisa2_irq(irq);
-}
-
-static struct irq_chip ip22_eisa2_irq_type = {
- .name = "IP22 EISA",
- .startup = startup_eisa2_irq,
- .ack = mask_and_ack_eisa2_irq,
- .mask = disable_eisa2_irq,
- .mask_ack = mask_and_ack_eisa2_irq,
- .unmask = enable_eisa2_irq,
- .end = end_eisa2_irq,
-};
-
static struct irqaction eisa_action = {
.handler = ip22_eisa_intr,
.name = "EISA",
};
-static struct irqaction cascade_action = {
- .handler = no_action,
- .name = "EISA cascade",
-};
-
int __init ip22_eisa_init(void)
{
int i, c;
@@ -248,29 +134,13 @@
outb(1, EISA_EXT_NMI_RESET_CTRL);
udelay(50); /* Wait long enough for the dust to settle */
outb(0, EISA_EXT_NMI_RESET_CTRL);
- outb(0x11, EISA_INT1_CTRL);
- outb(0x11, EISA_INT2_CTRL);
- outb(0, EISA_INT1_MASK);
- outb(8, EISA_INT2_MASK);
- outb(4, EISA_INT1_MASK);
- outb(2, EISA_INT2_MASK);
- outb(1, EISA_INT1_MASK);
- outb(1, EISA_INT2_MASK);
- outb(0xfb, EISA_INT1_MASK);
- outb(0xff, EISA_INT2_MASK);
outb(0, EISA_DMA2_WRITE_SINGLE);
- for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
- if (i < (SGINT_EISA + 8))
- set_irq_chip(i, &ip22_eisa1_irq_type);
- else
- set_irq_chip(i, &ip22_eisa2_irq_type);
- }
+ init_i8259_irqs();
/* Cannot use request_irq because of kmalloc not being ready at such
* an early stage. Yes, I've been bitten... */
setup_irq(SGI_EISA_IRQ, &eisa_action);
- setup_irq(SGINT_EISA + 2, &cascade_action);
EISA_bus = 1;
return 0;
diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c
index e19d60d..0177566 100644
--- a/arch/mips/sgi-ip22/ip22-nvram.c
+++ b/arch/mips/sgi-ip22/ip22-nvram.c
@@ -32,19 +32,19 @@
for (x=0; x<100000; x++) __asm__ __volatile__(""); })
#define eeprom_cs_on(ptr) ({ \
- *ptr &= ~EEPROM_DATO; \
- *ptr &= ~EEPROM_ECLK; \
- *ptr &= ~EEPROM_EPROT; \
- delay(); \
- *ptr |= EEPROM_CSEL; \
- *ptr |= EEPROM_ECLK; })
+ __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
+ __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
+ __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
+ delay(); \
+ __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
+ __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
#define eeprom_cs_off(ptr) ({ \
- *ptr &= ~EEPROM_ECLK; \
- *ptr &= ~EEPROM_CSEL; \
- *ptr |= EEPROM_EPROT; \
- *ptr |= EEPROM_ECLK; })
+ __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
+ __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
+ __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
+ __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
#define BITS_IN_COMMAND 11
/*
@@ -60,15 +60,17 @@
ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND));
for (i = 0; i < BITS_IN_COMMAND; i++) {
if (ser_cmd & (1<<15)) /* if high order bit set */
- writel(readl(ctrl) | EEPROM_DATO, ctrl);
+ __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl);
else
- writel(readl(ctrl) & ~EEPROM_DATO, ctrl);
- writel(readl(ctrl) & ~EEPROM_ECLK, ctrl);
- writel(readl(ctrl) | EEPROM_ECLK, ctrl);
+ __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl);
+ __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl);
+ delay();
+ __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl);
+ delay();
ser_cmd <<= 1;
}
/* see data sheet timing diagram */
- writel(readl(ctrl) & ~EEPROM_DATO, ctrl);
+ __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl);
}
unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg)
@@ -76,18 +78,18 @@
unsigned short res = 0;
int i;
- writel(readl(ctrl) & ~EEPROM_EPROT, ctrl);
+ __raw_writel(__raw_readl(ctrl) & ~EEPROM_EPROT, ctrl);
eeprom_cs_on(ctrl);
eeprom_cmd(ctrl, EEPROM_READ, reg);
/* clock the data ouf of serial mem */
for (i = 0; i < 16; i++) {
- writel(readl(ctrl) & ~EEPROM_ECLK, ctrl);
+ __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl);
delay();
- writel(readl(ctrl) | EEPROM_ECLK, ctrl);
+ __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl);
delay();
res <<= 1;
- if (readl(ctrl) & EEPROM_DATI)
+ if (__raw_readl(ctrl) & EEPROM_DATI)
res |= 1;
}
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index aab17dd..cab7cc2 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -209,18 +209,18 @@
static void enable_macepci_irq(unsigned int irq)
{
- macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
+ macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
mace->pci.control = macepci_mask;
- crime_mask |= 1 << (irq - 1);
+ crime_mask |= 1 << (irq - CRIME_IRQ_BASE);
crime->imask = crime_mask;
}
static void disable_macepci_irq(unsigned int irq)
{
- crime_mask &= ~(1 << (irq - 1));
+ crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE));
crime->imask = crime_mask;
flush_crime_bus();
- macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
+ macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
mace->pci.control = macepci_mask;
flush_mace_bus();
}
@@ -299,7 +299,7 @@
pr_debug("crime_int %08x enabled\n", crime_int);
crime_mask |= crime_int;
crime->imask = crime_mask;
- maceisa_mask |= 1 << (irq - 33);
+ maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ);
mace->perif.ctrl.imask = maceisa_mask;
}
@@ -307,7 +307,7 @@
{
unsigned int crime_int = 0;
- maceisa_mask &= ~(1 << (irq - 33));
+ maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
if (!(maceisa_mask & MACEISA_AUDIO_INT))
crime_int |= MACE_AUDIO_INT;
if (!(maceisa_mask & MACEISA_MISC_INT))
@@ -331,7 +331,7 @@
case MACEISA_SERIAL2_TDMAPR_IRQ:
/* edge triggered */
mace_int = mace->perif.ctrl.istat;
- mace_int &= ~(1 << (irq - 33));
+ mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
mace->perif.ctrl.istat = mace_int;
break;
}
@@ -359,13 +359,17 @@
static void enable_mace_irq(unsigned int irq)
{
- crime_mask |= 1 << (irq - 1);
+ unsigned int bit = irq - CRIME_IRQ_BASE;
+
+ crime_mask |= (1 << bit);
crime->imask = crime_mask;
}
static void disable_mace_irq(unsigned int irq)
{
- crime_mask &= ~(1 << (irq - 1));
+ unsigned int bit = irq - CRIME_IRQ_BASE;
+
+ crime_mask &= ~(1 << bit);
crime->imask = crime_mask;
flush_crime_bus();
}
@@ -489,7 +493,7 @@
mace->perif.ctrl.imask = 0;
mips_cpu_irq_init();
- for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) {
+ for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
switch (irq) {
case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
set_irq_chip(irq, &ip32_mace_interrupt);
diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig
index eeb089f..559acc0 100644
--- a/arch/mips/vr41xx/Kconfig
+++ b/arch/mips/vr41xx/Kconfig
@@ -6,6 +6,7 @@
config CASIO_E55
bool "CASIO CASSIOPEIA E-10/15/55/65"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select ISA
@@ -15,6 +16,7 @@
config IBM_WORKPAD
bool "IBM WorkPad z50"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select ISA
@@ -24,6 +26,7 @@
config NEC_CMBVR4133
bool "NEC CMB-VR4133"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
@@ -33,6 +36,7 @@
config TANBAC_TB022X
bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
@@ -48,6 +52,7 @@
config VICTOR_MPC30X
bool "Victor MP-C303/304"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
@@ -58,6 +63,7 @@
config ZAO_CAPCELLA
bool "ZAO Networks Capcella"
select CEVT_R4K
+ select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select HW_HAS_PCI
diff --git a/include/asm-mips/8253pit.h b/include/asm-mips/8253pit.h
deleted file mode 100644
index 285f784..0000000
--- a/include/asm-mips/8253pit.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * 8253/8254 Programmable Interval Timer
- */
-
-#ifndef _8253PIT_H
-#define _8253PIT_H
-
-#define PIT_TICK_RATE 1193182UL
-
-#endif
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
index 833437d..d6a6c21 100644
--- a/include/asm-mips/dma.h
+++ b/include/asm-mips/dma.h
@@ -92,6 +92,7 @@
#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
#endif
#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
+#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index 3e7e30d..17f082c 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -35,7 +35,7 @@
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %6 \n" \
- " j 2b \n" \
+ " j 3b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
@@ -61,7 +61,7 @@
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %6 \n" \
- " j 2b \n" \
+ " j 3b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
@@ -200,4 +200,4 @@
}
#endif
-#endif
+#endif /* _ASM_FUTEX_H */
diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h
index 032ca73..5dabc87 100644
--- a/include/asm-mips/i8253.h
+++ b/include/asm-mips/i8253.h
@@ -12,6 +12,8 @@
#define PIT_CH0 0x40
#define PIT_CH2 0x42
+#define PIT_TICK_RATE 1193182UL
+
extern spinlock_t i8253_lock;
extern void setup_pit_timer(void);
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index ab5612f..85bc530 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -22,7 +22,7 @@
* CPU interrupts are 0 ... 7
*/
- CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE,
+ CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8,
/*
* MACE
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 90e4b40..1030562 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -68,11 +68,15 @@
if (cpu_has_dsp) \
__save_dsp(prev); \
(last) = resume(prev, next, task_thread_info(next)); \
+} while (0)
+
+#define finish_arch_switch(prev) \
+do { \
if (cpu_has_dsp) \
__restore_dsp(current); \
if (cpu_has_userlocal) \
- write_c0_userlocal(task_thread_info(current)->tp_value);\
-} while(0)
+ write_c0_userlocal(current_thread_info()->tp_value); \
+} while (0)
static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
{
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index ee1663e..7717934 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -58,10 +58,22 @@
* Initialize the calling CPU's compare interrupt as clockevent device
*/
#ifdef CONFIG_CEVT_R4K
-extern void mips_clockevent_init(void);
+extern int mips_clockevent_init(void);
extern unsigned int __weak get_c0_compare_int(void);
#else
-static inline void mips_clockevent_init(void)
+static inline int mips_clockevent_init(void)
+{
+ return -ENXIO;
+}
+#endif
+
+/*
+ * Initialize the count register as a clocksource
+ */
+#ifdef CONFIG_CEVT_R4K
+extern void init_mips_clocksource(void);
+#else
+static inline void init_mips_clocksource(void)
{
}
#endif