| /* Copyright (c) 2019, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,camcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| #include "sda845-v2.1.dtsi" |
| #include "sdm845-sde-display.dtsi" |
| #include "sdm845-rb3.dtsi" |
| #include "sdm845-audio-overlay.dtsi" |
| |
| &usb1 { |
| status = "ok"; |
| }; |
| |
| &qusb_phy1 { |
| status = "ok"; |
| }; |
| |
| &usb_qmp_phy { |
| status = "ok"; |
| }; |
| |
| &pcie1 { |
| status = "disable"; |
| }; |
| |
| &soc { |
| clk40M: can_clock { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <40000000>; |
| }; |
| }; |
| |
| &qupv3_se0_spi { |
| status = "ok"; |
| can@0 { |
| compatible = "microchip,mcp2517fd"; |
| reg = <0>; |
| clocks = <&clk40M>; |
| interrupt-parent = <&tlmm>; |
| interrupts = <104 0>; |
| interrupt-names = "can_irq"; |
| spi-max-frequency = <10000000>; |
| gpio-controller; |
| status = "okay"; |
| }; |
| }; |
| |
| &qupv3_se3_i2c { |
| status = "disabled"; |
| }; |
| |
| &pmi8998_pdphy { |
| vbus-supply = <&smb2_vbus>; |
| }; |
| |
| &pmi8998_pwm_2 { |
| status = "ok"; |
| }; |
| |
| &wil6210 { |
| status = "disabled"; |
| }; |
| |
| &smb1355_0 { |
| status = "disabled"; |
| }; |
| |
| &smb1355_1 { |
| status = "disabled"; |
| }; |
| |
| &key_home_default { |
| pins = "gpio4"; |
| }; |
| |
| &max_rst_active { |
| mux { |
| pins = "gpio31","gpio77","gpio32"; |
| }; |
| config { |
| pins = "gpio31","gpio77","gpio32"; |
| }; |
| }; |
| |
| &pcie0 { |
| vreg-pcie-supply = <&pcie_vcc_eldo>; |
| qcom,vreg-pcie-voltage-level = <3300000 3300000 24000>; |
| status = "ok"; |
| }; |
| |
| &pcie1 { |
| /delete-property/ wake-gpio; |
| }; |
| |
| &max_rst_suspend { |
| mux { |
| pins = "gpio31","gpio77","gpio32"; |
| }; |
| config { |
| pins = "gpio31","gpio77","gpio32"; |
| }; |
| }; |
| |
| &camera_dvdd_en_default { |
| pins = "gpio11"; |
| }; |
| |
| &soc { |
| qcom,qbt1000 { |
| compatible = "qcom,qbt1000"; |
| clock-names = "core", "iface"; |
| clock-frequency = <25000000>; |
| qcom,ipc-gpio = <&tlmm 121 0>; |
| qcom,finger-detect-gpio = <&pm8998_gpios 4 0>; |
| }; |
| |
| qcom,rmnet-ipa { |
| status="disabled"; |
| }; |
| }; |
| |
| &ssc_sensors { |
| status = "disabled"; |
| }; |
| |
| &tlmm { |
| cam_sensor_tof_active: cam_sensor_tof_active { |
| /* RESET*/ |
| mux { |
| pins = "gpio8"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio8"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_tof_suspend: cam_sensor_tof_suspend { |
| /* RESET*/ |
| mux { |
| pins = "gpio8"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio8"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| output-low; |
| }; |
| }; |
| |
| cam_sensor_tracking_active: cam_sensor_tracking_active { |
| /* RESET */ |
| mux { |
| pins = "gpio21"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio21"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_tracking_suspend: cam_sensor_tracking_suspend { |
| /* RESET */ |
| mux { |
| pins = "gpio21"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio21"; |
| bias-pull-down; /* PULL DOWN */ |
| drive-strength = <2>; /* 2 MA */ |
| output-low; |
| }; |
| }; |
| |
| cam_sensor_rear4_active: cam_sensor_rear4_active { |
| /* RESET */ |
| mux { |
| pins = "gpio12","gpio69"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio12","gpio69"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| |
| cam_sensor_rear4_suspend: cam_sensor_rear4_suspend { |
| /* RESET */ |
| mux { |
| pins = "gpio12","gpio69"; |
| function = "gpio"; |
| }; |
| |
| config { |
| pins = "gpio12","gpio69"; |
| bias-disable; /* No PULL */ |
| drive-strength = <2>; /* 2 MA */ |
| }; |
| }; |
| }; |
| |
| &ipa_hw { |
| status="disabled"; |
| }; |
| |
| &dsi_nt35597_truly_dsc_cmd_display { |
| /delete-property/ qcom,dsi-display-active; |
| }; |
| |
| &mdss_mdp { |
| bridges = <<9611>; |
| }; |
| |
| &soc { |
| lt9611_vcc_eldo: lt9611-gpio-regulator@0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "lt9611_vcc_eldo"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-enable-ramp-delay = <233>; |
| gpio = <&tlmm 89 0>; |
| enable-active-high; |
| }; |
| |
| pcie_vcc_eldo: pcie-gpio-regulator@0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "pcie_vcc_eldo"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&tlmm 90 0>; |
| enable-active-high; |
| }; |
| |
| }; |
| |
| &qupv3_se10_i2c { |
| status = "ok"; |
| lt9611: lt,lt9611@3b { |
| compatible = "lt,lt9611"; |
| reg = <0x3b>; |
| interrupt-parent = <&tlmm>; |
| interrupts = <84 0>; |
| interrupt-names = "lt_irq"; |
| lt,irq-gpio = <&tlmm 84 0x0>; |
| lt,reset-gpio = <&tlmm 128 0x0>; |
| lt,non-pluggable; |
| lt,preferred-mode = "1920x1080"; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <<9611_pins>; |
| |
| vdd-supply = <<9611_vcc_eldo>; |
| lt,supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| lt,supply-entry@0 { |
| reg = <0>; |
| lt,supply-name = "vdd"; |
| lt,supply-min-voltage = <1800000>; |
| lt,supply-max-voltage = <1800000>; |
| lt,supply-enable-load = <200000>; |
| lt,supply-post-on-sleep = <150>; |
| }; |
| }; |
| |
| lt,customize-modes { |
| lt,customize-mode-id@0 { |
| lt,mode-h-active = <1920>; |
| lt,mode-h-front-porch = <88>; |
| lt,mode-h-pulse-width = <44>; |
| lt,mode-h-back-porch = <148>; |
| lt,mode-h-active-high; |
| lt,mode-v-active = <1080>; |
| lt,mode-v-front-porch = <4>; |
| lt,mode-v-pulse-width = <5>; |
| lt,mode-v-back-porch = <36>; |
| lt,mode-v-active-high; |
| lt,mode-refresh-rate = <60>; |
| lt,mode-clock-in-khz = <148500>; |
| }; |
| }; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| lt9611_in: endpoint { |
| remote-endpoint = <&ext_dsi_out>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| &ext_dsi_bridge_display { |
| qcom,dsi-display-active; |
| ports { |
| port@0 { |
| ext_dsi_out: endpoint { |
| remote-endpoint = <<9611_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| &qcom_seecom { |
| /delete-property/ qcom,commonlib64-loaded-by-uefi; |
| }; |