Merge "defconfig: sdxpoorwills: enable REGULATOR_FIXED_VOLTAGE" into msm-4.9
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index fe53218..592fcef 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -141,6 +141,20 @@
* qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed
after enabling the subunit.
+* Optional properties for CTI:
+
+ * qcom,cti-gpio-trigin: cti trigger input driven by gpio.
+
+ * qcom,cti-gpio-trigout: cti trigger output sent to gpio.
+
+ * pinctrl-names: names corresponding to the numbered pinctrl. The
+ allowed names are subset of the following: cti-trigin-pinctrl,
+ cti-trigout-pctrl.
+
+ * pinctrl-<n>: list of pinctrl phandles for the different pinctrl
+ states. Refer to
+ "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt"
+
* Required property for Remote ETMs:
* qcom,inst-id: must be present. QMI instance id for remote ETMs.
diff --git a/Documentation/devicetree/bindings/arm/msm/cmd-db.txt b/Documentation/devicetree/bindings/arm/msm/cmd-db.txt
index b989d8a..e704d70 100644
--- a/Documentation/devicetree/bindings/arm/msm/cmd-db.txt
+++ b/Documentation/devicetree/bindings/arm/msm/cmd-db.txt
@@ -24,10 +24,12 @@
Value type: <prop-encoded-array>
Definition: First element is the base address of shared memory
Second element is the size of the shared memory region
+ Points to the dictionary address that houses the command DB
+ start address and the size of the command DB region
Example:
qcom,cmd-db@861e0000 {
compatible = "qcom,cmd-db";
- reg = <0x861e0000 0x4000>;
+ reg = <0xc3f000c 0x8>;
}
diff --git a/Documentation/devicetree/bindings/arm/msm/wil6210.txt b/Documentation/devicetree/bindings/arm/msm/wil6210.txt
index b381bdeb..c467327 100644
--- a/Documentation/devicetree/bindings/arm/msm/wil6210.txt
+++ b/Documentation/devicetree/bindings/arm/msm/wil6210.txt
@@ -10,6 +10,10 @@
- compatible: "qcom,wil6210"
- qcom,smmu-support: Boolean flag indicating whether PCIe has SMMU support
+- qcom,smmu-s1-en: Boolean flag indicating whether SMMU stage1 should be enabled
+- qcom,smmu-fast-map: Boolean flag indicating whether SMMU fast mapping should be enabled
+- qcom,smmu-coherent: Boolean flag indicating SMMU dma and page table coherency
+- qcom,smmu-mapping: specifies the base address and size of SMMU space
- qcom,pcie-parent: phandle for the PCIe root complex to which 11ad card is connected
- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
the below optional properties:
@@ -33,6 +37,10 @@
wil6210: qcom,wil6210 {
compatible = "qcom,wil6210";
qcom,smmu-support;
+ qcom,smmu-s1-en;
+ qcom,smmu-fast-map;
+ qcom,smmu-coherent;
+ qcom,smmu-mapping = <0x20000000 0xe0000000>;
qcom,pcie-parent = <&pcie1>;
qcom,wigig-en = <&tlmm 94 0>;
qcom,msm-bus,name = "wil6210";
diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index bc226a7..a3ef34c 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -128,6 +128,8 @@
feature is available or not.
- qcom,sde-has-dim-layer: Boolean property to indicate if mixer has dim layer
feature is available or not.
+- qcom,sde-has-idle-pc: Boolean property to indicate if target has idle
+ power collapse feature available or not.
- qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction
feature available or not.
- qcom,sde-has-cdp: Boolean property to indicate if cdp feature is
@@ -420,6 +422,7 @@
qcom,sde-csc-type = "csc-10bit";
qcom,sde-highest-bank-bit = <15>;
qcom,sde-has-mixer-gc;
+ qcom,sde-has-idle-pc;
qcom,sde-sspp-max-rects = <1 1 1 1
1 1 1 1
1 1
diff --git a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt
index 3e7fcb7..ffba081 100644
--- a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt
+++ b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt
@@ -35,7 +35,7 @@
- qcom,mdss-dsi-panel-destination: A string that specifies the destination display for the panel.
"display_1" = DISPLAY_1
"display_2" = DISPLAY_2
-- qcom,mdss-dsi-panel-timings: An array of length 12 that specifies the PHY
+- qcom,mdss-dsi-panel-phy-timings: An array of length 12 that specifies the PHY
timing settings for the panel.
- qcom,mdss-dsi-panel-timings-8996: An array of length 40 char that specifies the 8996 PHY lane
timing settings for the panel.
@@ -456,28 +456,6 @@
with the supply entry index. For a detailed description of
fields in the supply entry, refer to the qcom,ctrl-supply-entries
binding above.
-- qcom,config-select: Optional property to select default configuration.
-
-[[Optional config sub-nodes]] These subnodes provide different configurations for a given same panel.
- Default configuration can be chosen by specifying phandle of the
- selected subnode in the qcom,config-select.
-Required properties for sub-nodes: None
-Optional properites:
-- qcom,lm-split: An array of two values indicating MDP should use two layer
- mixers to reduce power.
- Ex: Normally 1080x1920 display uses single DSI and thus one layer
- mixer. But if we use two layer mixers then mux the output of
- those two mixers into single stream and route it to single DSI
- then we can lower the clock requirements of MDP. To use this
- configuration we need two fill this array with <540 540>.
- Both values doesn't have to be same, but recommended, however sum of
- both values has to be equal to the panel-width.
- By default two mixer streams are merged using 2D mux, however if
- 2 DSC encoders are used then merge is performed within compression
- engine.
-- qcom,split-mode: String property indicating which split mode MDP should use. Valid
- entries are "pingpong-split" and "dualctl-split".
- This property is mutually exclusive with qcom,lm-split.
- qcom,mdss-dsc-version: An 8 bit value indicates the DSC version supported by panel. Bits[0.3]
provides information about minor version while Bits[4.7] provides
major version information. It supports only DSC rev 1(Major).1(Minor)
@@ -500,6 +478,21 @@
- qcom,mdss-dsc-block-prediction-enable: A boolean value to enable/disable the block prediction at decoder.
- qcom,mdss-dsc-config-by-manufacture-cmd: A boolean to indicates panel use manufacture command to setup pps
instead of standard dcs type 0x0A.
+- qcom,display-topology: Array of u32 values which specifies the list of topologies available
+ for the display. A display topology is defined by a
+ set of 3 values in the order:
+ - number of mixers
+ - number of compression encoders
+ - number of interfaces
+ Therefore, the array should always contain a tuple of 3 elements.
+- qcom,default-topology-index: An u32 value which indexes the topology set
+ specified by the node "qcom,display-topology"
+ to identify the default topology for the
+ display. The first set is indexed by the
+ value 0.
+
+Required properties for sub-nodes: None
+Optional properties:
- qcom,dba-panel: Indicates whether the current panel is used as a display bridge
to a non-DSI interface.
- qcom,bridge-name: A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name
@@ -692,18 +685,15 @@
29 00 00 00 00 00 02 F1 00];
qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode";
- qcom,config-select = <&dsi_sim_vid_config0>;
- dsi_sim_vid_config0: config0 {
- qcom,lm-split = <360 360>;
- qcom,mdss-dsc-encoders = <2>;
- qcom,mdss-dsc-slice-height = <16>;
- qcom,mdss-dsc-slice-width = <360>;
- qcom,mdss-dsc-slice-per-pkt = <2>;
- qcom,mdss-dsc-bit-per-component = <8>;
- qcom,mdss-dsc-bit-per-pixel = <8>;
- qcom,mdss-dsc-block-prediction-enable;
- qcom,mdss-dsc-config-by-manufacture-cmd;
- };
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ qcom,mdss-dsc-config-by-manufacture-cmd;
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
};
};
qcom,panel-supply-entries {
@@ -737,41 +727,19 @@
};
};
- qcom,config-select = <&dsi_sim_vid_config0>;
qcom,dba-panel;
qcom,bridge-name = "adv7533";
qcom,mdss-dsc-version = <0x11>;
qcom,mdss-dsc-scr-version = <0x1>;
-
- dsi_sim_vid_config0: config0 {
- qcom,lm-split = <360 360>;
- qcom,mdss-dsc-encoders = <2>;
- qcom,mdss-dsc-slice-height = <16>;
- qcom,mdss-dsc-slice-width = <360>;
- qcom,mdss-dsc-slice-per-pkt = <2>;
- qcom,mdss-dsc-bit-per-component = <8>;
- qcom,mdss-dsc-bit-per-pixel = <8>;
- qcom,mdss-dsc-block-prediction-enable;
- qcom,mdss-dsc-config-by-manufacture-cmd;
- };
-
- dsi_sim_vid_config1: config1 {
- qcom,mdss-dsc-encoders = <1>;
- qcom,mdss-dsc-slice-height = <16>;
- qcom,mdss-dsc-slice-width = <360>;
- qcom,mdss-dsc-slice-per-pkt = <2>;
- qcom,mdss-dsc-bit-per-component = <8>;
- qcom,mdss-dsc-bit-per-pixel = <8>;
- qcom,mdss-dsc-block-prediction-enable;
- qcom,mdss-dsc-config-by-manufacture-cmd;
- };
-
- dsi_sim_vid_config2: config2 {
- qcom,split-mode = "dualctl-split";
- };
-
- dsi_sim_vid_config3: config3 {
- qcom,split-mode = "pingpong-split";
- };
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ qcom,mdss-dsc-config-by-manufacture-cmd;
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <0>;
};
};
diff --git a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
index ea828da..bc844de 100644
--- a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
+++ b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
@@ -16,6 +16,10 @@
If "halt_base" is in same 4K pages this register then
this will be defined else "halt_q6", "halt_modem",
"halt_nc" is required.
+ "pdc_sync" is the power domain register introduced in
+ sdm845 for power domain of subsystems.
+ If alternative reset is required, "alt_reset" maps to
+ mss_alt_ares.
- interrupts: The modem watchdog interrupt
- vdd_cx-supply: Reference to the regulator that supplies the vdd_cx domain.
- vdd_cx-voltage: Voltage corner/level(max) for cx rail.
diff --git a/Documentation/devicetree/bindings/power/supply/qcom/smb1355-charger.txt b/Documentation/devicetree/bindings/power/supply/qcom/smb1355-charger.txt
new file mode 100644
index 0000000..ca584e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/supply/qcom/smb1355-charger.txt
@@ -0,0 +1,73 @@
+Qualcomm Technologies, Inc. SMB1355 Charger Specific Bindings
+
+SMB1355 slave charger is paired with QTI family of standalone chargers to
+enable a high current, low profile Li+ battery charging system.
+
+The device provides 28V DC withstand, wide operating input range of 3.8 to
+14.2V for standard 5V USB inputs as well as a wide variety of HVDCP Travel
+Adapters and is compatible with QTI's Quick Charge technology.
+
+=======================
+Required Node Structure
+=======================
+
+SMB1355 Charger must be described in two levels of device nodes.
+
+==================================
+First Level Node - SMB1355 Charger
+==================================
+
+Charger specific properties:
+- compatible
+ Usage: required
+ Value type: <string>
+ Definition: "qcom,smb1355".
+
+- qcom,pmic-revid
+ Usage: required
+ Value type: phandle
+ Definition: Should specify the phandle of SMB's revid module. This is used
+ to identify the SMB subtype.
+
+================================================
+Second Level Nodes - SMB1355 Charger Peripherals
+================================================
+
+Peripheral specific properties:
+- reg
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Address and size of the peripheral's register block.
+
+- interrupts
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Peripheral interrupt specifier.
+
+- interrupt-names
+ Usage: required
+ Value type: <stringlist>
+ Definition: Interrupt names. This list must match up 1-to-1 with the
+ interrupts specified in the 'interrupts' property.
+
+=======
+Example
+=======
+
+smb1355_charger: qcom,smb1355-charger {
+ compatible = "qcom,smb1355";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts = <0x10 0x1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "chg-state-change";
+ };
+
+ qcom,chgr-misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts = <0x16 0x1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "wdog-bark";
+ };
+};
diff --git a/Documentation/devicetree/bindings/regulator/cpr3-regulator.txt b/Documentation/devicetree/bindings/regulator/cpr3-regulator.txt
index 5bf560e..846bd22 100644
--- a/Documentation/devicetree/bindings/regulator/cpr3-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/cpr3-regulator.txt
@@ -216,6 +216,15 @@
as the corresponding addresses are specified in
the qcom,cpr-panic-reg-addr-list property.
+- qcom,cpr-reset-step-quot-loop-en
+ Usage: optional; only meaningful for CPR4 and CPRh controllers
+ Value type: <empty>
+ Definition: Boolean value which indicates that the CPR controller should
+ be configured to reset step_quot on each loop_en = 0
+ transition. This configuration allows the CPR controller to
+ first use the default step_quot and then later switch to the
+ run-time calibrated step_quot.
+
- qcom,saw-avs-ctrl
Usage: required if "saw" registers are specified by reg and
reg-names properties
diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt b/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt
index 04b624b..0173a3d 100644
--- a/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt
@@ -19,6 +19,7 @@
Optional properties:
- qcom,bus-mas: contains the bus master id needed to put in bus bandwidth votes
for inter-connect buses.
+- qcom,wakeup-byte: Byte to be injected in the tty layer during wakeup isr.
Example:
qupv3_uart11: qcom,qup_uart@0xa88000 {
@@ -34,4 +35,5 @@
pinctrl-1 = <&qup_1_uart_3_sleep>;
interrupts = <0 355 0>;
qcom,bus-mas = <MASTER_BLSP_2>;
+ qcom,wakeup-byte = <0xFF>;
};
diff --git a/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt b/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt
index 702f252..28ab2dd 100644
--- a/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt
+++ b/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt
@@ -11,8 +11,7 @@
VADC_TM node
Required properties:
-- compatible : should be "qcom,qpnp-adc-tm" for thermal ADC driver.
- : should be "qcom,qpnp-adc-tm-hc" for thermal ADC driver using
+- compatible : should be "qcom,qpnp-adc-tm-hc" for thermal ADC driver using
refreshed BTM peripheral.
- reg : offset and length of the PMIC Aribter register map.
- address-cells : Must be one.
@@ -156,51 +155,6 @@
qcom,client-adc_tm = <&pm8941_adc_tm>;
};
-Example for "qcom,qpnp-adc-tm" device:
- /* Main Node */
- qcom,vadc@3400 {
- compatible = "qcom,qpnp-adc-tm";
- reg = <0x3400 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0x0 0x34 0x0>,
- <0x0 0x34 0x3>,
- <0x0 0x34 0x4>;
- interrupt-names = "eoc-int-en-set",
- "high-thr-en-set",
- "low-thr-en-set";
- qcom,adc-bit-resolution = <15>;
- qcom,adc-vdd-reference = <1800>;
- qcom,adc_tm-vadc = <&pm8941_vadc>;
-
- /* Channel Node to be registered as part of thermal sysfs */
- chan@b5 {
- label = "pa_therm1";
- reg = <0xb5>;
- qcom,decimation = <0>;
- qcom,pre-div-channel-scaling = <0>;
- qcom,calibration-type = "absolute";
- qcom,scale-function = <2>;
- qcom,hw-settle-time = <0>;
- qcom,fast-avg-setup = <0>;
- qcom,btm-channel-number = <0x70>;
- qcom,thermal-node;
- };
-
- /* Channel Node */
- chan@6 {
- label = "vbat_sns";
- reg = <6>;
- qcom,decimation = <0>;
- qcom,pre-div-channel-scaling = <1>;
- qcom,calibration-type = "absolute";
- qcom,scale-function = <3>;
- qcom,hw-settle-time = <0>;
- qcom,fast-avg-setup = <0>;
- qcom,btm-channel-number = <0x78>;
- };
- };
-
Example for "qcom,qpnp-adc-tm-hc" device:
/* Main Node */
pm8998_adc_tm: vadc@3400 {
@@ -218,7 +172,7 @@
/* Channel Node to be registered as part of thermal sysfs */
chan@b5 {
- label = "pa_therm1";
+ label = "msm_therm";
reg = <0xb5>;
qcom,pre-div-channel-scaling = <0>;
qcom,calibration-type = "absolute";
@@ -239,3 +193,21 @@
qcom,btm-channel-number = <0x78>;
};
};
+
+/* Example to register thermal sensor using of_thermal */
+&thermal_zones {
+ msm-therm-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8998_adc_tm 0xb5>;
+ thermal-governor = "user_space";
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/thermal/qpnp-temp-alarm.txt b/Documentation/devicetree/bindings/thermal/qpnp-temp-alarm.txt
index bb20644..fc8ec87 100644
--- a/Documentation/devicetree/bindings/thermal/qpnp-temp-alarm.txt
+++ b/Documentation/devicetree/bindings/thermal/qpnp-temp-alarm.txt
@@ -12,10 +12,17 @@
- interrupts: PMIC temperature alarm interrupt
- label: A string used as a descriptive name for this thermal device.
This name should be 19 characters or less.
+- #thermal-sensor-cells: Must be 0. Please refer to
+ <devicetree/bindings/thermal/thermal.txt> for more
+ details.
Required structure:
- A qcom,qpnp-temp-alarm node must be a child of an SPMI node that has specified
the spmi-slave-container property
+- A top level device tree node named "thermal-zones" must exist. It must
+ contain a subnode with a property named "thermal-sensors" which is assigned
+ a phandle to the qpnp-temp-alarm device node. See
+ <devicetree/bindings/thermal/thermal.txt> for more details.
Optional properties:
- qcom,channel-num: VADC channel number associated PMIC DIE_TEMP thermistor.
@@ -38,11 +45,6 @@
1 = 50 Hz
2 = 25 Hz
3 = 12.5 Hz
-- qcom,allow-override: Boolean which controls the ability of software to
- override shutdowns. If present, then software is
- allowed to override automatic PMIC hardware stage 2 and
- stage 3 over temperature shutdowns. Otherwise, software
- is not allowed to override automatic shutdown.
- qcom,default-temp: Specifies the default temperature in millicelcius to use
if no ADC channel is present to read the real time
temperature.
@@ -64,7 +66,7 @@
#address-cells = <1>;
#size-cells = <1>;
- qcom,temp-alarm@2400 {
+ pm8941_tz: qcom,temp-alarm@2400 {
compatible = "qcom,qpnp-temp-alarm";
reg = <0x2400 0x100>;
interrupts = <0x0 0x24 0x0>;
@@ -72,6 +74,36 @@
qcom,channel-num = <8>;
qcom,threshold-set = <0>;
qcom,temp_alarm-vadc = <&pm8941_vadc>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+};
+
+Below is an example thermal zone definition for the temperature alarm
+peripheral.
+thermal-zones {
+ pm8941_tz {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8941_tz>;
+
+ trips {
+ pm8941-trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ pm8941-trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ pm8941-trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
};
};
};
diff --git a/Makefile b/Makefile
index 2b8f550..f834951 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
VERSION = 4
PATCHLEVEL = 9
-SUBLEVEL = 25
+SUBLEVEL = 27
EXTRAVERSION =
NAME = Roaring Lionus
diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h
index b65930a..54b54da 100644
--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -17,10 +17,11 @@
#include <asm/barrier.h>
#include <asm/smp.h>
+#define ATOMIC_INIT(i) { (i) }
+
#ifndef CONFIG_ARC_PLAT_EZNPS
#define atomic_read(v) READ_ONCE((v)->counter)
-#define ATOMIC_INIT(i) { (i) }
#ifdef CONFIG_ARC_HAS_LLSC
diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h
index b5ff87e..aee1a77 100644
--- a/arch/arc/include/asm/entry-arcv2.h
+++ b/arch/arc/include/asm/entry-arcv2.h
@@ -16,6 +16,7 @@
;
; Now manually save: r12, sp, fp, gp, r25
+ PUSH r30
PUSH r12
; Saving pt_regs->sp correctly requires some extra work due to the way
@@ -72,6 +73,7 @@
POPAX AUX_USER_SP
1:
POP r12
+ POP r30
.endm
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 69095da..47111d5 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -84,7 +84,7 @@
unsigned long fp;
unsigned long sp; /* user/kernel sp depending on where we came from */
- unsigned long r12;
+ unsigned long r12, r30;
/*------- Below list auto saved by h/w -----------*/
unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index c32324f..ff2cc3e 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -11,7 +11,8 @@
sdm845-v2-cdp.dtb \
sdm845-qrd.dtb \
sdm845-4k-panel-mtp.dtb \
- sdm845-4k-panel-cdp.dtb
+ sdm845-4k-panel-cdp.dtb \
+ sdm845-4k-panel-qrd.dtb
dtb-$(CONFIG_ARCH_SDM830) += sdm830-sim.dtb \
sdm830-rumi.dtb \
diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi
index f1501fa..6a3e8b4 100644
--- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi
@@ -61,7 +61,7 @@
reg = <0x15000000 0x80000>,
<0x150c2000 0x20>;
reg-names = "base", "tcu-base";
- #iommu-cells = <1>;
+ #iommu-cells = <2>;
qcom,skip-init;
#global-interrupts = <1>;
#size-cells = <1>;
@@ -145,7 +145,6 @@
<0 1000>;
anoc_1_tbu: anoc_1_tbu@0x150c5000 {
- status = "disabled";
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150c5000 0x1000>,
<0x150c2200 0x8>;
@@ -167,7 +166,6 @@
};
anoc_2_tbu: anoc_2_tbu@0x150c9000 {
- status = "disabled";
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150c9000 0x1000>,
<0x150c2208 0x8>;
@@ -189,7 +187,6 @@
};
mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 {
- status = "disabled";
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150cd000 0x1000>,
<0x150c2210 0x8>;
@@ -211,7 +208,6 @@
};
mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x150d1000 {
- status = "disabled";
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150d1000 0x1000>,
<0x150c2218 0x8>;
@@ -233,7 +229,6 @@
};
mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d5000 {
- status = "disabled";
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150d5000 0x1000>,
<0x150c2220 0x8>;
@@ -255,7 +250,6 @@
};
compute_dsp_tbu: compute_dsp_tbu@0x150d9000 {
- status = "disabled";
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150d9000 0x1000>,
<0x150c2228 0x8>;
@@ -276,7 +270,6 @@
};
adsp_tbu: adsp_tbu@0x150dd000 {
- status = "disabled";
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150dd000 0x1000>,
<0x150c2230 0x8>;
@@ -298,7 +291,6 @@
};
anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x150e1000 {
- status = "disabled";
compatible = "qcom,qsmmuv500-tbu";
reg = <0x150e1000 0x1000>,
<0x150c2238 0x8>;
@@ -336,9 +328,9 @@
apps_iommu_test_device {
compatible = "iommu-debug-test";
/*
- * This SID belongs to PCIE. We can't use a fake SID for
+ * This SID belongs to QUP1-GSI. We can't use a fake SID for
* the apps_smmu device.
*/
- iommus = <&apps_smmu 0x1c03>;
+ iommus = <&apps_smmu 0x16 0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi b/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi
index 4036ce5..655f447 100644
--- a/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi
@@ -362,7 +362,7 @@
compatible = "qcom,msm-audio-ion";
qcom,smmu-version = <2>;
qcom,smmu-enabled;
- iommus = <&apps_smmu 0x1821>;
+ iommus = <&apps_smmu 0x1821 0x0>;
};
qcom,msm-adsp-loader {
diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi
index 15db8da..b9a6c79 100644
--- a/arch/arm64/boot/dts/qcom/pm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi
@@ -62,11 +62,14 @@
};
};
- qcom,temp-alarm@2400 {
+ pm8998_tz: qcom,temp-alarm@2400 {
compatible = "qcom,qpnp-temp-alarm";
reg = <0x2400 0x100>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
label = "pm8998_tz";
+ qcom,channel-num = <6>;
+ qcom,temp_alarm-vadc = <&pm8998_vadc>;
+ #thermal-sensor-cells = <0>;
};
pm8998_gpios: pinctrl@c000 {
@@ -197,3 +200,30 @@
#size-cells = <0>;
};
};
+
+&thermal_zones {
+ pm8998_temp_alarm: pm8998_tz {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8998_tz>;
+
+ trips {
+ pm8998_trip0: pm8998-trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ pm8998_trip1: pm8998-trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ pm8998_trip2: pm8998-trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
index 923804f..b53f7ac 100644
--- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
@@ -31,11 +31,12 @@
reg = <0x800 0x100>;
};
- qcom,temp-alarm@2400 {
+ pmi8998_tz: qcom,temp-alarm@2400 {
compatible = "qcom,qpnp-temp-alarm";
reg = <0x2400 0x100>;
interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
label = "pmi8998_tz";
+ #thermal-sensor-cells = <0>;
};
pmi8998_gpios: pinctrl@c000 {
@@ -796,4 +797,28 @@
};
};
};
+
+ pmi8998_tz {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmi8998_tz>;
+
+ trips {
+ pmi8998_trip0: pmi8998-trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ pmi8998_trip1: pmi8998-trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ pmi8998_trip2: pmi8998-trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-4k-panel-cdp.dts b/arch/arm64/boot/dts/qcom/sdm845-4k-panel-cdp.dts
index d5646bf..6569219 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-4k-panel-cdp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-4k-panel-cdp.dts
@@ -21,3 +21,26 @@
compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
qcom,board-id = <1 1>;
};
+
+&dsi_dual_nt35597_truly_video_display {
+ /delete-property/ qcom,dsi-display-active;
+};
+
+&mdss_mdp {
+ connectors = <&sde_wb &dsi_sharp_4k_dsc_video_display>;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-panel-mode-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_sharp_4k_dsc_video_display {
+ qcom,dsi-display-active;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-4k-panel-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-4k-panel-mtp.dts
index d641276..2e893de 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-4k-panel-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-4k-panel-mtp.dts
@@ -21,3 +21,26 @@
compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
qcom,board-id = <8 1>;
};
+
+&dsi_dual_nt35597_truly_video_display {
+ /delete-property/ qcom,dsi-display-active;
+};
+
+&mdss_mdp {
+ connectors = <&sde_wb &dsi_sharp_4k_dsc_video_display>;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-panel-mode-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_sharp_4k_dsc_video_display {
+ qcom,dsi-display-active;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-4k-panel-qrd.dts b/arch/arm64/boot/dts/qcom/sdm845-4k-panel-qrd.dts
new file mode 100644
index 0000000..6171c7b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-4k-panel-qrd.dts
@@ -0,0 +1,23 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+
+#include "sdm845.dtsi"
+#include "sdm845-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. sdm845 4K Display Panel QRD";
+ compatible = "qcom,sdm845-qrd", "qcom,sdm845", "qcom,qrd";
+ qcom,board-id = <11 1>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-audio.dtsi b/arch/arm64/boot/dts/qcom/sdm845-audio.dtsi
index 9d59a16..69dfe46 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-audio.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-audio.dtsi
@@ -17,7 +17,7 @@
#include <dt-bindings/clock/qcom,audio-ext-clk.h>
&msm_audio_ion {
- iommus = <&apps_smmu 0x1821>;
+ iommus = <&apps_smmu 0x1821 0x0>;
qcom,smmu-sid-mask = /bits/ 64 <0xf>;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi
index c0189a4..922e990 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi
@@ -118,10 +118,12 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_rear_ldo>;
- qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
- qcom,cam-vreg-min-voltage = <0 3312000 1050000>;
- qcom,cam-vreg-max-voltage = <0 3600000 1050000>;
- qcom,cam-vreg-op-mode = <0 80000 105000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <0 3312000 1050000 0>;
+ qcom,cam-vreg-max-voltage = <0 3600000 1050000 0>;
+ qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_active
@@ -157,10 +159,12 @@
cam_vdig-supply = <&camera_ldo>;
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
- qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
- qcom,cam-vreg-min-voltage = <1050000 0 3312000>;
- qcom,cam-vreg-max-voltage = <1050000 0 3600000>;
- qcom,cam-vreg-op-mode = <105000 0 80000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <1050000 0 3312000 0>;
+ qcom,cam-vreg-max-voltage = <1050000 0 3600000 0>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk2_active
@@ -193,10 +197,12 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_ldo>;
- qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
- qcom,cam-vreg-min-voltage = <0 3312000 1050000>;
- qcom,cam-vreg-max-voltage = <0 3600000 1050000>;
- qcom,cam-vreg-op-mode = <0 80000 105000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <0 3312000 1050000 0>;
+ qcom,cam-vreg-max-voltage = <0 3600000 1050000 0>;
+ qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk1_active
@@ -240,10 +246,12 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_rear_ldo>;
- qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
- qcom,cam-vreg-min-voltage = <0 3312000 1050000>;
- qcom,cam-vreg-max-voltage = <0 3600000 1050000>;
- qcom,cam-vreg-op-mode = <0 80000 105000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <0 3312000 1050000 0>;
+ qcom,cam-vreg-max-voltage = <0 3600000 1050000 0>;
+ qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_active
@@ -280,10 +288,12 @@
cam_vdig-supply = <&camera_ldo>;
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
- qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
- qcom,cam-vreg-min-voltage = <1050000 0 3312000>;
- qcom,cam-vreg-max-voltage = <1050000 0 3600000>;
- qcom,cam-vreg-op-mode = <105000 0 80000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <1050000 0 3312000 0>;
+ qcom,cam-vreg-max-voltage = <1050000 0 3600000 0>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk2_active
@@ -322,10 +332,12 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_ldo>;
- qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
- qcom,cam-vreg-min-voltage = <0 3312000 1050000>;
- qcom,cam-vreg-max-voltage = <0 3600000 1050000>;
- qcom,cam-vreg-op-mode = <0 80000 105000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <0 3312000 1050000 0>;
+ qcom,cam-vreg-max-voltage = <0 3600000 1050000 0>;
+ qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk1_active
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi
index c0189a4..922e990 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi
@@ -118,10 +118,12 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_rear_ldo>;
- qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
- qcom,cam-vreg-min-voltage = <0 3312000 1050000>;
- qcom,cam-vreg-max-voltage = <0 3600000 1050000>;
- qcom,cam-vreg-op-mode = <0 80000 105000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <0 3312000 1050000 0>;
+ qcom,cam-vreg-max-voltage = <0 3600000 1050000 0>;
+ qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_active
@@ -157,10 +159,12 @@
cam_vdig-supply = <&camera_ldo>;
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
- qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
- qcom,cam-vreg-min-voltage = <1050000 0 3312000>;
- qcom,cam-vreg-max-voltage = <1050000 0 3600000>;
- qcom,cam-vreg-op-mode = <105000 0 80000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <1050000 0 3312000 0>;
+ qcom,cam-vreg-max-voltage = <1050000 0 3600000 0>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk2_active
@@ -193,10 +197,12 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_ldo>;
- qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
- qcom,cam-vreg-min-voltage = <0 3312000 1050000>;
- qcom,cam-vreg-max-voltage = <0 3600000 1050000>;
- qcom,cam-vreg-op-mode = <0 80000 105000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <0 3312000 1050000 0>;
+ qcom,cam-vreg-max-voltage = <0 3600000 1050000 0>;
+ qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk1_active
@@ -240,10 +246,12 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_rear_ldo>;
- qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
- qcom,cam-vreg-min-voltage = <0 3312000 1050000>;
- qcom,cam-vreg-max-voltage = <0 3600000 1050000>;
- qcom,cam-vreg-op-mode = <0 80000 105000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <0 3312000 1050000 0>;
+ qcom,cam-vreg-max-voltage = <0 3600000 1050000 0>;
+ qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_active
@@ -280,10 +288,12 @@
cam_vdig-supply = <&camera_ldo>;
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
- qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
- qcom,cam-vreg-min-voltage = <1050000 0 3312000>;
- qcom,cam-vreg-max-voltage = <1050000 0 3600000>;
- qcom,cam-vreg-op-mode = <105000 0 80000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <1050000 0 3312000 0>;
+ qcom,cam-vreg-max-voltage = <1050000 0 3600000 0>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk2_active
@@ -322,10 +332,12 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_ldo>;
- qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
- qcom,cam-vreg-min-voltage = <0 3312000 1050000>;
- qcom,cam-vreg-max-voltage = <0 3600000 1050000>;
- qcom,cam-vreg-op-mode = <0 80000 105000>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ qcom,cam-vreg-min-voltage = <0 3312000 1050000 0>;
+ qcom,cam-vreg-max-voltage = <0 3600000 1050000 0>;
+ qcom,cam-vreg-op-mode = <0 80000 105000 0>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk1_active
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
index cd9c8a8..3b9c26f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
@@ -71,7 +71,7 @@
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY1_CLK>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
- <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
<&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
<&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>;
clock-names = "camnoc_axi_clk",
@@ -225,4 +225,108 @@
status = "ok";
};
};
+
+ qcom,cam_smmu {
+ compatible = "qcom,msm-cam-smmu";
+ status = "ok";
+
+ msm_cam_smmu_ife {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x808>,
+ <&apps_smmu 0x810>,
+ <&apps_smmu 0x818>,
+ <&apps_smmu 0xc08>,
+ <&apps_smmu 0xc10>,
+ <&apps_smmu 0xc18>;
+ label = "ife";
+ ife_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_icp_fw {
+ compatible = "qcom,msm-cam-smmu-fw-dev";
+ label="icp";
+ memory-region = <&pil_camera_mem>;
+ };
+
+ msm_cam_smmu_icp {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x1078>,
+ <&apps_smmu 0x1020>,
+ <&apps_smmu 0x1028>,
+ <&apps_smmu 0x1040>,
+ <&apps_smmu 0x1048>,
+ <&apps_smmu 0x1030>,
+ <&apps_smmu 0x1050>;
+ label = "icp";
+ icp_iova_mem_map: iova-mem-map {
+ iova-mem-region-firmware {
+ /* Firmware region is 5MB */
+ iova-region-name = "firmware";
+ iova-region-start = <0x0>;
+ iova-region-len = <0x500000>;
+ iova-region-id = <0x0>;
+ status = "ok";
+ };
+
+ iova-mem-region-shared {
+ /* Shared region is 100MB long */
+ iova-region-name = "shared";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0x6400000>;
+ iova-region-id = <0x1>;
+ status = "ok";
+ };
+
+ iova-mem-region-io {
+ /* IO region is approximately 3.3 GB */
+ iova-region-name = "io";
+ iova-region-start = <0xd800000>;
+ iova-region-len = <0xd2800000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_cpas_cdm {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x1000>;
+ label = "cpas-cdm0";
+ cpas_cdm_iova_mem_map: iova-mem-map {
+ iova-mem-region-io {
+ /* IO region is approximately 3.4 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_secure {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x1001>;
+ label = "cam-secure";
+ cam_secure_iova_mem_map: iova-mem-map {
+ /* Secure IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi
index 68824d7..af28003 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi
@@ -93,6 +93,10 @@
};
};
+&mdss_mdp {
+ #cooling-cells = <2>;
+};
+
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v3";
@@ -202,6 +206,7 @@
spi0 = &qupv3_se8_spi;
i2c0 = &qupv3_se10_i2c;
i2c1 = &qupv3_se3_i2c;
+ hsuart0 = &qupv3_se6_4uart;
};
};
@@ -245,6 +250,10 @@
status = "ok";
};
+&qupv3_se6_4uart {
+ status = "ok";
+};
+
&usb1 {
status = "okay";
extcon = <&extcon_usb1>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
index 1d471f5..c0556e4 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi
@@ -391,9 +391,8 @@
coresight-name = "coresight-hwevent";
- clocks = <&clock_gcc RPMH_QDSS_CLK>,
- <&clock_gcc RPMH_QDSS_A_CLK>;
- clock-names = "core_clk", "core_a_clk";
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
};
csr: csr@6001000 {
@@ -483,6 +482,16 @@
};
port@1 {
+ reg = <0>;
+ funnel_in2_in_modem_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_etm0_out_funnel_in2>;
+ };
+
+ };
+
+ port@2 {
reg = <1>;
funnel_in2_in_replicator_swao: endpoint {
slave-mode;
@@ -492,7 +501,7 @@
};
- port@2 {
+ port@3 {
reg = <2>;
funnel_in2_in_funnel_modem: endpoint {
slave-mode;
@@ -502,7 +511,7 @@
};
- port@3 {
+ port@4 {
reg = <5>;
funnel_in2_in_funnel_apss_merg: endpoint {
slave-mode;
@@ -530,6 +539,7 @@
<2 32>,
<3 32>,
<5 32>,
+ <6 32>,
<10 32>,
<11 32>,
<13 32>;
@@ -589,6 +599,15 @@
};
port@5 {
+ reg = <6>;
+ tpda_in_funnel_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_turing_out_tpda>;
+ };
+ };
+
+ port@6 {
reg = <7>;
tpda_in_tpdm_vsense: endpoint {
slave-mode;
@@ -597,7 +616,7 @@
};
};
- port@6 {
+ port@7 {
reg = <10>;
tpda_in_tpdm_qm: endpoint {
slave-mode;
@@ -606,7 +625,7 @@
};
};
- port@7 {
+ port@8 {
reg = <11>;
tpda_in_tpdm_north: endpoint {
slave-mode;
@@ -615,7 +634,7 @@
};
};
- port@8 {
+ port@9 {
reg = <13>;
tpda_in_tpdm_pimem: endpoint {
slave-mode;
@@ -759,7 +778,7 @@
coresight-name = "coresight-tpdm-lpass";
clocks = <&clock_aop QDSS_CLK>;
- clock-names = "core_clk";
+ clock-names = "apb_pclk";
port {
tpdm_lpass_out_funnel_lpass: endpoint {
@@ -1039,6 +1058,69 @@
};
};
+ funnel_turing: funnel@6861000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b908>;
+
+ reg = <0x6861000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-turing";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_turing_out_tpda: endpoint {
+ remote-endpoint =
+ <&tpda_in_funnel_turing>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_turing_in_tpdm_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_turing_out_funnel_turing>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_turing_in_turing_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&turing_etm0_out_funnel_turing>;
+ };
+ };
+ };
+ };
+
+ tpdm_turing: tpdm@6860000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6860000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-turing";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_turing_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_turing>;
+ };
+ };
+ };
+
funnel_ddr_0: funnel@69e2000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x0003b908>;
@@ -1305,6 +1387,30 @@
};
};
+ cti_ddr0: cti@69e1000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b966>;
+ reg = <0x69e1000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ddr1: cti@69e4000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b966>;
+ reg = <0x69e4000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
cti0: cti@6010000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x0003b966>;
@@ -1341,6 +1447,10 @@
clocks = <&clock_aop QDSS_CLK>;
clock-names = "apb_pclk";
+
+ qcom,cti-gpio-trigout = <4>;
+ pinctrl-names = "cti-trigout-pctrl";
+ pinctrl-0 = <&trigout_a>;
};
cti3: cti@6013000 {
@@ -1617,6 +1727,20 @@
clock-names = "apb_pclk";
};
+ turing_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-turing-etm0";
+ qcom,inst-id = <1>;
+
+ port{
+ turing_etm0_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_turing_etm0>;
+ };
+ };
+ };
+
dummy_eud: dummy_sink {
compatible = "qcom,coresight-dummy";
@@ -1632,6 +1756,20 @@
};
};
+ modem_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-modem-etm0";
+ qcom,inst-id = <2>;
+
+ port {
+ modem_etm0_out_funnel_in2: endpoint {
+ remote-endpoint =
+ <&funnel_in2_in_modem_etm0>;
+ };
+ };
+ };
+
funnel_apss_merg: funnel@7810000 {
compatible = "arm,primecell";
arm,primecell-periphid = <0x0003b908>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-gpu.dtsi b/arch/arm64/boot/dts/qcom/sdm845-gpu.dtsi
index bfbaabb..77edb85 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-gpu.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-gpu.dtsi
@@ -12,6 +12,12 @@
&soc {
+ pil_gpu: qcom,kgsl-hyp {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <13>;
+ qcom,firmware-name = "a630_zap";
+ };
+
msm_bus: qcom,kgsl-busmon{
label = "kgsl-busmon";
compatible = "qcom,kgsl-busmon";
@@ -77,13 +83,16 @@
#cooling-cells = <2>;
clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK>,
- <&clock_gcc GCC_GPU_CFG_AHB_CLK>,
<&clock_gpucc GPU_CC_CXO_CLK>,
<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
- <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+ <&clock_gpucc GPU_CC_AHB_CLK>,
+ <&clock_gpucc GPU_CC_GX_CXO_CLK>;
- clock-names = "core_clk", "iface_clk", "rbbmtimer_clk",
- "mem_clk", "mem_iface_clk";
+ clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",
+ "mem_iface_clk", "gmu_clk", "ahb_clk",
+ "cxo_clk";
qcom,isense-clk-on-level = <1>;
@@ -162,19 +171,19 @@
qcom,gpu-pwrlevel@0 {
reg = <0>;
- qcom,gpu-freq = <548000000>;
- qcom,bus-freq = <12>;
- qcom,bus-min = <11>;
- qcom,bus-max = <12>;
+ qcom,gpu-freq = <280000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
- qcom,gpu-freq = <425000000>;
- qcom,bus-freq = <7>;
- qcom,bus-min = <6>;
- qcom,bus-max = <8>;
+ qcom,gpu-freq = <280000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
};
qcom,gpu-pwrlevel@2 {
@@ -187,10 +196,10 @@
qcom,gpu-pwrlevel@3 {
reg = <3>;
- qcom,gpu-freq = <27000000>;
- qcom,bus-freq = <0>;
- qcom,bus-min = <0>;
- qcom,bus-max = <0>;
+ qcom,gpu-freq = <280000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
};
};
@@ -248,13 +257,13 @@
clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
- <&clock_gcc GCC_GPU_CFG_AHB_CLK>,
<&clock_gpucc GPU_CC_CXO_CLK>,
<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
- <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&clock_gpucc GPU_CC_AHB_CLK>;
- clock-names = "gmu_clk", "ahb_clk", "cxo_clk",
- "axi_clk", "memnoc_clk";
+ clock-names = "gmu_clk", "cxo_clk", "axi_clk",
+ "memnoc_clk", "ahb_clk";
qcom,gmu-pwrlevels {
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
index 4391189..d316d63 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
#include "sdm845-camera-sensor-mtp.dtsi"
+#include "smb1355.dtsi"
/ {
bluetooth: bt_wcn3990 {
@@ -102,6 +103,10 @@
qcom,led-strings-list = [01 02];
};
+&mdss_mdp {
+ #cooling-cells = <2>;
+};
+
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v3";
@@ -199,12 +204,17 @@
qcom,battery-data = <&mtp_batterydata>;
};
+&smb1355_charger {
+ status = "ok";
+};
+
/ {
aliases {
serial0 = &qupv3_se9_2uart;
spi0 = &qupv3_se8_spi;
i2c0 = &qupv3_se10_i2c;
i2c1 = &qupv3_se3_i2c;
+ hsuart0 = &qupv3_se6_4uart;
};
};
@@ -224,6 +234,10 @@
status = "ok";
};
+&qupv3_se6_4uart {
+ status = "ok";
+};
+
&usb1 {
status = "okay";
extcon = <&extcon_usb1>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi
new file mode 100644
index 0000000..da5d6fa
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+
+&soc {
+ pcie0: qcom,pcie@0x1c00000 {
+ compatible = "qcom,pci-msm";
+ cell-index = <0>;
+
+ reg = <0x1c00000 0x2000>,
+ <0x1c06000 0x1000>,
+ <0x60000000 0xf1d>,
+ <0x60000f20 0xa8>,
+ <0x60100000 0x100000>,
+ <0x60200000 0x100000>,
+ <0x60300000 0xd00000>;
+
+ reg-names = "parf", "phy", "dm_core", "elbi",
+ "conf", "io", "bars";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x60300000 0x0 0xd00000>;
+ interrupt-parent = <&pcie0>;
+ interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
+ 36 37>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0xffffffff>;
+ interrupt-map = <0 0 0 0 &intc 0 141 0
+ 0 0 0 1 &intc 0 149 0
+ 0 0 0 2 &intc 0 150 0
+ 0 0 0 3 &intc 0 151 0
+ 0 0 0 4 &intc 0 152 0
+ 0 0 0 5 &intc 0 140 0
+ 0 0 0 6 &intc 0 672 0
+ 0 0 0 7 &intc 0 673 0
+ 0 0 0 8 &intc 0 674 0
+ 0 0 0 9 &intc 0 675 0
+ 0 0 0 10 &intc 0 676 0
+ 0 0 0 11 &intc 0 677 0
+ 0 0 0 12 &intc 0 678 0
+ 0 0 0 13 &intc 0 679 0
+ 0 0 0 14 &intc 0 680 0
+ 0 0 0 15 &intc 0 681 0
+ 0 0 0 16 &intc 0 682 0
+ 0 0 0 17 &intc 0 683 0
+ 0 0 0 18 &intc 0 684 0
+ 0 0 0 19 &intc 0 685 0
+ 0 0 0 20 &intc 0 686 0
+ 0 0 0 21 &intc 0 687 0
+ 0 0 0 22 &intc 0 688 0
+ 0 0 0 23 &intc 0 689 0
+ 0 0 0 24 &intc 0 690 0
+ 0 0 0 25 &intc 0 691 0
+ 0 0 0 26 &intc 0 692 0
+ 0 0 0 27 &intc 0 693 0
+ 0 0 0 28 &intc 0 694 0
+ 0 0 0 29 &intc 0 695 0
+ 0 0 0 30 &intc 0 696 0
+ 0 0 0 31 &intc 0 697 0
+ 0 0 0 32 &intc 0 698 0
+ 0 0 0 33 &intc 0 699 0
+ 0 0 0 34 &intc 0 700 0
+ 0 0 0 35 &intc 0 701 0
+ 0 0 0 36 &intc 0 702 0
+ 0 0 0 37 &intc 0 703 0>;
+
+ interrupt-names = "int_msi", "int_a", "int_b", "int_c",
+ "int_d", "int_global_int",
+ "msi_0", "msi_1", "msi_2", "msi_3",
+ "msi_4", "msi_5", "msi_6", "msi_7",
+ "msi_8", "msi_9", "msi_10", "msi_11",
+ "msi_12", "msi_13", "msi_14", "msi_15",
+ "msi_16", "msi_17", "msi_18", "msi_19",
+ "msi_20", "msi_21", "msi_22", "msi_23",
+ "msi_24", "msi_25", "msi_26", "msi_27",
+ "msi_28", "msi_29", "msi_30", "msi_31";
+
+ qcom,phy-sequence = <0x804 0x01 0x0
+ 0x034 0x14 0x0
+ 0x138 0x30 0x0
+ 0x048 0x07 0x0
+ 0x15c 0x06 0x0
+ 0x090 0x01 0x0
+ 0x088 0x20 0x0
+ 0x0f0 0x00 0x0
+ 0x0f8 0x01 0x0
+ 0x0f4 0xc9 0x0
+ 0x11c 0xff 0x0
+ 0x120 0x3f 0x0
+ 0x164 0x01 0x0
+ 0x154 0x00 0x0
+ 0x148 0x0a 0x0
+ 0x05c 0x19 0x0
+ 0x038 0x90 0x0
+ 0x0b0 0x82 0x0
+ 0x0c0 0x02 0x0
+ 0x0bc 0xea 0x0
+ 0x0b8 0xab 0x0
+ 0x0a0 0x00 0x0
+ 0x09c 0x0d 0x0
+ 0x098 0x04 0x0
+ 0x13c 0x00 0x0
+ 0x060 0x06 0x0
+ 0x068 0x16 0x0
+ 0x070 0x36 0x0
+ 0x184 0x01 0x0
+ 0x15c 0x16 0x0
+ 0x138 0x33 0x0
+ 0x03c 0x02 0x0
+ 0x040 0x07 0x0
+ 0x080 0x04 0x0
+ 0x0dc 0x00 0x0
+ 0x0d8 0x3f 0x0
+ 0x00c 0x09 0x0
+ 0x010 0x01 0x0
+ 0x01c 0x40 0x0
+ 0x020 0x01 0x0
+ 0x014 0x02 0x0
+ 0x018 0x00 0x0
+ 0x024 0x7e 0x0
+ 0x028 0x15 0x0
+ 0x244 0x02 0x0
+ 0x2a4 0x12 0x0
+ 0x260 0x10 0x0
+ 0x28c 0x06 0x0
+ 0x504 0x03 0x0
+ 0x500 0x1c 0x0
+ 0x50c 0x14 0x0
+ 0x4d4 0x0e 0x0
+ 0x4d8 0x04 0x0
+ 0x4dc 0x1a 0x0
+ 0x434 0x4b 0x0
+ 0x414 0x04 0x0
+ 0x40c 0x04 0x0
+ 0x4f8 0x71 0x0
+ 0x564 0x59 0x0
+ 0x568 0x59 0x0
+ 0x4fc 0x80 0x0
+ 0x51c 0x40 0x0
+ 0x444 0x71 0x0
+ 0x43c 0x40 0x0
+ 0x854 0x04 0x0
+ 0x62c 0x52 0x0
+ 0x654 0x50 0x0
+ 0x65c 0x1a 0x0
+ 0x660 0x06 0x0
+ 0x8c8 0x83 0x0
+ 0x8cc 0x09 0x0
+ 0x8d0 0xa2 0x0
+ 0x8d4 0x40 0x0
+ 0x8c4 0x02 0x0
+ 0x9ac 0x00 0x0
+ 0x8a0 0x01 0x0
+ 0x9e0 0x00 0x0
+ 0x9dc 0x20 0x0
+ 0x9a8 0x00 0x0
+ 0x8a4 0x01 0x0
+ 0x8a8 0x73 0x0
+ 0x9d8 0xaa 0x0
+ 0x9b0 0x03 0x0
+ 0xa0c 0x0d 0x0
+ 0x86c 0x00 0x0
+ 0x644 0x00 0x0
+ 0x804 0x03 0x0
+ 0x800 0x00 0x0
+ 0x808 0x03 0x0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_clkreq_default
+ &pcie0_perst_default
+ &pcie0_wake_default>;
+
+ perst-gpio = <&tlmm 35 0>;
+ wake-gpio = <&tlmm 37 0>;
+
+ gdsc-vdd-supply = <&pcie_0_gdsc>;
+ vreg-1.8-supply = <&pm8998_l26>;
+ vreg-0.9-supply = <&pm8998_l1>;
+ vreg-cx-supply = <&pm8998_s9_level>;
+
+ qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;
+ qcom,vreg-0.9-voltage-level = <880000 880000 24000>;
+ qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+ RPMH_REGULATOR_LEVEL_SVS 0>;
+
+ qcom,l1-supported;
+ qcom,l1ss-supported;
+ qcom,aux-clk-sync;
+
+ qcom,ep-latency = <10>;
+
+ qcom,boot-option = <0x1>;
+
+ linux,pci-domain = <0>;
+
+ qcom,msi-gicm-addr = <0x17a00040>;
+ qcom,msi-gicm-base = <0x2c0>;
+
+ qcom,pcie-phy-ver = <0x30>;
+ qcom,use-19p2mhz-aux-clk;
+
+ qcom,smmu-sid-base = <0x1c10>;
+
+ iommu-map = <0x100 &apps_smmu 0x1c11 0x1>,
+ <0x200 &apps_smmu 0x1c12 0x1>,
+ <0x300 &apps_smmu 0x1c13 0x1>,
+ <0x400 &apps_smmu 0x1c14 0x1>,
+ <0x500 &apps_smmu 0x1c15 0x1>,
+ <0x600 &apps_smmu 0x1c16 0x1>,
+ <0x700 &apps_smmu 0x1c17 0x1>,
+ <0x800 &apps_smmu 0x1c18 0x1>,
+ <0x900 &apps_smmu 0x1c19 0x1>,
+ <0xa00 &apps_smmu 0x1c1a 0x1>,
+ <0xb00 &apps_smmu 0x1c1b 0x1>,
+ <0xc00 &apps_smmu 0x1c1c 0x1>,
+ <0xd00 &apps_smmu 0x1c1d 0x1>,
+ <0xe00 &apps_smmu 0x1c1e 0x1>,
+ <0xf00 &apps_smmu 0x1c1f 0x1>;
+
+ qcom,msm-bus,name = "pcie0";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <45 512 0 0>,
+ <45 512 500 800>;
+
+ clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_PCIE_0_AUX_CLK>,
+ <&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&clock_gcc GCC_PCIE_0_CLKREF_CLK>,
+ <&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&clock_gcc GCC_PCIE_PHY_REFGEN_CLK>,
+ <&clock_gcc GCC_PCIE_PHY_AUX_CLK>;
+
+ clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
+ "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
+ "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
+ "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
+ "pcie_tbu_clk", "pcie_phy_refgen_clk",
+ "pcie_phy_aux_clk";
+
+ max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>,
+ <0>, <0>, <0>, <0>, <100000000>, <0>;
+
+ resets = <&clock_gcc GCC_PCIE_0_BCR>,
+ <&clock_gcc GCC_PCIE_0_PHY_BCR>;
+
+ reset-names = "pcie_0_core_reset",
+ "pcie_0_phy_reset";
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi
index d6af58b..947262fb 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi
@@ -160,6 +160,47 @@
};
};
+ pcie0 {
+ pcie0_clkreq_default: pcie0_clkreq_default {
+ mux {
+ pins = "gpio36";
+ function = "pci_e0";
+ };
+
+ config {
+ pins = "gpio36";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_perst_default: pcie0_perst_default {
+ mux {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio35";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie0_wake_default: pcie0_wake_default {
+ mux {
+ pins = "gpio37";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio37";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
cdc_reset_ctrl {
cdc_reset_sleep: cdc_reset_sleep {
mux {
@@ -417,6 +458,58 @@
};
};
+ sde_dp_aux_active: sde_dp_aux_active {
+ mux {
+ pins = "gpio43", "gpio51";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio43", "gpio51";
+ bias-disable = <0>; /* no pull */
+ drive-strength = <8>;
+ };
+ };
+
+ sde_dp_aux_suspend: sde_dp_aux_suspend {
+ mux {
+ pins = "gpio43", "gpio51";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio43", "gpio51";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+ };
+
+ sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {
+ mux {
+ pins = "gpio38";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ };
+
+ sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend {
+ mux {
+ pins = "gpio38";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+ };
+
sec_aux_pcm {
sec_aux_pcm_sleep: sec_aux_pcm_sleep {
mux {
@@ -2558,6 +2651,18 @@
drive-strength = <2>; /* 2 MA */
};
};
+
+ trigout_a: trigout_a {
+ mux {
+ pins = "gpio62", "gpio51";
+ function = "qdss_cti";
+ };
+ config {
+ pins = "gpio62", "gpio51";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-qrd.dtsi b/arch/arm64/boot/dts/qcom/sdm845-qrd.dtsi
index 1d5bf3a..e21ed36 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-qrd.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-qrd.dtsi
@@ -10,6 +10,8 @@
* GNU General Public License for more details.
*/
+#include "smb1355.dtsi"
+
/{
qrd_batterydata: qcom,battery-data {
qcom,batt-id-range-pct = <15>;
@@ -22,6 +24,14 @@
qcom,battery-data = <&qrd_batterydata>;
};
+&smb1355_charger {
+ status = "ok";
+};
+
+&mdss_mdp {
+ #cooling-cells = <2>;
+};
+
&soc {
sound-tavil {
qcom,wsa-max-devs = <1>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi b/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi
index dd0d08e..e5d1a74 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi
@@ -30,9 +30,11 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_4uart_active>;
pinctrl-1 = <&qupv3_se6_4uart_sleep>;
- interrupts = <GIC_SPI 607 0>;
+ interrupts-extended = <&intc GIC_SPI 607 0>,
+ <&tlmm 48 0>;
status = "disabled";
qcom,bus-mas = <MSM_BUS_MASTER_BLSP_1>;
+ qcom,wakeup-byte = <0xFD>;
};
qupv3_se7_4uart: qcom,qup_uart@0x89c000 {
@@ -46,9 +48,11 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_4uart_active>;
pinctrl-1 = <&qupv3_se7_4uart_sleep>;
- interrupts = <GIC_SPI 608 0>;
+ interrupts-extended = <&intc GIC_SPI 608 0>,
+ <&tlmm 96 0>;
status = "disabled";
qcom,bus-mas = <MSM_BUS_MASTER_BLSP_1>;
+ qcom,wakeup-byte = <0xFD>;
};
/* I2C */
diff --git a/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi b/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi
index 5c39e86..f6c1d76 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi
@@ -79,6 +79,7 @@
qcom,cpr-up-error-step-limit = <1>;
qcom,cpr-corner-switch-delay-time = <1042>;
qcom,cpr-voltage-settling-time = <1760>;
+ qcom,cpr-reset-step-quot-loop-en;
qcom,voltage-step = <4000>;
qcom,voltage-base = <352000>;
@@ -269,6 +270,7 @@
qcom,cpr-up-error-step-limit = <1>;
qcom,cpr-corner-switch-delay-time = <1042>;
qcom,cpr-voltage-settling-time = <1760>;
+ qcom,cpr-reset-step-quot-loop-en;
qcom,apm-threshold-voltage = <800000>;
qcom,apm-crossover-voltage = <880000>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
index 7f24c8b..efd8f45 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
@@ -116,6 +116,7 @@
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
qcom,dsi-panel = <&dsi_sharp_4k_dsc_video>;
vddio-supply = <&pm8998_l14>;
@@ -139,6 +140,7 @@
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
qcom,dsi-panel = <&dsi_sharp_4k_dsc_cmd>;
vddio-supply = <&pm8998_l14>;
@@ -162,6 +164,7 @@
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
qcom,dsi-panel = <&dsi_sharp_1080_cmd>;
vddio-supply = <&pm8998_l14>;
@@ -185,6 +188,7 @@
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
qcom,dsi-panel = <&dsi_dual_sharp_1080_120hz_cmd>;
vddio-supply = <&pm8998_l14>;
@@ -231,6 +235,7 @@
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;
vddio-supply = <&pm8998_l14>;
@@ -254,6 +259,7 @@
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;
vddio-supply = <&pm8998_l14>;
@@ -277,6 +283,7 @@
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 10 0>;
qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;
vddio-supply = <&pm8998_l14>;
@@ -296,43 +303,43 @@
};
&dsi_dual_nt35597_truly_video {
- qcom,mdss-dsi-panel-timings = [00 1c 07 07 23 21 07 07 05 03 04];
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 05 03 04 00];
qcom,mdss-dsi-t-clk-post = <0x0D>;
qcom,mdss-dsi-t-clk-pre = <0x2D>;
};
&dsi_dual_nt35597_truly_cmd {
- qcom,mdss-dsi-panel-timings = [00 1c 07 07 23 21 07 07 05 03 04];
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 05 03 04 00];
qcom,mdss-dsi-t-clk-post = <0x0D>;
qcom,mdss-dsi-t-clk-pre = <0x2D>;
};
&dsi_nt35597_truly_dsc_cmd {
- qcom,mdss-dsi-panel-timings = [00 15 05 05 20 1f 05 05 03 03 04];
+ qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 05 03 03 04 00];
qcom,mdss-dsi-t-clk-post = <0x0b>;
qcom,mdss-dsi-t-clk-pre = <0x23>;
};
&dsi_nt35597_truly_dsc_video {
- qcom,mdss-dsi-panel-timings = [00 15 05 05 20 1f 05 05 03 03 04];
+ qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 05 03 03 04 00];
qcom,mdss-dsi-t-clk-post = <0x0b>;
qcom,mdss-dsi-t-clk-pre = <0x23>;
};
&dsi_sharp_4k_dsc_video {
- qcom,mdss-dsi-panel-timings = [00 12 04 04 1e 1e 04 04 02 03 04];
- qcom,mdss-dsi-t-clk-post = <0x0a>;
- qcom,mdss-dsi-t-clk-pre = <0x1e>;
+ qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 06 04 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x0c>;
+ qcom,mdss-dsi-t-clk-pre = <0x27>;
};
&dsi_sharp_4k_dsc_cmd {
- qcom,mdss-dsi-panel-timings = [00 12 04 04 1e 1e 04 04 02 03 04];
- qcom,mdss-dsi-t-clk-post = <0x0a>;
- qcom,mdss-dsi-t-clk-pre = <0x1e>;
+ qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 06 04 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x0c>;
+ qcom,mdss-dsi-t-clk-pre = <0x27>;
};
&dsi_dual_sharp_1080_120hz_cmd {
- qcom,mdss-dsi-panel-timings = [00 24 09 09 26 24 09 09 06 03 04];
+ qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 09 06 03 04 00];
qcom,mdss-dsi-t-clk-post = <0x0f>;
qcom,mdss-dsi-t-clk-pre = <0x36>;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
index cb5d924..9c497fa 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
@@ -37,8 +37,8 @@
interrupts = <0 83 0>;
interrupt-controller;
#interrupt-cells = <1>;
- iommus = <&apps_smmu 0x880>, <&apps_smmu 0x888>,
- <&apps_smmu 0xc80>, <&apps_smmu 0xc88>;
+ iommus = <&apps_smmu 0x880 0x0>, <&apps_smmu 0x888 0x0>,
+ <&apps_smmu 0xc80 0x0>, <&apps_smmu 0xc88 0x0>;
#address-cells = <1>;
#size-cells = <0>;
@@ -97,8 +97,6 @@
1 5 9 13>;
qcom,sde-sspp-excl-rect = <1 1 1 1
1 1 1 1>;
- qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
- qcom,sde-smart-dma-rev = "smart_dma_v2";
qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>;
@@ -118,6 +116,7 @@
qcom,sde-wb-linewidth = <4096>;
qcom,sde-mixer-blendstages = <0xb>;
qcom,sde-highest-bank-bit = <0x2>;
+ qcom,sde-ubwc-version = <0x200>;
qcom,sde-panic-per-pipe;
qcom,sde-has-cdp;
qcom,sde-has-src-split;
@@ -208,7 +207,6 @@
};
mdss_rotator: qcom,mdss_rotator@ae00000 {
- status = "disabled";
compatible = "qcom,sde_rotator";
reg = <0x0ae00000 0xac000>,
<0x0aeb8000 0x3000>;
@@ -219,8 +217,6 @@
qcom,mdss-rot-mode = <1>;
qcom,mdss-highest-bank-bit = <0x2>;
- qcom,sde-ubwc-malsize = <1>;
- qcom,sde-ubwc-swizzle = <1>;
/* Bus Scale Settings */
qcom,msm-bus,name = "mdss_rotator";
@@ -238,12 +234,10 @@
<&clock_gcc GCC_DISP_AHB_CLK>,
<&clock_gcc GCC_DISP_AXI_CLK>,
<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
- <&clock_dispcc DISP_CC_MDSS_ROT_CLK_SRC>,
<&clock_dispcc DISP_CC_MDSS_ROT_CLK>,
<&clock_dispcc DISP_CC_MDSS_AXI_CLK>;
clock-names = "gcc_iface", "gcc_bus",
- "iface_clk", "rot_core_clk",
- "rot_clk", "axi_clk";
+ "iface_clk", "rot_clk", "axi_clk";
interrupt-parent = <&mdss_mdp>;
interrupts = <2 0>;
@@ -260,15 +254,12 @@
smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
compatible = "qcom,smmu_sde_rot_unsec";
- iommus = <&apps_smmu 0x1090>;
- gdsc-mdss-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
+ iommus = <&apps_smmu 0x1090 0x0>;
};
smmu_rot_sec: qcom,smmu_rot_sec_cb {
- status = "disabled";
compatible = "qcom,smmu_sde_rot_sec";
- iommus = <&apps_smmu 0x1091>;
- gdsc-mdss-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
+ iommus = <&apps_smmu 0x1091 0x0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-vidc.dtsi b/arch/arm64/boot/dts/qcom/sdm845-vidc.dtsi
index b9dc816..6f4b4ca 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-vidc.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-vidc.dtsi
@@ -97,9 +97,9 @@
compatible = "qcom,msm-vidc,context-bank";
label = "venus_ns";
iommus =
- <&apps_smmu 0x10a0>,
- <&apps_smmu 0x10a8>,
- <&apps_smmu 0x10b0>;
+ <&apps_smmu 0x10a0 0x0>,
+ <&apps_smmu 0x10a8 0x0>,
+ <&apps_smmu 0x10b0 0x0>;
buffer-types = <0xfff>;
virtual-addr-pool = <0x70800000 0x6f800000>;
};
@@ -108,10 +108,10 @@
compatible = "qcom,msm-vidc,context-bank";
label = "venus_sec_bitstream";
iommus =
- <&apps_smmu 0x10a1>,
- <&apps_smmu 0x10a9>,
- <&apps_smmu 0x10a5>,
- <&apps_smmu 0x10ad>;
+ <&apps_smmu 0x10a1 0x0>,
+ <&apps_smmu 0x10a9 0x0>,
+ <&apps_smmu 0x10a5 0x0>,
+ <&apps_smmu 0x10ad 0x0>;
buffer-types = <0x241>;
virtual-addr-pool = <0x4b000000 0x25800000>;
qcom,secure-context-bank;
@@ -121,8 +121,8 @@
compatible = "qcom,msm-vidc,context-bank";
label = "venus_sec_pixel";
iommus =
- <&apps_smmu 0x10a3>,
- <&apps_smmu 0x10ab>;
+ <&apps_smmu 0x10a3 0x0>,
+ <&apps_smmu 0x10ab 0x0>;
buffer-types = <0x106>;
virtual-addr-pool = <0x25800000 0x25800000>;
qcom,secure-context-bank;
@@ -132,9 +132,9 @@
compatible = "qcom,msm-vidc,context-bank";
label = "venus_sec_non_pixel";
iommus =
- <&apps_smmu 0x10a4>,
- <&apps_smmu 0x10ac>,
- <&apps_smmu 0x10b4>;
+ <&apps_smmu 0x10a4 0x0>,
+ <&apps_smmu 0x10ac 0x0>,
+ <&apps_smmu 0x10b4 0x0>;
buffer-types = <0x480>;
virtual-addr-pool = <0x1000000 0x24800000>;
qcom,secure-context-bank;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 5a8715c..b8018b6 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -34,6 +34,7 @@
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS slot */
ufshc2 = &ufshc_card; /* Removable UFS slot */
+ pci-domain0 = &pcie0;
sdhc2 = &sdhc_2; /* SDC2 SD card slot */
};
@@ -820,6 +821,13 @@
interrupts = <1 5 4>;
};
+ clock_rpmh: qcom,rpmhclk {
+ compatible = "qcom,rpmh-clk-sdm845";
+ #clock-cells = <1>;
+ mboxes = <&apps_rsc 0>;
+ mbox-names = "apps";
+ };
+
clock_gcc: qcom,gcc@100000 {
compatible = "qcom,gcc-sdm845", "syscon";
reg = <0x100000 0x1f0000>;
@@ -994,13 +1002,6 @@
#reset-cells = <1>;
};
- clock_rpmh: qcom,rpmhclk {
- compatible = "qcom,rpmh-clk-sdm845";
- #clock-cells = <1>;
- mboxes = <&apps_rsc 0>;
- mbox-names = "apps";
- };
-
clock_debug: qcom,cc-debug@100000 {
compatible = "qcom,debugcc-sdm845";
qcom,cc-count = <5>;
@@ -1021,6 +1022,29 @@
mbox-names = "qdss_clk";
};
+ ufs_ice: ufsice@1d90000 {
+ compatible = "qcom,ice";
+ reg = <0x1d90000 0x8000>;
+ qcom,enable-ice-clk;
+ clock-names = "ufs_core_clk", "bus_clk",
+ "iface_clk", "ice_core_clk";
+ clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
+ <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
+ <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
+ <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ qcom,msm-bus,name = "ufs_ice_noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 650 0 0>, /* No vote */
+ <1 650 1000 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN",
+ "MAX";
+ qcom,instance-type = "ufs";
+ };
+
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xda8>; /* PHY regs */
reg-names = "phy_mem";
@@ -1038,12 +1062,13 @@
status = "disabled";
};
- ufshc_mem: ufshc_mem@1d84000 {
+ ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x2500>;
interrupts = <0 265 0>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
+ ufs-qcom-crypto = <&ufs_ice>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
@@ -1290,9 +1315,12 @@
<0x1f65000 0x008>,
<0x1f64000 0x008>,
<0x4180000 0x020>,
- <0xc2b0000 0x004>;
+ <0xc2b0000 0x004>,
+ <0xb2e0100 0x004>,
+ <0x4180044 0x004>;
reg-names = "qdsp6_base", "halt_q6", "halt_modem",
- "halt_nc", "rmb_base", "restart_reg";
+ "halt_nc", "rmb_base", "restart_reg",
+ "pdc_sync", "alt_reset";
clocks = <&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_MSS_CFG_AHB_CLK>,
@@ -1419,6 +1447,7 @@
};
slim_qca: slim@17240000 {
+ status = "ok";
cell-index = <3>;
compatible = "qcom,slim-ngd";
reg = <0x17240000 0x2c000>,
@@ -1426,6 +1455,14 @@
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <0 291 0>, <0 292 0>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+
+ /* Slimbus Slave DT for WCN3990 */
+ btfmslim_codec: wcn3990 {
+ compatible = "qcom,btfmslim_slave";
+ elemental-addr = [00 01 20 02 17 02];
+ qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+ qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+ };
};
eud: qcom,msm-eud@88e0000 {
@@ -1537,76 +1574,76 @@
qcom,msm_fastrpc_compute_cb1 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
- iommus = <&apps_smmu 0x1401>,
- <&apps_smmu 0x1421>;
+ iommus = <&apps_smmu 0x1401 0x0>,
+ <&apps_smmu 0x1421 0x0>;
};
qcom,msm_fastrpc_compute_cb2 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
- iommus = <&apps_smmu 0x1402>,
- <&apps_smmu 0x1422>;
+ iommus = <&apps_smmu 0x1402 0x0>,
+ <&apps_smmu 0x1422 0x0>;
};
qcom,msm_fastrpc_compute_cb3 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
- iommus = <&apps_smmu 0x1403>,
- <&apps_smmu 0x1423>;
+ iommus = <&apps_smmu 0x1403 0x0>,
+ <&apps_smmu 0x1423 0x0>;
};
qcom,msm_fastrpc_compute_cb4 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
- iommus = <&apps_smmu 0x1404>,
- <&apps_smmu 0x1424>;
+ iommus = <&apps_smmu 0x1404 0x0>,
+ <&apps_smmu 0x1424 0x0>;
};
qcom,msm_fastrpc_compute_cb5 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
- iommus = <&apps_smmu 0x1405>,
- <&apps_smmu 0x1425>;
+ iommus = <&apps_smmu 0x1405 0x0>,
+ <&apps_smmu 0x1425 0x0>;
};
qcom,msm_fastrpc_compute_cb6 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
- iommus = <&apps_smmu 0x1406>,
- <&apps_smmu 0x1426>;
+ iommus = <&apps_smmu 0x1406 0x0>,
+ <&apps_smmu 0x1426 0x0>;
};
qcom,msm_fastrpc_compute_cb7 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
- iommus = <&apps_smmu 0x1407>,
- <&apps_smmu 0x1427>;
+ iommus = <&apps_smmu 0x1407 0x0>,
+ <&apps_smmu 0x1427 0x0>;
};
qcom,msm_fastrpc_compute_cb8 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
- iommus = <&apps_smmu 0x1408>,
- <&apps_smmu 0x1428>;
+ iommus = <&apps_smmu 0x1408 0x0>,
+ <&apps_smmu 0x1428 0x0>;
};
qcom,msm_fastrpc_compute_cb9 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
qcom,secure-context-bank;
- iommus = <&apps_smmu 0x1409>,
- <&apps_smmu 0x1419>,
- <&apps_smmu 0x1429>;
+ iommus = <&apps_smmu 0x1409 0x0>,
+ <&apps_smmu 0x1419 0x0>,
+ <&apps_smmu 0x1429 0x0>;
};
qcom,msm_fastrpc_compute_cb10 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
qcom,secure-context-bank;
- iommus = <&apps_smmu 0x140A>,
- <&apps_smmu 0x141A>,
- <&apps_smmu 0x142A>;
+ iommus = <&apps_smmu 0x140A 0x0>,
+ <&apps_smmu 0x141A 0x0>,
+ <&apps_smmu 0x142A 0x0>;
};
qcom,msm_fastrpc_compute_cb11 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
- iommus = <&apps_smmu 0x1823>;
+ iommus = <&apps_smmu 0x1823 0x0>;
};
qcom,msm_fastrpc_compute_cb12 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
- iommus = <&apps_smmu 0x1824>;
+ iommus = <&apps_smmu 0x1824 0x0>;
};
};
@@ -2148,6 +2185,65 @@
hyplog-size-offset = <0x414>;
};
+ qcom_cedev: qcedev@1de0000 {
+ compatible = "qcom,qcedev";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <0 272 0>;
+ qcom,bam-pipe-pair = <1>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,bam-ee = <0>;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <125 512 0 0>,
+ <125 512 393600 393600>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks = <&clock_gcc GCC_CE1_CLK>,
+ <&clock_gcc GCC_CE1_CLK>,
+ <&clock_gcc GCC_CE1_AHB_CLK>,
+ <&clock_gcc GCC_CE1_AXI_CLK>;
+ qcom,ce-opp-freq = <171430000>;
+ };
+
+ qcom_crypto: qcrypto@1de0000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <0 272 0>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,bam-ee = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <125 512 0 0>,
+ <125 512 393600 393600>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks = <&clock_gcc GCC_CE1_CLK>,
+ <&clock_gcc GCC_CE1_CLK>,
+ <&clock_gcc GCC_CE1_AHB_CLK>,
+ <&clock_gcc GCC_CE1_AXI_CLK>;
+ qcom,ce-opp-freq = <171430000>;
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-aead-algo;
+ qcom,use-sw-hmac-algo;
+ };
+
qcom,msm_gsi {
compatible = "qcom,msm_gsi";
};
@@ -2301,18 +2397,18 @@
ipa_smmu_ap: ipa_smmu_ap {
compatible = "qcom,ipa-smmu-ap-cb";
- iommus = <&apps_smmu 0x720>;
+ iommus = <&apps_smmu 0x720 0x0>;
qcom,iova-mapping = <0x20000000 0x40000000>;
};
ipa_smmu_wlan: ipa_smmu_wlan {
compatible = "qcom,ipa-smmu-wlan-cb";
- iommus = <&apps_smmu 0x721>;
+ iommus = <&apps_smmu 0x721 0x0>;
};
ipa_smmu_uc: ipa_smmu_uc {
compatible = "qcom,ipa-smmu-uc-cb";
- iommus = <&apps_smmu 0x722>;
+ iommus = <&apps_smmu 0x722 0x0>;
qcom,iova-mapping = <0x40000000 0x20000000>;
};
};
@@ -2356,7 +2452,7 @@
cmd_db: qcom,cmd-db@861e0000 {
compatible = "qcom,cmd-db";
- reg = <0x861e0000 0x4000>;
+ reg = <0xc3f000c 8>;
};
dcc: dcc_v2@10a2000 {
@@ -2379,8 +2475,8 @@
<0xa0000000 0x10000000>,
<0xb0000000 0x10000>;
reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
- iommus = <&apps_smmu 0x0040>,
- <&apps_smmu 0x0041>;
+ iommus = <&apps_smmu 0x0040 0x0>,
+ <&apps_smmu 0x0041 0x0>;
interrupts = <0 414 0 /* CE0 */ >,
<0 415 0 /* CE1 */ >,
<0 416 0 /* CE2 */ >,
@@ -3553,6 +3649,48 @@
#include "sdm845-vidc.dtsi"
#include "sdm845-pm.dtsi"
#include "sdm845-pinctrl.dtsi"
+#include "sdm845-pcie.dtsi"
#include "sdm845-audio.dtsi"
#include "sdm845-gpu.dtsi"
#include "sdm845-usb.dtsi"
+
+&pm8998_temp_alarm {
+ cooling-maps {
+ trip0_cpu0 {
+ trip = <&pm8998_trip0>;
+ cooling-device = <&CPU0 21 21>;
+ };
+ trip0_cpu4 {
+ trip = <&pm8998_trip0>;
+ cooling-device = <&CPU4 21 21>;
+ };
+ trip1_cpu1 {
+ trip = <&pm8998_trip1>;
+ cooling-device = <&CPU1 22 22>;
+ };
+ trip1_cpu2 {
+ trip = <&pm8998_trip1>;
+ cooling-device = <&CPU2 22 22>;
+ };
+ trip1_cpu3 {
+ trip = <&pm8998_trip1>;
+ cooling-device = <&CPU3 22 22>;
+ };
+ trip1_cpu4 {
+ trip = <&pm8998_trip1>;
+ cooling-device = <&CPU4 22 22>;
+ };
+ trip1_cpu5 {
+ trip = <&pm8998_trip1>;
+ cooling-device = <&CPU5 22 22>;
+ };
+ trip1_cpu6 {
+ trip = <&pm8998_trip1>;
+ cooling-device = <&CPU6 22 22>;
+ };
+ trip1_cpu7 {
+ trip = <&pm8998_trip1>;
+ cooling-device = <&CPU7 22 22>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/smb1355.dtsi b/arch/arm64/boot/dts/qcom/smb1355.dtsi
new file mode 100644
index 0000000..33c5e97
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/smb1355.dtsi
@@ -0,0 +1,55 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&qupv3_se10_i2c {
+ smb1355: qcom,smb1355@8 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x0 0xd1 0x0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt_names = "smb1355";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ qcom,periph-map = <0x10 0x12 0x13 0x16>;
+
+ smb1355_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ smb1355_charger: qcom,smb1355-charger@1000 {
+ compatible = "qcom,smb1355";
+ qcom,pmic-revid = <&smb1355_revid>;
+ reg = <0x1000 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&smb1355>;
+ status = "disabled";
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "chg-state-change";
+ };
+
+ qcom,chgr-misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog-bark";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/configs/sdm845-perf_defconfig b/arch/arm64/configs/sdm845-perf_defconfig
index fa6bae8..531d236 100644
--- a/arch/arm64/configs/sdm845-perf_defconfig
+++ b/arch/arm64/configs/sdm845-perf_defconfig
@@ -49,6 +49,7 @@
CONFIG_ARCH_SDM845=y
CONFIG_ARCH_SDM830=y
CONFIG_PCI=y
+CONFIG_PCI_MSM=y
CONFIG_SCHED_MC=y
CONFIG_NR_CPUS=8
CONFIG_PREEMPT=y
@@ -238,6 +239,7 @@
CONFIG_SCSI_UFSHCD=y
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_QCOM=y
+CONFIG_SCSI_UFS_QCOM_ICE=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
@@ -298,8 +300,8 @@
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_QPNP_FG_GEN3=y
+CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_SMB2=y
-CONFIG_SMB138X_CHARGER=y
CONFIG_QPNP_QNOVO=y
CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
CONFIG_THERMAL=y
@@ -336,6 +338,7 @@
CONFIG_MSM_VIDC_GOVERNORS=y
CONFIG_MSM_SDE_ROTATOR=y
CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y
+CONFIG_QCOM_KGSL=y
CONFIG_DRM=y
CONFIG_DRM_SDE_EVTLOG_DEBUG=y
CONFIG_DRM_SDE_RSC=y
@@ -445,6 +448,8 @@
CONFIG_QCOM_RUN_QUEUE_STATS=y
CONFIG_QCOM_LLCC=y
CONFIG_QCOM_SDM845_LLCC=y
+CONFIG_MSM_SERVICE_LOCATOR=y
+CONFIG_MSM_SERVICE_NOTIFIER=y
CONFIG_MSM_BOOT_STATS=y
CONFIG_QCOM_EUD=y
CONFIG_QCOM_WATCHDOG_V2=y
@@ -473,10 +478,13 @@
CONFIG_MSM_PIL_MSS_QDSP6V5=y
CONFIG_ICNSS=y
CONFIG_QCOM_COMMAND_DB=y
+CONFIG_MSM_ADSP_LOADER=y
+CONFIG_MSM_CDSP_LOADER=y
CONFIG_MSM_AVTIMER=y
CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_PM=y
CONFIG_APSS_CORE_EA=y
+CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
CONFIG_QCOM_BIMC_BWMON=y
CONFIG_ARM_MEMLAT_MON=y
CONFIG_QCOMCCI_HWMON=y
@@ -536,7 +544,10 @@
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_ANSI_CPRNG=y
-CONFIG_CRYPTO_DEV_QCE=y
+CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
+CONFIG_CRYPTO_DEV_QCRYPTO=y
+CONFIG_CRYPTO_DEV_QCEDEV=y
+CONFIG_CRYPTO_DEV_QCOM_ICE=y
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
diff --git a/arch/arm64/configs/sdm845_defconfig b/arch/arm64/configs/sdm845_defconfig
index 1f0418f..cbcf515 100644
--- a/arch/arm64/configs/sdm845_defconfig
+++ b/arch/arm64/configs/sdm845_defconfig
@@ -54,12 +54,14 @@
CONFIG_ARCH_SDM845=y
CONFIG_ARCH_SDM830=y
CONFIG_PCI=y
+CONFIG_PCI_MSM=y
CONFIG_SCHED_MC=y
CONFIG_NR_CPUS=8
CONFIG_PREEMPT=y
CONFIG_HZ_100=y
CONFIG_CLEANCACHE=y
CONFIG_CMA=y
+CONFIG_CMA_DEBUGFS=y
CONFIG_ZSMALLOC=y
CONFIG_BALANCE_ANON_FILE_RECLAIM=y
CONFIG_SECCOMP=y
@@ -248,6 +250,7 @@
CONFIG_SCSI_UFSHCD=y
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_QCOM=y
+CONFIG_SCSI_UFS_QCOM_ICE=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
@@ -306,8 +309,8 @@
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_QPNP_FG_GEN3=y
+CONFIG_SMB1355_SLAVE_CHARGER=y
CONFIG_QPNP_SMB2=y
-CONFIG_SMB138X_CHARGER=y
CONFIG_QPNP_QNOVO=y
CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y
CONFIG_THERMAL=y
@@ -462,6 +465,8 @@
CONFIG_QCOM_RUN_QUEUE_STATS=y
CONFIG_QCOM_LLCC=y
CONFIG_QCOM_SDM845_LLCC=y
+CONFIG_MSM_SERVICE_LOCATOR=y
+CONFIG_MSM_SERVICE_NOTIFIER=y
CONFIG_MSM_BOOT_STATS=y
CONFIG_MSM_CORE_HANG_DETECT=y
CONFIG_MSM_GLADIATOR_HANG_DETECT=y
@@ -493,11 +498,14 @@
CONFIG_ICNSS=y
CONFIG_ICNSS_DEBUG=y
CONFIG_QCOM_COMMAND_DB=y
+CONFIG_MSM_ADSP_LOADER=y
+CONFIG_MSM_CDSP_LOADER=y
CONFIG_MSM_AVTIMER=y
CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_PM=y
CONFIG_APSS_CORE_EA=y
CONFIG_QCOM_DCC_V2=y
+CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
CONFIG_QCOM_BIMC_BWMON=y
CONFIG_ARM_MEMLAT_MON=y
CONFIG_QCOMCCI_HWMON=y
@@ -606,7 +614,10 @@
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_ANSI_CPRNG=y
-CONFIG_CRYPTO_DEV_QCE=y
+CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
+CONFIG_CRYPTO_DEV_QCRYPTO=y
+CONFIG_CRYPTO_DEV_QCEDEV=y
+CONFIG_CRYPTO_DEV_QCOM_ICE=y
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 804d2a2..dd6a18b 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -80,7 +80,7 @@
}
/* Sorted insert of 75th percentile into buf2 */
- for (k = 0; k < i; ++k) {
+ for (k = 0; k < i && k < ARRAY_SIZE(buf2); ++k) {
if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) {
l = min_t(unsigned int,
i, ARRAY_SIZE(buf2) - 1);
diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c
index 6430bff..5c429d7 100644
--- a/arch/mips/kernel/elf.c
+++ b/arch/mips/kernel/elf.c
@@ -257,7 +257,7 @@
else if ((prog_req.fr1 && prog_req.frdefault) ||
(prog_req.single && !prog_req.frdefault))
/* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */
- state->overall_fp_mode = ((current_cpu_data.fpu_id & MIPS_FPIR_F64) &&
+ state->overall_fp_mode = ((raw_current_cpu_data.fpu_id & MIPS_FPIR_F64) &&
cpu_has_mips_r2_r6) ?
FP_FR1 : FP_FR0;
else if (prog_req.fr1)
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
index de63d36..732d617 100644
--- a/arch/mips/kernel/kgdb.c
+++ b/arch/mips/kernel/kgdb.c
@@ -244,9 +244,6 @@
void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
{
int reg;
- struct thread_info *ti = task_thread_info(p);
- unsigned long ksp = (unsigned long)ti + THREAD_SIZE - 32;
- struct pt_regs *regs = (struct pt_regs *)ksp - 1;
#if (KGDB_GDB_REG_SIZE == 32)
u32 *ptr = (u32 *)gdb_regs;
#else
@@ -254,25 +251,46 @@
#endif
for (reg = 0; reg < 16; reg++)
- *(ptr++) = regs->regs[reg];
+ *(ptr++) = 0;
/* S0 - S7 */
- for (reg = 16; reg < 24; reg++)
- *(ptr++) = regs->regs[reg];
+ *(ptr++) = p->thread.reg16;
+ *(ptr++) = p->thread.reg17;
+ *(ptr++) = p->thread.reg18;
+ *(ptr++) = p->thread.reg19;
+ *(ptr++) = p->thread.reg20;
+ *(ptr++) = p->thread.reg21;
+ *(ptr++) = p->thread.reg22;
+ *(ptr++) = p->thread.reg23;
for (reg = 24; reg < 28; reg++)
*(ptr++) = 0;
/* GP, SP, FP, RA */
- for (reg = 28; reg < 32; reg++)
- *(ptr++) = regs->regs[reg];
+ *(ptr++) = (long)p;
+ *(ptr++) = p->thread.reg29;
+ *(ptr++) = p->thread.reg30;
+ *(ptr++) = p->thread.reg31;
- *(ptr++) = regs->cp0_status;
- *(ptr++) = regs->lo;
- *(ptr++) = regs->hi;
- *(ptr++) = regs->cp0_badvaddr;
- *(ptr++) = regs->cp0_cause;
- *(ptr++) = regs->cp0_epc;
+ *(ptr++) = p->thread.cp0_status;
+
+ /* lo, hi */
+ *(ptr++) = 0;
+ *(ptr++) = 0;
+
+ /*
+ * BadVAddr, Cause
+ * Ideally these would come from the last exception frame up the stack
+ * but that requires unwinding, otherwise we can't know much for sure.
+ */
+ *(ptr++) = 0;
+ *(ptr++) = 0;
+
+ /*
+ * PC
+ * use return address (RA), i.e. the moment after return from resume()
+ */
+ *(ptr++) = p->thread.reg31;
}
void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc)
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index 1fb317f..b6802b9 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -673,6 +673,14 @@
return pte_pfn(pte);
}
+#define __HAVE_ARCH_PMD_WRITE
+static inline unsigned long pmd_write(pmd_t pmd)
+{
+ pte_t pte = __pte(pmd_val(pmd));
+
+ return pte_write(pte);
+}
+
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
static inline unsigned long pmd_dirty(pmd_t pmd)
{
@@ -688,13 +696,6 @@
return pte_young(pte);
}
-static inline unsigned long pmd_write(pmd_t pmd)
-{
- pte_t pte = __pte(pmd_val(pmd));
-
- return pte_write(pte);
-}
-
static inline unsigned long pmd_trans_huge(pmd_t pmd)
{
pte_t pte = __pte(pmd_val(pmd));
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index 37aa537..bd7e2aa 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -1495,7 +1495,7 @@
if ((long)addr < 0L) {
unsigned long pa = __pa(addr);
- if ((addr >> max_phys_bits) != 0UL)
+ if ((pa >> max_phys_bits) != 0UL)
return false;
return pfn_valid(pa >> PAGE_SHIFT);
diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c
index 8639bb2..6bf09f5 100644
--- a/arch/x86/kernel/ftrace.c
+++ b/arch/x86/kernel/ftrace.c
@@ -983,6 +983,18 @@
unsigned long return_hooker = (unsigned long)
&return_to_handler;
+ /*
+ * When resuming from suspend-to-ram, this function can be indirectly
+ * called from early CPU startup code while the CPU is in real mode,
+ * which would fail miserably. Make sure the stack pointer is a
+ * virtual address.
+ *
+ * This check isn't as accurate as virt_addr_valid(), but it should be
+ * good enough for this purpose, and it's fast.
+ */
+ if (unlikely((long)__builtin_frame_address(0) >= 0))
+ return;
+
if (unlikely(ftrace_graph_is_dead()))
return;
diff --git a/drivers/base/firmware_class.c b/drivers/base/firmware_class.c
index a95e1e5..f18ae62 100644
--- a/drivers/base/firmware_class.c
+++ b/drivers/base/firmware_class.c
@@ -229,20 +229,22 @@
static int fw_lookup_and_allocate_buf(const char *fw_name,
struct firmware_cache *fwc,
struct firmware_buf **buf, void *dbuf,
- size_t size)
+ size_t size, unsigned int opt_flags)
{
struct firmware_buf *tmp;
spin_lock(&fwc->lock);
- tmp = __fw_lookup_buf(fw_name);
- if (tmp) {
- kref_get(&tmp->ref);
- spin_unlock(&fwc->lock);
- *buf = tmp;
- return 1;
+ if (!(opt_flags & FW_OPT_NOCACHE)) {
+ tmp = __fw_lookup_buf(fw_name);
+ if (tmp) {
+ kref_get(&tmp->ref);
+ spin_unlock(&fwc->lock);
+ *buf = tmp;
+ return 1;
+ }
}
tmp = __allocate_fw_buf(fw_name, fwc, dbuf, size);
- if (tmp)
+ if (tmp && !(opt_flags & FW_OPT_NOCACHE))
list_add(&tmp->list, &fwc->head);
spin_unlock(&fwc->lock);
@@ -1051,7 +1053,8 @@
*/
static int
_request_firmware_prepare(struct firmware **firmware_p, const char *name,
- struct device *device, void *dbuf, size_t size)
+ struct device *device, void *dbuf, size_t size,
+ unsigned int opt_flags)
{
struct firmware *firmware;
struct firmware_buf *buf;
@@ -1069,7 +1072,8 @@
return 0; /* assigned */
}
- ret = fw_lookup_and_allocate_buf(name, &fw_cache, &buf, dbuf, size);
+ ret = fw_lookup_and_allocate_buf(name, &fw_cache, &buf, dbuf, size,
+ opt_flags);
/*
* bind with 'buf' now to avoid warning in failure path
@@ -1147,7 +1151,8 @@
goto out;
}
- ret = _request_firmware_prepare(&fw, name, device, buf, size);
+ ret = _request_firmware_prepare(&fw, name, device, buf, size,
+ opt_flags);
if (ret <= 0) /* error or already assigned */
goto out;
diff --git a/drivers/char/tpm/tpm-interface.c b/drivers/char/tpm/tpm-interface.c
index 3a9149c..d0ac2d5 100644
--- a/drivers/char/tpm/tpm-interface.c
+++ b/drivers/char/tpm/tpm-interface.c
@@ -489,8 +489,7 @@
int tpm_get_timeouts(struct tpm_chip *chip)
{
struct tpm_cmd_t tpm_cmd;
- unsigned long new_timeout[4];
- unsigned long old_timeout[4];
+ unsigned long timeout_old[4], timeout_chip[4], timeout_eff[4];
struct duration_t *duration_cap;
ssize_t rc;
@@ -542,11 +541,15 @@
!= sizeof(tpm_cmd.header.out) + sizeof(u32) + 4 * sizeof(u32))
return -EINVAL;
- old_timeout[0] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.a);
- old_timeout[1] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.b);
- old_timeout[2] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.c);
- old_timeout[3] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.d);
- memcpy(new_timeout, old_timeout, sizeof(new_timeout));
+ timeout_old[0] = jiffies_to_usecs(chip->timeout_a);
+ timeout_old[1] = jiffies_to_usecs(chip->timeout_b);
+ timeout_old[2] = jiffies_to_usecs(chip->timeout_c);
+ timeout_old[3] = jiffies_to_usecs(chip->timeout_d);
+ timeout_chip[0] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.a);
+ timeout_chip[1] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.b);
+ timeout_chip[2] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.c);
+ timeout_chip[3] = be32_to_cpu(tpm_cmd.params.getcap_out.cap.timeout.d);
+ memcpy(timeout_eff, timeout_chip, sizeof(timeout_eff));
/*
* Provide ability for vendor overrides of timeout values in case
@@ -554,16 +557,24 @@
*/
if (chip->ops->update_timeouts != NULL)
chip->timeout_adjusted =
- chip->ops->update_timeouts(chip, new_timeout);
+ chip->ops->update_timeouts(chip, timeout_eff);
if (!chip->timeout_adjusted) {
- /* Don't overwrite default if value is 0 */
- if (new_timeout[0] != 0 && new_timeout[0] < 1000) {
- int i;
+ /* Restore default if chip reported 0 */
+ int i;
+ for (i = 0; i < ARRAY_SIZE(timeout_eff); i++) {
+ if (timeout_eff[i])
+ continue;
+
+ timeout_eff[i] = timeout_old[i];
+ chip->timeout_adjusted = true;
+ }
+
+ if (timeout_eff[0] != 0 && timeout_eff[0] < 1000) {
/* timeouts in msec rather usec */
- for (i = 0; i != ARRAY_SIZE(new_timeout); i++)
- new_timeout[i] *= 1000;
+ for (i = 0; i != ARRAY_SIZE(timeout_eff); i++)
+ timeout_eff[i] *= 1000;
chip->timeout_adjusted = true;
}
}
@@ -572,16 +583,16 @@
if (chip->timeout_adjusted) {
dev_info(&chip->dev,
HW_ERR "Adjusting reported timeouts: A %lu->%luus B %lu->%luus C %lu->%luus D %lu->%luus\n",
- old_timeout[0], new_timeout[0],
- old_timeout[1], new_timeout[1],
- old_timeout[2], new_timeout[2],
- old_timeout[3], new_timeout[3]);
+ timeout_chip[0], timeout_eff[0],
+ timeout_chip[1], timeout_eff[1],
+ timeout_chip[2], timeout_eff[2],
+ timeout_chip[3], timeout_eff[3]);
}
- chip->timeout_a = usecs_to_jiffies(new_timeout[0]);
- chip->timeout_b = usecs_to_jiffies(new_timeout[1]);
- chip->timeout_c = usecs_to_jiffies(new_timeout[2]);
- chip->timeout_d = usecs_to_jiffies(new_timeout[3]);
+ chip->timeout_a = usecs_to_jiffies(timeout_eff[0]);
+ chip->timeout_b = usecs_to_jiffies(timeout_eff[1]);
+ chip->timeout_c = usecs_to_jiffies(timeout_eff[2]);
+ chip->timeout_d = usecs_to_jiffies(timeout_eff[3]);
duration:
tpm_cmd.header.in = tpm_getcap_header;
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index b248b1b..1b545d6 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1709,8 +1709,14 @@
}
}
+ /*
+ * The Fabia PLLs only have 16 bits to program the fractional divider.
+ * Hence the programmed rate might be slightly different than the
+ * requested one.
+ */
if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
- best_parent_rate != parent->rate)
+ (DIV_ROUND_CLOSEST(best_parent_rate, 1000) !=
+ DIV_ROUND_CLOSEST(parent->rate, 1000)))
top = clk_calc_new_rates(parent, best_parent_rate);
out:
@@ -2345,6 +2351,56 @@
NULL,
};
+static void clk_state_subtree(struct clk_core *c)
+{
+ int vdd_level = 0;
+ struct clk_core *child;
+
+ if (!c)
+ return;
+
+ if (c->vdd_class) {
+ vdd_level = clk_find_vdd_level(c, c->rate);
+ if (vdd_level < 0)
+ vdd_level = 0;
+ }
+
+ trace_clk_state(c->name, c->prepare_count, c->enable_count,
+ c->rate, vdd_level);
+
+ hlist_for_each_entry(child, &c->children, child_node)
+ clk_state_subtree(child);
+}
+
+static int clk_state_show(struct seq_file *s, void *data)
+{
+ struct clk_core *c;
+ struct hlist_head **lists = (struct hlist_head **)s->private;
+
+ clk_prepare_lock();
+
+ for (; *lists; lists++)
+ hlist_for_each_entry(c, *lists, child_node)
+ clk_state_subtree(c);
+
+ clk_prepare_unlock();
+
+ return 0;
+}
+
+
+static int clk_state_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, clk_state_show, inode->i_private);
+}
+
+static const struct file_operations clk_state_fops = {
+ .open = clk_state_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
int level)
{
@@ -2980,6 +3036,11 @@
if (!d)
return -ENOMEM;
+ d = debugfs_create_file("trace_clocks", 0444, rootdir, &all_lists,
+ &clk_state_fops);
+ if (!d)
+ return -ENOMEM;
+
mutex_lock(&clk_debug_lock);
hlist_for_each_entry(core, &clk_debug_list, debug_node)
clk_debug_create_one(core, rootdir);
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 6ff621d..d15d1bb 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -307,6 +307,15 @@
u64 quotient;
int alpha_bw = ALPHA_BITWIDTH;
+ /*
+ * The PLLs parent rate is zero probably since the parent hasn't
+ * registered yet. Return early with the requested rate.
+ */
+ if (!prate) {
+ pr_debug("PLLs parent rate hasn't been initialized.\n");
+ return rate;
+ }
+
quotient = rate;
remainder = do_div(quotient, prate);
*l = quotient;
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 2f9cfdf..3d101ac 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -1064,17 +1064,10 @@
}
static int clk_dp_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
+ struct clk_rate_request *req)
{
- if (!hw)
- return -EINVAL;
-
- if (!clk_hw_get_parent(hw)) {
- pr_err("Missing the parent for the DP RCG\n");
- return -EINVAL;
- }
-
- req->best_parent_rate = clk_get_rate(clk_hw_get_parent(hw)->clk);
+ req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw,
+ req->best_parent_rate);
return 0;
}
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
index 3b56fa1..d3a28e6 100644
--- a/drivers/clk/qcom/dispcc-sdm845.c
+++ b/drivers/clk/qcom/dispcc-sdm845.c
@@ -80,8 +80,8 @@
static const char * const disp_cc_parent_names_1[] = {
"bi_tcxo",
- "dp_phy_pll_link_clk",
- "dp_phy_pll_vco_div_clk",
+ "dp_link_clk_divsel_ten",
+ "dp_vco_divided_clk_src_mux",
"core_bi_pll_test_se",
};
@@ -217,12 +217,11 @@
},
};
-/* Need to get the exact frequencies that are supported */
static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = {
- F( 108000000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
- F( 180000000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
- F( 360000000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
- F( 540000000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
+ F( 108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
+ F( 180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
+ F( 360000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
+ F( 540000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
{ }
};
@@ -236,23 +235,22 @@
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_names = disp_cc_parent_names_1,
.num_parents = 4,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
VDD_CX_FMAX_MAP5(
- MIN, 12800000,
- LOWER, 108000000,
- LOW, 180000000,
- LOW_L1, 360000000,
- NOMINAL, 540000000),
+ MIN, 12800,
+ LOWER, 108000,
+ LOW, 180000,
+ LOW_L1, 360000,
+ NOMINAL, 540000),
},
};
-/* Need to get the exact frequencies that are supported */
static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
- F_SLEW( 162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0, 324000000),
- F_SLEW( 270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0, 540000000),
- F_SLEW( 540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0, 1080000000),
- F_SLEW( 810000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0, 1620000000),
+ F( 162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F( 270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F( 540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F( 810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
{ }
};
@@ -269,11 +267,11 @@
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_rcg2_ops,
VDD_CX_FMAX_MAP5(
- MIN, 19200000,
- LOWER, 162000000,
- LOW, 270000000,
- LOW_L1, 540000000,
- NOMINAL, 810000000),
+ MIN, 19200,
+ LOWER, 162000,
+ LOW, 270000,
+ LOW_L1, 540000,
+ NOMINAL, 810000),
},
};
@@ -284,17 +282,15 @@
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel1_clk_src",
- .parent_names = (const char *[]){
- "dp_phy_pll_vco_div_clk",
- },
- .num_parents = 1,
+ .parent_names = disp_cc_parent_names_1,
+ .num_parents = 4,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_dp_ops,
VDD_CX_FMAX_MAP4(
- MIN, 19200000,
- LOWER, 202500000,
- LOW, 296735905,
- LOW_L1, 675000000),
+ MIN, 19200,
+ LOWER, 202500,
+ LOW, 296735,
+ LOW_L1, 675000),
},
};
@@ -305,17 +301,15 @@
.parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src",
- .parent_names = (const char *[]){
- "dp_phy_pll_vco_div_clk",
- },
- .num_parents = 1,
+ .parent_names = disp_cc_parent_names_1,
+ .num_parents = 4,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.ops = &clk_dp_ops,
VDD_CX_FMAX_MAP4(
- MIN, 19200000,
- LOWER, 202500000,
- LOW, 296735905,
- LOW_L1, 675000000),
+ MIN, 19200,
+ LOWER, 202500,
+ LOW, 296735,
+ LOW_L1, 675000),
},
};
@@ -664,23 +658,7 @@
},
};
-static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
- .reg = 0x2150,
- .shift = 0,
- .width = 2,
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "disp_cc_mdss_dp_link_div_clk_src",
- .parent_names = (const char *[]){
- "disp_cc_mdss_dp_link_clk_src",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
- .ops = &clk_regmap_div_ops,
- },
- },
-};
-
+/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */
static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
.halt_reg = 0x2044,
.halt_check = BRANCH_HALT,
@@ -690,10 +668,10 @@
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_intf_clk",
.parent_names = (const char *[]){
- "disp_cc_mdss_dp_link_div_clk_src",
+ "disp_cc_mdss_dp_link_clk_src",
},
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .flags = CLK_GET_RATE_NOCACHE,
.ops = &clk_branch2_ops,
},
},
@@ -955,8 +933,6 @@
&disp_cc_mdss_dp_crypto_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
- [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =
- &disp_cc_mdss_dp_link_div_clk_src.clkr,
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
[DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =
diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c
index 9ce0afc..2cb9d05 100644
--- a/drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c
+++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c
@@ -1241,7 +1241,7 @@
static struct clk_regmap_mux dsi0pll_byteclk_mux = {
.shift = 0,
- .width = 0,
+ .width = 1,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "dsi0_phy_pll_out_byteclk",
@@ -1255,7 +1255,7 @@
static struct clk_regmap_mux dsi1pll_byteclk_mux = {
.shift = 0,
- .width = 0,
+ .width = 1,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "dsi1_phy_pll_out_byteclk",
@@ -1269,7 +1269,7 @@
static struct clk_regmap_mux dsi0pll_pclk_src_mux = {
.shift = 0,
- .width = 0,
+ .width = 1,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "dsi0pll_pclk_src_mux",
@@ -1284,7 +1284,7 @@
static struct clk_regmap_mux dsi1pll_pclk_src_mux = {
.shift = 0,
- .width = 0,
+ .width = 1,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "dsi1pll_pclk_src_mux",
@@ -1329,7 +1329,7 @@
static struct clk_regmap_mux dsi0pll_pclk_mux = {
.shift = 0,
- .width = 0,
+ .width = 1,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "dsi0_phy_pll_out_dsiclk",
@@ -1343,7 +1343,7 @@
static struct clk_regmap_mux dsi1pll_pclk_mux = {
.shift = 0,
- .width = 0,
+ .width = 1,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "dsi1_phy_pll_out_dsiclk",
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index fd02eba..f61b78a 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -385,58 +385,6 @@
Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES
algorithms execution.
-config CRYPTO_DEV_QCE50
- bool
-
-config FIPS_ENABLE
- bool "FIPS140-2 compliant build"
- default n
- help
- This flag is used to make current build FIPS140-2
- compliant. This flag will enable the patch of code
- which will perform this task. Please select Y here
- to enable.
-
-config CRYPTO_DEV_QCRYPTO
- tristate "QTI Crypto accelerator"
- select CRYPTO_DES
- select CRYPTO_ALGAPI
- select CRYPTO_AUTHENC
- select CRYPTO_BLKCIPHER
- default n
- help
- This driver supports QTI crypto acceleration
- for kernel clients. To compile this driver as a module,
- choose M here: the module will be called qcrypto. Please
- select Y here to enable.
-
-config CRYPTO_DEV_QCOM_MSM_QCE
- tristate "QTI Crypto Engine (QCE) module"
- default n
- help
- This driver supports QTI Crypto Engine 5.0.
- To compile this driver as a module, choose M here: the
- module is called qce50.
-
-config CRYPTO_DEV_QCEDEV
- tristate "QCEDEV Interface to CE module"
- default n
- help
- This driver supports QTI QCEDEV Crypto Engine 5.0.
- This exposes the interface to the QCE hardware accelerator
- via IOCTLs.
-
- To compile this driver as a module, choose M here: the
- module will be called qcedev.
-
-config CRYPTO_DEV_OTA_CRYPTO
- tristate "OTA Crypto module"
- help
- This driver supports QTI OTA Crypto in the FSM9xxx.
- To compile this driver as a module, choose M here: the
- module will be called ota_crypto. Please select Y here
- to enable.
-
config CRYPTO_DEV_NX
bool "Support for IBM PowerPC Nest (NX) cryptographic acceleration"
depends on PPC64
@@ -550,7 +498,49 @@
help
This driver supports Qualcomm crypto engine accelerator
hardware. To compile this driver as a module, choose M here. The
- module will be called qcrypto.
+ module will be called qcrypt.
+
+config CRYPTO_DEV_QCOM_MSM_QCE
+ tristate "QTI Crypto Engine (QCE) module"
+ depends on ARCH_QCOM
+ help
+ This driver supports QTI Crypto Engine accelerator hardware, which
+ is present on SDM845. This is the core crypto driver which adds
+ CE5.0 functionalities. To compile this driver as a module, choose
+ M here. The module will be called QCE50.
+
+config CRYPTO_DEV_QCRYPTO
+ tristate "QTI Crypto accelerator"
+ depends on ARCH_QCOM
+ select CRYPTO_DES
+ select CRYPTO_ALGAPI
+ select CRYPTO_AUTHENC
+ select CRYPTO_BLKCIPHER
+ help
+ This driver supports QTI crypto acceleration
+ for kernel clients. To compile this driver as a module,
+ choose M here: the module will be called qcrypto. Please
+ select Y here to enable.
+
+config CRYPTO_DEV_QCEDEV
+ tristate "QCEDEV Interface to CE module"
+ depends on ARCH_QCOM
+ help
+ This driver supports QTI QCEDEV Crypto Engine 5.0.
+ This exposes the interface to the QCE hardware accelerator
+ via IOCTLs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called qcedev.
+
+config CRYPTO_DEV_OTA_CRYPTO
+ tristate "OTA Crypto module"
+ depends on ARCH_QCOM
+ help
+ This driver supports QTI OTA Crypto in the FSM9xxx.
+ To compile this driver as a module, choose M here: the
+ module will be called ota_crypto. Please select Y here
+ to enable.
config CRYPTO_DEV_VMX
bool "Support for VMX cryptographic acceleration instructions"
diff --git a/drivers/crypto/msm/Kconfig b/drivers/crypto/msm/Kconfig
index 0f4568b..3011aa6 100644
--- a/drivers/crypto/msm/Kconfig
+++ b/drivers/crypto/msm/Kconfig
@@ -2,7 +2,7 @@
config CRYPTO_DEV_QCOM_ICE
tristate "Inline Crypto Module"
default n
- depends on PFK && BLK_DEV_DM
+ depends on BLK_DEV_DM
help
This driver supports Inline Crypto Engine for QTI chipsets, MSM8994
and later, to accelerate crypto operations for storage needs.
diff --git a/drivers/crypto/msm/ice.c b/drivers/crypto/msm/ice.c
index ba6825e..b411726 100644
--- a/drivers/crypto/msm/ice.c
+++ b/drivers/crypto/msm/ice.c
@@ -21,12 +21,31 @@
#include <linux/cdev.h>
#include <linux/regulator/consumer.h>
#include <linux/msm-bus.h>
-#include <linux/pfk.h>
#include <crypto/ice.h>
#include <soc/qcom/scm.h>
#include <soc/qcom/qseecomi.h>
#include "iceregs.h"
+#ifdef CONFIG_PFK
+#include <linux/pfk.h>
+#else
+#include <linux/bio.h>
+static inline int pfk_load_key_start(const struct bio *bio,
+ struct ice_crypto_setting *ice_setting, bool *is_pfe, bool async)
+{
+ return 0;
+}
+
+static inline int pfk_load_key_end(const struct bio *bio, bool *is_pfe)
+{
+ return 0;
+}
+
+static inline void pfk_clear_on_reset(void)
+{
+}
+#endif
+
#define TZ_SYSCALL_CREATE_SMC_ID(o, s, f) \
((uint32_t)((((o & 0x3f) << 24) | (s & 0xff) << 8) | (f & 0xff)))
diff --git a/drivers/crypto/qce/Makefile b/drivers/crypto/qce/Makefile
index 348dc31..7f584ee 100644
--- a/drivers/crypto/qce/Makefile
+++ b/drivers/crypto/qce/Makefile
@@ -1,5 +1,5 @@
-obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypto.o
-qcrypto-objs := core.o \
+obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypt.o
+qcrypt-objs := core.o \
common.o \
dma.o \
sha.o \
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
index 9a71ea0..5604bf1 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
@@ -259,15 +259,11 @@
dsi_ctrl->cell_index, op_state);
rc = -EINVAL;
} else if (state->power_state == DSI_CTRL_POWER_VREG_ON) {
- if ((state->cmd_engine_state == DSI_CTRL_ENGINE_ON) ||
- (state->vid_engine_state == DSI_CTRL_ENGINE_ON) ||
- (state->controller_state == DSI_CTRL_ENGINE_ON)) {
- pr_debug("[%d]State error: op=%d: %d, %d, %d\n",
+ if (state->vid_engine_state == DSI_CTRL_ENGINE_ON) {
+ pr_debug("[%d]State error: op=%d: %d\n",
dsi_ctrl->cell_index,
op_state,
- state->cmd_engine_state,
- state->vid_engine_state,
- state->controller_state);
+ state->vid_engine_state);
rc = -EINVAL;
}
}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
index ee39ec7..563285d 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
@@ -408,6 +408,7 @@
u32 pixel_clk_khz;
enum dsi_op_mode panel_mode;
u32 dsi_mode_flags;
+ struct msm_mode_info *mode_info;
};
#endif /* _DSI_DEFS_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index 106511c..3402d48 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -1373,6 +1373,11 @@
if (rc)
pr_err("%s: Failed to enable dsi clamps. rc=%d\n",
__func__, rc);
+
+ rc = dsi_display_phy_reset_config(display, false);
+ if (rc)
+ pr_err("%s: Failed to reset phy, rc=%d\n",
+ __func__, rc);
} else {
/* Make sure that controller is not in ULPS state when
* the DSI link is not active.
@@ -1428,6 +1433,13 @@
}
}
+ rc = dsi_display_phy_reset_config(display, true);
+ if (rc) {
+ pr_err("%s: Failed to reset phy, rc=%d\n",
+ __func__, rc);
+ goto error;
+ }
+
rc = dsi_display_set_clamp(display, false);
if (rc) {
pr_err("%s: Failed to disable dsi clamps. rc=%d\n",
@@ -2973,18 +2985,11 @@
goto error_phy_disable;
}
- rc = dsi_display_phy_reset_config(display, true);
- if (rc) {
- pr_err("[%s] failed to setup DSI controller, rc=%d\n",
- display->name, rc);
- goto error_ctrl_deinit;
- }
-
rc = dsi_display_set_clk_src(display);
if (rc) {
pr_err("[%s] failed to set DSI link clock source, rc=%d\n",
display->name, rc);
- goto error_phy_reset_off;
+ goto error_ctrl_deinit;
}
rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
@@ -2992,7 +2997,7 @@
if (rc) {
pr_err("[%s] failed to enable DSI link clocks, rc=%d\n",
display->name, rc);
- goto error_phy_reset_off;
+ goto error_ctrl_deinit;
}
rc = dsi_display_ctrl_host_enable(display);
@@ -3015,8 +3020,6 @@
error_ctrl_link_off:
(void)dsi_display_clk_ctrl(display->dsi_clk_handle,
DSI_LINK_CLK, DSI_CLK_OFF);
-error_phy_reset_off:
- (void)dsi_display_phy_reset_config(display, false);
error_ctrl_deinit:
(void)dsi_display_ctrl_deinit(display);
error_phy_disable:
@@ -3110,6 +3113,11 @@
pr_err("[%s] panel post-enable failed, rc=%d\n",
display->name, rc);
+ /* remove the clk vote for CMD mode panels */
+ if (display->config.panel_mode == DSI_OP_CMD_MODE)
+ dsi_display_clk_ctrl(display->dsi_clk_handle,
+ DSI_ALL_CLKS, DSI_CLK_OFF);
+
mutex_unlock(&display->display_lock);
return rc;
}
@@ -3125,6 +3133,11 @@
mutex_lock(&display->display_lock);
+ /* enable the clk vote for CMD mode panels */
+ if (display->config.panel_mode == DSI_OP_CMD_MODE)
+ dsi_display_clk_ctrl(display->dsi_clk_handle,
+ DSI_ALL_CLKS, DSI_CLK_ON);
+
rc = dsi_panel_pre_disable(display->panel);
if (rc)
pr_err("[%s] panel pre-disable failed, rc=%d\n",
@@ -3233,11 +3246,6 @@
pr_err("[%s] failed to disable DSI PHY, rc=%d\n",
display->name, rc);
- rc = dsi_display_phy_reset_config(display, false);
- if (rc)
- pr_err("[%s] failed to disable DSI PHY reset config, rc=%d\n",
- display->name, rc);
-
rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
DSI_CORE_CLK, DSI_CLK_OFF);
if (rc)
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
index 556c0d8..3f4bb5a5 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
@@ -50,6 +50,8 @@
dsi_mode->pixel_clk_khz = drm_mode->clock;
dsi_mode->panel_mode = 0; /* TODO: Panel Mode */
+ dsi_mode->mode_info = (struct msm_mode_info *)drm_mode->private;
+
if (msm_is_mode_seamless(drm_mode))
dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
if (msm_is_mode_dynamic_fps(drm_mode))
@@ -81,6 +83,8 @@
drm_mode->vrefresh = dsi_mode->timing.refresh_rate;
drm_mode->clock = dsi_mode->pixel_clk_khz;
+ drm_mode->private = (int *)dsi_mode->mode_info;
+
if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
drm_mode->flags |= DRM_MODE_FLAG_SEAMLESS;
if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
@@ -255,6 +259,26 @@
return ret;
}
+int dsi_conn_get_topology(const struct drm_display_mode *drm_mode,
+ struct msm_display_topology *topology,
+ u32 max_mixer_width)
+{
+ struct dsi_display_mode dsi_mode;
+
+ if (!drm_mode || !topology)
+ return -EINVAL;
+
+ convert_to_dsi_mode(drm_mode, &dsi_mode);
+
+ if (!dsi_mode.mode_info)
+ return -EINVAL;
+
+ memcpy(topology, &dsi_mode.mode_info->topology,
+ sizeof(struct msm_display_topology));
+
+ return 0;
+}
+
static const struct drm_bridge_funcs dsi_bridge_ops = {
.attach = dsi_bridge_attach,
.mode_fixup = dsi_bridge_mode_fixup,
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h
index 4339a11..68520a8 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h
@@ -64,6 +64,17 @@
void *display);
/**
+ * dsi_conn_get_topology - retrieve current topology for the mode selected
+ * @drm_mode: Display mode set for the display
+ * @topology: Out parameter. Topology for the mode.
+ * @max_mixer_width: max width supported by HW layer mixer
+ * Returns: Zero on success
+ */
+int dsi_conn_get_topology(const struct drm_display_mode *drm_mode,
+ struct msm_display_topology *topology,
+ u32 max_mixer_width);
+
+/**
* dsi_conn_mode_valid - callback to determine if specified mode is valid
* @connector: Pointer to drm connector structure
* @mode: Pointer to drm mode structure
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h
index 8250da3..174be9f 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h
@@ -37,7 +37,7 @@
readl_relaxed((dsi_hw)->disp_cc_base + (off))
#define DSI_DISP_CC_W32(dsi_hw, off, val) \
do {\
- pr_err("[DSI_%d][%s] - [0x%08x]\n", \
+ pr_debug("[DSI_%d][%s] - [0x%08x]\n", \
(dsi_hw)->index, #off, val); \
writel_relaxed((val), (dsi_hw)->disp_cc_base + (off)); \
} while (0)
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
index b814eb8..cb4afe4 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c
@@ -20,6 +20,19 @@
#include "dsi_panel.h"
#include "dsi_ctrl_hw.h"
+#define MAX_CMDLINE_PARAM_LEN 256
+static char display_config[MAX_CMDLINE_PARAM_LEN];
+
+/**
+ * topology is currently defined by a set of following 3 values:
+ * 1. num of layer mixers
+ * 2. num of compression encoders
+ * 3. num of interfaces
+ */
+#define TOPOLOGY_SET_LEN 3
+#define INT_BASE_10 10
+#define MAX_TOPOLOGY 5
+
#define DSI_PANEL_DEFAULT_LABEL "Default dsi panel"
#define DEFAULT_MDP_TRANSFER_TIME 14000
@@ -1912,25 +1925,18 @@
u32 data;
int rc = -EINVAL;
int intf_width;
- struct device_node *dsc_np = NULL;
if (!panel->dsc_enabled)
return 0;
- dsc_np = of_parse_phandle(of_node, "qcom,config-select", 0);
- if (!dsc_np) {
- pr_err("no dsc config found\n");
- goto error;
- }
-
- rc = of_property_read_u32(dsc_np, "qcom,mdss-dsc-slice-height", &data);
+ rc = of_property_read_u32(of_node, "qcom,mdss-dsc-slice-height", &data);
if (rc) {
pr_err("failed to parse qcom,mdss-dsc-slice-height\n");
goto error;
}
panel->dsc.slice_height = data;
- rc = of_property_read_u32(dsc_np, "qcom,mdss-dsc-slice-width", &data);
+ rc = of_property_read_u32(of_node, "qcom,mdss-dsc-slice-width", &data);
if (rc) {
pr_err("failed to parse qcom,mdss-dsc-slice-width\n");
goto error;
@@ -1946,14 +1952,15 @@
panel->dsc.pic_width = panel->mode.timing.h_active;
panel->dsc.pic_height = panel->mode.timing.v_active;
- rc = of_property_read_u32(dsc_np, "qcom,mdss-dsc-slice-per-pkt", &data);
+ rc = of_property_read_u32(of_node, "qcom,mdss-dsc-slice-per-pkt",
+ &data);
if (rc) {
pr_err("failed to parse qcom,mdss-dsc-slice-per-pkt\n");
goto error;
}
panel->dsc.slice_per_pkt = data;
- rc = of_property_read_u32(dsc_np, "qcom,mdss-dsc-bit-per-component",
+ rc = of_property_read_u32(of_node, "qcom,mdss-dsc-bit-per-component",
&data);
if (rc) {
pr_err("failed to parse qcom,mdss-dsc-bit-per-component\n");
@@ -1961,14 +1968,15 @@
}
panel->dsc.bpc = data;
- rc = of_property_read_u32(dsc_np, "qcom,mdss-dsc-bit-per-pixel", &data);
+ rc = of_property_read_u32(of_node, "qcom,mdss-dsc-bit-per-pixel",
+ &data);
if (rc) {
pr_err("failed to parse qcom,mdss-dsc-bit-per-pixel\n");
goto error;
}
panel->dsc.bpp = data;
- panel->dsc.block_pred_enable = of_property_read_bool(dsc_np,
+ panel->dsc.block_pred_enable = of_property_read_bool(of_node,
"qcom,mdss-dsc-block-prediction-enable");
panel->dsc.full_frame_slices = DIV_ROUND_UP(intf_width,
@@ -2027,6 +2035,112 @@
return 0;
}
+static int dsi_get_cmdline_top_override(void)
+{
+ char *str = display_config;
+ int top_index = -1;
+
+ /*
+ * This module need to be updated with needed cmd line argument parsing
+ * for other dsi parameters.
+ */
+ if (strlcat(str, "\0", sizeof(str)) > sizeof(str))
+ return -EINVAL;
+
+ str = strnstr(display_config, "config", strlen(display_config));
+ if (!str)
+ return -EINVAL;
+
+ if (kstrtol(str + strlen("config"), INT_BASE_10,
+ (unsigned long *)&top_index))
+ return -EINVAL;
+
+ return top_index;
+}
+
+static int dsi_panel_parse_topology(struct dsi_panel *panel,
+ struct device_node *of_node)
+{
+ struct msm_display_topology *topology;
+ u32 top_count, top_sel, *array = NULL;
+ int i, len = 0;
+ int rc = -EINVAL;
+
+ len = of_property_count_u32_elems(of_node, "qcom,display-topology");
+ if (len <= 0 || len % TOPOLOGY_SET_LEN ||
+ len > (TOPOLOGY_SET_LEN * MAX_TOPOLOGY)) {
+ pr_err("invalid topology list for the panel, rc = %d\n", rc);
+ return rc;
+ }
+
+ top_count = len / TOPOLOGY_SET_LEN;
+
+ array = kcalloc(len, sizeof(u32), GFP_KERNEL);
+ if (!array)
+ return -ENOMEM;
+
+ rc = of_property_read_u32_array(of_node,
+ "qcom,display-topology", array, len);
+ if (rc) {
+ pr_err("unable to read the display topologies, rc = %d\n", rc);
+ goto read_fail;
+ }
+
+ topology = kcalloc(top_count, sizeof(*topology), GFP_KERNEL);
+ if (!topology) {
+ rc = -ENOMEM;
+ goto read_fail;
+ }
+
+ for (i = 0; i < top_count; i++) {
+ struct msm_display_topology *top = &topology[i];
+
+ top->num_lm = array[i * TOPOLOGY_SET_LEN];
+ top->num_enc = array[i * TOPOLOGY_SET_LEN + 1];
+ top->num_intf = array[i * TOPOLOGY_SET_LEN + 2];
+ };
+
+ top_sel = dsi_get_cmdline_top_override();
+ if (top_sel >= 0 && top_sel < top_count) {
+ pr_info("overidden topology: lm: %d comp_enc:%d intf: %d\n",
+ topology[top_sel].num_lm,
+ topology[top_sel].num_enc,
+ topology[top_sel].num_intf);
+ goto parse_done;
+ }
+
+ rc = of_property_read_u32(of_node,
+ "qcom,default-topology-index", &top_sel);
+ if (rc) {
+ pr_err("no default topology selected, rc = %d\n", rc);
+ goto parse_fail;
+ }
+
+ if (top_sel >= top_count) {
+ rc = -EINVAL;
+ pr_err("default topology is specified is not valid, rc = %d\n",
+ rc);
+ goto parse_fail;
+ }
+
+ pr_info("default topology: lm: %d comp_enc:%d intf: %d\n",
+ topology[top_sel].num_lm,
+ topology[top_sel].num_enc,
+ topology[top_sel].num_intf);
+
+parse_done:
+ panel->mode.mode_info = kzalloc(sizeof(struct msm_mode_info),
+ GFP_KERNEL);
+ memcpy(&panel->mode.mode_info->topology, &topology[top_sel],
+ sizeof(struct msm_display_topology));
+parse_fail:
+ kfree(topology);
+read_fail:
+ kfree(array);
+
+ return rc;
+}
+
struct dsi_panel *dsi_panel_get(struct device *parent,
struct device_node *of_node)
{
@@ -2084,6 +2198,13 @@
panel->mode.pixel_clk_khz = (DSI_H_TOTAL(&panel->mode.timing) *
DSI_V_TOTAL(&panel->mode.timing) *
panel->mode.timing.refresh_rate) / 1000;
+
+ rc = dsi_panel_parse_topology(panel, of_node);
+ if (rc) {
+ pr_err("failed to parse panel topology, rc=%d\n", rc);
+ goto error;
+ }
+
rc = dsi_panel_parse_host_config(panel, of_node);
if (rc) {
pr_err("failed to parse host configuration, rc=%d\n", rc);
@@ -2153,6 +2274,8 @@
for (i = 0; i < DSI_CMD_SET_MAX; i++)
dsi_panel_destroy_cmd_packets(&panel->cmd_sets[i]);
+ kfree(panel->mode.mode_info);
+
/* TODO: more free */
kfree(panel);
}
@@ -2611,3 +2734,6 @@
mutex_unlock(&panel->panel_lock);
return rc;
}
+
+module_param_string(display_param, display_config, MAX_CMDLINE_PARAM_LEN, 0600);
+MODULE_PARM_DESC(display_param, "format: configx - x indexes the selected topology from the display topology list. Index 0 corresponds to the first topology in the list");
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
index ebfb40b8..a1a0e57 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
@@ -791,23 +791,12 @@
bool skip_validation)
{
int rc = 0;
- struct dsi_clk_ctrl_info clk_info;
if (!phy || !config) {
pr_err("Invalid params\n");
return -EINVAL;
}
- clk_info.client = DSI_CLK_REQ_DSI_CLIENT;
- clk_info.clk_type = DSI_CORE_CLK;
- clk_info.clk_state = DSI_CLK_ON;
-
- rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info);
- if (rc) {
- pr_err("failed to enable DSI core clocks\n");
- return rc;
- }
-
mutex_lock(&phy->phy_lock);
if (!skip_validation)
@@ -839,10 +828,6 @@
error:
mutex_unlock(&phy->phy_lock);
- clk_info.clk_state = DSI_CLK_OFF;
- rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info);
- if (rc)
- pr_err("failed to disable DSI core clocks\n");
return rc;
}
@@ -855,34 +840,17 @@
int dsi_phy_disable(struct msm_dsi_phy *phy)
{
int rc = 0;
- struct dsi_clk_ctrl_info clk_info;
if (!phy) {
pr_err("Invalid params\n");
return -EINVAL;
}
- clk_info.client = DSI_CLK_REQ_DSI_CLIENT;
- clk_info.clk_type = DSI_CORE_CLK;
- clk_info.clk_state = DSI_CLK_ON;
-
- rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info);
- if (rc) {
- pr_err("failed to enable DSI core clocks\n");
- return rc;
- }
-
mutex_lock(&phy->phy_lock);
dsi_phy_disable_hw(phy);
phy->dsi_phy_state = DSI_PHY_ENGINE_OFF;
mutex_unlock(&phy->phy_lock);
- clk_info.clk_state = DSI_CLK_OFF;
-
- rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info);
- if (rc)
- pr_err("failed to disable DSI core clocks\n");
-
return rc;
}
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 4471d0b..322b7f2 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -164,6 +164,8 @@
/* enum/bitmask properties */
CONNECTOR_PROP_TOPOLOGY_NAME,
CONNECTOR_PROP_TOPOLOGY_CONTROL,
+ CONNECTOR_PROP_AUTOREFRESH,
+ CONNECTOR_PROP_LP,
/* total # of properties */
CONNECTOR_PROP_COUNT
@@ -353,6 +355,26 @@
};
/**
+ * struct msm_display_topology - defines a display topology pipeline
+ * @num_lm: number of layer mixers used
+ * @num_enc: number of compression encoder blocks used
+ * @num_intf: number of interfaces the panel is mounted on
+ */
+struct msm_display_topology {
+ u32 num_lm;
+ u32 num_enc;
+ u32 num_intf;
+};
+
+/**
+ * struct msm_mode_info - defines all msm custom mode info
+ * @topology - supported topology for the mode
+ */
+struct msm_mode_info {
+ struct msm_display_topology topology;
+};
+
+/**
* struct msm_display_info - defines display properties
* @intf_type: DRM_MODE_CONNECTOR_ display type
* @capabilities: Bitmask of display flags
diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c
index 8487f46..3c3f335 100644
--- a/drivers/gpu/drm/msm/msm_rd.c
+++ b/drivers/gpu/drm/msm/msm_rd.c
@@ -105,9 +105,13 @@
static void rd_write(struct msm_rd_state *rd, const void *buf, int sz)
{
- struct circ_buf *fifo = &rd->fifo;
+ struct circ_buf *fifo;
const char *ptr = buf;
+ if (!rd || !buf)
+ return;
+
+ fifo = &rd->fifo;
while (sz > 0) {
char *fptr = &fifo->buf[fifo->head];
int n;
@@ -136,11 +140,18 @@
static ssize_t rd_read(struct file *file, char __user *buf,
size_t sz, loff_t *ppos)
{
- struct msm_rd_state *rd = file->private_data;
- struct circ_buf *fifo = &rd->fifo;
- const char *fptr = &fifo->buf[fifo->tail];
+ struct msm_rd_state *rd;
+ struct circ_buf *fifo;
+ const char *fptr;
int n = 0, ret = 0;
+ if (!file || !file->private_data || !buf || !ppos)
+ return -EINVAL;
+
+ rd = file->private_data;
+ fifo = &rd->fifo;
+ fptr = &fifo->buf[fifo->tail];
+
mutex_lock(&rd->read_lock);
ret = wait_event_interruptible(rd->fifo_event,
@@ -168,19 +179,34 @@
static int rd_open(struct inode *inode, struct file *file)
{
- struct msm_rd_state *rd = inode->i_private;
- struct drm_device *dev = rd->dev;
- struct msm_drm_private *priv = dev->dev_private;
- struct msm_gpu *gpu = priv->gpu;
+ struct msm_rd_state *rd;
+ struct drm_device *dev;
+ struct msm_drm_private *priv;
+ struct msm_gpu *gpu;
uint64_t val;
uint32_t gpu_id;
int ret = 0;
+ if (!file || !inode || !inode->i_private)
+ return -EINVAL;
+
+ rd = inode->i_private;
+ dev = rd->dev;
+
+ if (!dev || !dev->dev_private)
+ return -EINVAL;
+
+ priv = dev->dev_private;
+ gpu = priv->gpu;
+
mutex_lock(&dev->struct_mutex);
if (rd->open || !gpu) {
ret = -EBUSY;
goto out;
+ } else if (!gpu->funcs || !gpu->funcs->get_param) {
+ ret = -EINVAL;
+ goto out;
}
file->private_data = rd;
@@ -201,7 +227,12 @@
static int rd_release(struct inode *inode, struct file *file)
{
- struct msm_rd_state *rd = inode->i_private;
+ struct msm_rd_state *rd;
+
+ if (!inode || !inode->i_private)
+ return -EINVAL;
+
+ rd = inode->i_private;
rd->open = false;
return 0;
}
@@ -217,9 +248,14 @@
int msm_rd_debugfs_init(struct drm_minor *minor)
{
- struct msm_drm_private *priv = minor->dev->dev_private;
+ struct msm_drm_private *priv;
struct msm_rd_state *rd;
+ if (!minor || !minor->dev || !minor->dev->dev_private)
+ return -EINVAL;
+
+ priv = minor->dev->dev_private;
+
/* only create on first minor: */
if (priv->rd)
return 0;
@@ -265,8 +301,14 @@
void msm_rd_debugfs_cleanup(struct drm_minor *minor)
{
- struct msm_drm_private *priv = minor->dev->dev_private;
- struct msm_rd_state *rd = priv->rd;
+ struct msm_drm_private *priv;
+ struct msm_rd_state *rd;
+
+ if (!minor || !minor->dev || !minor->dev->dev_private)
+ return;
+
+ priv = minor->dev->dev_private;
+ rd = priv->rd;
if (!rd)
return;
@@ -315,13 +357,20 @@
/* called under struct_mutex */
void msm_rd_dump_submit(struct msm_gem_submit *submit)
{
- struct drm_device *dev = submit->dev;
- struct msm_drm_private *priv = dev->dev_private;
- struct msm_rd_state *rd = priv->rd;
+ struct drm_device *dev;
+ struct msm_drm_private *priv;
+ struct msm_rd_state *rd;
char msg[128];
int i, n;
- if (!rd->open)
+ if (!submit || !submit->dev || !submit->dev->dev_private)
+ return;
+
+ dev = submit->dev;
+ priv = dev->dev_private;
+ rd = priv->rd;
+
+ if (!rd || !rd->open)
return;
/* writing into fifo is serialized by caller, and
diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c
index e3f8261..58222f3 100644
--- a/drivers/gpu/drm/msm/sde/sde_connector.c
+++ b/drivers/gpu/drm/msm/sde/sde_connector.c
@@ -10,7 +10,7 @@
* GNU General Public License for more details.
*/
-#define pr_fmt(fmt) "sde-drm:[%s] " fmt, __func__
+#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
#include "msm_drv.h"
#include "sde_kms.h"
@@ -21,6 +21,9 @@
#define BL_NODE_NAME_SIZE 32
+/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely */
+#define AUTOREFRESH_MAX_FRAME_CNT 6
+
#define SDE_DEBUG_CONN(c, fmt, ...) SDE_DEBUG("conn%d " fmt,\
(c) ? (c)->base.base.id : -1, ##__VA_ARGS__)
@@ -41,6 +44,12 @@
{SDE_RM_TOPCTL_FORCE_TILING, "force_tiling"},
{SDE_RM_TOPCTL_PPSPLIT, "ppsplit"}
};
+static const struct drm_prop_enum_list e_power_mode[] = {
+ {SDE_MODE_DPMS_ON, "ON"},
+ {SDE_MODE_DPMS_LP1, "LP1"},
+ {SDE_MODE_DPMS_LP2, "LP2"},
+ {SDE_MODE_DPMS_OFF, "OFF"},
+};
static int sde_backlight_device_update_status(struct backlight_device *bd)
{
@@ -291,6 +300,7 @@
msm_property_destroy(&c_conn->property_info);
drm_connector_unregister(connector);
+ mutex_destroy(&c_conn->lock);
sde_fence_deinit(&c_conn->retire_fence);
drm_connector_cleanup(connector);
kfree(c_conn);
@@ -538,6 +548,56 @@
return 0;
}
+static int _sde_connector_update_power_locked(struct sde_connector *c_conn)
+{
+ struct drm_connector *connector;
+ void *display;
+ int (*set_power)(struct drm_connector *, int, void *);
+ int mode, rc = 0;
+
+ if (!c_conn)
+ return -EINVAL;
+ connector = &c_conn->base;
+
+ mode = c_conn->lp_mode;
+ if (c_conn->dpms_mode != DRM_MODE_DPMS_ON)
+ mode = SDE_MODE_DPMS_OFF;
+ switch (c_conn->dpms_mode) {
+ case DRM_MODE_DPMS_ON:
+ mode = c_conn->lp_mode;
+ break;
+ case DRM_MODE_DPMS_STANDBY:
+ mode = SDE_MODE_DPMS_STANDBY;
+ break;
+ case DRM_MODE_DPMS_SUSPEND:
+ mode = SDE_MODE_DPMS_SUSPEND;
+ break;
+ case DRM_MODE_DPMS_OFF:
+ mode = SDE_MODE_DPMS_OFF;
+ break;
+ default:
+ mode = c_conn->lp_mode;
+ SDE_ERROR("conn %d dpms set to unrecognized mode %d\n",
+ connector->base.id, mode);
+ break;
+ }
+
+ SDE_DEBUG("conn %d - dpms %d, lp %d, panel %d\n", connector->base.id,
+ c_conn->dpms_mode, c_conn->lp_mode, mode);
+
+ if (mode != c_conn->last_panel_power_mode && c_conn->ops.set_power) {
+ display = c_conn->display;
+ set_power = c_conn->ops.set_power;
+
+ mutex_unlock(&c_conn->lock);
+ rc = set_power(connector, mode, display);
+ mutex_lock(&c_conn->lock);
+ }
+ c_conn->last_panel_power_mode = mode;
+
+ return rc;
+}
+
static int sde_connector_atomic_set_property(struct drm_connector *connector,
struct drm_connector_state *state,
struct drm_property *property,
@@ -564,8 +624,8 @@
/* connector-specific property handling */
idx = msm_property_index(&c_conn->property_info, property);
-
- if (idx == CONNECTOR_PROP_OUT_FB) {
+ switch (idx) {
+ case CONNECTOR_PROP_OUT_FB:
/* clear old fb, if present */
if (c_state->out_fb)
_sde_connector_destroy_fb(c_conn, c_state);
@@ -595,12 +655,20 @@
if (rc)
SDE_ERROR("prep fb failed, %d\n", rc);
}
- }
-
- if (idx == CONNECTOR_PROP_TOPOLOGY_CONTROL) {
+ break;
+ case CONNECTOR_PROP_TOPOLOGY_CONTROL:
rc = sde_rm_check_property_topctl(val);
if (rc)
SDE_ERROR("invalid topology_control: 0x%llX\n", val);
+ break;
+ case CONNECTOR_PROP_LP:
+ mutex_lock(&c_conn->lock);
+ c_conn->lp_mode = val;
+ _sde_connector_update_power_locked(c_conn);
+ mutex_unlock(&c_conn->lock);
+ break;
+ default:
+ break;
}
if (idx == CONNECTOR_PROP_ROI_V1) {
@@ -716,6 +784,59 @@
return status;
}
+static int sde_connector_dpms(struct drm_connector *connector,
+ int mode)
+{
+ struct sde_connector *c_conn;
+
+ if (!connector) {
+ SDE_ERROR("invalid connector\n");
+ return -EINVAL;
+ }
+ c_conn = to_sde_connector(connector);
+
+ /* validate incoming dpms request */
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ case DRM_MODE_DPMS_OFF:
+ SDE_DEBUG("conn %d dpms set to %d\n", connector->base.id, mode);
+ break;
+ default:
+ SDE_ERROR("conn %d dpms set to unrecognized mode %d\n",
+ connector->base.id, mode);
+ break;
+ }
+
+ mutex_lock(&c_conn->lock);
+ c_conn->dpms_mode = mode;
+ _sde_connector_update_power_locked(c_conn);
+ mutex_unlock(&c_conn->lock);
+
+ /* use helper for boilerplate handling */
+ return drm_atomic_helper_connector_dpms(connector, mode);
+}
+
+int sde_connector_get_dpms(struct drm_connector *connector)
+{
+ struct sde_connector *c_conn;
+ int rc;
+
+ if (!connector) {
+ SDE_DEBUG("invalid connector\n");
+ return DRM_MODE_DPMS_OFF;
+ }
+
+ c_conn = to_sde_connector(connector);
+
+ mutex_lock(&c_conn->lock);
+ rc = c_conn->dpms_mode;
+ mutex_unlock(&c_conn->lock);
+
+ return rc;
+}
+
#ifdef CONFIG_DEBUG_FS
/**
* sde_connector_init_debugfs - initialize connector debugfs
@@ -758,7 +879,7 @@
}
static const struct drm_connector_funcs sde_connector_ops = {
- .dpms = drm_atomic_helper_connector_dpms,
+ .dpms = sde_connector_dpms,
.reset = sde_connector_atomic_reset,
.detect = sde_connector_detect,
.destroy = sde_connector_destroy,
@@ -882,6 +1003,10 @@
c_conn->panel = panel;
c_conn->display = display;
+ c_conn->dpms_mode = DRM_MODE_DPMS_ON;
+ c_conn->lp_mode = 0;
+ c_conn->last_panel_power_mode = SDE_MODE_DPMS_ON;
+
/* cache mmu_id's for later */
sde_kms = to_sde_kms(priv->kms);
if (sde_kms->vbif[VBIF_NRT]) {
@@ -916,6 +1041,8 @@
goto error_cleanup_conn;
}
+ mutex_init(&c_conn->lock);
+
rc = drm_mode_connector_attach_encoder(&c_conn->base, encoder);
if (rc) {
SDE_ERROR("failed to attach encoder to connector, %d\n", rc);
@@ -990,6 +1117,10 @@
msm_property_install_range(&c_conn->property_info, "RETIRE_FENCE",
0x0, 0, INR_OPEN_MAX, 0, CONNECTOR_PROP_RETIRE_FENCE);
+ msm_property_install_range(&c_conn->property_info, "autorefresh",
+ 0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0,
+ CONNECTOR_PROP_AUTOREFRESH);
+
/* enum/bitmask properties */
msm_property_install_enum(&c_conn->property_info, "topology_name",
DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name,
@@ -999,6 +1130,10 @@
0, 1, e_topology_control,
ARRAY_SIZE(e_topology_control),
CONNECTOR_PROP_TOPOLOGY_CONTROL);
+ msm_property_install_enum(&c_conn->property_info, "LP",
+ 0, 0, e_power_mode,
+ ARRAY_SIZE(e_power_mode),
+ CONNECTOR_PROP_LP);
rc = msm_property_install_get_status(&c_conn->property_info);
if (rc) {
@@ -1020,6 +1155,7 @@
drm_property_unreference_blob(c_conn->blob_hdr);
msm_property_destroy(&c_conn->property_info);
error_cleanup_fence:
+ mutex_destroy(&c_conn->lock);
sde_fence_deinit(&c_conn->retire_fence);
error_cleanup_conn:
drm_connector_cleanup(&c_conn->base);
diff --git a/drivers/gpu/drm/msm/sde/sde_connector.h b/drivers/gpu/drm/msm/sde/sde_connector.h
index 601299e..71e64e4 100644
--- a/drivers/gpu/drm/msm/sde/sde_connector.h
+++ b/drivers/gpu/drm/msm/sde/sde_connector.h
@@ -121,6 +121,17 @@
int (*get_info)(struct msm_display_info *info, void *display);
/**
+ * get_topology - retrieve current topology for the mode selected
+ * @drm_mode: Display mode set for the display
+ * @topology: Out parameter. Topology for the mode.
+ * @max_mixer_width: max width supported by HW layer mixer
+ * Returns: Zero on success
+ */
+ int (*get_topology)(const struct drm_display_mode *drm_mode,
+ struct msm_display_topology *topology,
+ u32 max_mixer_width);
+
+ /**
* enable_event - notify display of event registration/unregistration
* @connector: Pointer to drm connector structure
* @event_idx: SDE connector event index
@@ -158,6 +169,20 @@
* @enable: State of clks
*/
int (*clk_ctrl)(void *handle, u32 type, u32 state);
+
+ /**
+ * set_power - update dpms setting
+ * @connector: Pointer to drm connector structure
+ * @power_mode: One of the following,
+ * SDE_MODE_DPMS_ON
+ * SDE_MODE_DPMS_LP1
+ * SDE_MODE_DPMS_LP2
+ * SDE_MODE_DPMS_OFF
+ * @display: Pointer to private display structure
+ * Returns: Zero on success
+ */
+ int (*set_power)(struct drm_connector *connector,
+ int power_mode, void *display);
};
/**
@@ -192,8 +217,12 @@
* @mmu_secure: MMU id for secure buffers
* @mmu_unsecure: MMU id for unsecure buffers
* @name: ASCII name of connector
+ * @lock: Mutex lock object for this structure
* @retire_fence: Retire fence context reference
* @ops: Local callback function pointer table
+ * @dpms_mode: DPMS property setting from user space
+ * @lp_mode: LP property setting from user space
+ * @last_panel_power_mode: Last consolidated dpms/lp mode setting
* @property_info: Private structure for generic property handling
* @property_data: Array of private data for generic property handling
* @blob_caps: Pointer to blob structure for 'capabilities' property
@@ -215,8 +244,12 @@
char name[SDE_CONNECTOR_NAME_SIZE];
+ struct mutex lock;
struct sde_fence_context retire_fence;
struct sde_connector_ops ops;
+ int dpms_mode;
+ int lp_mode;
+ int last_panel_power_mode;
struct msm_property_info property_info;
struct msm_property_data property_data[CONNECTOR_PROP_COUNT];
@@ -381,6 +414,13 @@
void sde_connector_clk_ctrl(struct drm_connector *connector, bool enable);
/**
+ * sde_connector_get_dpms - query dpms setting
+ * @connector: Pointer to drm connector structure
+ * Returns: Current DPMS setting for connector
+ */
+int sde_connector_get_dpms(struct drm_connector *connector);
+
+/**
* sde_connector_trigger_event - indicate that an event has occurred
* Any callbacks that have been registered against this event will
* be called from the same thread context.
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 6bae083..1bd7654 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -808,6 +808,44 @@
return 0;
}
+static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc,
+ struct drm_crtc_state *state)
+{
+ struct sde_crtc *sde_crtc;
+ struct sde_crtc_state *crtc_state;
+ struct drm_connector *conn;
+ struct drm_connector_state *conn_state;
+ int i;
+
+ if (!crtc || !state)
+ return -EINVAL;
+
+ sde_crtc = to_sde_crtc(crtc);
+ crtc_state = to_sde_crtc_state(state);
+
+ if (sde_kms_rect_is_null(&crtc_state->crtc_roi))
+ return 0;
+
+ /* partial update active, check if autorefresh is also requested */
+ for_each_connector_in_state(state->state, conn, conn_state, i) {
+ uint64_t autorefresh;
+
+ if (!conn_state || conn_state->crtc != crtc)
+ continue;
+
+ autorefresh = sde_connector_get_property(conn_state,
+ CONNECTOR_PROP_AUTOREFRESH);
+ if (autorefresh) {
+ SDE_ERROR(
+ "%s: autorefresh & partial crtc roi incompatible %llu\n",
+ sde_crtc->name, autorefresh);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc,
struct drm_crtc_state *state, int lm_idx)
{
@@ -826,55 +864,82 @@
lm_bounds = &crtc_state->lm_bounds[lm_idx];
lm_roi = &crtc_state->lm_roi[lm_idx];
- if (!sde_kms_rect_is_null(crtc_roi)) {
- sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi);
- if (sde_kms_rect_is_null(lm_roi)) {
- SDE_ERROR("unsupported R/L only partial update\n");
- return -EINVAL;
- }
- } else {
+ if (sde_kms_rect_is_null(crtc_roi))
memcpy(lm_roi, lm_bounds, sizeof(*lm_roi));
- }
+ else
+ sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi);
SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx,
lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
+ /* if any dimension is zero, clear all dimensions for clarity */
+ if (sde_kms_rect_is_null(lm_roi))
+ memset(lm_roi, 0, sizeof(*lm_roi));
+
return 0;
}
+static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc,
+ struct drm_crtc_state *state)
+{
+ struct sde_crtc *sde_crtc;
+ struct sde_crtc_state *crtc_state;
+ u32 disp_bitmask = 0;
+ int i;
+
+ sde_crtc = to_sde_crtc(crtc);
+ crtc_state = to_sde_crtc_state(state);
+
+ for (i = 0; i < sde_crtc->num_mixers; i++) {
+ if (!sde_kms_rect_is_null(&crtc_state->lm_roi[i]))
+ disp_bitmask |= BIT(i);
+ }
+
+ SDE_DEBUG("affected displays 0x%x\n", disp_bitmask);
+
+ return disp_bitmask;
+}
+
static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct sde_crtc *sde_crtc;
struct sde_crtc_state *crtc_state;
- const struct sde_rect *roi_prv, *roi_cur;
- int lm_idx;
+ const struct sde_rect *roi[CRTC_DUAL_MIXERS];
if (!crtc || !state)
return -EINVAL;
+ sde_crtc = to_sde_crtc(crtc);
+ crtc_state = to_sde_crtc_state(state);
+
+ if (sde_crtc->num_mixers == 1)
+ return 0;
+
+ if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
+ SDE_ERROR("%s: unsupported number of mixers: %d\n",
+ sde_crtc->name, sde_crtc->num_mixers);
+ return -EINVAL;
+ }
+
/*
* On certain HW, ROIs must be centered on the split between LMs,
* and be of equal width.
*/
+ roi[0] = &crtc_state->lm_roi[0];
+ roi[1] = &crtc_state->lm_roi[1];
- sde_crtc = to_sde_crtc(crtc);
- crtc_state = to_sde_crtc_state(state);
+ /* if one of the roi is null it's a left/right-only update */
+ if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1]))
+ return 0;
- roi_prv = &crtc_state->lm_roi[0];
- for (lm_idx = 1; lm_idx < sde_crtc->num_mixers; lm_idx++) {
- roi_cur = &crtc_state->lm_roi[lm_idx];
-
- /* check lm rois are equal width & first roi ends at 2nd roi */
- if (((roi_prv->x + roi_prv->w) != roi_cur->x) ||
- (roi_prv->w != roi_cur->w)) {
- SDE_ERROR("%s: roi lm%d x %d w %d lm%d x %d w %d\n",
- sde_crtc->name,
- lm_idx-1, roi_prv->x, roi_prv->w,
- lm_idx, roi_cur->x, roi_cur->w);
- return -EINVAL;
- }
- roi_prv = roi_cur;
+ /* check lm rois are equal width & first roi ends at 2nd roi */
+ if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) {
+ SDE_ERROR(
+ "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n",
+ sde_crtc->name, roi[0]->x, roi[0]->w,
+ roi[1]->x, roi[1]->w);
+ return -EINVAL;
}
return 0;
@@ -953,6 +1018,10 @@
if (rc)
return rc;
+ rc = _sde_crtc_check_autorefresh(crtc, state);
+ if (rc)
+ return rc;
+
for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx);
if (rc)
@@ -1146,13 +1215,21 @@
*/
static void _sde_crtc_blend_setup(struct drm_crtc *crtc)
{
- struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
- struct sde_crtc_mixer *mixer = sde_crtc->mixers;
+ struct sde_crtc *sde_crtc;
+ struct sde_crtc_state *sde_crtc_state;
+ struct sde_crtc_mixer *mixer;
struct sde_hw_ctl *ctl;
struct sde_hw_mixer *lm;
int i;
+ if (!crtc)
+ return;
+
+ sde_crtc = to_sde_crtc(crtc);
+ sde_crtc_state = to_sde_crtc_state(crtc->state);
+ mixer = sde_crtc->mixers;
+
SDE_DEBUG("%s\n", sde_crtc->name);
if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
@@ -1183,9 +1260,19 @@
_sde_crtc_blend_setup_mixer(crtc, sde_crtc, mixer);
for (i = 0; i < sde_crtc->num_mixers; i++) {
+ const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i];
+
ctl = mixer[i].hw_ctl;
lm = mixer[i].hw_lm;
+ if (sde_kms_rect_is_null(lm_roi)) {
+ SDE_DEBUG(
+ "%s: lm%d leave ctl%d mask 0 since null roi\n",
+ sde_crtc->name, lm->idx - LM_0,
+ ctl->idx - CTL_0);
+ continue;
+ }
+
lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl,
@@ -1678,9 +1765,9 @@
struct drm_crtc_state *old_state)
{
struct sde_crtc *sde_crtc;
+ struct drm_encoder *encoder;
struct drm_device *dev;
unsigned long flags;
- u32 i;
if (!crtc) {
SDE_ERROR("invalid crtc\n");
@@ -1711,12 +1798,12 @@
spin_unlock_irqrestore(&dev->event_lock, flags);
}
- /* Reset flush mask from previous commit */
- for (i = 0; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
- struct sde_hw_ctl *ctl = sde_crtc->mixers[i].hw_ctl;
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ if (encoder->crtc != crtc)
+ continue;
- if (ctl)
- ctl->ops.clear_pending_flush(ctl);
+ /* encoder will trigger pending mask now */
+ sde_encoder_trigger_kickoff_pending(encoder);
}
/*
@@ -1859,6 +1946,14 @@
priv = sde_kms->dev->dev_private;
cstate = to_sde_crtc_state(crtc->state);
+ /*
+ * If no mixers has been allocated in sde_crtc_atomic_check(),
+ * it means we are trying to start a CRTC whose state is disabled:
+ * nothing else needs to be done.
+ */
+ if (unlikely(!sde_crtc->num_mixers))
+ return;
+
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
struct sde_encoder_kickoff_params params = { 0 };
@@ -1870,6 +1965,8 @@
* If so, it may delay and flush at an irq event (e.g. ppdone)
*/
params.inline_rotate_prefill = cstate->sbuf_prefill_line;
+ params.affected_displays = _sde_crtc_get_displays_affected(crtc,
+ crtc->state);
sde_encoder_prepare_for_kickoff(encoder, ¶ms);
}
@@ -2074,21 +2171,89 @@
crtc->state = &cstate->base;
}
+static int _sde_crtc_vblank_no_lock(struct sde_crtc *sde_crtc, bool en)
+{
+ if (!sde_crtc) {
+ SDE_ERROR("invalid crtc\n");
+ return -EINVAL;
+ } else if (en && atomic_inc_return(&sde_crtc->vblank_refcount) == 1) {
+ SDE_DEBUG("crtc%d vblank enable\n", sde_crtc->base.base.id);
+ if (!sde_crtc->suspend)
+ _sde_crtc_vblank_enable_nolock(sde_crtc, true);
+ } else if (!en && atomic_read(&sde_crtc->vblank_refcount) < 1) {
+ SDE_ERROR("crtc%d invalid vblank disable\n",
+ sde_crtc->base.base.id);
+ return -EINVAL;
+ } else if (!en && atomic_dec_return(&sde_crtc->vblank_refcount) == 0) {
+ SDE_DEBUG("crtc%d vblank disable\n", sde_crtc->base.base.id);
+ if (!sde_crtc->suspend)
+ _sde_crtc_vblank_enable_nolock(sde_crtc, false);
+ } else {
+ SDE_DEBUG("crtc%d vblank %s refcount:%d\n",
+ sde_crtc->base.base.id,
+ en ? "enable" : "disable",
+ atomic_read(&sde_crtc->vblank_refcount));
+ }
+
+ return 0;
+}
+
+static void sde_crtc_handle_power_event(u32 event_type, void *arg)
+{
+ struct drm_crtc *crtc = arg;
+ struct sde_crtc *sde_crtc;
+ struct drm_encoder *encoder;
+
+ if (!crtc) {
+ SDE_ERROR("invalid crtc\n");
+ return;
+ }
+ sde_crtc = to_sde_crtc(crtc);
+
+ mutex_lock(&sde_crtc->crtc_lock);
+
+ SDE_EVT32(DRMID(crtc), event_type);
+
+ if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
+ /* restore encoder; crtc will be programmed during commit */
+ drm_for_each_encoder(encoder, crtc->dev) {
+ if (encoder->crtc != crtc)
+ continue;
+
+ sde_encoder_virt_restore(encoder);
+ }
+
+ } else if (event_type == SDE_POWER_EVENT_POST_DISABLE) {
+ struct drm_plane *plane;
+
+ /*
+ * set revalidate flag in planes, so it will be re-programmed
+ * in the next frame update
+ */
+ drm_atomic_crtc_for_each_plane(plane, crtc)
+ sde_plane_set_revalidate(plane, true);
+ }
+
+ mutex_unlock(&sde_crtc->crtc_lock);
+}
+
static void sde_crtc_disable(struct drm_crtc *crtc)
{
struct sde_crtc *sde_crtc;
struct sde_crtc_state *cstate;
struct drm_encoder *encoder;
+ struct msm_drm_private *priv;
unsigned long flags;
struct sde_crtc_irq_info *node = NULL;
int ret;
- if (!crtc || !crtc->dev || !crtc->state) {
+ if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
SDE_ERROR("invalid crtc\n");
return;
}
sde_crtc = to_sde_crtc(crtc);
cstate = to_sde_crtc_state(crtc->state);
+ priv = crtc->dev->dev_private;
SDE_DEBUG("crtc%d\n", crtc->base.id);
@@ -2103,13 +2268,9 @@
crtc->base.id);
SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->vblank_refcount),
SDE_EVTLOG_FUNC_CASE1);
- drm_for_each_encoder(encoder, crtc->dev) {
- if (encoder->crtc != crtc)
- continue;
- sde_encoder_register_vblank_callback(encoder, NULL,
- NULL);
- }
- atomic_set(&sde_crtc->vblank_refcount, 0);
+ while (atomic_read(&sde_crtc->vblank_refcount))
+ if (_sde_crtc_vblank_no_lock(sde_crtc, false))
+ break;
}
if (atomic_read(&sde_crtc->frame_pending)) {
@@ -2132,6 +2293,10 @@
cstate->rsc_update = false;
}
+ if (sde_crtc->power_event)
+ sde_power_handle_unregister_event(&priv->phandle,
+ sde_crtc->power_event);
+
memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
sde_crtc->num_mixers = 0;
@@ -2153,14 +2318,16 @@
{
struct sde_crtc *sde_crtc;
struct drm_encoder *encoder;
+ struct msm_drm_private *priv;
unsigned long flags;
struct sde_crtc_irq_info *node = NULL;
int ret;
- if (!crtc) {
+ if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
SDE_ERROR("invalid crtc\n");
return;
}
+ priv = crtc->dev->dev_private;
SDE_DEBUG("crtc%d\n", crtc->base.id);
SDE_EVT32(DRMID(crtc));
@@ -2183,6 +2350,11 @@
sde_crtc->name, node->event);
}
spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
+
+ sde_crtc->power_event = sde_power_handle_register_event(
+ &priv->phandle,
+ SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE,
+ sde_crtc_handle_power_event, crtc, sde_crtc->name);
}
struct plane_state {
@@ -2245,6 +2417,10 @@
mode = &state->adjusted_mode;
SDE_DEBUG("%s: check", sde_crtc->name);
+ /* force a full mode set if active state changed */
+ if (state->active_changed)
+ state->mode_changed = true;
+
memset(pipe_staged, 0, sizeof(pipe_staged));
mixer_width = sde_crtc_mixer_width(sde_crtc, mode);
@@ -2463,7 +2639,7 @@
int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
{
struct sde_crtc *sde_crtc;
- int rc = 0;
+ int rc;
if (!crtc) {
SDE_ERROR("invalid crtc\n");
@@ -2472,25 +2648,9 @@
sde_crtc = to_sde_crtc(crtc);
mutex_lock(&sde_crtc->crtc_lock);
- if (en && atomic_inc_return(&sde_crtc->vblank_refcount) == 1) {
- SDE_DEBUG("crtc%d vblank enable\n", crtc->base.id);
- if (!sde_crtc->suspend)
- _sde_crtc_vblank_enable_nolock(sde_crtc, true);
- } else if (!en && atomic_read(&sde_crtc->vblank_refcount) < 1) {
- SDE_ERROR("crtc%d invalid vblank disable\n", crtc->base.id);
- rc = -EINVAL;
- } else if (!en && atomic_dec_return(&sde_crtc->vblank_refcount) == 0) {
- SDE_DEBUG("crtc%d vblank disable\n", crtc->base.id);
- if (!sde_crtc->suspend)
- _sde_crtc_vblank_enable_nolock(sde_crtc, false);
- } else {
- SDE_DEBUG("crtc%d vblank %s refcount:%d\n",
- crtc->base.id,
- en ? "enable" : "disable",
- atomic_read(&sde_crtc->vblank_refcount));
- }
-
+ rc = _sde_crtc_vblank_no_lock(sde_crtc, en);
mutex_unlock(&sde_crtc->crtc_lock);
+
return rc;
}
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h
index 7ad0955..ec5ec1d 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.h
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.h
@@ -138,6 +138,7 @@
* @event_free_list : List of available event structures
* @event_lock : Spinlock around event handling code
* @misr_enable : boolean entry indicates misr enable/disable status.
+ * @power_event : registered power event handle
*/
struct sde_crtc {
struct drm_crtc base;
@@ -187,6 +188,8 @@
struct list_head event_free_list;
spinlock_t event_lock;
bool misr_enable;
+
+ struct sde_power_event *power_event;
};
#define to_sde_crtc(x) container_of(x, struct sde_crtc, base)
@@ -248,10 +251,10 @@
* @num_connectors: Number of associated drm connectors
* @intf_mode : Interface mode of the primary connector
* @rsc_client : sde rsc client when mode is valid
- * @lm_bounds : LM boundaries based on current mode full resolution, no ROI.
- * Origin top left of CRTC.
* @crtc_roi : Current CRTC ROI. Possibly sub-rectangle of mode.
* Origin top left of CRTC.
+ * @lm_bounds : LM boundaries based on current mode full resolution, no ROI.
+ * Origin top left of CRTC.
* @lm_roi : Current LM ROI, possibly sub-rectangle of mode.
* Origin top left of CRTC.
* @user_roi_list : List of user's requested ROIs as from set property
@@ -274,8 +277,8 @@
struct sde_rsc_client *rsc_client;
bool rsc_update;
- struct sde_rect lm_bounds[CRTC_DUAL_MIXERS];
struct sde_rect crtc_roi;
+ struct sde_rect lm_bounds[CRTC_DUAL_MIXERS];
struct sde_rect lm_roi[CRTC_DUAL_MIXERS];
struct msm_roi_list user_roi_list;
@@ -316,6 +319,21 @@
}
/**
+ * sde_crtc_frame_pending - retun the number of pending frames
+ * @crtc: Pointer to drm crtc object
+ */
+static inline int sde_crtc_frame_pending(struct drm_crtc *crtc)
+{
+ struct sde_crtc *sde_crtc;
+
+ if (!crtc)
+ return -EINVAL;
+
+ sde_crtc = to_sde_crtc(crtc);
+ return atomic_read(&sde_crtc->frame_pending);
+}
+
+/**
* sde_crtc_vblank - enable or disable vblanks for this crtc
* @crtc: Pointer to drm crtc object
* @en: true to enable vblanks, false to disable
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index 742ea20..a136645 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -34,6 +34,7 @@
#include "sde_encoder_phys.h"
#include "sde_power_handle.h"
#include "sde_hw_dsc.h"
+#include "sde_crtc.h"
#define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
@@ -58,6 +59,56 @@
#define MISR_BUFF_SIZE 256
+#define IDLE_TIMEOUT 64
+
+/**
+ * enum sde_enc_rc_events - events for resource control state machine
+ * @SDE_ENC_RC_EVENT_KICKOFF:
+ * This event happens at NORMAL priority.
+ * Event that signals the start of the transfer. When this event is
+ * received, enable MDP/DSI core clocks and request RSC with CMD state.
+ * Regardless of the previous state, the resource should be in ON state
+ * at the end of this event.
+ * @SDE_ENC_RC_EVENT_FRAME_DONE:
+ * This event happens at INTERRUPT level.
+ * Event signals the end of the data transfer after the PP FRAME_DONE
+ * event. At the end of this event, a delayed work is scheduled to go to
+ * IDLE_PC state after IDLE_TIMEOUT time.
+ * @SDE_ENC_RC_EVENT_STOP:
+ * This event happens at NORMAL priority.
+ * When this event is received, disable all the MDP/DSI core clocks
+ * and request RSC with IDLE state. Resource state should be in OFF
+ * at the end of the event.
+ * @SDE_ENC_RC_EARLY_WAKEUP
+ * This event happens at NORMAL priority from a work item.
+ * Event signals that there will be frame update soon and the driver should
+ * wake up early to update the frame with minimum latency.
+ * @SDE_ENC_RC_EVENT_ENTER_IDLE:
+ * This event happens at NORMAL priority from a work item.
+ * Event signals that there were no frame updates for IDLE_TIMEOUT time.
+ * This would disable MDP/DSI core clocks and request RSC with IDLE state
+ * and change the resource state to IDLE.
+ */
+enum sde_enc_rc_events {
+ SDE_ENC_RC_EVENT_KICKOFF = 1,
+ SDE_ENC_RC_EVENT_FRAME_DONE,
+ SDE_ENC_RC_EVENT_STOP,
+ SDE_ENC_RC_EVENT_EARLY_WAKE_UP,
+ SDE_ENC_RC_EVENT_ENTER_IDLE
+};
+
+/*
+ * enum sde_enc_rc_states - states that the resource control maintains
+ * @SDE_ENC_RC_STATE_OFF: Resource is in OFF state
+ * @SDE_ENC_RC_STATE_ON: Resource is in ON state
+ * @SDE_ENC_RC_STATE_IDLE: Resource is in IDLE state
+ */
+enum sde_enc_rc_states {
+ SDE_ENC_RC_STATE_OFF,
+ SDE_ENC_RC_STATE_ON,
+ SDE_ENC_RC_STATE_IDLE
+};
+
/**
* struct sde_encoder_virt - virtual encoder. Container of one or more physical
* encoders. Virtual encoder manages one "logical" display. Physical
@@ -91,7 +142,16 @@
* @crtc_frame_event: callback event
* @frame_done_timeout: frame done timeout in Hz
* @frame_done_timer: watchdog timer for frame done event
+ * @rsc_client: rsc client pointer
+ * @rsc_state_init: boolean to indicate rsc config init
+ * @disp_info: local copy of msm_display_info struct
* @misr_enable: misr enable/disable status
+ * @idle_pc_supported: indicate if idle power collaps is supported
+ * @rc_lock: resource control mutex lock to protect
+ * virt encoder over various state changes
+ * @rc_state: resource controller state
+ * @delayed_off_work: delayed worker to schedule disabling of
+ * clks and resources after IDLE_TIMEOUT time.
*/
struct sde_encoder_virt {
struct drm_encoder base;
@@ -120,9 +180,14 @@
struct timer_list frame_done_timer;
struct sde_rsc_client *rsc_client;
+ bool rsc_state_init;
struct msm_display_info disp_info;
- bool rsc_state_update;
bool misr_enable;
+
+ bool idle_pc_supported;
+ struct mutex rc_lock;
+ enum sde_enc_rc_states rc_state;
+ struct delayed_work delayed_off_work;
};
#define to_sde_encoder_virt(x) container_of(x, struct sde_encoder_virt, base)
@@ -700,6 +765,11 @@
sde_enc = to_sde_encoder_virt(drm_enc);
disp_info = &sde_enc->disp_info;
+ if (!sde_enc->rsc_client) {
+ SDE_DEBUG("rsc client not created\n");
+ return 0;
+ }
+
/**
* only primary command mode panel can request CMD state.
* all other panels/displays can request for VID state including
@@ -710,14 +780,14 @@
disp_info->is_primary) ? SDE_RSC_CMD_STATE :
SDE_RSC_VID_STATE) : SDE_RSC_IDLE_STATE;
- if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_update
+ if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
&& disp_info->is_primary) {
rsc_config.fps = disp_info->frame_rate;
rsc_config.vtotal = disp_info->vtotal;
rsc_config.prefill_lines = disp_info->prefill_lines;
rsc_config.jitter = disp_info->jitter;
/* update it only once */
- sde_enc->rsc_state_update = true;
+ sde_enc->rsc_state_init = true;
ret = sde_rsc_client_state_update(sde_enc->rsc_client,
rsc_state, &rsc_config,
@@ -748,6 +818,277 @@
return disp_info->is_primary ? sde_enc->rsc_client : NULL;
}
+static void _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
+ bool enable)
+{
+ struct msm_drm_private *priv;
+ struct sde_kms *sde_kms;
+ struct sde_encoder_virt *sde_enc;
+ int i;
+
+ sde_enc = to_sde_encoder_virt(drm_enc);
+ priv = drm_enc->dev->dev_private;
+ sde_kms = to_sde_kms(priv->kms);
+
+ SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
+ SDE_EVT32(DRMID(drm_enc), enable);
+
+ if (!sde_enc->cur_master) {
+ SDE_ERROR("encoder master not set\n");
+ return;
+ }
+
+ if (enable) {
+ /* enable SDE core clks */
+ sde_power_resource_enable(&priv->phandle,
+ sde_kms->core_client, true);
+
+ /* enable DSI clks */
+ sde_connector_clk_ctrl(sde_enc->cur_master->connector, true);
+
+ /* enable all the irq */
+ for (i = 0; i < sde_enc->num_phys_encs; i++) {
+ struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+ if (phys && phys->ops.irq_control)
+ phys->ops.irq_control(phys, true);
+ }
+
+ /* enable RSC */
+ sde_encoder_update_rsc_client(drm_enc, true);
+
+ } else {
+
+ /* disable RSC */
+ sde_encoder_update_rsc_client(drm_enc, false);
+
+ /* disable all the irq */
+ for (i = 0; i < sde_enc->num_phys_encs; i++) {
+ struct sde_encoder_phys *phys =
+ sde_enc->phys_encs[i];
+
+ if (phys && phys->ops.irq_control)
+ phys->ops.irq_control(phys, false);
+ }
+
+ /* disable DSI clks */
+ sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
+
+ /* disable SDE core clks */
+ sde_power_resource_enable(&priv->phandle,
+ sde_kms->core_client, false);
+ }
+
+}
+
+static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
+ u32 sw_event)
+{
+ bool schedule_off = false;
+ struct sde_encoder_virt *sde_enc;
+
+ if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
+ SDE_ERROR("invalid parameters\n");
+ return -EINVAL;
+ }
+ sde_enc = to_sde_encoder_virt(drm_enc);
+
+ /*
+ * when idle_pc is not supported, process only KICKOFF and STOP
+ * event and return early for other events (ie video mode).
+ */
+ if (!sde_enc->idle_pc_supported &&
+ (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
+ sw_event != SDE_ENC_RC_EVENT_STOP))
+ return 0;
+
+ SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc_supported:%d\n", sw_event,
+ sde_enc->idle_pc_supported);
+ SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->idle_pc_supported,
+ sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
+
+ switch (sw_event) {
+ case SDE_ENC_RC_EVENT_KICKOFF:
+ /* cancel delayed off work, if any */
+ if (cancel_delayed_work_sync(&sde_enc->delayed_off_work))
+ SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
+ sw_event);
+
+ mutex_lock(&sde_enc->rc_lock);
+
+ /* return if the resource control is already in ON state */
+ if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
+ SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
+ sw_event);
+ mutex_unlock(&sde_enc->rc_lock);
+ return 0;
+ }
+
+ /* enable all the clks and resources */
+ _sde_encoder_resource_control_helper(drm_enc, true);
+
+ SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
+ SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
+ sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
+
+ mutex_unlock(&sde_enc->rc_lock);
+ break;
+
+ case SDE_ENC_RC_EVENT_FRAME_DONE:
+ /*
+ * mutex lock is not used as this event happens at interrupt
+ * context. And locking is not required as, the other events
+ * like KICKOFF and STOP does a wait-for-idle before executing
+ * the resource_control
+ */
+ if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
+ SDE_ERROR_ENC(sde_enc, "sw_event:%d,rc:%d-unexpected\n",
+ sw_event, sde_enc->rc_state);
+ return -EINVAL;
+ }
+
+ /*
+ * schedule off work item only when there are no
+ * frames pending
+ */
+ if (sde_crtc_frame_pending(drm_enc->crtc) > 1) {
+ SDE_DEBUG_ENC(sde_enc, "skip schedule work");
+ return 0;
+ }
+
+ /* schedule delayed off work */
+ schedule_delayed_work(&sde_enc->delayed_off_work,
+ msecs_to_jiffies(IDLE_TIMEOUT));
+ SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
+ SDE_EVTLOG_FUNC_CASE2);
+ SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
+ sw_event);
+ break;
+
+ case SDE_ENC_RC_EVENT_STOP:
+ /* cancel delayed off work, if any */
+ if (cancel_delayed_work_sync(&sde_enc->delayed_off_work))
+ SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
+ sw_event);
+
+ mutex_lock(&sde_enc->rc_lock);
+
+ /* return if the resource control is already in OFF state */
+ if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
+ SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
+ sw_event);
+ mutex_unlock(&sde_enc->rc_lock);
+ return 0;
+ }
+
+ /*
+ * disable the clks and resources only if the resource control
+ * is in ON state, otherwise the clks and resources would have
+ * been disabled while going into IDLE state
+ */
+ if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON)
+ _sde_encoder_resource_control_helper(drm_enc, false);
+
+ SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
+ SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE3);
+ sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
+
+ mutex_unlock(&sde_enc->rc_lock);
+ break;
+
+ case SDE_ENC_RC_EVENT_EARLY_WAKE_UP:
+ /* cancel delayed off work, if any */
+ if (cancel_delayed_work_sync(&sde_enc->delayed_off_work)) {
+ SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
+ sw_event);
+ schedule_off = true;
+ }
+
+ mutex_lock(&sde_enc->rc_lock);
+
+ SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
+ schedule_off, SDE_EVTLOG_FUNC_CASE4);
+
+ /* return if the resource control is in OFF state */
+ if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
+ SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
+ sw_event);
+ mutex_unlock(&sde_enc->rc_lock);
+ return 0;
+ }
+
+ /*
+ * enable all the clks and resources if resource control is
+ * coming out of IDLE state
+ */
+ if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
+ _sde_encoder_resource_control_helper(drm_enc, true);
+ sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
+ schedule_off = true;
+ }
+
+ /*
+ * schedule off work when there are no frames pending and
+ * 1. early wakeup cancelled off work
+ * 2. early wakeup changed the rc_state to ON - this is to
+ * handle cases where early wakeup is called but no
+ * frame updates
+ */
+ if (schedule_off && !sde_crtc_frame_pending(drm_enc->crtc)) {
+ /* schedule delayed off work */
+ schedule_delayed_work(&sde_enc->delayed_off_work,
+ msecs_to_jiffies(IDLE_TIMEOUT));
+ SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
+ sw_event);
+ }
+
+ mutex_unlock(&sde_enc->rc_lock);
+ break;
+
+ case SDE_ENC_RC_EVENT_ENTER_IDLE:
+ mutex_lock(&sde_enc->rc_lock);
+
+ if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
+ SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
+ sw_event, sde_enc->rc_state);
+ mutex_unlock(&sde_enc->rc_lock);
+ return 0;
+ }
+
+ /* disable all the clks and resources */
+ _sde_encoder_resource_control_helper(drm_enc, false);
+ SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
+ SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE5);
+ sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
+
+ mutex_unlock(&sde_enc->rc_lock);
+ break;
+
+ default:
+ SDE_ERROR("unexpected sw_event: %d\n", sw_event);
+ break;
+ }
+
+ SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->idle_pc_supported,
+ sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
+ return 0;
+}
+
+static void sde_encoder_off_work(struct work_struct *work)
+{
+ struct delayed_work *dw = to_delayed_work(work);
+ struct sde_encoder_virt *sde_enc = container_of(dw,
+ struct sde_encoder_virt, delayed_off_work);
+
+ if (!sde_enc) {
+ SDE_ERROR("invalid sde encoder\n");
+ return;
+ }
+
+ sde_encoder_resource_control(&sde_enc->base,
+ SDE_ENC_RC_EVENT_ENTER_IDLE);
+}
+
static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
struct drm_display_mode *mode,
struct drm_display_mode *adj_mode)
@@ -828,61 +1169,116 @@
}
}
-static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
+static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
{
struct sde_encoder_virt *sde_enc = NULL;
- int i = 0;
+ struct msm_drm_private *priv;
+ struct sde_kms *sde_kms;
int ret = 0;
+ if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
+ SDE_ERROR("invalid parameters\n");
+ return;
+ }
+ priv = drm_enc->dev->dev_private;
+
+ sde_enc = to_sde_encoder_virt(drm_enc);
+ if (!sde_enc || !sde_enc->cur_master) {
+ SDE_ERROR("invalid sde encoder/master\n");
+ return;
+ }
+
+ sde_kms = to_sde_kms(priv->kms);
+ if (!sde_kms) {
+ SDE_ERROR("invalid sde_kms\n");
+ return;
+ }
+
+ if (sde_enc->cur_master->hw_mdptop &&
+ sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
+ sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
+ sde_enc->cur_master->hw_mdptop,
+ sde_kms->catalog);
+
+ if (_sde_is_dsc_enabled(sde_enc)) {
+ ret = _sde_encoder_dsc_setup(sde_enc);
+ if (ret)
+ SDE_ERROR_ENC(sde_enc, "failed to setup DSC:%d\n", ret);
+ }
+}
+
+void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
+{
+ struct sde_encoder_virt *sde_enc = NULL;
+ int i;
+
if (!drm_enc) {
SDE_ERROR("invalid encoder\n");
return;
- } else if (!drm_enc->dev) {
- SDE_ERROR("invalid dev\n");
- return;
- } else if (!drm_enc->dev->dev_private) {
- SDE_ERROR("invalid dev_private\n");
- return;
+ }
+ sde_enc = to_sde_encoder_virt(drm_enc);
+
+ for (i = 0; i < sde_enc->num_phys_encs; i++) {
+ struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+ if (phys && (phys != sde_enc->cur_master) && phys->ops.restore)
+ phys->ops.restore(phys);
}
+ if (sde_enc->cur_master && sde_enc->cur_master->ops.restore)
+ sde_enc->cur_master->ops.restore(sde_enc->cur_master);
+
+ _sde_encoder_virt_enable_helper(drm_enc);
+}
+
+static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
+{
+ struct sde_encoder_virt *sde_enc = NULL;
+ int i, ret = 0;
+
+ if (!drm_enc) {
+ SDE_ERROR("invalid encoder\n");
+ return;
+ }
sde_enc = to_sde_encoder_virt(drm_enc);
SDE_DEBUG_ENC(sde_enc, "\n");
SDE_EVT32(DRMID(drm_enc));
- ret = _sde_encoder_power_enable(sde_enc, true);
- if (ret)
- return;
-
sde_enc->cur_master = NULL;
+ for (i = 0; i < sde_enc->num_phys_encs; i++) {
+ struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
+
+ if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
+ SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
+ sde_enc->cur_master = phys;
+ break;
+ }
+ }
+
+ if (!sde_enc->cur_master) {
+ SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
+ return;
+ }
+
+ ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
+ if (ret) {
+ SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
+ ret);
+ return;
+ }
for (i = 0; i < sde_enc->num_phys_encs; i++) {
struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
- if (phys) {
- if (phys->ops.is_master && phys->ops.is_master(phys)) {
- SDE_DEBUG_ENC(sde_enc,
- "master is now idx %d\n", i);
- sde_enc->cur_master = phys;
- } else if (phys->ops.enable) {
- phys->ops.enable(phys);
- }
- }
+ if (phys && (phys != sde_enc->cur_master) && phys->ops.enable)
+ phys->ops.enable(phys);
}
- sde_encoder_update_rsc_client(drm_enc, true);
-
- if (!sde_enc->cur_master)
- SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
- else if (sde_enc->cur_master->ops.enable)
+ if (sde_enc->cur_master->ops.enable)
sde_enc->cur_master->ops.enable(sde_enc->cur_master);
- if (_sde_is_dsc_enabled(sde_enc)) {
- ret = _sde_encoder_dsc_setup(sde_enc);
- if (ret)
- SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n",
- ret);
- }
+ _sde_encoder_virt_enable_helper(drm_enc);
}
static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
@@ -914,9 +1310,8 @@
for (i = 0; i < sde_enc->num_phys_encs; i++) {
struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
- if (phys) {
- if (phys->ops.disable && !phys->ops.is_master(phys))
- phys->ops.disable(phys);
+ if (phys && phys->ops.disable && !phys->ops.is_master(phys)) {
+ phys->ops.disable(phys);
phys->connector = NULL;
}
}
@@ -927,17 +1322,19 @@
del_timer_sync(&sde_enc->frame_done_timer);
}
- sde_encoder_update_rsc_client(drm_enc, false);
-
if (sde_enc->cur_master && sde_enc->cur_master->ops.disable)
sde_enc->cur_master->ops.disable(sde_enc->cur_master);
- sde_enc->cur_master = NULL;
- SDE_DEBUG_ENC(sde_enc, "cleared master\n");
+ sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
+
+ if (sde_enc->cur_master) {
+ sde_enc->cur_master->connector = NULL;
+ sde_enc->cur_master = NULL;
+ }
+
+ SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
sde_rm_release(&sde_kms->rm, drm_enc);
-
- _sde_encoder_power_enable(sde_enc, false);
}
static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
@@ -1066,6 +1463,9 @@
atomic_set(&sde_enc->frame_done_timeout, 0);
del_timer(&sde_enc->frame_done_timer);
+ sde_encoder_resource_control(drm_enc,
+ SDE_ENC_RC_EVENT_FRAME_DONE);
+
if (sde_enc->crtc_frame_event_cb)
sde_enc->crtc_frame_event_cb(
sde_enc->crtc_frame_event_cb_data,
@@ -1097,6 +1497,14 @@
return;
}
+ if (phys->split_role == ENC_ROLE_SKIP) {
+ SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
+ "skip flush pp%d ctl%d\n",
+ phys->hw_pp->idx - PINGPONG_0,
+ ctl->idx - CTL_0);
+ return;
+ }
+
pending_kickoff_cnt = sde_encoder_phys_inc_pending(phys);
if (extra_flush_bits && ctl->ops.update_pending_flush)
@@ -1118,11 +1526,21 @@
*/
static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
{
+ struct sde_hw_ctl *ctl;
+
if (!phys) {
SDE_ERROR("invalid encoder\n");
return;
}
+ ctl = phys->hw_ctl;
+ if (phys->split_role == ENC_ROLE_SKIP) {
+ SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
+ "skip start pp%d ctl%d\n",
+ phys->hw_pp->idx - PINGPONG_0,
+ ctl->idx - CTL_0);
+ return;
+ }
if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
phys->ops.trigger_start(phys);
}
@@ -1254,9 +1672,13 @@
topology = sde_connector_get_topology_name(
phys->connector);
- /* don't wait on ppsplit slaves, they dont register irqs */
+ /*
+ * don't wait on ppsplit slaves or skipped encoders because
+ * they dont receive irqs
+ */
if (!(topology == SDE_RM_TOPOLOGY_PPSPLIT &&
- phys->split_role == ENC_ROLE_SLAVE))
+ phys->split_role == ENC_ROLE_SLAVE) &&
+ phys->split_role != ENC_ROLE_SKIP)
set_bit(i, sde_enc->frame_busy_mask);
if (!phys->ops.needs_single_flush ||
@@ -1279,6 +1701,92 @@
spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
}
+static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
+ struct sde_encoder_kickoff_params *params)
+{
+ struct sde_encoder_virt *sde_enc;
+ struct sde_encoder_phys *phys;
+ int i, num_active_phys;
+ bool master_assigned = false;
+
+ if (!drm_enc || !params)
+ return;
+
+ sde_enc = to_sde_encoder_virt(drm_enc);
+
+ if (sde_enc->num_phys_encs <= 1)
+ return;
+
+ /* count bits set */
+ num_active_phys = hweight_long(params->affected_displays);
+
+ SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
+ params->affected_displays, num_active_phys);
+
+ for (i = 0; i < sde_enc->num_phys_encs; i++) {
+ enum sde_enc_split_role prv_role, new_role;
+ bool active;
+
+ phys = sde_enc->phys_encs[i];
+ if (!phys || !phys->ops.update_split_role)
+ continue;
+
+ active = test_bit(i, ¶ms->affected_displays);
+ prv_role = phys->split_role;
+
+ if (active && num_active_phys == 1)
+ new_role = ENC_ROLE_SOLO;
+ else if (active && !master_assigned)
+ new_role = ENC_ROLE_MASTER;
+ else if (active)
+ new_role = ENC_ROLE_SLAVE;
+ else
+ new_role = ENC_ROLE_SKIP;
+
+ phys->ops.update_split_role(phys, new_role);
+ if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
+ sde_enc->cur_master = phys;
+ master_assigned = true;
+ }
+
+ SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
+ phys->hw_pp->idx - PINGPONG_0, prv_role,
+ phys->split_role, active);
+ }
+}
+
+void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
+{
+ struct sde_encoder_virt *sde_enc;
+ struct sde_encoder_phys *phys;
+ unsigned int i;
+ struct sde_hw_ctl *ctl;
+ struct msm_display_info *disp_info;
+
+ if (!drm_enc) {
+ SDE_ERROR("invalid encoder\n");
+ return;
+ }
+ sde_enc = to_sde_encoder_virt(drm_enc);
+ disp_info = &sde_enc->disp_info;
+
+ for (i = 0; i < sde_enc->num_phys_encs; i++) {
+ phys = sde_enc->phys_encs[i];
+
+ if (phys && phys->hw_ctl) {
+ ctl = phys->hw_ctl;
+ if (ctl->ops.clear_pending_flush)
+ ctl->ops.clear_pending_flush(ctl);
+
+ /* update only for command mode primary ctl */
+ if ((phys == sde_enc->cur_master) &&
+ (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
+ && ctl->ops.trigger_pending)
+ ctl->ops.trigger_pending(ctl);
+ }
+ }
+}
+
void sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
struct sde_encoder_kickoff_params *params)
{
@@ -1288,8 +1796,8 @@
unsigned int i;
int rc;
- if (!drm_enc) {
- SDE_ERROR("invalid encoder\n");
+ if (!drm_enc || !params) {
+ SDE_ERROR("invalid args\n");
return;
}
sde_enc = to_sde_encoder_virt(drm_enc);
@@ -1308,8 +1816,11 @@
}
}
+ sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
+
/* if any phys needs reset, reset all phys, in-order */
if (needs_hw_reset) {
+ SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_FUNC_CASE1);
for (i = 0; i < sde_enc->num_phys_encs; i++) {
phys = sde_enc->phys_encs[i];
if (phys && phys->ops.hw_reset)
@@ -1317,6 +1828,8 @@
}
}
+ _sde_encoder_update_master(drm_enc, params);
+
if (sde_enc->cur_master && sde_enc->cur_master->connector) {
rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
if (rc)
@@ -1798,6 +2311,9 @@
phys_params.comp_type = disp_info->comp_info.comp_type;
+ if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
+ sde_enc->idle_pc_supported = sde_kms->catalog->has_idle_pc;
+
mutex_lock(&sde_enc->enc_lock);
for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
/*
@@ -1958,6 +2474,9 @@
sde_enc->rsc_client = NULL;
}
+ mutex_init(&sde_enc->rc_lock);
+ INIT_DELAYED_WORK(&sde_enc->delayed_off_work, sde_encoder_off_work);
+
memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
SDE_DEBUG_ENC(sde_enc, "created\n");
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.h b/drivers/gpu/drm/msm/sde/sde_encoder.h
index 5795e04..c5ddee6 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.h
@@ -47,9 +47,12 @@
/**
* sde_encoder_kickoff_params - info encoder requires at kickoff
* @inline_rotate_prefill: number of lines to prefill for inline rotation
+ * @affected_displays: bitmask, bit set means the ROI of the commit lies within
+ * the bounds of the physical display at the bit index
*/
struct sde_encoder_kickoff_params {
u32 inline_rotate_prefill;
+ unsigned long affected_displays;
};
/**
@@ -101,6 +104,13 @@
struct sde_encoder_kickoff_params *params);
/**
+ * sde_encoder_trigger_kickoff_pending - Clear the flush bits from previous
+ * kickoff and trigger the ctl prepare progress for command mode display.
+ * @encoder: encoder pointer
+ */
+void sde_encoder_trigger_kickoff_pending(struct drm_encoder *encoder);
+
+/**
* sde_encoder_kickoff - trigger a double buffer flip of the ctl path
* (i.e. ctl flush and start) immediately.
* @encoder: encoder pointer
@@ -124,6 +134,12 @@
enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder);
/**
+ * sde_encoder_virt_restore - restore the encoder configs
+ * @encoder: encoder pointer
+ */
+void sde_encoder_virt_restore(struct drm_encoder *encoder);
+
+/**
* enum sde_encoder_property - property tags for sde enoder
* @SDE_ENCODER_PROPERTY_INLINE_ROTATE_REFILL: # of prefill line, 0 to disable
*/
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
index da155b0..a3b112d 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys.h
@@ -41,11 +41,13 @@
* @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master.
* @ENC_ROLE_MASTER: This encoder is the master of a split panel config.
* @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config.
+ * @ENC_ROLE_SKIP: This encoder is not participating in kickoffs
*/
enum sde_enc_split_role {
ENC_ROLE_SOLO,
ENC_ROLE_MASTER,
- ENC_ROLE_SLAVE
+ ENC_ROLE_SLAVE,
+ ENC_ROLE_SKIP
};
/**
@@ -117,6 +119,9 @@
* @collect_misr: Collects MISR data on frame update
* @hw_reset: Issue HW recovery such as CTL reset and clear
* SDE_ENC_ERR_NEEDS_HW_RESET state
+ * @irq_control: Handler to enable/disable all the encoder IRQs
+ * @update_split_role: Update the split role of the phys enc
+ * @restore: Restore all the encoder configs.
*/
struct sde_encoder_phys_ops {
@@ -150,6 +155,10 @@
bool enable, u32 frame_count);
u32 (*collect_misr)(struct sde_encoder_phys *phys_enc);
void (*hw_reset)(struct sde_encoder_phys *phys_enc);
+ void (*irq_control)(struct sde_encoder_phys *phys, bool enable);
+ void (*update_split_role)(struct sde_encoder_phys *phys_enc,
+ enum sde_enc_split_role role);
+ void (*restore)(struct sde_encoder_phys *phys);
};
/**
@@ -163,6 +172,7 @@
INTR_IDX_VSYNC,
INTR_IDX_PINGPONG,
INTR_IDX_UNDERRUN,
+ INTR_IDX_CTL_START,
INTR_IDX_RDPTR,
INTR_IDX_MAX,
};
@@ -196,6 +206,8 @@
* vs. the number of done/vblank irqs. Should hover
* between 0-2 Incremented when a new kickoff is
* scheduled. Decremented in irq handler
+ * @pending_ctlstart_cnt: Atomic counter tracking the number of ctl start
+ * pending.
* @pending_kickoff_wq: Wait queue for blocking until kickoff completes
*/
struct sde_encoder_phys {
@@ -219,12 +231,14 @@
atomic_t vblank_refcount;
atomic_t vsync_cnt;
atomic_t underrun_cnt;
+ atomic_t pending_ctlstart_cnt;
atomic_t pending_kickoff_cnt;
wait_queue_head_t pending_kickoff_wq;
};
static inline int sde_encoder_phys_inc_pending(struct sde_encoder_phys *phys)
{
+ atomic_inc_return(&phys->pending_ctlstart_cnt);
return atomic_inc_return(&phys->pending_kickoff_cnt);
}
@@ -263,7 +277,6 @@
*/
struct sde_encoder_phys_cmd {
struct sde_encoder_phys base;
- int intf_idx;
int stream_sel;
int irq_idx[INTR_IDX_MAX];
struct sde_irq_callback irq_cb[INTR_IDX_MAX];
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
index 5b59828..572bd9e 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
@@ -21,18 +21,21 @@
#define SDE_DEBUG_CMDENC(e, fmt, ...) SDE_DEBUG("enc%d intf%d " fmt, \
(e) && (e)->base.parent ? \
(e)->base.parent->base.id : -1, \
- (e) ? (e)->intf_idx - INTF_0 : -1, ##__VA_ARGS__)
+ (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
#define SDE_ERROR_CMDENC(e, fmt, ...) SDE_ERROR("enc%d intf%d " fmt, \
(e) && (e)->base.parent ? \
(e)->base.parent->base.id : -1, \
- (e) ? (e)->intf_idx - INTF_0 : -1, ##__VA_ARGS__)
+ (e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)
#define to_sde_encoder_phys_cmd(x) \
container_of(x, struct sde_encoder_phys_cmd, base)
#define PP_TIMEOUT_MAX_TRIALS 10
+/* wait for 2 vyncs only */
+#define CTL_START_TIMEOUT_MS 32
+
/*
* Tearcheck sync start and continue thresholds are empirically found
* based on common panels In the future, may want to allow panels to override
@@ -57,6 +60,46 @@
return true;
}
+static void _sde_encoder_phys_cmd_update_flush_mask(
+ struct sde_encoder_phys *phys_enc)
+{
+ struct sde_encoder_phys_cmd *cmd_enc =
+ to_sde_encoder_phys_cmd(phys_enc);
+ struct sde_hw_ctl *ctl;
+ u32 flush_mask = 0;
+
+ ctl = phys_enc->hw_ctl;
+ if (!ctl || !ctl->ops.get_bitmask_intf ||
+ !ctl->ops.update_pending_flush)
+ return;
+
+ ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx);
+ ctl->ops.update_pending_flush(ctl, flush_mask);
+
+ SDE_DEBUG_CMDENC(cmd_enc, "update pending flush ctl %d flush_mask %x\n",
+ ctl->idx - CTL_0, flush_mask);
+}
+
+static void _sde_encoder_phys_cmd_update_intf_cfg(
+ struct sde_encoder_phys *phys_enc)
+{
+ struct sde_encoder_phys_cmd *cmd_enc =
+ to_sde_encoder_phys_cmd(phys_enc);
+ struct sde_hw_ctl *ctl;
+ struct sde_hw_intf_cfg intf_cfg = { 0 };
+
+ ctl = phys_enc->hw_ctl;
+ if (!ctl || !ctl->ops.setup_intf_cfg)
+ return;
+
+ intf_cfg.intf = phys_enc->intf_idx;
+ intf_cfg.intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
+ intf_cfg.stream_sel = cmd_enc->stream_sel;
+ intf_cfg.mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
+ ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
+}
+
+
static void sde_encoder_phys_cmd_mode_set(
struct sde_encoder_phys *phys_enc,
struct drm_display_mode *mode,
@@ -130,11 +173,35 @@
if (!cmd_enc)
return;
+ SDE_EVT32_IRQ(DRMID(phys_enc->parent),
+ phys_enc->hw_pp->idx - PINGPONG_0, 0xfff);
+
if (phys_enc->parent_ops.handle_vblank_virt)
phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
phys_enc);
}
+static void sde_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx)
+{
+ struct sde_encoder_phys_cmd *cmd_enc = arg;
+ struct sde_encoder_phys *phys_enc;
+ struct sde_hw_ctl *ctl;
+
+ if (!cmd_enc)
+ return;
+
+ phys_enc = &cmd_enc->base;
+ if (!phys_enc->hw_ctl)
+ return;
+
+ ctl = phys_enc->hw_ctl;
+ SDE_EVT32_IRQ(DRMID(phys_enc->parent), ctl->idx - CTL_0, 0xfff);
+ atomic_add_unless(&phys_enc->pending_ctlstart_cnt, -1, 0);
+
+ /* Signal any waiting ctl start interrupt */
+ wake_up_all(&phys_enc->pending_kickoff_wq);
+}
+
static bool _sde_encoder_phys_is_ppsplit(struct sde_encoder_phys *phys_enc)
{
enum sde_rm_topology_name topology;
@@ -240,7 +307,7 @@
if (ret <= 0) {
/* read and clear interrupt */
irq_status = sde_core_irq_read(phys_enc->sde_kms,
- INTR_IDX_PINGPONG, true);
+ cmd_enc->irq_idx[INTR_IDX_PINGPONG], true);
if (irq_status) {
unsigned long flags;
SDE_EVT32(DRMID(phys_enc->parent),
@@ -295,8 +362,13 @@
return -EINVAL;
}
- idx_lookup = (intr_type == SDE_IRQ_TYPE_INTF_UNDER_RUN) ?
- cmd_enc->intf_idx : phys_enc->hw_pp->idx;
+ if (intr_type == SDE_IRQ_TYPE_INTF_UNDER_RUN)
+ idx_lookup = phys_enc->intf_idx;
+ else if (intr_type == SDE_IRQ_TYPE_CTL_START)
+ idx_lookup = phys_enc->hw_ctl ? phys_enc->hw_ctl->idx : -1;
+ else
+ idx_lookup = phys_enc->hw_pp->idx;
+
cmd_enc->irq_idx[idx] = sde_core_irq_idx_lookup(phys_enc->sde_kms,
intr_type, idx_lookup);
if (cmd_enc->irq_idx[idx] < 0) {
@@ -363,6 +435,92 @@
return 0;
}
+static int sde_encoder_phys_cmd_control_vblank_irq(
+ struct sde_encoder_phys *phys_enc,
+ bool enable)
+{
+ struct sde_encoder_phys_cmd *cmd_enc =
+ to_sde_encoder_phys_cmd(phys_enc);
+ int ret = 0;
+
+ if (!phys_enc) {
+ SDE_ERROR("invalid encoder\n");
+ return -EINVAL;
+ }
+
+ /* Slave encoders don't report vblank */
+ if (!sde_encoder_phys_cmd_is_master(phys_enc))
+ goto end;
+
+ SDE_DEBUG_CMDENC(cmd_enc, "[%pS] enable=%d/%d\n",
+ __builtin_return_address(0),
+ enable, atomic_read(&phys_enc->vblank_refcount));
+
+ SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
+ enable, atomic_read(&phys_enc->vblank_refcount));
+
+ if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
+ ret = sde_encoder_phys_cmd_register_irq(phys_enc,
+ SDE_IRQ_TYPE_PING_PONG_RD_PTR,
+ INTR_IDX_RDPTR,
+ sde_encoder_phys_cmd_pp_rd_ptr_irq,
+ "pp_rd_ptr");
+ else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
+ ret = sde_encoder_phys_cmd_unregister_irq(phys_enc,
+ INTR_IDX_RDPTR);
+
+end:
+ if (ret)
+ SDE_ERROR_CMDENC(cmd_enc,
+ "control vblank irq error %d, enable %d\n",
+ ret, enable);
+
+ return ret;
+}
+
+void sde_encoder_phys_cmd_irq_control(struct sde_encoder_phys *phys_enc,
+ bool enable)
+{
+ struct sde_encoder_phys_cmd *cmd_enc;
+
+ if (!phys_enc || _sde_encoder_phys_is_ppsplit_slave(phys_enc))
+ return;
+
+ cmd_enc = to_sde_encoder_phys_cmd(phys_enc);
+
+ if (enable) {
+ sde_encoder_phys_cmd_register_irq(phys_enc,
+ SDE_IRQ_TYPE_PING_PONG_COMP,
+ INTR_IDX_PINGPONG,
+ sde_encoder_phys_cmd_pp_tx_done_irq,
+ "pp_tx_done");
+
+ sde_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
+
+ sde_encoder_phys_cmd_register_irq(phys_enc,
+ SDE_IRQ_TYPE_INTF_UNDER_RUN,
+ INTR_IDX_UNDERRUN,
+ sde_encoder_phys_cmd_underrun_irq,
+ "underrun");
+
+ if (sde_encoder_phys_cmd_is_master(phys_enc))
+ sde_encoder_phys_cmd_register_irq(phys_enc,
+ SDE_IRQ_TYPE_CTL_START,
+ INTR_IDX_CTL_START,
+ sde_encoder_phys_cmd_ctl_start_irq,
+ "ctl_start");
+ } else {
+ if (sde_encoder_phys_cmd_is_master(phys_enc))
+ sde_encoder_phys_cmd_unregister_irq(
+ phys_enc, INTR_IDX_CTL_START);
+ sde_encoder_phys_cmd_unregister_irq(
+ phys_enc, INTR_IDX_UNDERRUN);
+ sde_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
+ sde_encoder_phys_cmd_unregister_irq(
+ phys_enc, INTR_IDX_PINGPONG);
+ }
+}
+
static void sde_encoder_phys_cmd_tearcheck_config(
struct sde_encoder_phys *phys_enc)
{
@@ -441,12 +599,11 @@
phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, tc_enable);
}
-static void sde_encoder_phys_cmd_pingpong_config(
+static void _sde_encoder_phys_cmd_pingpong_config(
struct sde_encoder_phys *phys_enc)
{
struct sde_encoder_phys_cmd *cmd_enc =
to_sde_encoder_phys_cmd(phys_enc);
- struct sde_hw_intf_cfg intf_cfg = { 0 };
if (!phys_enc || !phys_enc->hw_ctl ||
!phys_enc->hw_ctl->ops.setup_intf_cfg) {
@@ -458,13 +615,7 @@
phys_enc->hw_pp->idx - PINGPONG_0);
drm_mode_debug_printmodeline(&phys_enc->cached_mode);
- intf_cfg.intf = cmd_enc->intf_idx;
- intf_cfg.intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
- intf_cfg.stream_sel = cmd_enc->stream_sel;
- intf_cfg.mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
-
- phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
-
+ _sde_encoder_phys_cmd_update_intf_cfg(phys_enc);
sde_encoder_phys_cmd_tearcheck_config(phys_enc);
}
@@ -477,59 +628,33 @@
return _sde_encoder_phys_is_ppsplit(phys_enc);
}
-static int sde_encoder_phys_cmd_control_vblank_irq(
- struct sde_encoder_phys *phys_enc,
- bool enable)
+static void sde_encoder_phys_cmd_enable_helper(
+ struct sde_encoder_phys *phys_enc)
{
- struct sde_encoder_phys_cmd *cmd_enc =
- to_sde_encoder_phys_cmd(phys_enc);
- int ret = 0;
+ struct sde_hw_ctl *ctl;
+ u32 flush_mask = 0;
- if (!phys_enc) {
- SDE_ERROR("invalid encoder\n");
- return -EINVAL;
+ if (!phys_enc || !phys_enc->hw_ctl) {
+ SDE_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
+ return;
}
- /* Slave encoders don't report vblank */
- if (!sde_encoder_phys_cmd_is_master(phys_enc))
- goto end;
+ sde_encoder_helper_split_config(phys_enc, phys_enc->intf_idx);
- SDE_DEBUG_CMDENC(cmd_enc, "[%pS] enable=%d/%d\n",
- __builtin_return_address(0),
- enable, atomic_read(&phys_enc->vblank_refcount));
+ _sde_encoder_phys_cmd_pingpong_config(phys_enc);
- SDE_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0,
- enable, atomic_read(&phys_enc->vblank_refcount));
-
- if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1)
- ret = sde_encoder_phys_cmd_register_irq(phys_enc,
- SDE_IRQ_TYPE_PING_PONG_RD_PTR,
- INTR_IDX_RDPTR,
- sde_encoder_phys_cmd_pp_rd_ptr_irq,
- "pp_rd_ptr");
- else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0)
- ret = sde_encoder_phys_cmd_unregister_irq(phys_enc,
- INTR_IDX_RDPTR);
-
-end:
- if (ret)
- SDE_ERROR_CMDENC(cmd_enc,
- "control vblank irq error %d, enable %d\n",
- ret, enable);
-
- return ret;
+ ctl = phys_enc->hw_ctl;
+ ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx);
+ ctl->ops.update_pending_flush(ctl, flush_mask);
}
static void sde_encoder_phys_cmd_enable(struct sde_encoder_phys *phys_enc)
{
struct sde_encoder_phys_cmd *cmd_enc =
to_sde_encoder_phys_cmd(phys_enc);
- struct sde_hw_ctl *ctl;
- u32 flush_mask = 0;
- int ret;
- if (!phys_enc || !phys_enc->hw_ctl) {
- SDE_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
+ if (!phys_enc) {
+ SDE_ERROR("invalid phys encoder\n");
return;
}
SDE_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
@@ -539,49 +664,8 @@
return;
}
- sde_encoder_helper_split_config(phys_enc, cmd_enc->intf_idx);
-
- sde_encoder_phys_cmd_pingpong_config(phys_enc);
-
- if (_sde_encoder_phys_is_ppsplit_slave(phys_enc))
- goto update_flush;
-
- /* Both master and slave need to register for pp_tx_done */
- ret = sde_encoder_phys_cmd_register_irq(phys_enc,
- SDE_IRQ_TYPE_PING_PONG_COMP,
- INTR_IDX_PINGPONG,
- sde_encoder_phys_cmd_pp_tx_done_irq,
- "pp_tx_done");
- if (ret)
- return;
-
- ret = sde_encoder_phys_cmd_control_vblank_irq(phys_enc, true);
- if (ret) {
- sde_encoder_phys_cmd_unregister_irq(phys_enc,
- INTR_IDX_PINGPONG);
- return;
- }
-
- ret = sde_encoder_phys_cmd_register_irq(phys_enc,
- SDE_IRQ_TYPE_INTF_UNDER_RUN,
- INTR_IDX_UNDERRUN,
- sde_encoder_phys_cmd_underrun_irq,
- "underrun");
- if (ret) {
- sde_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
- sde_encoder_phys_cmd_unregister_irq(phys_enc,
- INTR_IDX_PINGPONG);
- return;
- }
-
-update_flush:
- ctl = phys_enc->hw_ctl;
- ctl->ops.get_bitmask_intf(ctl, &flush_mask, cmd_enc->intf_idx);
- ctl->ops.update_pending_flush(ctl, flush_mask);
+ sde_encoder_phys_cmd_enable_helper(phys_enc);
phys_enc->enable_state = SDE_ENC_ENABLED;
-
- SDE_DEBUG_CMDENC(cmd_enc, "update pending flush ctl %d flush_mask %x\n",
- ctl->idx - CTL_0, flush_mask);
}
static void sde_encoder_phys_cmd_disable(struct sde_encoder_phys *phys_enc)
@@ -613,21 +697,9 @@
SDE_EVT32(DRMID(phys_enc->parent),
phys_enc->hw_pp->idx - PINGPONG_0, ret);
}
-
- sde_encoder_phys_cmd_unregister_irq(
- phys_enc, INTR_IDX_UNDERRUN);
- sde_encoder_phys_cmd_control_vblank_irq(phys_enc, false);
- sde_encoder_phys_cmd_unregister_irq(
- phys_enc, INTR_IDX_PINGPONG);
}
phys_enc->enable_state = SDE_ENC_DISABLED;
-
- if (atomic_read(&phys_enc->vblank_refcount))
- SDE_ERROR("enc:%d role:%d invalid vblank refcount %d\n",
- phys_enc->parent->base.id,
- phys_enc->split_role,
- atomic_read(&phys_enc->vblank_refcount));
}
static void sde_encoder_phys_cmd_destroy(struct sde_encoder_phys *phys_enc)
@@ -655,7 +727,7 @@
return;
}
SDE_DEBUG_CMDENC(cmd_enc, "\n");
- hw_res->intfs[cmd_enc->intf_idx - INTF_0] = INTF_MODE_CMD;
+ hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_CMD;
}
static void sde_encoder_phys_cmd_prepare_for_kickoff(
@@ -687,24 +759,93 @@
}
}
+static int _sde_encoder_phys_cmd_wait_for_ctl_start(
+ struct sde_encoder_phys *phys_enc)
+{
+ int rc = 0;
+ struct sde_hw_ctl *ctl;
+ u32 irq_status;
+ struct sde_encoder_phys_cmd *cmd_enc;
+
+ if (!phys_enc->hw_ctl) {
+ SDE_ERROR("invalid ctl\n");
+ return -EINVAL;
+ }
+
+ ctl = phys_enc->hw_ctl;
+ cmd_enc = to_sde_encoder_phys_cmd(phys_enc);
+ rc = sde_encoder_helper_wait_event_timeout(DRMID(phys_enc->parent),
+ ctl->idx - CTL_0,
+ &phys_enc->pending_kickoff_wq,
+ &phys_enc->pending_ctlstart_cnt,
+ CTL_START_TIMEOUT_MS);
+ if (rc <= 0) {
+ /* read and clear interrupt */
+ irq_status = sde_core_irq_read(phys_enc->sde_kms,
+ cmd_enc->irq_idx[INTR_IDX_CTL_START], true);
+ if (irq_status) {
+ unsigned long flags;
+
+ SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
+ SDE_DEBUG_CMDENC(cmd_enc,
+ "ctl:%d start done but irq not triggered\n",
+ ctl->idx - CTL_0);
+ local_irq_save(flags);
+ sde_encoder_phys_cmd_ctl_start_irq(cmd_enc,
+ INTR_IDX_CTL_START);
+ local_irq_restore(flags);
+ rc = 0;
+ } else {
+ SDE_ERROR("ctl start interrupt wait failed\n");
+ rc = -EINVAL;
+ }
+ } else {
+ rc = 0;
+ }
+
+ return rc;
+}
+
static int sde_encoder_phys_cmd_wait_for_commit_done(
struct sde_encoder_phys *phys_enc)
{
- struct sde_encoder_phys_cmd *cmd_enc =
- to_sde_encoder_phys_cmd(phys_enc);
+ int rc = 0;
+ struct sde_encoder_phys_cmd *cmd_enc;
- if (cmd_enc->serialize_wait4pp)
+ if (!phys_enc)
+ return -EINVAL;
+
+ cmd_enc = to_sde_encoder_phys_cmd(phys_enc);
+
+ /* only required for master controller */
+ if (sde_encoder_phys_cmd_is_master(phys_enc))
+ rc = _sde_encoder_phys_cmd_wait_for_ctl_start(phys_enc);
+
+ /* required for both controllers */
+ if (!rc && cmd_enc->serialize_wait4pp)
sde_encoder_phys_cmd_prepare_for_kickoff(phys_enc, NULL);
- /*
- * following statement is true serialize_wait4pp is false.
- *
- * Since ctl_start "commits" the transaction to hardware, and the
- * tearcheck block takes it from there, there is no need to have a
- * separate wait for committed, a la wait-for-vsync in video mode
- */
+ return rc;
+}
- return 0;
+static void sde_encoder_phys_cmd_update_split_role(
+ struct sde_encoder_phys *phys_enc,
+ enum sde_enc_split_role role)
+{
+ struct sde_encoder_phys_cmd *cmd_enc =
+ to_sde_encoder_phys_cmd(phys_enc);
+ enum sde_enc_split_role old_role = phys_enc->split_role;
+
+ SDE_DEBUG_CMDENC(cmd_enc, "old role %d new role %d\n",
+ old_role, role);
+
+ phys_enc->split_role = role;
+ if (role == ENC_ROLE_SKIP || role == old_role)
+ return;
+
+ sde_encoder_helper_split_config(phys_enc, phys_enc->intf_idx);
+ _sde_encoder_phys_cmd_pingpong_config(phys_enc);
+ _sde_encoder_phys_cmd_update_flush_mask(phys_enc);
}
static void sde_encoder_phys_cmd_init_ops(
@@ -723,6 +864,9 @@
ops->trigger_start = sde_encoder_helper_trigger_start;
ops->needs_single_flush = sde_encoder_phys_cmd_needs_single_flush;
ops->hw_reset = sde_encoder_helper_hw_reset;
+ ops->irq_control = sde_encoder_phys_cmd_irq_control;
+ ops->update_split_role = sde_encoder_phys_cmd_update_split_role;
+ ops->restore = sde_encoder_phys_cmd_enable_helper;
}
struct sde_encoder_phys *sde_encoder_phys_cmd_init(
@@ -750,8 +894,6 @@
goto fail_mdp_init;
}
phys_enc->hw_mdptop = hw_mdp;
-
- cmd_enc->intf_idx = p->intf_idx;
phys_enc->intf_idx = p->intf_idx;
sde_encoder_phys_cmd_init_ops(&phys_enc->ops);
@@ -768,6 +910,7 @@
INIT_LIST_HEAD(&cmd_enc->irq_cb[i].list);
atomic_set(&phys_enc->vblank_refcount, 0);
atomic_set(&phys_enc->pending_kickoff_cnt, 0);
+ atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
init_waitqueue_head(&phys_enc->pending_kickoff_wq);
SDE_DEBUG_CMDENC(cmd_enc, "created\n");
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
index df099d3..5cb84b4 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
@@ -391,10 +391,24 @@
phys_enc);
}
+static bool _sde_encoder_phys_is_ppsplit(struct sde_encoder_phys *phys_enc)
+{
+ enum sde_rm_topology_name topology;
+
+ if (!phys_enc)
+ return false;
+
+ topology = sde_connector_get_topology_name(phys_enc->connector);
+ if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
+ return true;
+
+ return false;
+}
+
static bool sde_encoder_phys_vid_needs_single_flush(
struct sde_encoder_phys *phys_enc)
{
- return phys_enc && phys_enc->split_role != ENC_ROLE_SOLO;
+ return phys_enc && _sde_encoder_phys_is_ppsplit(phys_enc);
}
static int sde_encoder_phys_vid_register_irq(struct sde_encoder_phys *phys_enc,
@@ -680,7 +694,7 @@
KICKOFF_TIMEOUT_MS);
if (ret <= 0) {
irq_status = sde_core_irq_read(phys_enc->sde_kms,
- INTR_IDX_VSYNC, true);
+ vid_enc->irq_idx[INTR_IDX_VSYNC], true);
if (irq_status) {
SDE_EVT32(DRMID(phys_enc->parent),
vid_enc->hw_intf->idx - INTF_0);
diff --git a/drivers/gpu/drm/msm/sde/sde_fence.c b/drivers/gpu/drm/msm/sde/sde_fence.c
index 46823b6..826fe14 100644
--- a/drivers/gpu/drm/msm/sde/sde_fence.c
+++ b/drivers/gpu/drm/msm/sde/sde_fence.c
@@ -16,6 +16,8 @@
#include "sde_kms.h"
#include "sde_fence.h"
+#define TIMELINE_VAL_LENGTH 128
+
void *sde_sync_get(uint64_t fd)
{
/* force signed compare, fdget accepts an int argument */
@@ -31,14 +33,31 @@
signed long sde_sync_wait(void *fnc, long timeout_ms)
{
struct fence *fence = fnc;
+ int rc;
+ char timeline_str[TIMELINE_VAL_LENGTH];
if (!fence)
return -EINVAL;
else if (fence_is_signaled(fence))
return timeout_ms ? msecs_to_jiffies(timeout_ms) : 1;
- return fence_wait_timeout(fence, true,
+ rc = fence_wait_timeout(fence, true,
msecs_to_jiffies(timeout_ms));
+ if (!rc || (rc == -EINVAL)) {
+ if (fence->ops->timeline_value_str)
+ fence->ops->timeline_value_str(fence,
+ timeline_str, TIMELINE_VAL_LENGTH);
+
+ SDE_ERROR(
+ "fence driver name:%s timeline name:%s seqno:0x%x timeline:%s signaled:0x%x\n",
+ fence->ops->get_driver_name(fence),
+ fence->ops->get_timeline_name(fence),
+ fence->seqno, timeline_str,
+ fence->ops->signaled ?
+ fence->ops->signaled(fence) : 0xffffffff);
+ }
+
+ return rc;
}
uint32_t sde_sync_get_name_prefix(void *fence)
@@ -120,10 +139,9 @@
struct sde_fence *f = to_sde_fence(fence);
struct sde_fence *fc, *next;
struct sde_fence_context *ctx = f->ctx;
- unsigned long flags;
bool release_kref = false;
- spin_lock_irqsave(&ctx->lock, flags);
+ spin_lock(&ctx->list_lock);
list_for_each_entry_safe(fc, next, &ctx->fence_list_head,
fence_list) {
/* fence release called before signal */
@@ -133,7 +151,7 @@
break;
}
}
- spin_unlock_irqrestore(&ctx->lock, flags);
+ spin_unlock(&ctx->list_lock);
/* keep kput outside spin_lock because it may release ctx */
if (release_kref)
@@ -179,7 +197,6 @@
struct sync_file *sync_file;
signed int fd = -EINVAL;
struct sde_fence_context *ctx = fence_ctx;
- unsigned long flags;
if (!ctx) {
SDE_ERROR("invalid context\n");
@@ -215,12 +232,12 @@
fd_install(fd, sync_file->file);
- spin_lock_irqsave(&ctx->lock, flags);
+ spin_lock(&ctx->list_lock);
sde_fence->ctx = fence_ctx;
sde_fence->fd = fd;
list_add_tail(&sde_fence->fence_list, &ctx->fence_list_head);
kref_get(&ctx->kref);
- spin_unlock_irqrestore(&ctx->lock, flags);
+ spin_unlock(&ctx->list_lock);
exit:
return fd;
}
@@ -241,6 +258,7 @@
ctx->context = fence_context_alloc(1);
spin_lock_init(&ctx->lock);
+ spin_lock_init(&ctx->list_lock);
INIT_LIST_HEAD(&ctx->fence_list_head);
return 0;
@@ -314,7 +332,8 @@
{
unsigned long flags;
struct sde_fence *fc, *next;
- uint32_t count = 0;
+ bool is_signaled = false;
+ struct list_head local_list_head;
if (!ctx) {
SDE_ERROR("invalid ctx, %pK\n", ctx);
@@ -323,37 +342,45 @@
return;
}
+ INIT_LIST_HEAD(&local_list_head);
+
spin_lock_irqsave(&ctx->lock, flags);
if ((int)(ctx->done_count - ctx->commit_count) < 0) {
++ctx->done_count;
+ SDE_DEBUG("fence_signal:done count:%d commit count:%d\n",
+ ctx->commit_count, ctx->done_count);
} else {
SDE_ERROR("extra signal attempt! done count:%d commit:%d\n",
ctx->done_count, ctx->commit_count);
- goto end;
+ spin_unlock_irqrestore(&ctx->lock, flags);
+ return;
}
+ spin_unlock_irqrestore(&ctx->lock, flags);
+ spin_lock(&ctx->list_lock);
if (list_empty(&ctx->fence_list_head)) {
SDE_DEBUG("nothing to trigger!-no get_prop call\n");
- goto end;
+ spin_unlock(&ctx->list_lock);
+ return;
}
- SDE_DEBUG("fence_signal:done count:%d commit count:%d\n",
- ctx->commit_count, ctx->done_count);
+ list_for_each_entry_safe(fc, next, &ctx->fence_list_head, fence_list)
+ list_move(&fc->fence_list, &local_list_head);
+ spin_unlock(&ctx->list_lock);
- list_for_each_entry_safe(fc, next, &ctx->fence_list_head,
- fence_list) {
- if (fence_is_signaled_locked(&fc->base)) {
- list_del_init(&fc->fence_list);
- count++;
+ list_for_each_entry_safe(fc, next, &local_list_head, fence_list) {
+ spin_lock_irqsave(&ctx->lock, flags);
+ is_signaled = fence_signal_locked(&fc->base);
+ spin_unlock_irqrestore(&ctx->lock, flags);
+
+ if (is_signaled) {
+ kref_put(&ctx->kref, sde_fence_destroy);
+ } else {
+ spin_lock(&ctx->list_lock);
+ list_move(&fc->fence_list, &ctx->fence_list_head);
+ spin_unlock(&ctx->list_lock);
}
}
SDE_EVT32(ctx->drm_id, ctx->done_count);
-
-end:
- spin_unlock_irqrestore(&ctx->lock, flags);
-
- /* keep this outside spin_lock because same ctx may be released */
- for (; count > 0; count--)
- kref_put(&ctx->kref, sde_fence_destroy);
}
diff --git a/drivers/gpu/drm/msm/sde/sde_fence.h b/drivers/gpu/drm/msm/sde/sde_fence.h
index f3f8b35..207f29c 100644
--- a/drivers/gpu/drm/msm/sde/sde_fence.h
+++ b/drivers/gpu/drm/msm/sde/sde_fence.h
@@ -29,7 +29,8 @@
* @done_count: Number of completed commits since bootup
* @drm_id: ID number of owning DRM Object
* @ref: kref counter on timeline
- * @lock: spinlock for timeline and fence counter protection
+ * @lock: spinlock for fence counter protection
+ * @list_lock: spinlock for timeline protection
* @context: fence context
* @list_head: fence list to hold all the fence created on this context
* @name: name of fence context/timeline
@@ -40,6 +41,7 @@
uint32_t drm_id;
struct kref kref;
spinlock_t lock;
+ spinlock_t list_lock;
u64 context;
struct list_head fence_list_head;
char name[SDE_FENCE_NAME_SIZE];
diff --git a/drivers/gpu/drm/msm/sde/sde_formats.c b/drivers/gpu/drm/msm/sde/sde_formats.c
index e7f3df7..c3477b5 100644
--- a/drivers/gpu/drm/msm/sde/sde_formats.c
+++ b/drivers/gpu/drm/msm/sde/sde_formats.c
@@ -1072,7 +1072,8 @@
DRM_ERROR("invalid handle for plane %d\n", i);
return -EINVAL;
}
- bos_total_size += bos[i]->size;
+ if ((i == 0) || (bos[i] != bos[0]))
+ bos_total_size += bos[i]->size;
}
if (bos_total_size < layout.total_size) {
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index cfa3b5e..b8ab066 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -120,6 +120,7 @@
SRC_SPLIT,
DIM_LAYER,
SMART_DMA_REV,
+ IDLE_PC,
SDE_PROP_MAX,
};
@@ -313,6 +314,7 @@
{SRC_SPLIT, "qcom,sde-has-src-split", false, PROP_TYPE_BOOL},
{DIM_LAYER, "qcom,sde-has-dim-layer", false, PROP_TYPE_BOOL},
{SMART_DMA_REV, "qcom,sde-smart-dma-rev", false, PROP_TYPE_STRING},
+ {IDLE_PC, "qcom,sde-has-idle-pc", false, PROP_TYPE_BOOL},
};
static struct sde_prop_type sde_perf_prop[] = {
@@ -2214,6 +2216,7 @@
cfg->has_src_split = PROP_VALUE_ACCESS(prop_value, SRC_SPLIT, 0);
cfg->has_dim_layer = PROP_VALUE_ACCESS(prop_value, DIM_LAYER, 0);
+ cfg->has_idle_pc = PROP_VALUE_ACCESS(prop_value, IDLE_PC, 0);
end:
kfree(prop_value);
return rc;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index 97da08f..b5f83ad 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -713,6 +713,7 @@
* @ubwc_version UBWC feature version (0x0 for not supported)
* @has_sbuf indicate if stream buffer is available
* @sbuf_headroom stream buffer headroom in lines
+ * @has_idle_pc indicate if idle power collapse feature is supported
* @dma_formats Supported formats for dma pipe
* @cursor_formats Supported formats for cursor pipe
* @vig_formats Supported formats for vig pipe
@@ -735,6 +736,7 @@
u32 ubwc_version;
bool has_sbuf;
u32 sbuf_headroom;
+ bool has_idle_pc;
u32 mdss_count;
struct sde_mdss_base_cfg mdss[MAX_BLOCKS];
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ctl.c b/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
index 82f1c09..a62aa6e 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
@@ -26,6 +26,7 @@
#define CTL_TOP 0x014
#define CTL_FLUSH 0x018
#define CTL_START 0x01C
+#define CTL_PREPARE 0x0d0
#define CTL_SW_RESET 0x030
#define CTL_LAYER_EXTN_OFFSET 0x40
#define CTL_ROT_TOP 0x0C0
@@ -78,6 +79,11 @@
SDE_REG_WRITE(&ctx->hw, CTL_START, 0x1);
}
+static inline void sde_hw_ctl_trigger_pending(struct sde_hw_ctl *ctx)
+{
+ SDE_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
+}
+
static inline void sde_hw_ctl_trigger_rot_start(struct sde_hw_ctl *ctx)
{
SDE_REG_WRITE(&ctx->hw, CTL_ROT_START, BIT(0));
@@ -537,6 +543,7 @@
ops->trigger_flush = sde_hw_ctl_trigger_flush;
ops->get_flush_register = sde_hw_ctl_get_flush_register;
ops->trigger_start = sde_hw_ctl_trigger_start;
+ ops->trigger_pending = sde_hw_ctl_trigger_pending;
ops->setup_intf_cfg = sde_hw_ctl_intf_cfg;
ops->reset = sde_hw_ctl_reset_control;
ops->wait_reset_status = sde_hw_ctl_wait_reset_status;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ctl.h b/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
index 7ae43b7..ace05e8 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ctl.h
@@ -91,6 +91,14 @@
void (*trigger_start)(struct sde_hw_ctl *ctx);
/**
+ * kickoff prepare is in progress hw operation for sw
+ * controlled interfaces: DSI cmd mode and WB interface
+ * are SW controlled
+ * @ctx : ctl path ctx pointer
+ */
+ void (*trigger_pending)(struct sde_hw_ctl *ctx);
+
+ /**
* kickoff rotator operation for Sw controlled interfaces
* DSI cmd mode and WB interface are SW controlled
* @ctx : ctl path ctx pointer
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
index f1b9c32..8df4de2 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
@@ -25,6 +25,9 @@
{
int i;
+ if (!m || !addr || !b)
+ return ERR_PTR(-EINVAL);
+
for (i = 0; i < m->dspp_count; i++) {
if (dspp == m->dspp[i].id) {
b->base_off = addr;
@@ -43,6 +46,9 @@
{
int i = 0, ret;
+ if (!c || !c->cap || !c->cap->sblk)
+ return;
+
for (i = 0; i < SDE_DSPP_MAX; i++) {
if (!test_bit(i, &features))
continue;
@@ -119,6 +125,9 @@
struct sde_hw_dspp *c;
struct sde_dspp_cfg *cfg;
+ if (!addr || !m)
+ return ERR_PTR(-EINVAL);
+
c = kzalloc(sizeof(*c), GFP_KERNEL);
if (!c)
return ERR_PTR(-ENOMEM);
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.h b/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
index 6020476..70b3e56 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
@@ -192,6 +192,7 @@
* should be called once before accessing every dspp.
* @idx: DSPP index for which driver object is required
* @addr: Mapped register io address of MDP
+ * @Return: pointer to structure or ERR_PTR
*/
struct sde_hw_dspp *sde_hw_dspp_init(enum sde_dspp idx,
void __iomem *addr,
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c
index d5289c0..24f16c6 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.c
@@ -31,9 +31,9 @@
#define MDP_INTF_4_OFF 0x6D000
#define MDP_AD4_0_OFF 0x7D000
#define MDP_AD4_1_OFF 0x7E000
-#define MDP_AD4_INTR_EN_OFF 0x41c
-#define MDP_AD4_INTR_CLEAR_OFF 0x424
-#define MDP_AD4_INTR_STATUS_OFF 0x420
+#define MDP_AD4_INTR_EN_OFF 0x41c
+#define MDP_AD4_INTR_CLEAR_OFF 0x424
+#define MDP_AD4_INTR_STATUS_OFF 0x420
/**
* WB interrupt status bit definitions
@@ -87,7 +87,7 @@
* Pingpong Secondary interrupt status bit definitions
*/
#define SDE_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0)
-#define SDE_INTR_PING_PONG_S0_WR_PTR BIT(4)
+#define SDE_INTR_PING_PONG_S0_WR_PTR BIT(4)
#define SDE_INTR_PING_PONG_S0_RD_PTR BIT(8)
#define SDE_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22)
#define SDE_INTR_PING_PONG_S0_TE_DETECTED BIT(28)
@@ -109,6 +109,15 @@
#define SDE_INTR_PING_PONG_3_TE_DETECTED BIT(27)
/**
+ * Ctl start interrupt status bit definitions
+ */
+#define SDE_INTR_CTL_0_START BIT(9)
+#define SDE_INTR_CTL_1_START BIT(10)
+#define SDE_INTR_CTL_2_START BIT(11)
+#define SDE_INTR_CTL_3_START BIT(12)
+#define SDE_INTR_CTL_4_START BIT(13)
+
+/**
* Concurrent WB overflow interrupt status bit definitions
*/
#define SDE_INTR_CWB_2_OVERFLOW BIT(14)
@@ -325,15 +334,21 @@
{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
- /* irq_idx: 40-43 */
+ /* irq_idx: 40 */
{ SDE_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,
SDE_INTR_PING_PONG_S0_RD_PTR, 1},
- { SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
- { SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
- { SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
- /* irq_idx: 44-47 */
- { SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
- { SDE_IRQ_TYPE_RESERVED, 0, 0, 1},
+ /* irq_idx: 41-45 */
+ { SDE_IRQ_TYPE_CTL_START, CTL_0,
+ SDE_INTR_CTL_0_START, 1},
+ { SDE_IRQ_TYPE_CTL_START, CTL_1,
+ SDE_INTR_CTL_1_START, 1},
+ { SDE_IRQ_TYPE_CTL_START, CTL_2,
+ SDE_INTR_CTL_2_START, 1},
+ { SDE_IRQ_TYPE_CTL_START, CTL_3,
+ SDE_INTR_CTL_3_START, 1},
+ { SDE_IRQ_TYPE_CTL_START, CTL_4,
+ SDE_INTR_CTL_4_START, 1},
+ /* irq_idx: 46-47 */
{ SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_2, SDE_INTR_CWB_2_OVERFLOW, 1},
{ SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_3, SDE_INTR_CWB_3_OVERFLOW, 1},
/* irq_idx: 48-51 */
@@ -696,6 +711,9 @@
static void sde_hw_intr_set_mask(struct sde_hw_intr *intr, uint32_t reg_off,
uint32_t mask)
{
+ if (!intr)
+ return;
+
SDE_REG_WRITE(&intr->hw, reg_off, mask);
}
@@ -710,6 +728,9 @@
u32 irq_status;
unsigned long irq_flags;
+ if (!intr)
+ return;
+
/*
* The dispatcher will save the IRQ status before calling here.
* Now need to go through each IRQ status and find matching
@@ -726,6 +747,10 @@
start_idx = reg_idx * 32;
end_idx = start_idx + 32;
+ if (start_idx >= ARRAY_SIZE(sde_irq_map) ||
+ end_idx > ARRAY_SIZE(sde_irq_map))
+ continue;
+
/*
* Search through matching intr status from irq map.
* start_idx and end_idx defined the search range in
@@ -769,6 +794,9 @@
const char *dbgstr = NULL;
uint32_t cache_irq_mask;
+ if (!intr)
+ return -EINVAL;
+
if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(sde_irq_map)) {
pr_err("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
@@ -810,6 +838,9 @@
const char *dbgstr = NULL;
uint32_t cache_irq_mask;
+ if (!intr)
+ return -EINVAL;
+
if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(sde_irq_map)) {
pr_err("invalid IRQ index: [%d]\n", irq_idx);
return -EINVAL;
@@ -846,6 +877,9 @@
{
int i;
+ if (!intr)
+ return -EINVAL;
+
for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++)
SDE_REG_WRITE(&intr->hw, sde_intr_set[i].clr_off, 0xffffffff);
@@ -856,6 +890,9 @@
{
int i;
+ if (!intr)
+ return -EINVAL;
+
for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++)
SDE_REG_WRITE(&intr->hw, sde_intr_set[i].en_off, 0x00000000);
@@ -865,15 +902,23 @@
static int sde_hw_intr_get_valid_interrupts(struct sde_hw_intr *intr,
uint32_t *mask)
{
+ if (!intr || !mask)
+ return -EINVAL;
+
*mask = IRQ_SOURCE_MDP | IRQ_SOURCE_DSI0 | IRQ_SOURCE_DSI1
| IRQ_SOURCE_HDMI | IRQ_SOURCE_EDP;
+
return 0;
}
static int sde_hw_intr_get_interrupt_sources(struct sde_hw_intr *intr,
uint32_t *sources)
{
+ if (!intr || !sources)
+ return -EINVAL;
+
*sources = SDE_REG_READ(&intr->hw, HW_INTR_STATUS);
+
return 0;
}
@@ -883,6 +928,9 @@
u32 enable_mask;
unsigned long irq_flags;
+ if (!intr)
+ return;
+
spin_lock_irqsave(&intr->status_lock, irq_flags);
for (i = 0; i < ARRAY_SIZE(sde_intr_set); i++) {
/* Read interrupt status */
@@ -909,6 +957,9 @@
int reg_idx;
unsigned long irq_flags;
+ if (!intr)
+ return;
+
spin_lock_irqsave(&intr->mask_lock, irq_flags);
reg_idx = sde_irq_map[irq_idx].reg_idx;
@@ -925,6 +976,9 @@
unsigned long irq_flags;
u32 intr_status;
+ if (!intr)
+ return 0;
+
spin_lock_irqsave(&intr->mask_lock, irq_flags);
reg_idx = sde_irq_map[irq_idx].reg_idx;
@@ -959,7 +1013,7 @@
static struct sde_mdss_base_cfg *__intr_offset(struct sde_mdss_cfg *m,
void __iomem *addr, struct sde_hw_blk_reg_map *hw)
{
- if (m->mdp_count == 0)
+ if (!m || !addr || !hw || m->mdp_count == 0)
return NULL;
hw->base_off = addr;
@@ -971,9 +1025,13 @@
struct sde_hw_intr *sde_hw_intr_init(void __iomem *addr,
struct sde_mdss_cfg *m)
{
- struct sde_hw_intr *intr = kzalloc(sizeof(*intr), GFP_KERNEL);
+ struct sde_hw_intr *intr;
struct sde_mdss_base_cfg *cfg;
+ if (!addr || !m)
+ return ERR_PTR(-EINVAL);
+
+ intr = kzalloc(sizeof(*intr), GFP_KERNEL);
if (!intr)
return ERR_PTR(-ENOMEM);
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h
index 7805df1..aaba1be 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_interrupts.h
@@ -25,7 +25,7 @@
#define IRQ_SOURCE_DSI1 BIT(5)
#define IRQ_SOURCE_HDMI BIT(8)
#define IRQ_SOURCE_EDP BIT(12)
-#define IRQ_SOURCE_MHL BIT(16)
+#define IRQ_SOURCE_MHL BIT(16)
/**
* sde_intr_type - HW Interrupt Type
@@ -55,6 +55,7 @@
* @SDE_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static
* @SDE_IRQ_TYPE_PROG_LINE: Programmable Line interrupt
* @SDE_IRQ_TYPE_AD4_BL_DONE: AD4 backlight
+ * @SDE_IRQ_TYPE_CTL_START: Control start
* @SDE_IRQ_TYPE_RESERVED: Reserved for expansion
*/
enum sde_intr_type {
@@ -84,6 +85,7 @@
SDE_IRQ_TYPE_SFI_CMD_2_OUT,
SDE_IRQ_TYPE_PROG_LINE,
SDE_IRQ_TYPE_AD4_BL_DONE,
+ SDE_IRQ_TYPE_CTL_START,
SDE_IRQ_TYPE_RESERVED,
};
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_rot.c b/drivers/gpu/drm/msm/sde/sde_hw_rot.c
index 01fe3c8..d15b804 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_rot.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_rot.c
@@ -574,9 +574,16 @@
rot_cmd.video_mode = data->video_mode;
rot_cmd.fps = data->fps;
+
+ /*
+ * DRM rotation property is specified in counter clockwise direction
+ * whereas rotator h/w rotates in clockwise direction.
+ * Convert rotation property to clockwise 90 by toggling h/v flip
+ */
rot_cmd.rot90 = data->rot90;
- rot_cmd.hflip = data->hflip;
- rot_cmd.vflip = data->vflip;
+ rot_cmd.hflip = data->rot90 ? !data->hflip : data->hflip;
+ rot_cmd.vflip = data->rot90 ? !data->vflip : data->vflip;
+
rot_cmd.secure = data->secure;
rot_cmd.clkrate = data->clkrate;
rot_cmd.data_bw = 0;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_top.c b/drivers/gpu/drm/msm/sde/sde_hw_top.c
index b20b3bc..cf54611 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_top.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_top.c
@@ -39,13 +39,15 @@
static void sde_hw_setup_split_pipe(struct sde_hw_mdp *mdp,
struct split_pipe_cfg *cfg)
{
- struct sde_hw_blk_reg_map *c = &mdp->hw;
+ struct sde_hw_blk_reg_map *c;
u32 upper_pipe = 0;
u32 lower_pipe = 0;
if (!mdp || !cfg)
return;
+ c = &mdp->hw;
+
if (cfg->en) {
if (cfg->mode == INTF_MODE_CMD) {
lower_pipe = FLD_SPLIT_DISPLAY_CMD;
@@ -107,9 +109,14 @@
static void sde_hw_setup_cdm_output(struct sde_hw_mdp *mdp,
struct cdm_output_cfg *cfg)
{
- struct sde_hw_blk_reg_map *c = &mdp->hw;
+ struct sde_hw_blk_reg_map *c;
u32 out_ctl = 0;
+ if (!mdp || !cfg)
+ return;
+
+ c = &mdp->hw;
+
if (cfg->wb_en)
out_ctl |= BIT(24);
else if (cfg->intf_en)
@@ -121,11 +128,16 @@
static bool sde_hw_setup_clk_force_ctrl(struct sde_hw_mdp *mdp,
enum sde_clk_ctrl_type clk_ctrl, bool enable)
{
- struct sde_hw_blk_reg_map *c = &mdp->hw;
+ struct sde_hw_blk_reg_map *c;
u32 reg_off, bit_off;
u32 reg_val, new_val;
bool clk_forced_on;
+ if (!mdp)
+ return false;
+
+ c = &mdp->hw;
+
if (clk_ctrl <= SDE_CLK_CTRL_NONE || clk_ctrl >= SDE_CLK_CTRL_MAX)
return false;
@@ -150,9 +162,14 @@
static void sde_hw_get_danger_status(struct sde_hw_mdp *mdp,
struct sde_danger_safe_status *status)
{
- struct sde_hw_blk_reg_map *c = &mdp->hw;
+ struct sde_hw_blk_reg_map *c;
u32 value;
+ if (!mdp || !status)
+ return;
+
+ c = &mdp->hw;
+
value = SDE_REG_READ(c, DANGER_STATUS);
status->mdp = (value >> 0) & 0x3;
status->sspp[SSPP_VIG0] = (value >> 4) & 0x3;
@@ -178,9 +195,14 @@
static void sde_hw_get_safe_status(struct sde_hw_mdp *mdp,
struct sde_danger_safe_status *status)
{
- struct sde_hw_blk_reg_map *c = &mdp->hw;
+ struct sde_hw_blk_reg_map *c;
u32 value;
+ if (!mdp || !status)
+ return;
+
+ c = &mdp->hw;
+
value = SDE_REG_READ(c, SAFE_STATUS);
status->mdp = (value >> 0) & 0x1;
status->sspp[SSPP_VIG0] = (value >> 4) & 0x1;
@@ -205,11 +227,32 @@
static void sde_hw_setup_dce(struct sde_hw_mdp *mdp, u32 dce_sel)
{
- struct sde_hw_blk_reg_map *c = &mdp->hw;
+ struct sde_hw_blk_reg_map *c;
+
+ if (!mdp)
+ return;
+
+ c = &mdp->hw;
SDE_REG_WRITE(c, DCE_SEL, dce_sel);
}
+void sde_hw_reset_ubwc(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m)
+{
+ struct sde_hw_blk_reg_map c;
+
+ if (!mdp || !m)
+ return;
+
+ if (!IS_UBWC_20_SUPPORTED(m->ubwc_version))
+ return;
+
+ /* force blk offset to zero to access beginning of register region */
+ c = mdp->hw;
+ c.blk_off = 0x0;
+ SDE_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);
+}
+
static void _setup_mdp_ops(struct sde_hw_mdp_ops *ops,
unsigned long cap)
{
@@ -220,6 +263,7 @@
ops->get_danger_status = sde_hw_get_danger_status;
ops->get_safe_status = sde_hw_get_safe_status;
ops->setup_dce = sde_hw_setup_dce;
+ ops->reset_ubwc = sde_hw_reset_ubwc;
}
static const struct sde_mdp_cfg *_top_offset(enum sde_mdp mdp,
@@ -229,6 +273,9 @@
{
int i;
+ if (!m || !addr || !b)
+ return ERR_PTR(-EINVAL);
+
for (i = 0; i < m->mdp_count; i++) {
if (mdp == m->mdp[i].id) {
b->base_off = addr;
@@ -243,25 +290,6 @@
return ERR_PTR(-EINVAL);
}
-static inline void _sde_hw_mdptop_init_ubwc(void __iomem *addr,
- const struct sde_mdss_cfg *m)
-{
- struct sde_hw_blk_reg_map hw;
-
- if (!addr || !m)
- return;
-
- if (!IS_UBWC_20_SUPPORTED(m->ubwc_version))
- return;
-
- memset(&hw, 0, sizeof(hw));
- hw.base_off = addr;
- hw.blk_off = 0x0;
- hw.hwversion = m->hwversion;
- hw.log_mask = SDE_DBG_MASK_TOP;
- SDE_REG_WRITE(&hw, UBWC_STATIC, m->mdp[0].ubwc_static);
-}
-
struct sde_hw_mdp *sde_hw_mdptop_init(enum sde_mdp idx,
void __iomem *addr,
const struct sde_mdss_cfg *m)
@@ -294,8 +322,6 @@
mdp->hw.xin_id);
sde_dbg_set_sde_top_offset(mdp->hw.blk_off);
- _sde_hw_mdptop_init_ubwc(addr, m);
-
return mdp;
}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_top.h b/drivers/gpu/drm/msm/sde/sde_hw_top.h
index 9cb0c55..7511358 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_top.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_top.h
@@ -148,6 +148,13 @@
*/
void (*get_safe_status)(struct sde_hw_mdp *mdp,
struct sde_danger_safe_status *status);
+
+ /**
+ * reset_ubwc - reset top level UBWC configuration
+ * @mdp: mdp top context driver
+ * @m: pointer to mdss catalog data
+ */
+ void (*reset_ubwc)(struct sde_hw_mdp *mdp, struct sde_mdss_cfg *m);
};
struct sde_hw_mdp {
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index 93268be..c408861 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -75,12 +75,6 @@
#define TX_MODE_BUFFER_LINE_THRES 2
-/* dirty bits for update function */
-#define SDE_PLANE_DIRTY_RECTS 0x1
-#define SDE_PLANE_DIRTY_FORMAT 0x2
-#define SDE_PLANE_DIRTY_SHARPEN 0x4
-#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
-
#define SDE_QSEED3_DEFAULT_PRELOAD_H 0x4
#define SDE_QSEED3_DEFAULT_PRELOAD_V 0x3
@@ -107,7 +101,8 @@
* @csc_ptr: Points to sde_csc_cfg structure to use for current
* @catalog: Points to sde catalog structure
* @sbuf_mode: force stream buffer mode if set
- * @sbuf_writeback: fource stream buffer writeback if set
+ * @sbuf_writeback: force stream buffer writeback if set
+ * @revalidate: force revalidation of all the plane properties
* @blob_rot_caps: Pointer to rotator capability blob
*/
struct sde_plane {
@@ -134,6 +129,7 @@
struct sde_mdss_cfg *catalog;
u32 sbuf_mode;
u32 sbuf_writeback;
+ bool revalidate;
struct sde_hw_pixel_ext pixel_ext;
bool pixel_ext_usr;
@@ -499,6 +495,17 @@
&psde->pipe_qos_cfg);
}
+void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
+{
+ struct sde_plane *psde;
+
+ if (!plane)
+ return;
+
+ psde = to_sde_plane(plane);
+ psde->revalidate = enable;
+}
+
int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
{
struct sde_plane *psde;
@@ -2250,6 +2257,14 @@
state->crtc_w, state->crtc_h,
state->crtc_x, state->crtc_y);
+ /* force reprogramming of all the parameters, if the flag is set */
+ if (psde->revalidate) {
+ SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
+ plane->base.id);
+ pstate->dirty = SDE_PLANE_DIRTY_ALL;
+ psde->revalidate = false;
+ }
+
/* determine what needs to be refreshed */
while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
switch (idx) {
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.h b/drivers/gpu/drm/msm/sde/sde_plane.h
index e955f41..ac70542 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.h
+++ b/drivers/gpu/drm/msm/sde/sde_plane.h
@@ -91,6 +91,12 @@
int out_xpos;
};
+/* dirty bits for update function */
+#define SDE_PLANE_DIRTY_RECTS 0x1
+#define SDE_PLANE_DIRTY_FORMAT 0x2
+#define SDE_PLANE_DIRTY_SHARPEN 0x4
+#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
+
/**
* struct sde_plane_state: Define sde extension of drm plane state object
* @base: base drm plane state object
@@ -222,4 +228,12 @@
int sde_plane_color_fill(struct drm_plane *plane,
uint32_t color, uint32_t alpha);
+/**
+ * sde_plane_set_revalidate - sets revalidate flag which forces a full
+ * validation of the plane properties in the next atomic check
+ * @plane: Pointer to DRM plane object
+ * @enable: Boolean to set/unset the flag
+ */
+void sde_plane_set_revalidate(struct drm_plane *plane, bool enable);
+
#endif /* _SDE_PLANE_H_ */
diff --git a/drivers/gpu/drm/msm/sde/sde_wb.c b/drivers/gpu/drm/msm/sde/sde_wb.c
index 2220925..b2665be 100644
--- a/drivers/gpu/drm/msm/sde/sde_wb.c
+++ b/drivers/gpu/drm/msm/sde/sde_wb.c
@@ -286,6 +286,27 @@
return 0;
}
+int sde_wb_get_topology(const struct drm_display_mode *drm_mode,
+ struct msm_display_topology *topology, u32 max_mixer_width)
+{
+ const u32 dual_lm = 2;
+ const u32 single_lm = 1;
+ const u32 single_intf = 1;
+ const u32 no_enc = 0;
+
+ if (!drm_mode || !topology || !max_mixer_width) {
+ pr_err("invalid params\n");
+ return -EINVAL;
+ }
+
+ topology->num_lm = (max_mixer_width <= drm_mode->hdisplay) ?
+ dual_lm : single_lm;
+ topology->num_enc = no_enc;
+ topology->num_intf = single_intf;
+
+ return 0;
+}
+
int sde_wb_connector_post_init(struct drm_connector *connector,
void *info,
void *display)
diff --git a/drivers/gpu/drm/msm/sde/sde_wb.h b/drivers/gpu/drm/msm/sde/sde_wb.h
index 4e33595..205ff24 100644
--- a/drivers/gpu/drm/msm/sde/sde_wb.h
+++ b/drivers/gpu/drm/msm/sde/sde_wb.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -31,6 +31,7 @@
* @wb_lock Serialization lock for writeback context structure
* @connector: Connector associated with writeback device
* @encoder: Encoder associated with writeback device
+ * @max_mixer_width: Max width supported by SDE LM HW block
* @count_modes: Length of writeback connector modes array
* @modes: Writeback connector modes array
*/
@@ -49,6 +50,8 @@
struct drm_encoder *encoder;
enum drm_connector_status detect_status;
+ u32 max_mixer_width;
+
u32 count_modes;
struct drm_mode_modeinfo *modes;
};
@@ -183,6 +186,17 @@
int sde_wb_get_info(struct msm_display_info *info, void *display);
/**
+ * sde_wb_get_topology - retrieve current topology for the mode selected
+ * @drm_mode: Display mode set for the display
+ * @topology: Out parameter. Topology for the mode.
+ * @max_mixer_width: max width supported by HW layer mixer
+ * Returns: zero on success
+ */
+int sde_wb_get_topology(const struct drm_display_mode *drm_mode,
+ struct msm_display_topology *topology,
+ u32 max_mixer_width);
+
+/**
* sde_wb_connector_get_wb - retrieve writeback device of the given connector
* @connector: Pointer to drm connector
* Returns: Pointer to writeback device on success; NULL otherwise
diff --git a/drivers/gpu/drm/msm/sde_power_handle.c b/drivers/gpu/drm/msm/sde_power_handle.c
index 3618479..1e4f6b1 100644
--- a/drivers/gpu/drm/msm/sde_power_handle.c
+++ b/drivers/gpu/drm/msm/sde_power_handle.c
@@ -841,7 +841,15 @@
goto data_bus_hdl_err;
}
- if (!phandle->rsc_client_init) {
+ /*
+ * - When the target is RSCC enabled, regulator should
+ * be enabled by the s/w only for the first time during
+ * bootup. After that, RSCC hardware takes care of enabling/
+ * disabling it.
+ * - When the target is not RSCC enabled, regulator should
+ * be totally handled by the software.
+ */
+ if (!phandle->rsc_client) {
rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg,
enable);
if (rc) {
@@ -883,7 +891,7 @@
sde_power_reg_bus_update(phandle->reg_bus_hdl,
max_usecase_ndx);
- if (!phandle->rsc_client_init)
+ if (!phandle->rsc_client)
msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg,
enable);
sde_power_data_bus_update(&phandle->data_bus_handle, enable);
@@ -901,7 +909,7 @@
rsc_err:
sde_power_reg_bus_update(phandle->reg_bus_hdl, prev_usecase_ndx);
reg_bus_hdl_err:
- if (!phandle->rsc_client_init)
+ if (!phandle->rsc_client)
msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0);
vreg_err:
sde_power_data_bus_update(&phandle->data_bus_handle, 0);
diff --git a/drivers/gpu/drm/msm/sde_power_handle.h b/drivers/gpu/drm/msm/sde_power_handle.h
index b26ef9f..d753f0a 100644
--- a/drivers/gpu/drm/msm/sde_power_handle.h
+++ b/drivers/gpu/drm/msm/sde_power_handle.h
@@ -16,9 +16,9 @@
#define MAX_CLIENT_NAME_LEN 128
-#define SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA 64000
+#define SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA 2000000000
#define SDE_POWER_HANDLE_DISABLE_BUS_AB_QUOTA 0
-#define SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA 64000
+#define SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA 2000000000
#define SDE_POWER_HANDLE_DISABLE_BUS_IB_QUOTA 0
#include <linux/sde_io_util.h>
diff --git a/drivers/gpu/drm/msm/sde_rsc.c b/drivers/gpu/drm/msm/sde_rsc.c
index d762904..1f770c3 100644
--- a/drivers/gpu/drm/msm/sde_rsc.c
+++ b/drivers/gpu/drm/msm/sde_rsc.c
@@ -28,16 +28,19 @@
#include <drm/drmP.h>
#include <drm/drm_irq.h>
#include "sde_rsc_priv.h"
+#include "sde_dbg.h"
-/* this time is ~0.02ms */
-#define RSC_BACKOFF_TIME_NS 20000
+/* worst case time to execute the one tcs vote(sleep/wake) - ~1ms */
+#define TCS_CASE_EXECUTION_TIME 1064000
-/* next two values should be same based on doc */
+/* this time is ~1ms - only wake tcs in any mode */
+#define RSC_BACKOFF_TIME_NS (TCS_CASE_EXECUTION_TIME + 100)
-/* this time is ~0.2ms */
-#define RSC_MODE_THRESHOLD_TIME_IN_NS 200000
-/* this time is ~0.2ms */
-#define RSC_TIME_SLOT_0_NS 200000
+/* this time is ~1ms - only wake TCS in mode-0 */
+#define RSC_MODE_THRESHOLD_TIME_IN_NS ((TCS_CASE_EXECUTION_TIME >> 1) + 100)
+
+/* this time is ~2ms - sleep+ wake TCS in mode-1 */
+#define RSC_TIME_SLOT_0_NS ((TCS_CASE_EXECUTION_TIME * 2) + 100)
#define DEFAULT_PANEL_FPS 60
#define DEFAULT_PANEL_JITTER 5
@@ -74,6 +77,7 @@
{
struct sde_rsc_client *client;
struct sde_rsc_priv *rsc;
+ static int id;
if (!client_name) {
pr_err("client name is null- not supported\n");
@@ -83,7 +87,7 @@
return ERR_PTR(-EINVAL);
} else if (!rsc_prv_list[rsc_index]) {
pr_err("rsc not probed yet or not available\n");
- return ERR_PTR(-EINVAL);
+ return NULL;
}
rsc = rsc_prv_list[rsc_index];
@@ -95,12 +99,14 @@
strlcpy(client->name, client_name, MAX_RSC_CLIENT_NAME_LEN);
client->current_state = SDE_RSC_IDLE_STATE;
client->rsc_index = rsc_index;
+ client->id = id;
if (is_primary_client)
rsc->primary_client = client;
pr_debug("client %s rsc index:%d primary:%d\n", client_name,
rsc_index, is_primary_client);
list_add(&client->list, &rsc->client_list);
+ id++;
mutex_unlock(&rsc->client_lock);
return client;
@@ -381,6 +387,8 @@
} else if (rsc->hw_ops.state_update) {
rc = rsc->hw_ops.state_update(rsc, SDE_RSC_IDLE_STATE);
+ if (!rc)
+ rpmh_mode_solver_set(rsc->disp_rsc, false);
}
return rc;
@@ -413,8 +421,11 @@
if (client->current_state == SDE_RSC_VID_STATE)
goto end;
- if (rsc->hw_ops.state_update)
+ if (rsc->hw_ops.state_update) {
rc = rsc->hw_ops.state_update(rsc, SDE_RSC_CMD_STATE);
+ if (!rc)
+ rpmh_mode_solver_set(rsc->disp_rsc, true);
+ }
/* wait for vsync for vid to cmd state switch */
if (!rc && (rsc->current_state == SDE_RSC_VID_STATE))
@@ -434,8 +445,11 @@
(client->current_state == SDE_RSC_CMD_STATE))
goto end;
- if (rsc->hw_ops.state_update)
+ if (rsc->hw_ops.state_update) {
rc = rsc->hw_ops.state_update(rsc, SDE_RSC_CLK_STATE);
+ if (!rc)
+ rpmh_mode_solver_set(rsc->disp_rsc, false);
+ }
/* wait for vsync for cmd to clk state switch */
if (!rc && rsc->primary_client &&
@@ -457,8 +471,11 @@
sde_rsc_timer_calculate(rsc, config);
/* video state switch should be done immediately */
- if (rsc->hw_ops.state_update)
+ if (rsc->hw_ops.state_update) {
rc = rsc->hw_ops.state_update(rsc, SDE_RSC_VID_STATE);
+ if (!rc)
+ rpmh_mode_solver_set(rsc->disp_rsc, false);
+ }
/* wait for vsync for cmd to vid state switch */
if (!rc && rsc->primary_client &&
@@ -502,6 +519,8 @@
return -EINVAL;
mutex_lock(&rsc->client_lock);
+ SDE_EVT32(caller_client->id, caller_client->current_state,
+ state, rsc->current_state, SDE_EVTLOG_FUNC_ENTRY);
caller_client->crtc_id = crtc_id;
caller_client->current_state = state;
@@ -559,14 +578,20 @@
if (rc == STATE_UPDATE_NOT_ALLOWED) {
rc = 0;
+ SDE_EVT32(caller_client->id, caller_client->current_state,
+ state, rsc->current_state, rc, SDE_EVTLOG_FUNC_CASE1);
goto clk_disable;
} else if (rc) {
pr_debug("state:%d update failed rc:%d\n", state, rc);
+ SDE_EVT32(caller_client->id, caller_client->current_state,
+ state, rsc->current_state, rc, SDE_EVTLOG_FUNC_CASE2);
goto clk_disable;
}
pr_debug("state switch successfully complete: %d\n", state);
rsc->current_state = state;
+ SDE_EVT32(caller_client->id, caller_client->current_state,
+ state, rsc->current_state, SDE_EVTLOG_FUNC_EXIT);
clk_disable:
if (rsc->current_state == SDE_RSC_IDLE_STATE)
@@ -1063,9 +1088,6 @@
pr_err("sde rsc:get display rsc failed ret:%d\n", ret);
goto sde_rsc_fail;
}
- rpmh_invalidate(rsc->disp_rsc);
- /* call flush to disable the disp rsc interrupt */
- rpmh_flush(rsc->disp_rsc);
ret = msm_dss_ioremap_byname(pdev, &rsc->wrapper_io, "wrapper");
if (ret) {
diff --git a/drivers/gpu/drm/msm/sde_rsc_hw.c b/drivers/gpu/drm/msm/sde_rsc_hw.c
index b63fbc6..c87dac4 100644
--- a/drivers/gpu/drm/msm/sde_rsc_hw.c
+++ b/drivers/gpu/drm/msm/sde_rsc_hw.c
@@ -95,6 +95,7 @@
#define SDE_RSCC_F1_QTMR_V1_CNTP_CTL 0x302C
#define MAX_CHECK_LOOPS 500
+#define POWER_CTRL_BIT_12 12
static void rsc_event_trigger(struct sde_rsc_priv *rsc, uint32_t event_type)
{
@@ -191,27 +192,27 @@
dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x18,
0xa138ebaa, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x1c,
- 0xe0a581e1, rsc->debug_mode);
+ 0xaca581e1, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x20,
- 0x82e2a2ed, rsc->debug_mode);
+ 0xe2a2ede0, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x24,
- 0x88ea8a39, rsc->debug_mode);
+ 0xea8a3982, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x28,
- 0xa6e9a920, rsc->debug_mode);
+ 0xa920888c, rsc->debug_mode);
/* tcs sleep sequence */
dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x2c,
- 0xa92089e6, rsc->debug_mode);
+ 0x89e6a6e9, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x30,
- 0x89e7a7e9, rsc->debug_mode);
+ 0xa7e9a920, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x34,
- 0x00000020, rsc->debug_mode);
+ 0x002079e7, rsc->debug_mode);
/* branch address */
dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_0_DRV0,
- 0x29, rsc->debug_mode);
+ 0x2b, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_1_DRV0,
- 0x2f, rsc->debug_mode);
+ 0x31, rsc->debug_mode);
return 0;
}
@@ -266,7 +267,7 @@
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM0_DRV0_MODE0,
mode_0_start_addr, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM1_DRV0_MODE0,
- 0x80000010, rsc->debug_mode);
+ 0x80000000, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM2_DRV0_MODE0,
rsc->timer_config.rsc_backoff_time_ns, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM3_DRV0_MODE0,
@@ -275,7 +276,7 @@
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM0_DRV0_MODE1,
mode_1_start_addr, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM1_DRV0_MODE1,
- 0x80000010, rsc->debug_mode);
+ 0x80000000, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM2_DRV0_MODE1,
rsc->timer_config.rsc_backoff_time_ns, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM3_DRV0_MODE1,
@@ -284,9 +285,9 @@
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM0_DRV0_MODE2,
mode_2_start_addr, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM1_DRV0_MODE2,
- 0x80000010, rsc->debug_mode);
+ 0x80000000, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM2_DRV0_MODE2,
- rsc->timer_config.rsc_backoff_time_ns, rsc->debug_mode);
+ 0x0, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_MODE_PARM3_DRV0_MODE2,
rsc->timer_config.pdc_backoff_time_ns, rsc->debug_mode);
@@ -297,6 +298,7 @@
{
int rc;
int count, wrapper_status;
+ unsigned long reg;
if (rsc->power_collapse_block)
return -EINVAL;
@@ -355,6 +357,18 @@
if (rc) {
pr_err("vdd fs is still enabled\n");
goto end;
+ } else {
+ rc = -EINVAL;
+ /* this wait is required to turn off the rscc clocks */
+ for (count = MAX_CHECK_LOOPS; count > 0; count--) {
+ reg = dss_reg_r(&rsc->wrapper_io,
+ SDE_RSCC_PWR_CTRL, rsc->debug_mode);
+ if (test_bit(POWER_CTRL_BIT_12, ®)) {
+ rc = 0;
+ break;
+ }
+ usleep_range(1, 2);
+ }
}
if ((rsc->current_state == SDE_RSC_VID_STATE) ||
@@ -458,9 +472,6 @@
0x1, rsc->debug_mode);
dss_reg_w(&rsc->drv_io, SDE_RSCC_SOLVER_OVERRIDE_CTRL_DRV0,
0x0, rsc->debug_mode);
- dss_reg_w(&rsc->drv_io,
- SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0, 0x7,
- rsc->debug_mode);
reg = dss_reg_r(&rsc->wrapper_io,
SDE_RSCC_WRAPPER_OVERRIDE_CTRL, rsc->debug_mode);
reg |= (BIT(0) | BIT(8));
@@ -484,9 +495,6 @@
reg &= ~(BIT(1) | BIT(0));
dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_OVERRIDE_CTRL,
reg, rsc->debug_mode);
- dss_reg_w(&rsc->drv_io,
- SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0, 0x5,
- rsc->debug_mode);
/* make sure that solver mode is override */
wmb();
@@ -501,9 +509,6 @@
reg &= ~(BIT(8) | BIT(0));
dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_OVERRIDE_CTRL,
reg, rsc->debug_mode);
- dss_reg_w(&rsc->drv_io,
- SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0, 0x5,
- rsc->debug_mode);
/* make sure that solver mode is disabled */
wmb();
break;
diff --git a/drivers/gpu/msm/a6xx_reg.h b/drivers/gpu/msm/a6xx_reg.h
index 69b639a..14a19a4 100644
--- a/drivers/gpu/msm/a6xx_reg.h
+++ b/drivers/gpu/msm/a6xx_reg.h
@@ -111,14 +111,6 @@
#define A6XX_VSC_ADDR_MODE_CNTL 0xC01
/* RBBM registers */
-#define A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x10
-#define A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x1f
-#define A6XX_RBBM_INT_CLEAR_CMD 0x37
-#define A6XX_RBBM_INT_0_MASK 0x38
-#define A6XX_RBBM_SW_RESET_CMD 0x43
-#define A6XX_RBBM_BLOCK_SW_RESET_CMD 0x45
-#define A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x46
-#define A6XX_RBBM_CLOCK_CNTL 0xAE
#define A6XX_RBBM_INT_0_STATUS 0x201
#define A6XX_RBBM_STATUS 0x210
#define A6XX_RBBM_STATUS3 0x213
@@ -390,6 +382,8 @@
#define A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x509
#define A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x50A
+#define A6XX_RBBM_ISDB_CNT 0x533
+
#define A6XX_RBBM_SECVID_TRUST_CNTL 0xF400
#define A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0xF800
#define A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0xF801
@@ -397,6 +391,122 @@
#define A6XX_RBBM_SECVID_TSB_CNTL 0xF803
#define A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0xF810
+#define A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00010
+#define A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0001f
+#define A6XX_RBBM_INT_CLEAR_CMD 0x00037
+#define A6XX_RBBM_INT_0_MASK 0x00038
+#define A6XX_RBBM_SP_HYST_CNT 0x00042
+#define A6XX_RBBM_SW_RESET_CMD 0x00043
+#define A6XX_RBBM_RAC_THRESHOLD_CNT 0x00044
+#define A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00045
+#define A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00046
+#define A6XX_RBBM_CLOCK_CNTL 0x000ae
+#define A6XX_RBBM_CLOCK_CNTL_SP0 0x000b0
+#define A6XX_RBBM_CLOCK_CNTL_SP1 0x000b1
+#define A6XX_RBBM_CLOCK_CNTL_SP2 0x000b2
+#define A6XX_RBBM_CLOCK_CNTL_SP3 0x000b3
+#define A6XX_RBBM_CLOCK_CNTL2_SP0 0x000b4
+#define A6XX_RBBM_CLOCK_CNTL2_SP1 0x000b5
+#define A6XX_RBBM_CLOCK_CNTL2_SP2 0x000b6
+#define A6XX_RBBM_CLOCK_CNTL2_SP3 0x000b7
+#define A6XX_RBBM_CLOCK_DELAY_SP0 0x000b8
+#define A6XX_RBBM_CLOCK_DELAY_SP1 0x000b9
+#define A6XX_RBBM_CLOCK_DELAY_SP2 0x000ba
+#define A6XX_RBBM_CLOCK_DELAY_SP3 0x000bb
+#define A6XX_RBBM_CLOCK_HYST_SP0 0x000bc
+#define A6XX_RBBM_CLOCK_HYST_SP1 0x000bd
+#define A6XX_RBBM_CLOCK_HYST_SP2 0x000be
+#define A6XX_RBBM_CLOCK_HYST_SP3 0x000bf
+#define A6XX_RBBM_CLOCK_CNTL_TP0 0x000c0
+#define A6XX_RBBM_CLOCK_CNTL_TP1 0x000c1
+#define A6XX_RBBM_CLOCK_CNTL_TP2 0x000c2
+#define A6XX_RBBM_CLOCK_CNTL_TP3 0x000c3
+#define A6XX_RBBM_CLOCK_CNTL2_TP0 0x000c4
+#define A6XX_RBBM_CLOCK_CNTL2_TP1 0x000c5
+#define A6XX_RBBM_CLOCK_CNTL2_TP2 0x000c6
+#define A6XX_RBBM_CLOCK_CNTL2_TP3 0x000c7
+#define A6XX_RBBM_CLOCK_CNTL3_TP0 0x000c8
+#define A6XX_RBBM_CLOCK_CNTL3_TP1 0x000c9
+#define A6XX_RBBM_CLOCK_CNTL3_TP2 0x000ca
+#define A6XX_RBBM_CLOCK_CNTL3_TP3 0x000cb
+#define A6XX_RBBM_CLOCK_CNTL4_TP0 0x000cc
+#define A6XX_RBBM_CLOCK_CNTL4_TP1 0x000cd
+#define A6XX_RBBM_CLOCK_CNTL4_TP2 0x000ce
+#define A6XX_RBBM_CLOCK_CNTL4_TP3 0x000cf
+#define A6XX_RBBM_CLOCK_DELAY_TP0 0x000d0
+#define A6XX_RBBM_CLOCK_DELAY_TP1 0x000d1
+#define A6XX_RBBM_CLOCK_DELAY_TP2 0x000d2
+#define A6XX_RBBM_CLOCK_DELAY_TP3 0x000d3
+#define A6XX_RBBM_CLOCK_DELAY2_TP0 0x000d4
+#define A6XX_RBBM_CLOCK_DELAY2_TP1 0x000d5
+#define A6XX_RBBM_CLOCK_DELAY2_TP2 0x000d6
+#define A6XX_RBBM_CLOCK_DELAY2_TP3 0x000d7
+#define A6XX_RBBM_CLOCK_DELAY3_TP0 0x000d8
+#define A6XX_RBBM_CLOCK_DELAY3_TP1 0x000d9
+#define A6XX_RBBM_CLOCK_DELAY3_TP2 0x000da
+#define A6XX_RBBM_CLOCK_DELAY3_TP3 0x000db
+#define A6XX_RBBM_CLOCK_DELAY4_TP0 0x000dc
+#define A6XX_RBBM_CLOCK_DELAY4_TP1 0x000dd
+#define A6XX_RBBM_CLOCK_DELAY4_TP2 0x000de
+#define A6XX_RBBM_CLOCK_DELAY4_TP3 0x000df
+#define A6XX_RBBM_CLOCK_HYST_TP0 0x000e0
+#define A6XX_RBBM_CLOCK_HYST_TP1 0x000e1
+#define A6XX_RBBM_CLOCK_HYST_TP2 0x000e2
+#define A6XX_RBBM_CLOCK_HYST_TP3 0x000e3
+#define A6XX_RBBM_CLOCK_HYST2_TP0 0x000e4
+#define A6XX_RBBM_CLOCK_HYST2_TP1 0x000e5
+#define A6XX_RBBM_CLOCK_HYST2_TP2 0x000e6
+#define A6XX_RBBM_CLOCK_HYST2_TP3 0x000e7
+#define A6XX_RBBM_CLOCK_HYST3_TP0 0x000e8
+#define A6XX_RBBM_CLOCK_HYST3_TP1 0x000e9
+#define A6XX_RBBM_CLOCK_HYST3_TP2 0x000ea
+#define A6XX_RBBM_CLOCK_HYST3_TP3 0x000eb
+#define A6XX_RBBM_CLOCK_HYST4_TP0 0x000ec
+#define A6XX_RBBM_CLOCK_HYST4_TP1 0x000ed
+#define A6XX_RBBM_CLOCK_HYST4_TP2 0x000ee
+#define A6XX_RBBM_CLOCK_HYST4_TP3 0x000ef
+#define A6XX_RBBM_CLOCK_CNTL_RB0 0x000f0
+#define A6XX_RBBM_CLOCK_CNTL_RB1 0x000f1
+#define A6XX_RBBM_CLOCK_CNTL_RB2 0x000f2
+#define A6XX_RBBM_CLOCK_CNTL_RB3 0x000f3
+#define A6XX_RBBM_CLOCK_CNTL2_RB0 0x000f4
+#define A6XX_RBBM_CLOCK_CNTL2_RB1 0x000f5
+#define A6XX_RBBM_CLOCK_CNTL2_RB2 0x000f6
+#define A6XX_RBBM_CLOCK_CNTL2_RB3 0x000f7
+#define A6XX_RBBM_CLOCK_CNTL_CCU0 0x000f8
+#define A6XX_RBBM_CLOCK_CNTL_CCU1 0x000f9
+#define A6XX_RBBM_CLOCK_CNTL_CCU2 0x000fa
+#define A6XX_RBBM_CLOCK_CNTL_CCU3 0x000fb
+#define A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00100
+#define A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00101
+#define A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00102
+#define A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00103
+#define A6XX_RBBM_CLOCK_CNTL_RAC 0x00104
+#define A6XX_RBBM_CLOCK_CNTL2_RAC 0x00105
+#define A6XX_RBBM_CLOCK_DELAY_RAC 0x00106
+#define A6XX_RBBM_CLOCK_HYST_RAC 0x00107
+#define A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00108
+#define A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00109
+#define A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0010a
+#define A6XX_RBBM_CLOCK_CNTL_UCHE 0x0010b
+#define A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0010c
+#define A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0010d
+#define A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0010e
+#define A6XX_RBBM_CLOCK_DELAY_UCHE 0x0010f
+#define A6XX_RBBM_CLOCK_HYST_UCHE 0x00110
+#define A6XX_RBBM_CLOCK_MODE_VFD 0x00111
+#define A6XX_RBBM_CLOCK_DELAY_VFD 0x00112
+#define A6XX_RBBM_CLOCK_HYST_VFD 0x00113
+#define A6XX_RBBM_CLOCK_MODE_GPC 0x00114
+#define A6XX_RBBM_CLOCK_DELAY_GPC 0x00115
+#define A6XX_RBBM_CLOCK_HYST_GPC 0x00116
+#define A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00117
+#define A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00118
+#define A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00119
+#define A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0011a
+#define A6XX_RBBM_CLOCK_MODE_HLSQ 0x0011b
+#define A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0011c
+
/* DBGC_CFG registers */
#define A6XX_DBGC_CFG_DBGBUS_SEL_A 0x600
#define A6XX_DBGC_CFG_DBGBUS_SEL_B 0x601
@@ -666,6 +776,7 @@
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT 0x8
/* GMU control registers */
+#define A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x1A880
#define A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x1A881
#define A6XX_GMU_CM3_ITCM_START 0x1B400
#define A6XX_GMU_CM3_DTCM_START 0x1C400
@@ -722,6 +833,9 @@
#define A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x23B04
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x23B05
#define A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x23B06
+#define A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x23B09
+#define A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x23B0A
+#define A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x23B0B
#define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x23B0C
#define A6XX_GMU_AHB_FENCE_STATUS 0x23B13
#define A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x23B15
diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h
index 876ff0c..9a44f34 100644
--- a/drivers/gpu/msm/adreno-gpulist.h
+++ b/drivers/gpu/msm/adreno-gpulist.h
@@ -326,8 +326,7 @@
.major = 3,
.minor = 0,
.patchid = ANY_ID,
- .features = ADRENO_64BIT |
- ADRENO_GPMU | ADRENO_RPMH,
+ .features = ADRENO_64BIT | ADRENO_RPMH,
.sqefw_name = "a630_sqe.fw",
.zap_name = "a630_zap",
.gpudev = &adreno_a6xx_gpudev,
diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c
index 3c3f99f..585beb9 100644
--- a/drivers/gpu/msm/adreno_a6xx.c
+++ b/drivers/gpu/msm/adreno_a6xx.c
@@ -59,6 +59,127 @@
{ adreno_is_a630, a630_vbif },
};
+
+struct kgsl_hwcg_reg {
+ unsigned int off;
+ unsigned int val;
+};
+static const struct kgsl_hwcg_reg a630_hwcg_regs[] = {
+ {A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},
+ {A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220},
+ {A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220},
+ {A6XX_RBBM_CLOCK_DELAY_SP0, 0x0000F3CF},
+ {A6XX_RBBM_CLOCK_DELAY_SP1, 0x0000F3CF},
+ {A6XX_RBBM_CLOCK_DELAY_SP2, 0x0000F3CF},
+ {A6XX_RBBM_CLOCK_DELAY_SP3, 0x0000F3CF},
+ {A6XX_RBBM_CLOCK_HYST_SP0, 0x00000080},
+ {A6XX_RBBM_CLOCK_HYST_SP1, 0x00000080},
+ {A6XX_RBBM_CLOCK_HYST_SP2, 0x00000080},
+ {A6XX_RBBM_CLOCK_HYST_SP3, 0x00000080},
+ {A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_TP2, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_TP3, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
+ {A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
+ {A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
+ {A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
+ {A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
+ {A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
+ {A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
+ {A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
+ {A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
+ {A6XX_RBBM_CLOCK_HYST3_TP0, 0x07777777},
+ {A6XX_RBBM_CLOCK_HYST3_TP1, 0x07777777},
+ {A6XX_RBBM_CLOCK_HYST3_TP2, 0x07777777},
+ {A6XX_RBBM_CLOCK_HYST3_TP3, 0x07777777},
+ {A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
+ {A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
+ {A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
+ {A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
+ {A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
+ {A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
+ {A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
+ {A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
+ {A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
+ {A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
+ {A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
+ {A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
+ {A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
+ {A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
+ {A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
+ {A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+ {A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
+ {A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
+ {A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
+ {A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
+ {A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {A6XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
+ {A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
+ {A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}
+};
+
+static const struct {
+ int (*devfunc)(struct adreno_device *adreno_dev);
+ const struct kgsl_hwcg_reg *regs;
+ unsigned int count;
+} a6xx_hwcg_registers[] = {
+ {adreno_is_a630, a630_hwcg_regs, ARRAY_SIZE(a630_hwcg_regs)}
+};
+
static struct a6xx_protected_regs {
unsigned int base;
unsigned int count;
@@ -103,9 +224,27 @@
adreno_dev->sp_pvt_gpuaddr = addr + SZ_64K;
}
+static void _update_always_on_regs(struct adreno_device *adreno_dev)
+{
+ struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
+ unsigned int *const regs = gpudev->reg_offsets->offsets;
+
+ regs[ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO] =
+ A6XX_CP_ALWAYS_ON_COUNTER_LO;
+ regs[ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI] =
+ A6XX_CP_ALWAYS_ON_COUNTER_HI;
+}
+
static void a6xx_init(struct adreno_device *adreno_dev)
{
a6xx_crashdump_init(adreno_dev);
+
+ /*
+ * If the GMU is not enabled, rewrite the offset for the always on
+ * counters to point to the CP always on instead of GMU always on
+ */
+ if (!kgsl_gmu_isenabled(KGSL_DEVICE(adreno_dev)))
+ _update_always_on_regs(adreno_dev);
}
/**
@@ -125,7 +264,7 @@
unsigned int mmu_base = 0, mmu_range = 0, cur_range;
/* enable access protection to privileged registers */
- kgsl_regwrite(device, A6XX_CP_PROTECT_CNTL, 0x00000007);
+ kgsl_regwrite(device, A6XX_CP_PROTECT_CNTL, 0x00000003);
if (mmu_prot) {
mmu_base = mmu_prot->base;
@@ -181,6 +320,48 @@
kgsl_regwrite(device, A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
}
+
+static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+ const struct kgsl_hwcg_reg *regs;
+ int i, j;
+
+ if (!test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag))
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(a6xx_hwcg_registers); i++) {
+ if (a6xx_hwcg_registers[i].devfunc(adreno_dev))
+ break;
+ }
+
+ if (i == ARRAY_SIZE(a6xx_hwcg_registers))
+ return;
+
+ regs = a6xx_hwcg_registers[i].regs;
+
+ /* Disable SP clock before programming HWCG registers */
+ kgsl_gmu_regrmw(device, A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 0);
+
+ for (j = 0; j < a6xx_hwcg_registers[i].count; j++)
+ kgsl_regwrite(device, regs[j].off, on ? regs[j].val : 0);
+
+ if (kgsl_gmu_isenabled(device)) {
+ kgsl_gmu_regwrite(device, A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
+ 0x00020222);
+ kgsl_gmu_regwrite(device, A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
+ 0x00010111);
+ kgsl_gmu_regwrite(device, A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
+ 0x00050555);
+ }
+ /* Enable SP clock */
+ kgsl_gmu_regrmw(device, A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
+
+ /* enable top level HWCG */
+ kgsl_regwrite(device, A6XX_RBBM_CLOCK_CNTL, on ? 0x8AA8AA02 : 0);
+ kgsl_regwrite(device, A5XX_RBBM_ISDB_CNT, on ? 0x00000182 : 0x00000180);
+}
+
/*
* a6xx_start() - Device start
* @adreno_dev: Pointer to adreno device
@@ -197,6 +378,8 @@
if (!kgsl_gmu_isenabled(device))
/* Legacy idle management if gmu is disabled */
ADRENO_GPU_DEVICE(adreno_dev)->hw_isidle = NULL;
+ /* enable hardware clockgating */
+ a6xx_hwcg_set(adreno_dev, true);
adreno_vbif_start(adreno_dev, a6xx_vbif_platforms,
ARRAY_SIZE(a6xx_vbif_platforms));
@@ -235,6 +418,9 @@
/* Set the AHB default slave response to "ERROR" */
kgsl_regwrite(device, A6XX_CP_AHB_CNTL, 0x1);
+ /* Turn on performance counters */
+ kgsl_regwrite(device, A6XX_RBBM_PERFCTR_CNTL, 0x1);
+
if (of_property_read_u32(device->pdev->dev.of_node,
"qcom,highest-bank-bit", &bit))
bit = MIN_HBB;
@@ -282,8 +468,9 @@
kgsl_regwrite(device, A6XX_UCHE_MODE_CNTL, (glbl_inv << 29) |
(mal << 23) | (bit << 21));
+ /* Set hang detection threshold to 4 million cycles (0x3FFFF*16) */
kgsl_regwrite(device, A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
- (1 << 30) | 0x4000);
+ (1 << 30) | 0x3ffff);
kgsl_regwrite(device, A6XX_UCHE_CLIENT_PF, 1);
@@ -1553,7 +1740,10 @@
else if (client_id != 3)
return fault_block[client_id];
+ mutex_lock(&device->mutex);
kgsl_regread(device, A6XX_UCHE_CLIENT_PF, &uche_client_id);
+ mutex_unlock(&device->mutex);
+
return uche_client[uche_client_id & A6XX_UCHE_CLIENT_PF_CLIENT_ID_MASK];
}
@@ -2033,10 +2223,6 @@
A6XX_RBBM_PERFCTR_LOAD_VALUE_LO),
ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,
A6XX_RBBM_PERFCTR_LOAD_VALUE_HI),
- ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO,
- A6XX_CP_ALWAYS_ON_COUNTER_LO),
- ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI,
- A6XX_CP_ALWAYS_ON_COUNTER_HI),
ADRENO_REG_DEFINE(ADRENO_REG_VBIF_VERSION, A6XX_VBIF_VERSION),
ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO,
A6XX_GMU_ALWAYS_ON_COUNTER_L),
diff --git a/drivers/gpu/msm/adreno_a6xx_snapshot.c b/drivers/gpu/msm/adreno_a6xx_snapshot.c
index ba83cd7..01ecb01 100644
--- a/drivers/gpu/msm/adreno_a6xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a6xx_snapshot.c
@@ -121,6 +121,8 @@
unsigned int statetype;
const unsigned int *regs;
unsigned int num_sets;
+ unsigned int offset0;
+ unsigned int offset1;
} a6xx_dbgahb_ctx_clusters[] = {
{ CP_CLUSTER_SP_VS, 0x0002E000, 0x41, a6xx_sp_vs_hlsq_cluster,
ARRAY_SIZE(a6xx_sp_vs_hlsq_cluster) / 2 },
@@ -624,8 +626,8 @@
return val;
}
-static size_t a6xx_snapshot_cluster_dbgahb(struct kgsl_device *device, u8 *buf,
- size_t remain, void *priv)
+static size_t a6xx_legacy_snapshot_cluster_dbgahb(struct kgsl_device *device,
+ u8 *buf, size_t remain, void *priv)
{
struct kgsl_snapshot_mvc_regs *header =
(struct kgsl_snapshot_mvc_regs *)buf;
@@ -678,6 +680,63 @@
return data_size + sizeof(*header);
}
+static size_t a6xx_snapshot_cluster_dbgahb(struct kgsl_device *device, u8 *buf,
+ size_t remain, void *priv)
+{
+ struct kgsl_snapshot_mvc_regs *header =
+ (struct kgsl_snapshot_mvc_regs *)buf;
+ struct a6xx_cluster_dbgahb_regs_info *info =
+ (struct a6xx_cluster_dbgahb_regs_info *)priv;
+ struct a6xx_cluster_dbgahb_registers *cluster = info->cluster;
+ unsigned int data_size = 0;
+ unsigned int *data = (unsigned int *)(buf + sizeof(*header));
+ int i, j;
+ unsigned int *src;
+
+
+ if (crash_dump_valid == false)
+ return a6xx_legacy_snapshot_cluster_dbgahb(device, buf, remain,
+ info);
+
+ if (remain < sizeof(*header)) {
+ SNAPSHOT_ERR_NOMEM(device, "REGISTERS");
+ return 0;
+ }
+
+ remain -= sizeof(*header);
+
+ header->ctxt_id = info->ctxt_id;
+ header->cluster_id = cluster->id;
+
+ src = (unsigned int *)(a6xx_crashdump_registers.hostptr +
+ (header->ctxt_id ? cluster->offset1 : cluster->offset0));
+
+ for (i = 0; i < cluster->num_sets; i++) {
+ unsigned int start;
+ unsigned int end;
+
+ start = cluster->regs[2 * i];
+ end = cluster->regs[2 * i + 1];
+
+ if (remain < (end - start + 3) * 4) {
+ SNAPSHOT_ERR_NOMEM(device, "MVC REGISTERS");
+ goto out;
+ }
+
+ remain -= (end - start + 3) * 4;
+ data_size += (end - start + 3) * 4;
+
+ *data++ = start | (1 << 31);
+ *data++ = end;
+ for (j = start; j <= end; j++)
+ *data++ = *src++;
+ }
+out:
+ return data_size + sizeof(*header);
+}
+
+
+
static size_t a6xx_snapshot_non_ctx_dbgahb(struct kgsl_device *device, u8 *buf,
size_t remain, void *priv)
{
@@ -1391,6 +1450,47 @@
return qwords;
}
+static int _a6xx_crashdump_init_ctx_dbgahb(uint64_t *ptr, uint64_t *offset)
+{
+ int qwords = 0;
+ unsigned int i, j, k;
+ unsigned int count;
+
+ for (i = 0; i < ARRAY_SIZE(a6xx_dbgahb_ctx_clusters); i++) {
+ struct a6xx_cluster_dbgahb_registers *cluster =
+ &a6xx_dbgahb_ctx_clusters[i];
+
+ cluster->offset0 = *offset;
+
+ for (j = 0; j < A6XX_NUM_CTXTS; j++) {
+ if (j == 1)
+ cluster->offset1 = *offset;
+
+ /* Program the aperture */
+ ptr[qwords++] =
+ ((cluster->statetype + j * 2) & 0xff) << 8;
+ ptr[qwords++] =
+ (((uint64_t)A6XX_HLSQ_DBG_READ_SEL << 44)) |
+ (1 << 21) | 1;
+
+ for (k = 0; k < cluster->num_sets; k++) {
+ unsigned int start = cluster->regs[2 * k];
+
+ count = REG_PAIR_COUNT(cluster->regs, k);
+ ptr[qwords++] =
+ a6xx_crashdump_registers.gpuaddr + *offset;
+ ptr[qwords++] =
+ (((uint64_t)(A6XX_HLSQ_DBG_AHB_READ_APERTURE +
+ start - cluster->regbase / 4) << 44)) |
+ count;
+
+ *offset += count * sizeof(unsigned int);
+ }
+ }
+ }
+ return qwords;
+}
+
void a6xx_crashdump_init(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -1458,6 +1558,26 @@
}
}
+ /* Calculate the script and data size for debug AHB registers */
+ for (i = 0; i < ARRAY_SIZE(a6xx_dbgahb_ctx_clusters); i++) {
+ struct a6xx_cluster_dbgahb_registers *cluster =
+ &a6xx_dbgahb_ctx_clusters[i];
+
+ for (j = 0; j < A6XX_NUM_CTXTS; j++) {
+
+ /* 16 bytes for programming the aperture */
+ script_size += 16;
+
+ /* Reading each pair of registers takes 16 bytes */
+ script_size += 16 * cluster->num_sets;
+
+ /* A dword per register read from the cluster list */
+ for (k = 0; k < cluster->num_sets; k++)
+ data_size += REG_PAIR_COUNT(cluster->regs, k) *
+ sizeof(unsigned int);
+ }
+ }
+
/* Now allocate the script and data buffers */
/* The script buffers needs 2 extra qwords on the end */
@@ -1497,6 +1617,8 @@
/* Program the capturescript for the MVC regsiters */
ptr += _a6xx_crashdump_init_mvc(ptr, &offset);
+ ptr += _a6xx_crashdump_init_ctx_dbgahb(ptr, &offset);
+
*ptr++ = 0;
*ptr++ = 0;
}
diff --git a/drivers/gpu/msm/adreno_dispatch.c b/drivers/gpu/msm/adreno_dispatch.c
index ed5b714..1cb0259 100644
--- a/drivers/gpu/msm/adreno_dispatch.c
+++ b/drivers/gpu/msm/adreno_dispatch.c
@@ -1045,6 +1045,13 @@
*/
if (drawctxt->base.flags & KGSL_CONTEXT_NO_FAULT_TOLERANCE)
set_bit(KGSL_FT_DISABLE, &cmdobj->fault_policy);
+ /*
+ * Set the fault tolerance policy to FT_REPLAY - As context wants
+ * to invalidate it after a replay attempt fails. This doesn't
+ * require to execute the default FT policy.
+ */
+ else if (drawctxt->base.flags & KGSL_CONTEXT_INVALIDATE_ON_FAULT)
+ set_bit(KGSL_FT_REPLAY, &cmdobj->fault_policy);
else
cmdobj->fault_policy = adreno_dev->ft_policy;
}
diff --git a/drivers/gpu/msm/adreno_drawctxt.c b/drivers/gpu/msm/adreno_drawctxt.c
index f77d438..f217822 100644
--- a/drivers/gpu/msm/adreno_drawctxt.c
+++ b/drivers/gpu/msm/adreno_drawctxt.c
@@ -342,13 +342,14 @@
struct kgsl_device *device = dev_priv->device;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
int ret;
- unsigned long local;
+ unsigned int local;
local = *flags & (KGSL_CONTEXT_PREAMBLE |
KGSL_CONTEXT_NO_GMEM_ALLOC |
KGSL_CONTEXT_PER_CONTEXT_TS |
KGSL_CONTEXT_USER_GENERATED_TS |
KGSL_CONTEXT_NO_FAULT_TOLERANCE |
+ KGSL_CONTEXT_INVALIDATE_ON_FAULT |
KGSL_CONTEXT_CTX_SWITCH |
KGSL_CONTEXT_PRIORITY_MASK |
KGSL_CONTEXT_TYPE_MASK |
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 32175f5..fbff535 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -54,10 +54,21 @@
/* Read always on registers */
if (!adreno_is_a3xx(adreno_dev)) {
- adreno_readreg64(adreno_dev,
- ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO,
- ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI,
- &time->ticks);
+ if (kgsl_gmu_isenabled(KGSL_DEVICE(adreno_dev))) {
+ uint32_t val_lo, val_hi;
+
+ adreno_read_gmureg(adreno_dev,
+ ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO, &val_lo);
+ adreno_read_gmureg(adreno_dev,
+ ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI, &val_hi);
+
+ time->ticks = (val_lo | ((uint64_t)val_hi << 32));
+ } else {
+ adreno_readreg64(adreno_dev,
+ ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO,
+ ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI,
+ &time->ticks);
+ }
/* Mask hi bits as they may be incorrect on some targets */
if (ADRENO_GPUREV(adreno_dev) >= 400 &&
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 15f68bf..d836cbb 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -43,6 +43,7 @@
#include "kgsl_sync.h"
#include "kgsl_compat.h"
#include "kgsl_pool.h"
+#include "adreno.h"
#undef MODULE_PARAM_PREFIX
#define MODULE_PARAM_PREFIX "kgsl."
@@ -1045,7 +1046,10 @@
int result = 0;
mutex_lock(&device->mutex);
- device->open_count--;
+
+ if (!adreno_is_a6xx(ADRENO_DEVICE(device)))
+ device->open_count--;
+
if (device->open_count == 0) {
/* Wait for the active count to go to 0 */
@@ -1627,7 +1631,8 @@
/* If no profiling buffer was specified, clear the flag */
if (cmdobj->profiling_buf_entry == NULL)
- DRAWOBJ(cmdobj)->flags &= ~KGSL_DRAWOBJ_PROFILING;
+ DRAWOBJ(cmdobj)->flags &=
+ ~(unsigned long)KGSL_DRAWOBJ_PROFILING;
}
result = device->ftbl->queue_cmds(dev_priv, context, drawobj,
@@ -1716,7 +1721,8 @@
/* If no profiling buffer was specified, clear the flag */
if (cmdobj->profiling_buf_entry == NULL)
- DRAWOBJ(cmdobj)->flags &= ~KGSL_DRAWOBJ_PROFILING;
+ DRAWOBJ(cmdobj)->flags &=
+ ~(unsigned long)KGSL_DRAWOBJ_PROFILING;
}
result = device->ftbl->queue_cmds(dev_priv, context, drawobj,
@@ -2041,7 +2047,7 @@
unsigned long flags_requested = (VM_READ | VM_WRITE);
if (flags & KGSL_MEMFLAGS_GPUREADONLY)
- flags_requested &= ~VM_WRITE;
+ flags_requested &= ~(unsigned long)VM_WRITE;
if ((vma->vm_flags & flags_requested) == flags_requested)
return 0;
@@ -2135,7 +2141,7 @@
entry->memdesc.pagetable = pagetable;
entry->memdesc.size = (uint64_t) size;
entry->memdesc.useraddr = hostptr;
- entry->memdesc.flags |= KGSL_MEMFLAGS_USERMEM_ADDR;
+ entry->memdesc.flags |= (uint64_t)KGSL_MEMFLAGS_USERMEM_ADDR;
if (kgsl_memdesc_use_cpu_map(&entry->memdesc)) {
int ret;
@@ -2166,7 +2172,7 @@
static void _setup_cache_mode(struct kgsl_mem_entry *entry,
struct vm_area_struct *vma)
{
- unsigned int mode;
+ uint64_t mode;
pgprot_t pgprot = vma->vm_page_prot;
if (pgprot_val(pgprot) == pgprot_val(pgprot_noncached(pgprot)))
@@ -2525,7 +2531,7 @@
entry->memdesc.size = 0;
/* USE_CPU_MAP is not impemented for ION. */
entry->memdesc.flags &= ~((uint64_t) KGSL_MEMFLAGS_USE_CPU_MAP);
- entry->memdesc.flags |= KGSL_MEMFLAGS_USERMEM_ION;
+ entry->memdesc.flags |= (uint64_t)KGSL_MEMFLAGS_USERMEM_ION;
sg_table = dma_buf_map_attachment(attach, DMA_TO_DEVICE);
@@ -3028,8 +3034,9 @@
if ((flags & KGSL_CACHEMODE_MASK) >> KGSL_CACHEMODE_SHIFT ==
KGSL_CACHEMODE_WRITETHROUGH) {
flags &= ~((uint64_t) KGSL_CACHEMODE_MASK);
- flags |= (KGSL_CACHEMODE_WRITEBACK << KGSL_CACHEMODE_SHIFT) &
- KGSL_CACHEMODE_MASK;
+ flags |= (uint64_t)((KGSL_CACHEMODE_WRITEBACK <<
+ KGSL_CACHEMODE_SHIFT) &
+ KGSL_CACHEMODE_MASK);
}
return flags;
}
@@ -3083,8 +3090,9 @@
KGSL_MAX_ALIGN >> 10);
flags &= ~((uint64_t) KGSL_MEMALIGN_MASK);
- flags |= (ilog2(KGSL_MAX_ALIGN) << KGSL_MEMALIGN_SHIFT) &
- KGSL_MEMALIGN_MASK;
+ flags |= (uint64_t)((ilog2(KGSL_MAX_ALIGN) <<
+ KGSL_MEMALIGN_SHIFT) &
+ KGSL_MEMALIGN_MASK);
}
/* For now only allow allocations up to 4G */
@@ -3975,7 +3983,8 @@
if (param->flags & KGSL_GPUOBJ_SET_INFO_TYPE) {
entry->memdesc.flags &= ~((uint64_t) KGSL_MEMTYPE_MASK);
- entry->memdesc.flags |= param->type << KGSL_MEMTYPE_SHIFT;
+ entry->memdesc.flags |= (uint64_t)(param->type <<
+ KGSL_MEMTYPE_SHIFT);
}
kgsl_mem_entry_put(entry);
diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h
index d955aa0..db105c5 100644
--- a/drivers/gpu/msm/kgsl_device.h
+++ b/drivers/gpu/msm/kgsl_device.h
@@ -80,6 +80,7 @@
{ KGSL_CONTEXT_PER_CONTEXT_TS, "PER_CONTEXT_TS" }, \
{ KGSL_CONTEXT_USER_GENERATED_TS, "USER_TS" }, \
{ KGSL_CONTEXT_NO_FAULT_TOLERANCE, "NO_FT" }, \
+ { KGSL_CONTEXT_INVALIDATE_ON_FAULT, "INVALIDATE_ON_FAULT" }, \
{ KGSL_CONTEXT_PWR_CONSTRAINT, "PWR" }, \
{ KGSL_CONTEXT_SAVE_GMEM, "SAVE_GMEM" }
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index 86d4d61..938c96d 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -1608,6 +1608,8 @@
ret = PTR_ERR(mmu->defaultpagetable);
mmu->defaultpagetable = NULL;
return ret;
+ } else if (mmu->defaultpagetable == NULL) {
+ return -ENOMEM;
}
}
@@ -2598,7 +2600,7 @@
static const struct {
char *feature;
- int bit;
+ unsigned long bit;
} kgsl_iommu_features[] = {
{ "qcom,retention", KGSL_MMU_RETENTION },
{ "qcom,global_pt", KGSL_MMU_GLOBAL_PAGETABLE },
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index b3e2b6a..a9a3c94 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -67,7 +67,9 @@
"isense_clk",
"rbcpr_clk",
"iref_clk",
- "gmu_clk"
+ "gmu_clk",
+ "ahb_clk",
+ "cxo_clk"
};
static unsigned int ib_votes[KGSL_MAX_BUSLEVELS];
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h
index 62ee597..6b22fd4 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.h
+++ b/drivers/gpu/msm/kgsl_pwrctrl.h
@@ -25,7 +25,7 @@
#define KGSL_PWR_ON 0xFFFF
-#define KGSL_MAX_CLKS 15
+#define KGSL_MAX_CLKS 17
#define KGSL_MAX_REGULATORS 2
#define KGSL_MAX_PWRLEVELS 10
diff --git a/drivers/gpu/msm/kgsl_pwrscale.c b/drivers/gpu/msm/kgsl_pwrscale.c
index 07a54d9..7636a42 100644
--- a/drivers/gpu/msm/kgsl_pwrscale.c
+++ b/drivers/gpu/msm/kgsl_pwrscale.c
@@ -927,8 +927,7 @@
&data->bin.ctxt_aware_target_pwrlevel))
data->bin.ctxt_aware_target_pwrlevel = 1;
- if ((data->bin.ctxt_aware_target_pwrlevel < 0) ||
- (data->bin.ctxt_aware_target_pwrlevel >
+ if ((data->bin.ctxt_aware_target_pwrlevel >
pwr->num_pwrlevels))
data->bin.ctxt_aware_target_pwrlevel = 1;
diff --git a/drivers/gpu/msm/kgsl_sharedmem.h b/drivers/gpu/msm/kgsl_sharedmem.h
index 10b37ae..dd41e4e 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.h
+++ b/drivers/gpu/msm/kgsl_sharedmem.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2002,2007-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2002,2007-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -131,8 +131,9 @@
if (align > 32)
align = 32;
- memdesc->flags &= ~KGSL_MEMALIGN_MASK;
- memdesc->flags |= (align << KGSL_MEMALIGN_SHIFT) & KGSL_MEMALIGN_MASK;
+ memdesc->flags &= ~(uint64_t)KGSL_MEMALIGN_MASK;
+ memdesc->flags |= (uint64_t)((align << KGSL_MEMALIGN_SHIFT) &
+ KGSL_MEMALIGN_MASK);
return 0;
}
diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c
index 4314616..b99c1df 100644
--- a/drivers/hwmon/it87.c
+++ b/drivers/hwmon/it87.c
@@ -3115,7 +3115,7 @@
{
int sioaddr[2] = { REG_2E, REG_4E };
struct it87_sio_data sio_data;
- unsigned short isa_address;
+ unsigned short isa_address[2];
bool found = false;
int i, err;
@@ -3125,15 +3125,29 @@
for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
memset(&sio_data, 0, sizeof(struct it87_sio_data));
- isa_address = 0;
- err = it87_find(sioaddr[i], &isa_address, &sio_data);
- if (err || isa_address == 0)
+ isa_address[i] = 0;
+ err = it87_find(sioaddr[i], &isa_address[i], &sio_data);
+ if (err || isa_address[i] == 0)
continue;
+ /*
+ * Don't register second chip if its ISA address matches
+ * the first chip's ISA address.
+ */
+ if (i && isa_address[i] == isa_address[0])
+ break;
- err = it87_device_add(i, isa_address, &sio_data);
+ err = it87_device_add(i, isa_address[i], &sio_data);
if (err)
goto exit_dev_unregister;
+
found = true;
+
+ /*
+ * IT8705F may respond on both SIO addresses.
+ * Stop probing after finding one.
+ */
+ if (sio_data.type == it87)
+ break;
}
if (!found) {
diff --git a/drivers/hwtracing/coresight/coresight-hwevent.c b/drivers/hwtracing/coresight/coresight-hwevent.c
index 5857d30..22e9d6f 100644
--- a/drivers/hwtracing/coresight/coresight-hwevent.c
+++ b/drivers/hwtracing/coresight/coresight-hwevent.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -216,14 +216,10 @@
mutex_init(&drvdata->mutex);
- drvdata->clk = devm_clk_get(dev, "core_clk");
+ drvdata->clk = devm_clk_get(dev, "apb_pclk");
if (IS_ERR(drvdata->clk))
return PTR_ERR(drvdata->clk);
- ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE);
- if (ret)
- return ret;
-
drvdata->nr_hclk = of_property_count_strings(pdev->dev.of_node,
"qcom,hwevent-clks");
drvdata->nr_hreg = of_property_count_strings(pdev->dev.of_node,
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 833f10d..475ea75 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -495,7 +495,7 @@
}
}
-static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
+void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
{
CS_UNLOCK(drvdata->base);
@@ -557,6 +557,207 @@
}
}
+static void tmc_etr_fill_usb_bam_data(struct tmc_drvdata *drvdata)
+{
+ struct tmc_etr_bam_data *bamdata = drvdata->bamdata;
+
+ get_qdss_bam_connection_info(&bamdata->dest,
+ &bamdata->dest_pipe_idx,
+ &bamdata->src_pipe_idx,
+ &bamdata->desc_fifo,
+ &bamdata->data_fifo,
+ NULL);
+}
+
+static void __tmc_etr_enable_to_bam(struct tmc_drvdata *drvdata)
+{
+ struct tmc_etr_bam_data *bamdata = drvdata->bamdata;
+ uint32_t axictl;
+
+ if (drvdata->enable_to_bam)
+ return;
+
+ /* Configure and enable required CSR registers */
+ msm_qdss_csr_enable_bam_to_usb();
+
+ /* Configure and enable ETR for usb bam output */
+
+ CS_UNLOCK(drvdata->base);
+
+ writel_relaxed(bamdata->data_fifo.size / 4, drvdata->base + TMC_RSZ);
+ writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
+
+ axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
+ axictl |= (0xF << 8);
+ writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
+ axictl &= ~(0x1 << 7);
+ writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
+ axictl = (axictl & ~0x3) | 0x2;
+ writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
+
+ writel_relaxed((uint32_t)bamdata->data_fifo.phys_base,
+ drvdata->base + TMC_DBALO);
+ writel_relaxed((((uint64_t)bamdata->data_fifo.phys_base) >> 32) & 0xFF,
+ drvdata->base + TMC_DBAHI);
+ /* Set FOnFlIn for periodic flush */
+ writel_relaxed(0x133, drvdata->base + TMC_FFCR);
+ writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
+ tmc_enable_hw(drvdata);
+
+ CS_LOCK(drvdata->base);
+
+ drvdata->enable_to_bam = true;
+}
+
+static int tmc_etr_bam_enable(struct tmc_drvdata *drvdata)
+{
+ struct tmc_etr_bam_data *bamdata = drvdata->bamdata;
+ int ret;
+
+ if (bamdata->enable)
+ return 0;
+
+ /* Reset bam to start with */
+ ret = sps_device_reset(bamdata->handle);
+ if (ret)
+ goto err0;
+
+ /* Now configure and enable bam */
+
+ bamdata->pipe = sps_alloc_endpoint();
+ if (!bamdata->pipe)
+ return -ENOMEM;
+
+ ret = sps_get_config(bamdata->pipe, &bamdata->connect);
+ if (ret)
+ goto err1;
+
+ bamdata->connect.mode = SPS_MODE_SRC;
+ bamdata->connect.source = bamdata->handle;
+ bamdata->connect.event_thresh = 0x4;
+ bamdata->connect.src_pipe_index = TMC_ETR_BAM_PIPE_INDEX;
+ bamdata->connect.options = SPS_O_AUTO_ENABLE;
+
+ bamdata->connect.destination = bamdata->dest;
+ bamdata->connect.dest_pipe_index = bamdata->dest_pipe_idx;
+ bamdata->connect.desc = bamdata->desc_fifo;
+ bamdata->connect.data = bamdata->data_fifo;
+
+ ret = sps_connect(bamdata->pipe, &bamdata->connect);
+ if (ret)
+ goto err1;
+
+ bamdata->enable = true;
+ return 0;
+err1:
+ sps_free_endpoint(bamdata->pipe);
+err0:
+ return ret;
+}
+
+static void tmc_wait_for_flush(struct tmc_drvdata *drvdata)
+{
+ int count;
+
+ /* Ensure no flush is in progress */
+ for (count = TIMEOUT_US;
+ BVAL(readl_relaxed(drvdata->base + TMC_FFSR), 0) != 0
+ && count > 0; count--)
+ udelay(1);
+ WARN(count == 0, "timeout while waiting for TMC flush, TMC_FFSR: %#x\n",
+ readl_relaxed(drvdata->base + TMC_FFSR));
+}
+
+void __tmc_etr_disable_to_bam(struct tmc_drvdata *drvdata)
+{
+ if (!drvdata->enable_to_bam)
+ return;
+
+ /* Ensure periodic flush is disabled in CSR block */
+ msm_qdss_csr_disable_flush();
+
+ CS_UNLOCK(drvdata->base);
+
+ tmc_wait_for_flush(drvdata);
+ tmc_disable_hw(drvdata);
+
+ CS_LOCK(drvdata);
+
+ /* Disable CSR configuration */
+ msm_qdss_csr_disable_bam_to_usb();
+ drvdata->enable_to_bam = false;
+}
+
+void tmc_etr_bam_disable(struct tmc_drvdata *drvdata)
+{
+ struct tmc_etr_bam_data *bamdata = drvdata->bamdata;
+
+ if (!bamdata->enable)
+ return;
+
+ sps_disconnect(bamdata->pipe);
+ sps_free_endpoint(bamdata->pipe);
+ bamdata->enable = false;
+}
+
+void usb_notifier(void *priv, unsigned int event, struct qdss_request *d_req,
+ struct usb_qdss_ch *ch)
+{
+ struct tmc_drvdata *drvdata = priv;
+ unsigned long flags;
+ int ret = 0;
+
+ mutex_lock(&drvdata->mem_lock);
+ if (event == USB_QDSS_CONNECT) {
+ tmc_etr_fill_usb_bam_data(drvdata);
+ ret = tmc_etr_bam_enable(drvdata);
+ if (ret)
+ dev_err(drvdata->dev, "ETR BAM enable failed\n");
+
+ spin_lock_irqsave(&drvdata->spinlock, flags);
+ __tmc_etr_enable_to_bam(drvdata);
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ } else if (event == USB_QDSS_DISCONNECT) {
+ spin_lock_irqsave(&drvdata->spinlock, flags);
+ __tmc_etr_disable_to_bam(drvdata);
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ tmc_etr_bam_disable(drvdata);
+ }
+ mutex_unlock(&drvdata->mem_lock);
+}
+
+int tmc_etr_bam_init(struct amba_device *adev,
+ struct tmc_drvdata *drvdata)
+{
+ int ret;
+ struct device *dev = &adev->dev;
+ struct resource res;
+ struct tmc_etr_bam_data *bamdata;
+
+ bamdata = devm_kzalloc(dev, sizeof(*bamdata), GFP_KERNEL);
+ if (!bamdata)
+ return -ENOMEM;
+ drvdata->bamdata = bamdata;
+
+ ret = of_address_to_resource(adev->dev.of_node, 1, &res);
+ if (ret)
+ return -ENODEV;
+
+ bamdata->props.phys_addr = res.start;
+ bamdata->props.virt_addr = devm_ioremap(dev, res.start,
+ resource_size(&res));
+ if (!bamdata->props.virt_addr)
+ return -ENOMEM;
+ bamdata->props.virt_size = resource_size(&res);
+
+ bamdata->props.event_threshold = 0x4; /* Pipe event threshold */
+ bamdata->props.summing_threshold = 0x10; /* BAM event threshold */
+ bamdata->props.irq = 0;
+ bamdata->props.num_pipes = TMC_ETR_BAM_NR_PIPES;
+
+ return sps_register_bam_device(&bamdata->props, &bamdata->handle);
+}
+
static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev, u32 mode)
{
int ret = 0;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 10e8da4..01dc5e1 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -63,11 +63,13 @@
void tmc_enable_hw(struct tmc_drvdata *drvdata)
{
+ drvdata->enable = true;
writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
}
void tmc_disable_hw(struct tmc_drvdata *drvdata)
{
+ drvdata->enable = false;
writel_relaxed(0x0, drvdata->base + TMC_CTL);
}
@@ -309,6 +311,100 @@
}
static DEVICE_ATTR_RW(mem_size);
+static ssize_t out_mode_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ return scnprintf(buf, PAGE_SIZE, "%s\n",
+ str_tmc_etr_out_mode[drvdata->out_mode]);
+}
+
+static ssize_t out_mode_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ char str[10] = "";
+ unsigned long flags;
+ int ret;
+
+ if (strlen(buf) >= 10)
+ return -EINVAL;
+ if (sscanf(buf, "%10s", str) != 1)
+ return -EINVAL;
+
+ mutex_lock(&drvdata->mem_lock);
+ if (!strcmp(str, str_tmc_etr_out_mode[TMC_ETR_OUT_MODE_MEM])) {
+ if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM)
+ goto out;
+
+ spin_lock_irqsave(&drvdata->spinlock, flags);
+ if (!drvdata->enable) {
+ drvdata->out_mode = TMC_ETR_OUT_MODE_MEM;
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ goto out;
+ }
+ __tmc_etr_disable_to_bam(drvdata);
+ tmc_etr_enable_hw(drvdata);
+ drvdata->out_mode = TMC_ETR_OUT_MODE_MEM;
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+
+ tmc_etr_bam_disable(drvdata);
+ usb_qdss_close(drvdata->usbch);
+ } else if (!strcmp(str, str_tmc_etr_out_mode[TMC_ETR_OUT_MODE_USB])) {
+ if (drvdata->out_mode == TMC_ETR_OUT_MODE_USB)
+ goto out;
+
+ spin_lock_irqsave(&drvdata->spinlock, flags);
+ if (!drvdata->enable) {
+ drvdata->out_mode = TMC_ETR_OUT_MODE_USB;
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ goto out;
+ }
+ if (drvdata->reading) {
+ ret = -EBUSY;
+ goto err1;
+ }
+ tmc_etr_disable_hw(drvdata);
+ drvdata->out_mode = TMC_ETR_OUT_MODE_USB;
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+
+ drvdata->usbch = usb_qdss_open("qdss", drvdata,
+ usb_notifier);
+ if (IS_ERR(drvdata->usbch)) {
+ dev_err(drvdata->dev, "usb_qdss_open failed\n");
+ ret = PTR_ERR(drvdata->usbch);
+ goto err0;
+ }
+ }
+out:
+ mutex_unlock(&drvdata->mem_lock);
+ return size;
+err1:
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+err0:
+ mutex_unlock(&drvdata->mem_lock);
+ return ret;
+}
+static DEVICE_ATTR_RW(out_mode);
+
+static ssize_t available_out_modes_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ ssize_t len = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(str_tmc_etr_out_mode); i++)
+ len += scnprintf(buf + len, PAGE_SIZE - len, "%s ",
+ str_tmc_etr_out_mode[i]);
+
+ len += scnprintf(buf + len, PAGE_SIZE - len, "\n");
+ return len;
+}
+static DEVICE_ATTR_RO(available_out_modes);
+
static ssize_t mem_type_show(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -355,6 +451,8 @@
&dev_attr_mem_size.attr,
&dev_attr_mem_type.attr,
&dev_attr_trigger_cntr.attr,
+ &dev_attr_out_mode.attr,
+ &dev_attr_available_out_modes.attr,
NULL,
};
@@ -460,6 +558,10 @@
desc.ops = &tmc_etr_cs_ops;
desc.groups = coresight_tmc_etr_groups;
desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
+
+ ret = tmc_etr_bam_init(adev, drvdata);
+ if (ret)
+ goto out;
} else {
desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
desc.ops = &tmc_etf_cs_ops;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 726dcd6..3d6e823 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -19,7 +19,12 @@
#define _CORESIGHT_TMC_H
#include <linux/miscdevice.h>
+#include <linux/delay.h>
#include <asm/cacheflush.h>
+#include <linux/of_address.h>
+#include <linux/amba/bus.h>
+#include <linux/usb_bam.h>
+#include <linux/usb/usb_qdss.h>
#define TMC_RSZ 0x004
#define TMC_STS 0x00c
@@ -77,6 +82,8 @@
#define TMC_ETR_SG_NXT_TBL(phys_pte) (((phys_pte >> PAGE_SHIFT) << 4) | 0x3)
#define TMC_ETR_SG_LST_ENT(phys_pte) (((phys_pte >> PAGE_SHIFT) << 4) | 0x1)
+#define TMC_ETR_BAM_PIPE_INDEX 0
+#define TMC_ETR_BAM_NR_PIPES 2
enum tmc_config_type {
TMC_CONFIG_TYPE_ETB,
@@ -107,6 +114,30 @@
[TMC_ETR_MEM_TYPE_SG] = "sg",
};
+enum tmc_etr_out_mode {
+ TMC_ETR_OUT_MODE_NONE,
+ TMC_ETR_OUT_MODE_MEM,
+ TMC_ETR_OUT_MODE_USB,
+};
+
+static const char * const str_tmc_etr_out_mode[] = {
+ [TMC_ETR_OUT_MODE_NONE] = "none",
+ [TMC_ETR_OUT_MODE_MEM] = "mem",
+ [TMC_ETR_OUT_MODE_USB] = "usb",
+};
+
+struct tmc_etr_bam_data {
+ struct sps_bam_props props;
+ unsigned long handle;
+ struct sps_pipe *pipe;
+ struct sps_connect connect;
+ uint32_t src_pipe_idx;
+ unsigned long dest;
+ uint32_t dest_pipe_idx;
+ struct sps_mem_buffer desc_fifo;
+ struct sps_mem_buffer data_fifo;
+ bool enable;
+};
/**
* struct tmc_drvdata - specifics associated to an TMC component
@@ -132,6 +163,7 @@
struct miscdevice miscdev;
spinlock_t spinlock;
bool reading;
+ bool enable;
char *buf;
dma_addr_t paddr;
void __iomem *vaddr;
@@ -147,6 +179,11 @@
enum tmc_etr_mem_type memtype;
u32 delta_bottom;
int sg_blk_num;
+ enum tmc_etr_out_mode out_mode;
+ struct usb_qdss_ch *usbch;
+ struct tmc_etr_bam_data *bamdata;
+ bool enable_to_bam;
+
};
/* Generic functions */
@@ -166,5 +203,13 @@
char **bufpp, size_t *len);
int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
+void __tmc_etr_disable_to_bam(struct tmc_drvdata *drvdata);
+void tmc_etr_bam_disable(struct tmc_drvdata *drvdata);
+void tmc_etr_enable_hw(struct tmc_drvdata *drvdata);
+void tmc_etr_disable_hw(struct tmc_drvdata *drvdata);
+void usb_notifier(void *priv, unsigned int event, struct qdss_request *d_req,
+ struct usb_qdss_ch *ch);
+int tmc_etr_bam_init(struct amba_device *adev,
+ struct tmc_drvdata *drvdata);
extern const struct coresight_ops tmc_etr_cs_ops;
#endif
diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h
index 25eab45..e7b96f1 100644
--- a/drivers/input/serio/i8042-x86ia64io.h
+++ b/drivers/input/serio/i8042-x86ia64io.h
@@ -685,6 +685,13 @@
DMI_MATCH(DMI_PRODUCT_NAME, "20046"),
},
},
+ {
+ /* Clevo P650RS, 650RP6, Sager NP8152-S, and others */
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Notebook"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "P65xRP"),
+ },
+ },
{ }
};
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index 261c125..7f9d9e1 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -1770,3 +1770,16 @@
*id = fwspec->ids[0];
return 0;
}
+
+/*
+ * Until a formal solution for probe deferral becomes part
+ * of the iommu framework...
+ */
+int iommu_is_available(struct device *dev)
+{
+ if (!dev->bus->iommu_ops ||
+ !dev->iommu_fwspec ||
+ !dev->iommu_group)
+ return -EPROBE_DEFER;
+ return 0;
+}
diff --git a/drivers/leds/leds-qpnp-wled.c b/drivers/leds/leds-qpnp-wled.c
index 3060cfa..cb19cef 100644
--- a/drivers/leds/leds-qpnp-wled.c
+++ b/drivers/leds/leds-qpnp-wled.c
@@ -2264,7 +2264,7 @@
{
return platform_driver_register(&qpnp_wled_driver);
}
-module_init(qpnp_wled_init);
+subsys_initcall(qpnp_wled_init);
static void __exit qpnp_wled_exit(void)
{
diff --git a/drivers/mailbox/qti-tcs.c b/drivers/mailbox/qti-tcs.c
index dfed3cd..6d0e913 100644
--- a/drivers/mailbox/qti-tcs.c
+++ b/drivers/mailbox/qti-tcs.c
@@ -333,6 +333,20 @@
tasklet_schedule(&resp->tasklet);
}
+static inline void enable_tcs_irq(struct tcs_drv *drv, int m, bool enable)
+{
+ void __iomem *base = drv->reg_base;
+ u32 data;
+
+ /* Enable interrupts for non-ACTIVE TCS */
+ data = read_tcs_reg(base, TCS_DRV_IRQ_ENABLE, 0, 0);
+ if (enable)
+ data |= BIT(m);
+ else
+ data &= ~BIT(m);
+ write_tcs_reg(base, TCS_DRV_IRQ_ENABLE, 0, 0, data);
+}
+
/**
* tcs_irq_handler: TX Done / Recv data handler
*/
@@ -350,10 +364,9 @@
/* Know which TCSes were triggered */
irq_status = read_tcs_reg(base, TCS_DRV_IRQ_STATUS, 0, 0);
- for (m = 0; irq_status >= BIT(m); m++) {
- if (!(irq_status & BIT(m)))
+ for (m = 0; m < drv->num_tcs; m++) {
+ if (!(irq_status & (u32)BIT(m)))
continue;
-
atomic_inc(&drv->tcs_irq_count[m]);
resp = get_response(drv, m);
@@ -395,6 +408,12 @@
data = read_tcs_reg(base, TCS_DRV_CONTROL, m, 0);
data &= ~TCS_AMC_MODE_ENABLE;
write_tcs_reg(base, TCS_DRV_CONTROL, m, 0, data);
+ /*
+ * Disable interrupt for this TCS to avoid being
+ * spammed with interrupts coming when the solver
+ * sends its wake votes.
+ */
+ enable_tcs_irq(drv, m, false);
} else {
/* Clear the enable bit for the commands */
write_tcs_reg(base, TCS_DRV_CMD_ENABLE, m, 0, 0);
@@ -523,9 +542,11 @@
continue;
curr_enabled = read_tcs_reg(base, TCS_DRV_CMD_ENABLE, m, 0);
- for (j = 0; j < curr_enabled; j++) {
- if (!(curr_enabled & BIT(j)))
+
+ for (j = 0; j < MAX_CMDS_PER_TCS; j++) {
+ if (!(curr_enabled & (u32)BIT(j)))
continue;
+
addr = read_tcs_reg(base, TCS_DRV_CMD_ADDR, m, j);
for (k = 0; k < msg->num_payload; k++) {
if (addr == msg->payload[k].addr)
@@ -659,6 +680,9 @@
/* Mark the TCS as busy */
atomic_set(&drv->tcs_in_use[m], 1);
atomic_inc(&drv->tcs_send_count[m]);
+ /* Enable interrupt for active votes through wake TCS */
+ if (tcs->type != ACTIVE_TCS)
+ enable_tcs_irq(drv, m, true);
}
/* Write to the TCS or AMC */
@@ -902,7 +926,6 @@
u32 config, max_tcs, ncpt;
int tcs_type_count[TCS_TYPE_NR] = { 0 };
struct resource *res;
- u32 irq_mask;
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
if (!drv)
@@ -1043,14 +1066,9 @@
if (ret)
return ret;
- /*
- * Enable interrupts for AMC TCS,
- * if there are no AMC TCS, use wake TCS.
- */
- irq_mask = (drv->tcs[ACTIVE_TCS].num_tcs) ?
- drv->tcs[ACTIVE_TCS].tcs_mask :
- drv->tcs[WAKE_TCS].tcs_mask;
- write_tcs_reg(drv->reg_base, TCS_DRV_IRQ_ENABLE, 0, 0, irq_mask);
+ /* Enable interrupts for AMC TCS */
+ write_tcs_reg(drv->reg_base, TCS_DRV_IRQ_ENABLE, 0, 0,
+ drv->tcs[ACTIVE_TCS].tcs_mask);
for (i = 0; i < ARRAY_SIZE(drv->tcs_in_use); i++)
atomic_set(&drv->tcs_in_use[i], 0);
diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c
index 89ec6d2..be13ebf 100644
--- a/drivers/md/dm-ioctl.c
+++ b/drivers/md/dm-ioctl.c
@@ -1847,7 +1847,7 @@
if (r)
goto out;
- param->data_size = sizeof(*param);
+ param->data_size = offsetof(struct dm_ioctl, data);
r = fn(param, input_param_size);
if (unlikely(param->flags & DM_BUFFER_FULL_FLAG) &&
diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index e66f404..aac7161 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -69,6 +69,13 @@
struct dm_stats_aux stats_aux;
};
+union map_info *dm_get_rq_mapinfo(struct request *rq)
+{
+ if (rq && rq->end_io_data)
+ return &((struct dm_rq_target_io *)rq->end_io_data)->info;
+ return NULL;
+}
+
#define MINOR_ALLOCED ((void *)-1)
/*
diff --git a/drivers/media/platform/msm/camera/cam_core/cam_subdev.c b/drivers/media/platform/msm/camera/cam_core/cam_subdev.c
index 03b18cf..429474b 100644
--- a/drivers/media/platform/msm/camera/cam_core/cam_subdev.c
+++ b/drivers/media/platform/msm/camera/cam_core/cam_subdev.c
@@ -75,7 +75,26 @@
static long cam_subdev_compat_ioctl(struct v4l2_subdev *sd,
unsigned int cmd, unsigned long arg)
{
- return cam_subdev_ioctl(sd, cmd, compat_ptr(arg));
+ struct cam_control cmd_data;
+ int rc;
+
+ if (copy_from_user(&cmd_data, (void __user *)arg,
+ sizeof(cmd_data))) {
+ pr_err("Failed to copy from user_ptr=%pK size=%zu\n",
+ (void __user *)arg, sizeof(cmd_data));
+ return -EFAULT;
+ }
+ rc = cam_subdev_ioctl(sd, cmd, &cmd_data);
+ if (!rc) {
+ if (copy_to_user((void __user *)arg, &cmd_data,
+ sizeof(cmd_data))) {
+ pr_err("Failed to copy to user_ptr=%pK size=%zu\n",
+ (void __user *)arg, sizeof(cmd_data));
+ rc = -EFAULT;
+ }
+ }
+
+ return rc;
}
#endif
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/Makefile b/drivers/media/platform/msm/camera/cam_req_mgr/Makefile
index 87707b1..e6da6ca 100644
--- a/drivers/media/platform/msm/camera/cam_req_mgr/Makefile
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/Makefile
@@ -1,3 +1,9 @@
ccflags-y += -Idrivers/media/platform/msm/camera/cam_smmu/
-obj-$(CONFIG_SPECTRA_CAMERA) += cam_req_mgr_dev.o cam_req_mgr_util.o cam_req_mgr_core.o cam_req_mgr_workq.o cam_mem_mgr.o
+obj-$(CONFIG_SPECTRA_CAMERA) += cam_req_mgr_dev.o \
+ cam_req_mgr_util.o \
+ cam_req_mgr_core.o \
+ cam_req_mgr_workq.o \
+ cam_mem_mgr.o \
+ cam_req_mgr_timer.o \
+ cam_req_mgr_debug.o
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c
index a34703c..e62c101 100644
--- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c
@@ -18,588 +18,1960 @@
#include "cam_req_mgr_util.h"
#include "cam_req_mgr_core.h"
#include "cam_req_mgr_workq.h"
-
-/* Forward declarations */
-static int cam_req_mgr_cb_notify_sof(
- struct cam_req_mgr_sof_notify *sof_data);
-
+#include "cam_req_mgr_debug.h"
static struct cam_req_mgr_core_device *g_crm_core_dev;
-static struct cam_req_mgr_crm_cb cam_req_mgr_ops = {
- .notify_sof = cam_req_mgr_cb_notify_sof,
- .notify_err = NULL,
- .add_req = NULL,
-};
+static int __cam_req_mgr_setup_payload(struct cam_req_mgr_core_workq *workq)
+{
+ int32_t i = 0;
+ int rc = 0;
+ struct crm_task_payload *task_data = NULL;
+
+ task_data = kcalloc(
+ workq->task.num_task, sizeof(*task_data),
+ GFP_KERNEL);
+ if (!task_data) {
+ rc = -ENOMEM;
+ } else {
+ for (i = 0; i < workq->task.num_task; i++)
+ workq->task.pool[i].payload = &task_data[i];
+ }
+
+ return rc;
+}
/**
- * cam_req_mgr_pvt_find_link()
+ * __cam_req_mgr_reset_req_tbl()
*
- * @brief: Finds link matching with handle within session
- * @session: session indetifier
- * @link_hdl: link handle
+ * @brief : Initialize req table data
+ * @in_q : request queue pointer
*
- * Returns pointer to link matching handle
+ * @return: 0 for success, negative for failure
+ *
*/
-static struct cam_req_mgr_core_link *cam_req_mgr_pvt_find_link(
- struct cam_req_mgr_core_session *session, int32_t link_hdl)
+static int __cam_req_mgr_print_req_tbl(struct cam_req_mgr_req_data *req)
{
- int32_t i;
+ int rc = 0;
+ int32_t i = 0;
+ struct cam_req_mgr_req_queue *in_q = req->in_q;
+ struct cam_req_mgr_req_tbl *req_tbl = req->l_tbl;
+
+ if (!in_q || !req_tbl) {
+ CRM_WARN("NULL pointer %pK %pK", in_q, req_tbl);
+ return -EINVAL;
+ }
+ CRM_DBG("in_q %pK %pK %d", in_q, req_tbl, req_tbl->num_slots);
+ mutex_lock(&req->lock);
+ for (i = 0; i < in_q->num_slots; i++) {
+ CRM_DBG("IN_Q %d: idx %d, red_id %lld", i,
+ in_q->slot[i].idx, CRM_GET_REQ_ID(in_q, i));
+ }
+
+ while (req_tbl != NULL) {
+ for (i = 0; i < req_tbl->num_slots; i++) {
+ CRM_DBG("idx= %d, map= %x, state= %d",
+ req_tbl->slot[i].idx,
+ req_tbl->slot[i].req_ready_map,
+ req_tbl->slot[i].state);
+ }
+ CRM_DBG("TBL:id= %d, pd=%d cnt=%d mask=%x skip=%d num_slt= %d",
+ req_tbl->id, req_tbl->pd, req_tbl->dev_count,
+ req_tbl->dev_mask, req_tbl->skip_traverse,
+ req_tbl->num_slots);
+ req_tbl = req_tbl->next;
+ }
+ mutex_unlock(&req->lock);
+
+ return rc;
+}
+
+/**
+ * __cam_req_mgr_find_pd_tbl()
+ *
+ * @brief : Find pipeline delay based table pointer which matches delay
+ * @tbl : Pointer to list of request table
+ * @delay : Pipeline delay value to be searched for comparison
+ *
+ * @return : pointer to request table for matching pipeline delay table.
+ *
+ */
+static struct cam_req_mgr_req_tbl *__cam_req_mgr_find_pd_tbl(
+ struct cam_req_mgr_req_tbl *tbl, int32_t delay)
+{
+ if (!tbl)
+ return NULL;
+
+ do {
+ if (delay != tbl->pd)
+ tbl = tbl->next;
+ else
+ return tbl;
+ } while (tbl != NULL);
+
+ return NULL;
+}
+
+/**
+ * __cam_req_mgr_inc_idx()
+ *
+ * @brief : Increment val passed by step size and rollover after max_val
+ * @val : value to be incremented
+ * @step : amount/step by which val is incremented
+ * @max_val : max val after which idx will roll over
+ *
+ */
+static void __cam_req_mgr_inc_idx(int32_t *val, int32_t step, int32_t max_val)
+{
+ *val = (*val + step) % max_val;
+}
+
+/**
+ * __cam_req_mgr_dec_idx()
+ *
+ * @brief : Decrement val passed by step size and rollover after max_val
+ * @val : value to be decremented
+ * @step : amount/step by which val is decremented
+ * @max_val : after zero value will roll over to max val
+ *
+ */
+static void __cam_req_mgr_dec_idx(int32_t *val, int32_t step, int32_t max_val)
+{
+ *val = *val - step;
+ if (*val < 0)
+ *val = max_val + (*val);
+}
+
+/**
+ * __cam_req_mgr_traverse()
+ *
+ * @brief : Traverse through pd tables, it will internally cover all linked
+ * pd tables. Each pd table visited will check if idx passed to its
+ * in ready state. If ready means all devices linked to the pd table
+ * have this request id packet ready. Then it calls subsequent pd
+ * tbl with new idx. New idx value takes into account the delta
+ * between current pd table and next one.
+ * @traverse_data: contains all the info to traverse through pd tables
+ *
+ * @return: 0 for success, negative for failure
+ *
+ */
+static int __cam_req_mgr_traverse(struct cam_req_mgr_traverse *traverse_data)
+{
+ int rc = 0;
+ int32_t next_idx = traverse_data->idx;
+ int32_t curr_idx = traverse_data->idx;
+ struct cam_req_mgr_req_tbl *tbl;
+ struct cam_req_mgr_apply *apply_data;
+
+ if (!traverse_data->tbl || !traverse_data->apply_data) {
+ CRM_ERR("NULL pointer %pK %pK",
+ traverse_data->tbl, traverse_data->apply_data);
+ traverse_data->result = 0;
+ return -EINVAL;
+ }
+
+ tbl = traverse_data->tbl;
+ apply_data = traverse_data->apply_data;
+ CRM_DBG("Enter pd %d idx %d state %d skip %d status %d",
+ tbl->pd, curr_idx, tbl->slot[curr_idx].state,
+ tbl->skip_traverse, traverse_data->in_q->slot[curr_idx].status);
+
+ /* Check if req is ready or in skip mode or pd tbl is in skip mode */
+ if (tbl->slot[curr_idx].state == CRM_REQ_STATE_READY ||
+ traverse_data->in_q->slot[curr_idx].skip_idx == 1 ||
+ tbl->skip_traverse > 0) {
+ if (tbl->next) {
+ __cam_req_mgr_dec_idx(&next_idx, tbl->pd_delta,
+ tbl->num_slots);
+ traverse_data->idx = next_idx;
+ traverse_data->tbl = tbl->next;
+ rc = __cam_req_mgr_traverse(traverse_data);
+ }
+ if (rc >= 0) {
+ SET_SUCCESS_BIT(traverse_data->result, tbl->pd);
+ apply_data[tbl->pd].pd = tbl->pd;
+ apply_data[tbl->pd].req_id =
+ CRM_GET_REQ_ID(traverse_data->in_q, curr_idx);
+ apply_data[tbl->pd].idx = curr_idx;
+
+ /* If traverse is sucessful decrement traverse skip */
+ if (tbl->skip_traverse > 0) {
+ apply_data[tbl->pd].req_id = -1;
+ tbl->skip_traverse--;
+ }
+ } else {
+ /* linked pd table is not ready for this traverse yet */
+ return rc;
+ }
+ } else {
+ /* This pd table is not ready to proceed with asked idx */
+ SET_FAILURE_BIT(traverse_data->result, tbl->pd);
+ return -EAGAIN;
+ }
+ return 0;
+}
+
+/**
+ * __cam_req_mgr_in_q_skip_idx()
+ *
+ * @brief : Decrement val passed by step size and rollover after max_val
+ * @in_q : input queue pointer
+ * @idx : Sets skip_idx bit of the particular slot to true so when traverse
+ * happens for this idx, no req will be submitted for devices
+ * handling this idx.
+ *
+ */
+static void __cam_req_mgr_in_q_skip_idx(struct cam_req_mgr_req_queue *in_q,
+ int32_t idx)
+{
+ in_q->slot[idx].req_id = -1;
+ in_q->slot[idx].skip_idx = 1;
+ in_q->slot[idx].status = CRM_SLOT_STATUS_REQ_ADDED;
+ CRM_DBG("SET IDX SKIP on slot= %d", idx);
+}
+
+/**
+ * __cam_req_mgr_tbl_set_id()
+ *
+ * @brief : Set unique id to table
+ * @tbl : pipeline based table which requires new id
+ * @req : pointer to request data wihch contains num_tables counter
+ *
+ */
+static void __cam_req_mgr_tbl_set_id(struct cam_req_mgr_req_tbl *tbl,
+ struct cam_req_mgr_req_data *req)
+{
+ if (!tbl)
+ return;
+ do {
+ tbl->id = req->num_tbl++;
+ CRM_DBG("%d: pd %d skip_traverse %d delta %d",
+ tbl->id, tbl->pd, tbl->skip_traverse,
+ tbl->pd_delta);
+ tbl = tbl->next;
+ } while (tbl != NULL);
+}
+
+/**
+ * __cam_req_mgr_tbl_set_all_skip_cnt()
+ *
+ * @brief : Each pd table sets skip value based on delta between itself and
+ * max pd value. During initial streamon or bubble case this is
+ * used. That way each pd table skips required num of traverse and
+ * align themselve with req mgr connected devs.
+ * @l_tbl : iterates through list of pd tables and sets skip traverse
+ *
+ */
+static void __cam_req_mgr_tbl_set_all_skip_cnt(
+ struct cam_req_mgr_req_tbl **l_tbl)
+{
+ struct cam_req_mgr_req_tbl *tbl = *l_tbl;
+ int32_t max_pd;
+
+ if (!tbl)
+ return;
+
+ max_pd = tbl->pd;
+ do {
+ tbl->skip_traverse = max_pd - tbl->pd;
+ CRM_DBG("%d: pd %d skip_traverse %d delta %d",
+ tbl->id, tbl->pd, tbl->skip_traverse,
+ tbl->pd_delta);
+ tbl = tbl->next;
+ } while (tbl != NULL);
+}
+
+/**
+ * __cam_req_mgr_reset_req_slot()
+ *
+ * @brief : reset specified idx/slot in input queue as well as all pd tables
+ * @link : link pointer
+ * @idx : slot index which will be reset
+ *
+ */
+static void __cam_req_mgr_reset_req_slot(struct cam_req_mgr_core_link *link,
+ int32_t idx)
+{
+ struct cam_req_mgr_slot *slot;
+ struct cam_req_mgr_req_tbl *tbl = link->req.l_tbl;
+ struct cam_req_mgr_req_queue *in_q = link->req.in_q;
+
+ slot = &in_q->slot[idx];
+ CRM_DBG("RESET: idx: %d: slot->status %d", idx, slot->status);
+
+ /* Check if CSL has already pushed new request*/
+ if (slot->status == CRM_SLOT_STATUS_REQ_ADDED)
+ return;
+
+ /* Reset input queue slot */
+ slot->req_id = -1;
+ slot->skip_idx = 0;
+ slot->recover = 0;
+ slot->status = CRM_SLOT_STATUS_NO_REQ;
+
+ /* Reset all pd table slot */
+ while (tbl != NULL) {
+ CRM_DBG("pd: %d: idx %d state %d",
+ tbl->pd, idx, tbl->slot[idx].state);
+ tbl->slot[idx].req_ready_map = 0;
+ tbl->slot[idx].state = CRM_REQ_STATE_EMPTY;
+ tbl = tbl->next;
+ }
+}
+
+/**
+ * __cam_req_mgr_check_next_req_slot()
+ *
+ * @brief : While streaming if input queue does not contain any pending
+ * request, req mgr still needs to submit pending request ids to
+ * devices with lower pipeline delay value.
+ * @in_q : Pointer to input queue where req mgr wil peep into
+ *
+ */
+static void __cam_req_mgr_check_next_req_slot(
+ struct cam_req_mgr_req_queue *in_q)
+{
+ int32_t idx = in_q->rd_idx;
+ struct cam_req_mgr_slot *slot;
+
+ __cam_req_mgr_inc_idx(&idx, 1, in_q->num_slots);
+ slot = &in_q->slot[idx];
+
+ CRM_DBG("idx: %d: slot->status %d", idx, slot->status);
+
+ /* Check if there is new req from CSL, if not complete req */
+ if (slot->status == CRM_SLOT_STATUS_NO_REQ) {
+ __cam_req_mgr_in_q_skip_idx(in_q, idx);
+ if (in_q->wr_idx != idx)
+ CRM_WARN("CHECK here wr %d, rd %d", in_q->wr_idx, idx);
+ __cam_req_mgr_inc_idx(&in_q->wr_idx, 1, in_q->num_slots);
+ }
+}
+
+/**
+ * __cam_req_mgr_send_req()
+ *
+ * @brief : send request id to be applied to each device connected on link
+ * @link : pointer to link whose input queue and req tbl are
+ * traversed through
+ * @in_q : pointer to input request queue
+ *
+ * @return : 0 for success, negative for failure
+ *
+ */
+static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link,
+ struct cam_req_mgr_req_queue *in_q)
+{
+ int rc = 0, pd, i, idx;
+ struct cam_req_mgr_connected_device *dev = NULL;
+ struct cam_req_mgr_apply_request apply_req;
+ struct cam_req_mgr_link_evt_data evt_data;
+
+ apply_req.link_hdl = link->link_hdl;
+ apply_req.report_if_bubble = 0;
+
+ for (i = 0; i < link->num_devs; i++) {
+ dev = &link->l_dev[i];
+ if (dev) {
+ pd = dev->dev_info.p_delay;
+ if (pd >= CAM_PIPELINE_DELAY_MAX) {
+ CRM_WARN("pd %d greater than max",
+ pd);
+ continue;
+ }
+ if (link->req.apply_data[pd].skip_idx ||
+ link->req.apply_data[pd].req_id < 0) {
+ CRM_DBG("skip %d req_id %lld",
+ link->req.apply_data[pd].skip_idx,
+ link->req.apply_data[pd].req_id);
+ continue;
+ }
+ apply_req.dev_hdl = dev->dev_hdl;
+ apply_req.request_id =
+ link->req.apply_data[pd].req_id;
+ idx = link->req.apply_data[pd].idx;
+ apply_req.report_if_bubble =
+ in_q->slot[idx].recover;
+ CRM_DBG("SEND: pd %d req_id %lld",
+ pd, apply_req.request_id);
+ if (dev->ops && dev->ops->apply_req) {
+ rc = dev->ops->apply_req(&apply_req);
+ if (rc < 0)
+ break;
+ }
+ }
+ }
+ if (rc < 0) {
+ CRM_ERR("APPLY FAILED pd %d req_id %lld",
+ dev->dev_info.p_delay, apply_req.request_id);
+ /* Apply req failed notify already applied devs */
+ for (; i >= 0; i--) {
+ dev = &link->l_dev[i];
+ evt_data.evt_type = CAM_REQ_MGR_LINK_EVT_ERR;
+ evt_data.link_hdl = link->link_hdl;
+ evt_data.req_id = apply_req.request_id;
+ evt_data.u.error = CRM_KMD_ERR_BUBBLE;
+ if (dev->ops && dev->ops->process_evt)
+ dev->ops->process_evt(&evt_data);
+ }
+ }
+ return rc;
+}
+
+/**
+ * __cam_req_mgr_check_link_is_ready()
+ *
+ * @brief : traverse through all request tables and see if all devices are
+ * ready to apply request settings.
+ * @link : pointer to link whose input queue and req tbl are
+ * traversed through
+ * @idx : index within input request queue
+ *
+ * @return : 0 for success, negative for failure
+ *
+ */
+static int __cam_req_mgr_check_link_is_ready(struct cam_req_mgr_core_link *link,
+ int32_t idx)
+{
+ int rc;
+ struct cam_req_mgr_traverse traverse_data;
+ struct cam_req_mgr_req_queue *in_q;
+ struct cam_req_mgr_apply *apply_data;
+
+ in_q = link->req.in_q;
+
+ apply_data = link->req.apply_data;
+ memset(apply_data, 0,
+ sizeof(struct cam_req_mgr_apply) * CAM_PIPELINE_DELAY_MAX);
+
+ traverse_data.apply_data = apply_data;
+ traverse_data.idx = idx;
+ traverse_data.tbl = link->req.l_tbl;
+ traverse_data.in_q = in_q;
+ traverse_data.result = 0;
+ /*
+ * Traverse through all pd tables, if result is success,
+ * apply the settings
+ */
+
+ rc = __cam_req_mgr_traverse(&traverse_data);
+ CRM_DBG("SOF: idx %d result %x pd_mask %x rc %d",
+ idx, traverse_data.result, link->pd_mask, rc);
+
+ if (!rc && traverse_data.result == link->pd_mask) {
+ CRM_DBG("APPLY: link_hdl= %x idx= %d, req_id= %lld :%lld :%lld",
+ link->link_hdl, idx,
+ apply_data[2].req_id, apply_data[1].req_id,
+ apply_data[0].req_id);
+ } else
+ rc = -EAGAIN;
+
+ return rc;
+}
+
+/**
+ * __cam_req_mgr_process_req()
+ *
+ * @brief : processes read index in request queue and traverse through table
+ * @link : pointer to link whose input queue and req tbl are
+ * traversed through
+ *
+ * @return : 0 for success, negative for failure
+ *
+ */
+static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link)
+{
+ int rc = 0, idx;
+ struct cam_req_mgr_slot *slot = NULL;
+ struct cam_req_mgr_req_queue *in_q;
+ struct cam_req_mgr_core_session *session;
+
+ in_q = link->req.in_q;
+ session = (struct cam_req_mgr_core_session *)link->parent;
+
+ /*
+ * 1. Check if new read index,
+ * - if in pending state, traverse again to complete
+ * transaction of this read index.
+ * - if in applied_state, somthign wrong.
+ * - if in no_req state, no new req
+ */
+ CRM_DBG("idx %d req_status %d",
+ in_q->rd_idx, in_q->slot[in_q->rd_idx].status);
+
+ slot = &in_q->slot[in_q->rd_idx];
+ if (slot->status == CRM_SLOT_STATUS_NO_REQ) {
+ CRM_DBG("No Pending req");
+ return 0;
+ }
+
+ rc = __cam_req_mgr_check_link_is_ready(link, slot->idx);
+ if (rc >= 0) {
+ rc = __cam_req_mgr_send_req(link, link->req.in_q);
+ if (rc < 0) {
+ /* Apply req failed retry at next sof */
+ slot->status = CRM_SLOT_STATUS_REQ_PENDING;
+ } else {
+ slot->status = CRM_SLOT_STATUS_REQ_APPLIED;
+
+ if (link->state == CAM_CRM_LINK_STATE_ERR) {
+ CRM_WARN("Err recovery done idx %d status %d",
+ in_q->rd_idx,
+ in_q->slot[in_q->rd_idx].status);
+ mutex_lock(&link->lock);
+ link->state = CAM_CRM_LINK_STATE_READY;
+ mutex_unlock(&link->lock);
+ }
+
+ /*
+ * 2. Check if any new req is pending in input queue,
+ * if not finish the lower pipeline delay device with
+ * available req ids.
+ */
+ __cam_req_mgr_check_next_req_slot(in_q);
+
+ /*
+ * 3. Older req slots can be safely reset as no err ack.
+ */
+ idx = in_q->rd_idx;
+ __cam_req_mgr_dec_idx(&idx, link->max_delay + 1,
+ in_q->num_slots);
+ __cam_req_mgr_reset_req_slot(link, idx);
+ }
+ } else {
+ /*
+ * 4.If traverse result is not success, then some devices are
+ * not ready with packet for the asked request id,
+ * hence try again in next sof
+ */
+ slot->status = CRM_SLOT_STATUS_REQ_PENDING;
+ if (link->state == CAM_CRM_LINK_STATE_ERR) {
+ /*
+ * During error recovery all tables should be ready
+ * don't expect to enter here.
+ * @TODO: gracefully handle if recovery fails.
+ */
+ CRM_ERR("FATAL recovery cant finish idx %d status %d",
+ in_q->rd_idx, in_q->slot[in_q->rd_idx].status);
+ rc = -EPERM;
+ }
+ }
+
+ return rc;
+}
+
+/**
+ * __cam_req_mgr_add_tbl_to_link()
+ *
+ * @brief : Add table to list under link sorted by pd decremeting order
+ * @l_tbl : list of pipeline delay tables.
+ * @new_tbl : new tbl which will be appended to above list as per its pd value
+ *
+ */
+static void __cam_req_mgr_add_tbl_to_link(struct cam_req_mgr_req_tbl **l_tbl,
+ struct cam_req_mgr_req_tbl *new_tbl)
+{
+ struct cam_req_mgr_req_tbl *tbl;
+
+ if (!(*l_tbl) || (*l_tbl)->pd < new_tbl->pd) {
+ new_tbl->next = *l_tbl;
+ if (*l_tbl) {
+ new_tbl->pd_delta =
+ new_tbl->pd - (*l_tbl)->pd;
+ }
+ *l_tbl = new_tbl;
+ } else {
+ tbl = *l_tbl;
+
+ /* Reach existing tbl which has less pd value */
+ while (tbl->next != NULL &&
+ new_tbl->pd < tbl->next->pd) {
+ tbl = tbl->next;
+ }
+ if (tbl->next != NULL) {
+ new_tbl->pd_delta =
+ new_tbl->pd - tbl->next->pd;
+ } else {
+ /* This is last table in linked list*/
+ new_tbl->pd_delta = 0;
+ }
+ new_tbl->next = tbl->next;
+ tbl->next = new_tbl;
+ tbl->pd_delta = tbl->pd - new_tbl->pd;
+ }
+ CRM_DBG("added pd %d tbl to link delta %d", new_tbl->pd,
+ new_tbl->pd_delta);
+}
+
+/**
+ * __cam_req_mgr_create_pd_tbl()
+ *
+ * @brief : Creates new request table for new delay value
+ * @delay : New pd table allocated will have this delay value
+ *
+ * @return : pointer to newly allocated table, NULL for failure
+ *
+ */
+static struct cam_req_mgr_req_tbl *__cam_req_mgr_create_pd_tbl(int32_t delay)
+{
+ struct cam_req_mgr_req_tbl *tbl =
+ kzalloc(sizeof(struct cam_req_mgr_req_tbl), GFP_KERNEL);
+ if (tbl != NULL) {
+ tbl->num_slots = MAX_REQ_SLOTS;
+ CRM_DBG("pd= %d slots= %d", delay, tbl->num_slots);
+ }
+
+ return tbl;
+}
+
+/**
+ * __cam_req_mgr_destroy_all_tbl()
+ *
+ * @brief : This func will destroy all pipeline delay based req table structs
+ * @l_tbl : pointer to first table in list and it has max pd .
+ *
+ */
+static void __cam_req_mgr_destroy_all_tbl(struct cam_req_mgr_req_tbl **l_tbl)
+{
+ struct cam_req_mgr_req_tbl *tbl = *l_tbl, *temp;
+
+ CRM_DBG("*l_tbl %pK", tbl);
+ while (tbl != NULL) {
+ temp = tbl->next;
+ kfree(tbl);
+ tbl = temp;
+ }
+ *l_tbl = NULL;
+}
+
+/**
+ * __cam_req_mgr_find_slot_for_req()
+ *
+ * @brief : Find idx from input queue at which req id is enqueued
+ * @in_q : input request queue pointer
+ * @req_id : request id which needs to be searched in input queue
+ *
+ * @return : slot index where passed request id is stored, -1 for failure
+ *
+ */
+static int32_t __cam_req_mgr_find_slot_for_req(
+ struct cam_req_mgr_req_queue *in_q, int64_t req_id)
+{
+ int32_t idx, i;
+ struct cam_req_mgr_slot *slot;
+
+ idx = in_q->wr_idx;
+ for (i = 0; i < in_q->num_slots; i++) {
+ slot = &in_q->slot[idx];
+ if (slot->req_id == req_id) {
+ CRM_DBG("req %lld found at %d %d status %d",
+ req_id, idx, slot->idx,
+ slot->status);
+ break;
+ }
+ __cam_req_mgr_dec_idx(&idx, 1, in_q->num_slots);
+ }
+ if (i >= in_q->num_slots)
+ idx = -1;
+
+ return idx;
+}
+
+/**
+ * __cam_req_mgr_setup_in_q()
+ *
+ * @brief : Initialize req table data
+ * @req : request data pointer
+ *
+ * @return: 0 for success, negative for failure
+ *
+ */
+static int __cam_req_mgr_setup_in_q(struct cam_req_mgr_req_data *req)
+{
+ int i;
+ struct cam_req_mgr_req_queue *in_q = req->in_q;
+
+ if (!in_q) {
+ CRM_ERR("NULL in_q");
+ return -EINVAL;
+ }
+
+ mutex_lock(&req->lock);
+ in_q->num_slots = MAX_REQ_SLOTS;
+
+ for (i = 0; i < in_q->num_slots; i++) {
+ in_q->slot[i].idx = i;
+ in_q->slot[i].req_id = -1;
+ in_q->slot[i].skip_idx = 0;
+ in_q->slot[i].status = CRM_SLOT_STATUS_NO_REQ;
+ }
+
+ in_q->wr_idx = 0;
+ in_q->rd_idx = 0;
+ mutex_unlock(&req->lock);
+
+ return 0;
+}
+
+/**
+ * __cam_req_mgr_reset_req_tbl()
+ *
+ * @brief : Initialize req table data
+ * @req : request queue pointer
+ *
+ * @return: 0 for success, negative for failure
+ *
+ */
+static int __cam_req_mgr_reset_in_q(struct cam_req_mgr_req_data *req)
+{
+ struct cam_req_mgr_req_queue *in_q = req->in_q;
+
+ if (!in_q) {
+ CRM_ERR("NULL in_q");
+ return -EINVAL;
+ }
+
+ mutex_lock(&req->lock);
+ memset(in_q->slot, 0,
+ sizeof(struct cam_req_mgr_slot) * in_q->num_slots);
+ in_q->num_slots = 0;
+
+ in_q->wr_idx = 0;
+ in_q->rd_idx = 0;
+ mutex_unlock(&req->lock);
+
+ return 0;
+}
+
+/**
+ * __cam_req_mgr_sof_freeze()
+ *
+ * @brief : Apoptosis - Handles case when connected devices are not responding
+ * @data : timer pointer
+ *
+ */
+static void __cam_req_mgr_sof_freeze(unsigned long data)
+{
+ struct cam_req_mgr_timer *timer = (struct cam_req_mgr_timer *)data;
struct cam_req_mgr_core_link *link = NULL;
- if (!session) {
- CRM_ERR("NULL session ptr");
+ if (!timer) {
+ CRM_ERR("NULL timer");
+ return;
+ }
+ link = (struct cam_req_mgr_core_link *)timer->parent;
+ CRM_ERR("SOF freeze for link %x", link->link_hdl);
+}
+
+/**
+ * __cam_req_mgr_create_subdevs()
+ *
+ * @brief : Create new crm subdev to link with realtime devices
+ * @l_dev : list of subdevs internal to crm
+ * @num_dev : num of subdevs to be created for link
+ *
+ * @return : pointer to allocated list of devices
+ */
+static int __cam_req_mgr_create_subdevs(
+ struct cam_req_mgr_connected_device **l_dev, int32_t num_dev)
+{
+ int rc = 0;
+ *l_dev = (struct cam_req_mgr_connected_device *)
+ kzalloc(sizeof(struct cam_req_mgr_connected_device) * num_dev,
+ GFP_KERNEL);
+ if (!*l_dev)
+ rc = -ENOMEM;
+
+ return rc;
+}
+
+/**
+ * __cam_req_mgr_destroy_subdev()
+ *
+ * @brief : Cleans up the subdevs allocated by crm for link
+ * @l_device : pointer to list of subdevs crm created
+ *
+ */
+static void __cam_req_mgr_destroy_subdev(
+ struct cam_req_mgr_connected_device *l_device)
+{
+ kfree(l_device);
+ l_device = NULL;
+}
+
+/**
+ * __cam_req_mgr_destroy_link_info()
+ *
+ * @brief : Cleans up the mem allocated while linking
+ * @link : pointer to link, mem associated with this link is freed
+ *
+ */
+static void __cam_req_mgr_destroy_link_info(struct cam_req_mgr_core_link *link)
+{
+ int32_t i = 0;
+ struct cam_req_mgr_connected_device *dev;
+ struct cam_req_mgr_core_dev_link_setup link_data;
+
+ mutex_lock(&link->lock);
+
+ link_data.link_enable = 0;
+ link_data.link_hdl = link->link_hdl;
+ link_data.crm_cb = NULL;
+
+ /* Using device ops unlink devices */
+ for (i = 0; i < link->num_devs; i++) {
+ dev = &link->l_dev[i];
+ if (dev != NULL) {
+ if (dev->ops && dev->ops->link_setup)
+ dev->ops->link_setup(&link_data);
+ dev->dev_hdl = 0;
+ dev->parent = NULL;
+ dev->ops = NULL;
+ }
+ }
+ __cam_req_mgr_destroy_all_tbl(&link->req.l_tbl);
+ __cam_req_mgr_reset_in_q(&link->req);
+ link->req.num_tbl = 0;
+ mutex_destroy(&link->req.lock);
+
+ link->pd_mask = 0;
+ link->num_devs = 0;
+ link->max_delay = 0;
+
+ mutex_unlock(&link->lock);
+}
+
+/**
+ * __cam_req_mgr_reserve_link()
+ *
+ * @brief: Reserves one link data struct within session
+ * @session: session identifier
+ *
+ * @return: pointer to link reserved
+ *
+ */
+static struct cam_req_mgr_core_link *__cam_req_mgr_reserve_link(
+ struct cam_req_mgr_core_session *session)
+{
+ struct cam_req_mgr_core_link *link;
+ struct cam_req_mgr_req_queue *in_q;
+
+ if (!session || !g_crm_core_dev) {
+ CRM_ERR("NULL session/core_dev ptr");
return NULL;
}
- spin_lock(&session->lock);
- for (i = 0; i < MAX_LINKS_PER_SESSION; i++) {
- link = &session->links[i];
- spin_lock(&link->lock);
- if (link->link_hdl == link_hdl) {
- CRM_DBG("Link found p_delay %d",
- link->max_pipeline_delay);
- spin_unlock(&link->lock);
- break;
- }
- spin_unlock(&link->lock);
+ if (session->num_links >= MAX_LINKS_PER_SESSION) {
+ CRM_ERR("Reached max links %d per session limit %d",
+ session->num_links, MAX_LINKS_PER_SESSION);
+ return NULL;
}
- if (i >= MAX_LINKS_PER_SESSION)
- link = NULL;
- spin_unlock(&session->lock);
+
+ link = (struct cam_req_mgr_core_link *)
+ kzalloc(sizeof(struct cam_req_mgr_core_link), GFP_KERNEL);
+ if (!link) {
+ CRM_ERR("failed to create link, no mem");
+ return NULL;
+ }
+ in_q = &session->in_q;
+ mutex_init(&link->lock);
+
+ mutex_lock(&link->lock);
+ link->state = CAM_CRM_LINK_STATE_AVAILABLE;
+ link->num_devs = 0;
+ link->max_delay = 0;
+ memset(in_q->slot, 0,
+ sizeof(struct cam_req_mgr_slot) * MAX_REQ_SLOTS);
+ link->req.in_q = in_q;
+ in_q->num_slots = 0;
+ link->state = CAM_CRM_LINK_STATE_IDLE;
+ link->parent = (void *)session;
+ mutex_unlock(&link->lock);
+
+ mutex_lock(&session->lock);
+ session->links[session->num_links] = link;
+ session->num_links++;
+ CRM_DBG("Active session links (%d)",
+ session->num_links);
+ mutex_unlock(&session->lock);
return link;
}
/**
+ * __cam_req_mgr_reserve_link()
+ *
+ * @brief : Reserves one link data struct within session
+ * @session: session identifier
+ * @link : link identifier
+ *
+ */
+static void __cam_req_mgr_unreserve_link(
+ struct cam_req_mgr_core_session *session,
+ struct cam_req_mgr_core_link **link)
+{
+ int32_t i = 0;
+
+ if (!session || !*link) {
+ CRM_ERR("NULL session/link ptr %pK %pK",
+ session, *link);
+ return;
+ }
+
+ mutex_lock(&session->lock);
+ if (!session->num_links)
+ CRM_WARN("No active link or invalid state %d",
+ session->num_links);
+ else {
+ for (i = 0; i < session->num_links; i++) {
+ if (session->links[i] == *link)
+ session->links[i] = NULL;
+ }
+ session->num_links--;
+ CRM_DBG("Active session links (%d)",
+ session->num_links);
+ }
+ kfree(*link);
+ *link = NULL;
+ mutex_unlock(&session->lock);
+
+}
+
+/* Workqueue context processing section */
+
+/**
+ * cam_req_mgr_process_send_req()
+ *
+ * @brief: This runs in workque thread context. Call core funcs to send
+ * apply request id to drivers.
+ * @priv : link information.
+ * @data : contains information about frame_id, link etc.
+ *
+ * @return: 0 on success.
+ */
+int cam_req_mgr_process_send_req(void *priv, void *data)
+{
+ int rc = 0;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_send_request *send_req = NULL;
+ struct cam_req_mgr_req_queue *in_q = NULL;
+
+ if (!data || !priv) {
+ CRM_ERR("input args NULL %pK %pK", data, priv);
+ rc = -EINVAL;
+ goto end;
+ }
+ link = (struct cam_req_mgr_core_link *)priv;
+ send_req = (struct cam_req_mgr_send_request *)data;
+ in_q = send_req->in_q;
+
+ rc = __cam_req_mgr_send_req(link, in_q);
+end:
+ return rc;
+}
+
+/**
+ * cam_req_mgr_process_flush_req()
+ *
+ * @brief: This runs in workque thread context. Call core funcs to check
+ * which requests need to be removedcancelled.
+ * @priv : link information.
+ * @data : contains information about frame_id, link etc.
+ *
+ * @return: 0 on success.
+ */
+int cam_req_mgr_process_flush_req(void *priv, void *data)
+{
+ int rc = 0, i = 0, idx = -1;
+ struct cam_req_mgr_flush_info *flush_info = NULL;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_req_queue *in_q = NULL;
+ struct cam_req_mgr_slot *slot = NULL;
+ struct cam_req_mgr_connected_device *device = NULL;
+ struct cam_req_mgr_flush_request flush_req;
+ struct crm_task_payload *task_data = NULL;
+
+ if (!data || !priv) {
+ CRM_ERR("input args NULL %pK %pK", data, priv);
+ rc = -EINVAL;
+ goto end;
+ }
+ link = (struct cam_req_mgr_core_link *)priv;
+ task_data = (struct crm_task_payload *)data;
+ flush_info = (struct cam_req_mgr_flush_info *)&task_data->u;
+ CRM_DBG("link_hdl %x req_id %lld type %d",
+ flush_info->link_hdl,
+ flush_info->req_id,
+ flush_info->flush_type);
+
+ in_q = link->req.in_q;
+
+ mutex_lock(&link->req.lock);
+ if (flush_info->flush_type == CAM_REQ_MGR_FLUSH_TYPE_ALL) {
+ for (i = 0; i < in_q->num_slots; i++) {
+ slot = &in_q->slot[i];
+ slot->req_id = -1;
+ slot->skip_idx = 1;
+ slot->status = CRM_SLOT_STATUS_NO_REQ;
+ }
+ in_q->wr_idx = 0;
+ in_q->rd_idx = 0;
+ } else if (flush_info->flush_type ==
+ CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) {
+ idx = __cam_req_mgr_find_slot_for_req(in_q, flush_info->req_id);
+ if (idx < 0) {
+ CRM_ERR("req_id %lld not found in input queue",
+ flush_info->req_id);
+ } else {
+ CRM_DBG("req_id %lld found at idx %d",
+ flush_info->req_id, idx);
+ slot = &in_q->slot[idx];
+ if (slot->status == CRM_SLOT_STATUS_REQ_PENDING ||
+ slot->status == CRM_SLOT_STATUS_REQ_APPLIED) {
+ CRM_WARN("req_id %lld can not be cancelled",
+ flush_info->req_id);
+ mutex_unlock(&link->req.lock);
+ return -EINVAL;
+ }
+ __cam_req_mgr_in_q_skip_idx(in_q, idx);
+ }
+ }
+
+ for (i = 0; i < link->num_devs; i++) {
+ device = &link->l_dev[i];
+ flush_req.link_hdl = flush_info->link_hdl;
+ flush_req.dev_hdl = device->dev_hdl;
+ flush_req.req_id = flush_info->req_id;
+ flush_req.type = flush_info->flush_type;
+ /* @TODO: error return handling from drivers */
+ if (device->ops && device->ops->flush_req)
+ rc = device->ops->flush_req(&flush_req);
+ }
+ mutex_unlock(&link->req.lock);
+
+ complete(&link->workq_comp);
+end:
+ return rc;
+}
+
+/**
+ * cam_req_mgr_process_sched_req()
+ *
+ * @brief: This runs in workque thread context. Call core funcs to check
+ * which peding requests can be processed.
+ * @priv : link information.
+ * @data : contains information about frame_id, link etc.
+ *
+ * @return: 0 on success.
+ */
+int cam_req_mgr_process_sched_req(void *priv, void *data)
+{
+ int rc = 0;
+ struct cam_req_mgr_sched_request *sched_req = NULL;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_req_queue *in_q = NULL;
+ struct cam_req_mgr_slot *slot = NULL;
+ struct crm_task_payload *task_data = NULL;
+
+ if (!data || !priv) {
+ CRM_ERR("input args NULL %pK %pK", data, priv);
+ rc = -EINVAL;
+ goto end;
+ }
+ link = (struct cam_req_mgr_core_link *)priv;
+ task_data = (struct crm_task_payload *)data;
+ sched_req = (struct cam_req_mgr_sched_request *)&task_data->u;
+ CRM_DBG("link_hdl %x req_id %lld",
+ sched_req->link_hdl,
+ sched_req->req_id);
+
+ in_q = link->req.in_q;
+
+ mutex_lock(&link->req.lock);
+ slot = &in_q->slot[in_q->wr_idx];
+
+ if (slot->status != CRM_SLOT_STATUS_NO_REQ &&
+ slot->status != CRM_SLOT_STATUS_REQ_APPLIED) {
+ CRM_ERR("in_q overwrite %d", slot->status);
+ /* @TODO: error handling */
+ }
+ CRM_DBG("sched_req %lld at slot %d",
+ sched_req->req_id, in_q->wr_idx);
+
+ slot->status = CRM_SLOT_STATUS_REQ_ADDED;
+ slot->req_id = sched_req->req_id;
+ slot->skip_idx = 0;
+ slot->recover = sched_req->bubble_enable;
+ __cam_req_mgr_inc_idx(&in_q->wr_idx, 1, in_q->num_slots);
+ mutex_unlock(&link->req.lock);
+
+ complete(&link->workq_comp);
+end:
+ return rc;
+}
+
+/**
+ * cam_req_mgr_process_add_req()
+ *
+ * @brief: This runs in workque thread context. Call core funcs to check
+ * which peding requests can be processed.
+ * @priv : link information.
+ * @data : contains information about frame_id, link etc.
+ *
+ * @return: 0 on success.
+ */
+int cam_req_mgr_process_add_req(void *priv, void *data)
+{
+ int rc = 0, i = 0, idx;
+ struct cam_req_mgr_add_request *add_req = NULL;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_connected_device *device = NULL;
+ struct cam_req_mgr_req_tbl *tbl = NULL;
+ struct cam_req_mgr_tbl_slot *slot = NULL;
+ struct crm_task_payload *task_data = NULL;
+
+ if (!data || !priv) {
+ CRM_ERR("input args NULL %pK %pK", data, priv);
+ rc = -EINVAL;
+ goto end;
+ }
+
+ link = (struct cam_req_mgr_core_link *)priv;
+ task_data = (struct crm_task_payload *)data;
+ add_req = (struct cam_req_mgr_add_request *)&task_data->u;
+
+ for (i = 0; i < link->num_devs; i++) {
+ device = &link->l_dev[i];
+ if (device->dev_hdl == add_req->dev_hdl) {
+ tbl = device->pd_tbl;
+ break;
+ }
+ }
+ if (!tbl) {
+ CRM_ERR("dev_hdl not found %x, %x %x",
+ add_req->dev_hdl,
+ link->l_dev[0].dev_hdl,
+ link->l_dev[1].dev_hdl);
+ rc = -EINVAL;
+ goto end;
+ }
+ /*
+ * Go through request table and add
+ * request id to proper table
+ * 1. find req slot in in_q matching req_id.sent by dev
+ * 2. goto table of this device based on p_delay
+ * 3. mark req_ready_map with this dev_bit.
+ */
+
+ mutex_lock(&link->req.lock);
+ idx = __cam_req_mgr_find_slot_for_req(link->req.in_q, add_req->req_id);
+ if (idx < 0) {
+ CRM_ERR("req %lld not found in in_q", add_req->req_id);
+ rc = -EBADSLT;
+ mutex_unlock(&link->req.lock);
+ goto end;
+ }
+ slot = &tbl->slot[idx];
+ if (slot->state != CRM_REQ_STATE_PENDING &&
+ slot->state != CRM_REQ_STATE_EMPTY) {
+ CRM_WARN("Unexpected state %d for slot %d map %x",
+ slot->state, idx, slot->req_ready_map);
+ }
+
+ slot->state = CRM_REQ_STATE_PENDING;
+ slot->req_ready_map |= (1 << device->dev_bit);
+
+ CRM_DBG("idx %d dev_hdl %x req_id %lld pd %d ready_map %x",
+ idx, add_req->dev_hdl, add_req->req_id, tbl->pd,
+ slot->req_ready_map);
+
+ if (slot->req_ready_map == tbl->dev_mask) {
+ CRM_DBG("idx %d req_id %lld pd %d SLOT READY",
+ idx, add_req->req_id, tbl->pd);
+ slot->state = CRM_REQ_STATE_READY;
+ }
+ mutex_unlock(&link->req.lock);
+
+end:
+ return rc;
+}
+
+/**
+ * cam_req_mgr_process_error()
+ *
+ * @brief: This runs in workque thread context. bubble /err recovery.
+ * @priv : link information.
+ * @data : contains information about frame_id, link etc.
+ *
+ * @return: 0 on success.
+ */
+int cam_req_mgr_process_error(void *priv, void *data)
+{
+ int rc = 0, idx = -1, i;
+ struct cam_req_mgr_error_notify *err_info = NULL;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_req_queue *in_q = NULL;
+ struct cam_req_mgr_slot *slot = NULL;
+ struct cam_req_mgr_connected_device *device = NULL;
+ struct cam_req_mgr_link_evt_data evt_data;
+ struct crm_task_payload *task_data = NULL;
+
+ if (!data || !priv) {
+ CRM_ERR("input args NULL %pK %pK", data, priv);
+ rc = -EINVAL;
+ goto end;
+ }
+ link = (struct cam_req_mgr_core_link *)priv;
+ task_data = (struct crm_task_payload *)data;
+ err_info = (struct cam_req_mgr_error_notify *)&task_data->u;
+ CRM_DBG("link_hdl %x req_id %lld error %d",
+ err_info->link_hdl,
+ err_info->req_id,
+ err_info->error);
+
+ in_q = link->req.in_q;
+
+ mutex_lock(&link->req.lock);
+ if (err_info->error == CRM_KMD_ERR_BUBBLE) {
+ idx = __cam_req_mgr_find_slot_for_req(in_q, err_info->req_id);
+ if (idx < 0) {
+ CRM_ERR("req_id %lld not found in input queue",
+ err_info->req_id);
+ } else {
+ CRM_DBG("req_id %lld found at idx %d",
+ err_info->req_id, idx);
+ slot = &in_q->slot[idx];
+ if (!slot->recover) {
+ CRM_WARN("err recovery disabled req_id %lld",
+ err_info->req_id);
+ mutex_unlock(&link->req.lock);
+ return 0;
+ } else if (slot->status != CRM_SLOT_STATUS_REQ_PENDING
+ && slot->status != CRM_SLOT_STATUS_REQ_APPLIED) {
+ CRM_WARN("req_id %lld can not be recovered %d",
+ err_info->req_id, slot->status);
+ mutex_unlock(&link->req.lock);
+ return -EINVAL;
+ }
+ /* Notify all devices in the link about error */
+ for (i = 0; i < link->num_devs; i++) {
+ device = &link->l_dev[i];
+ if (device != NULL) {
+ evt_data.dev_hdl = device->dev_hdl;
+ evt_data.evt_type =
+ CAM_REQ_MGR_LINK_EVT_ERR;
+ evt_data.link_hdl = link->link_hdl;
+ evt_data.req_id = err_info->req_id;
+ evt_data.u.error = err_info->error;
+ if (device->ops &&
+ device->ops->process_evt)
+ rc = device->ops->
+ process_evt(&evt_data);
+ }
+ }
+ /* Bring processing pointer to bubbled req id */
+ __cam_req_mgr_tbl_set_all_skip_cnt(&link->req.l_tbl);
+ in_q->rd_idx = idx;
+ in_q->slot[idx].status = CRM_SLOT_STATUS_REQ_ADDED;
+ mutex_lock(&link->lock);
+ link->state = CAM_CRM_LINK_STATE_ERR;
+ mutex_unlock(&link->lock);
+ }
+ }
+ mutex_unlock(&link->req.lock);
+
+end:
+ return rc;
+}
+
+/**
* cam_req_mgr_process_sof()
*
* @brief: This runs in workque thread context. Call core funcs to check
- * which peding requests can be processed.
- * @data:contains information about frame_id, link etc.
+ * which peding requests can be processed.
+ * @priv : link information.
+ * @data : contains information about frame_id, link etc.
*
- * Returns 0 on success.
+ * @return: 0 on success.
*/
static int cam_req_mgr_process_sof(void *priv, void *data)
{
- int ret = 0, i = 0;
- struct cam_req_mgr_sof_notify *sof_data = NULL;
- struct cam_req_mgr_core_link *link = NULL;
- struct cam_req_mgr_connected_device *device = NULL;
- struct cam_req_mgr_apply_request apply_req;
+ int rc = 0;
+ struct cam_req_mgr_sof_notify *sof_data = NULL;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_req_queue *in_q = NULL;
+ struct crm_task_payload *task_data = NULL;
if (!data || !priv) {
CRM_ERR("input args NULL %pK %pK", data, priv);
- ret = -EINVAL;
+ rc = -EINVAL;
goto end;
}
link = (struct cam_req_mgr_core_link *)priv;
- sof_data = (struct cam_req_mgr_sof_notify *)data;
+ task_data = (struct crm_task_payload *)data;
+ sof_data = (struct cam_req_mgr_sof_notify *)&task_data->u;
CRM_DBG("link_hdl %x frame_id %lld",
sof_data->link_hdl,
sof_data->frame_id);
- apply_req.link_hdl = sof_data->link_hdl;
- /* @TODO: go through request table and issue
- * request id based on dev status
+ in_q = link->req.in_q;
+
+ mutex_lock(&link->req.lock);
+ /*
+ * Check if current read index is in applied state, if yes make it free
+ * and increment read index to next slot.
*/
- apply_req.request_id = sof_data->frame_id;
- apply_req.report_if_bubble = 0;
+ CRM_DBG("link_hdl %x curent idx %d req_status %d",
+ link->link_hdl, in_q->rd_idx, in_q->slot[in_q->rd_idx].status);
- CRM_DBG("link %pK l_dev %pK num_dev %d",
- link, link->l_devices, link->num_connections);
- for (i = 0; i < link->num_connections; i++) {
- device = &link->l_devices[i];
- if (device != NULL) {
- CRM_DBG("dev_id %d dev_hdl %x ops %pK p_delay %d",
- device->dev_info.dev_id, device->dev_hdl,
- device->ops, device->dev_info.p_delay);
- apply_req.dev_hdl = device->dev_hdl;
- if (device->ops && device->ops->apply_req) {
- ret = device->ops->apply_req(&apply_req);
- /* Error handling for this failure is pending */
- if (ret < 0)
- CRM_ERR("Failure:%d dev=%d", ret,
- device->dev_info.dev_id);
- }
+ if (link->state == CAM_CRM_LINK_STATE_ERR)
+ CRM_WARN("Error recovery idx %d status %d",
+ in_q->rd_idx,
+ in_q->slot[in_q->rd_idx].status);
- }
+ if (in_q->slot[in_q->rd_idx].status == CRM_SLOT_STATUS_REQ_APPLIED) {
+ /*
+ * Do NOT reset req q slot data here, it can not be done
+ * here because we need to preserve the data to handle bubble.
+ */
+ __cam_req_mgr_inc_idx(&in_q->rd_idx, 1, in_q->num_slots);
}
+ rc = __cam_req_mgr_process_req(link);
+ mutex_unlock(&link->req.lock);
end:
- return ret;
+ return rc;
}
-/**
- * cam_req_mgr_notify_sof()
- *
- * @brief: SOF received from device, sends trigger through workqueue
- * @sof_data: contains information about frame_id, link etc.
- *
- * Returns 0 on success
- */
-static int cam_req_mgr_cb_notify_sof(struct cam_req_mgr_sof_notify *sof_data)
-{
- int ret = 0;
- struct crm_workq_task *task = NULL;
- struct cam_req_mgr_core_link *link = NULL;
- if (!sof_data) {
+/* Linked devices' Callback section */
+
+/**
+ * cam_req_mgr_cb_add_req()
+ *
+ * @brief : Drivers call this function to notify new packet is available.
+ * @add_req : Information about new request available at a device.
+ *
+ * @return : 0 on success, negative in case of failure
+ *
+ */
+static int cam_req_mgr_cb_add_req(struct cam_req_mgr_add_request *add_req)
+{
+ int rc = 0, idx;
+ struct crm_workq_task *task = NULL;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_add_request *dev_req;
+ struct crm_task_payload *task_data;
+
+ if (!add_req) {
CRM_ERR("sof_data is NULL");
- ret = -EINVAL;
+ rc = -EINVAL;
goto end;
}
- CRM_DBG("link_hdl %x frame_id %lld",
- sof_data->link_hdl,
- sof_data->frame_id);
+ link = (struct cam_req_mgr_core_link *)
+ cam_get_device_priv(add_req->link_hdl);
+
+ if (!link) {
+ CRM_DBG("link ptr NULL %x", add_req->link_hdl);
+ rc = -EINVAL;
+ goto end;
+ }
+
+ /* Validate if req id is present in input queue */
+ idx = __cam_req_mgr_find_slot_for_req(link->req.in_q, add_req->req_id);
+ if (idx < 0) {
+ CRM_ERR("req %lld not found in in_q", add_req->req_id);
+ rc = -ENOENT;
+ goto end;
+ }
+
+ task = cam_req_mgr_workq_get_task(link->workq);
+ if (!task) {
+ CRM_ERR("no empty task dev %x req %lld",
+ add_req->dev_hdl, add_req->req_id);
+ rc = -EBUSY;
+ goto end;
+ }
+
+ task_data = (struct crm_task_payload *)task->payload;
+ task_data->type = CRM_WORKQ_TASK_DEV_ADD_REQ;
+ dev_req = (struct cam_req_mgr_add_request *)&task_data->u;
+ dev_req->req_id = add_req->req_id;
+ dev_req->link_hdl = add_req->link_hdl;
+ dev_req->dev_hdl = add_req->dev_hdl;
+ task->process_cb = &cam_req_mgr_process_add_req;
+ rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0);
+
+end:
+ return rc;
+}
+
+/**
+ * cam_req_mgr_cb_notify_err()
+ *
+ * @brief : Error received from device, sends bubble recovery
+ * @err_info : contains information about error occurred like bubble/overflow
+ *
+ * @return : 0 on success, negative in case of failure
+ *
+ */
+static int cam_req_mgr_cb_notify_err(
+ struct cam_req_mgr_error_notify *err_info)
+{
+ int rc = 0;
+ struct crm_workq_task *task = NULL;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_error_notify *notify_err;
+ struct crm_task_payload *task_data;
+
+ if (!err_info) {
+ CRM_ERR("err_info is NULL");
+ rc = -EINVAL;
+ goto end;
+ }
+
+ link = (struct cam_req_mgr_core_link *)
+ cam_get_device_priv(err_info->link_hdl);
+ if (!link) {
+ CRM_DBG("link ptr NULL %x", err_info->link_hdl);
+ rc = -EINVAL;
+ goto end;
+ }
+
+ crm_timer_reset(link->watchdog);
+ task = cam_req_mgr_workq_get_task(link->workq);
+ if (!task) {
+ CRM_ERR("no empty task req_id %lld", err_info->req_id);
+ rc = -EBUSY;
+ goto end;
+ }
+
+ task_data = (struct crm_task_payload *)task->payload;
+ task_data->type = CRM_WORKQ_TASK_NOTIFY_ERR;
+ notify_err = (struct cam_req_mgr_error_notify *)&task_data->u;
+ notify_err->req_id = err_info->req_id;
+ notify_err->link_hdl = err_info->link_hdl;
+ notify_err->dev_hdl = err_info->dev_hdl;
+ notify_err->error = err_info->error;
+ task->process_cb = &cam_req_mgr_process_error;
+ rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0);
+
+end:
+ return rc;
+}
+
+/**
+ * cam_req_mgr_cb_notify_sof()
+ *
+ * @brief : SOF received from device, sends trigger through workqueue
+ * @sof_data: contains information about frame_id, link etc.
+ *
+ * @return : 0 on success
+ *
+ */
+static int cam_req_mgr_cb_notify_sof(
+ struct cam_req_mgr_sof_notify *sof_data)
+{
+ int rc = 0;
+ struct crm_workq_task *task = NULL;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_sof_notify *notify_sof;
+ struct crm_task_payload *task_data;
+
+ if (!sof_data) {
+ CRM_ERR("sof_data is NULL");
+ rc = -EINVAL;
+ goto end;
+ }
link = (struct cam_req_mgr_core_link *)
cam_get_device_priv(sof_data->link_hdl);
if (!link) {
CRM_DBG("link ptr NULL %x", sof_data->link_hdl);
- ret = -EINVAL;
+ rc = -EINVAL;
goto end;
-
}
+ crm_timer_reset(link->watchdog);
task = cam_req_mgr_workq_get_task(link->workq);
if (!task) {
CRM_ERR("no empty task frame %lld", sof_data->frame_id);
- ret = -EBUSY;
+ rc = -EBUSY;
goto end;
}
- task->type = CRM_WORKQ_TASK_NOTIFY_SOF;
- task->u.notify_sof.frame_id = sof_data->frame_id;
- task->u.notify_sof.link_hdl = sof_data->link_hdl;
- task->u.notify_sof.dev_hdl = sof_data->dev_hdl;
+ task_data = (struct crm_task_payload *)task->payload;
+ task_data->type = CRM_WORKQ_TASK_NOTIFY_SOF;
+ notify_sof = (struct cam_req_mgr_sof_notify *)&task_data->u;
+ notify_sof->frame_id = sof_data->frame_id;
+ notify_sof->link_hdl = sof_data->link_hdl;
+ notify_sof->dev_hdl = sof_data->dev_hdl;
task->process_cb = &cam_req_mgr_process_sof;
- task->priv = link;
- cam_req_mgr_workq_enqueue_task(task);
+ rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0);
end:
- return ret;
+ return rc;
}
+static struct cam_req_mgr_crm_cb cam_req_mgr_ops = {
+ .notify_sof = cam_req_mgr_cb_notify_sof,
+ .notify_err = cam_req_mgr_cb_notify_err,
+ .add_req = cam_req_mgr_cb_add_req,
+};
+
/**
- * cam_req_mgr_pvt_reserve_link()
+ * __cam_req_mgr_setup_link_info()
*
- * @brief: Reserves one link data struct within session
- * @session: session identifier
+ * @brief : Sets up input queue, create pd based tables, communicate with
+ * devs connected on this link and setup communication.
+ * @link : pointer to link to setup
+ * @link_info : link_info coming from CSL to prepare link
*
- * Returns pointer to link reserved
+ * @return : 0 on success, negative in case of failure
+ *
*/
-static struct cam_req_mgr_core_link *cam_req_mgr_pvt_reserve_link(
- struct cam_req_mgr_core_session *session)
+static int __cam_req_mgr_setup_link_info(struct cam_req_mgr_core_link *link,
+ struct cam_req_mgr_link_info *link_info)
{
- int32_t i;
- struct cam_req_mgr_core_link *link;
+ int rc = 0, i = 0;
+ struct cam_req_mgr_core_dev_link_setup link_data;
+ struct cam_req_mgr_connected_device *dev;
+ struct cam_req_mgr_req_tbl *pd_tbl;
+ enum cam_pipeline_delay max_delay;
- if (!session) {
- CRM_ERR("NULL session ptr");
- return NULL;
- }
+ if (link_info->num_devices > CAM_REQ_MGR_MAX_HANDLES)
+ return -EPERM;
- spin_lock(&session->lock);
- for (i = 0; i < MAX_LINKS_PER_SESSION; i++) {
- link = &session->links[i];
- spin_lock(&link->lock);
- if (link->link_state == CAM_CRM_LINK_STATE_AVAILABLE) {
- link->num_connections = 0;
- link->max_pipeline_delay = 0;
- memset(link->req_table, 0,
- sizeof(struct cam_req_mgr_request_table));
- link->link_state = CAM_CRM_LINK_STATE_IDLE;
- spin_unlock(&link->lock);
- break;
+ mutex_init(&link->req.lock);
+ CRM_DBG("LOCK_DBG in_q lock %pK", &link->req.lock);
+ link->req.num_tbl = 0;
+
+ rc = __cam_req_mgr_setup_in_q(&link->req);
+ if (rc < 0)
+ return rc;
+
+ mutex_lock(&link->lock);
+ max_delay = CAM_PIPELINE_DELAY_0;
+ for (i = 0; i < link_info->num_devices; i++) {
+ dev = &link->l_dev[i];
+ /* Using dev hdl, get ops ptr to communicate with device */
+ dev->ops = (struct cam_req_mgr_kmd_ops *)
+ cam_get_device_ops(link_info->dev_hdls[i]);
+ if (!dev->ops ||
+ !dev->ops->get_dev_info ||
+ !dev->ops->link_setup) {
+ CRM_ERR("FATAL: device ops NULL");
+ rc = -ENXIO;
+ goto error;
}
- spin_unlock(&link->lock);
- }
- CRM_DBG("Link available (total %d)", session->num_active_links);
- spin_unlock(&session->lock);
-
- if (i >= MAX_LINKS_PER_SESSION)
- link = NULL;
-
- return link;
-}
-
-/**
- * cam_req_mgr_pvt_create_subdevs()
- *
- * @brief: Create new crm subdev to link with realtime devices
- * @l_devices: list of subdevs internal to crm
- * @num_dev: num of subdevs to be created for link
- *
- * Returns pointer to allocated list of devices
- */
-static struct cam_req_mgr_connected_device *
- cam_req_mgr_pvt_create_subdevs(int32_t num_dev)
-{
- struct cam_req_mgr_connected_device *l_devices;
-
- l_devices = (struct cam_req_mgr_connected_device *)
- kzalloc(sizeof(struct cam_req_mgr_connected_device) * num_dev,
- GFP_KERNEL);
- if (!l_devices)
- CRM_DBG("Insufficient memory %lu",
- sizeof(struct cam_req_mgr_connected_device) * num_dev);
-
- return l_devices;
-}
-
-/**
- * cam_req_mgr_pvt_destroy_subdev()
- *
- * @brief: Cleans up the subdevs allocated by crm for link
- * @l_device: pointer to list of subdevs crm created
- *
- * Returns 0 for success
- */
-static int cam_req_mgr_pvt_destroy_subdev(
- struct cam_req_mgr_connected_device **l_device)
-{
- int ret = 0;
-
- if (!(*l_device))
- ret = -EINVAL;
- else {
- kfree(*l_device);
- *l_device = NULL;
+ dev->dev_hdl = link_info->dev_hdls[i];
+ dev->parent = (void *)link;
+ dev->dev_info.dev_hdl = dev->dev_hdl;
+ rc = dev->ops->get_dev_info(&dev->dev_info);
+ CRM_DBG("%x: connected: %s, id %d, delay %d",
+ link_info->session_hdl, dev->dev_info.name,
+ dev->dev_info.dev_id, dev->dev_info.p_delay);
+ if (rc < 0 ||
+ dev->dev_info.p_delay >=
+ CAM_PIPELINE_DELAY_MAX ||
+ dev->dev_info.p_delay <
+ CAM_PIPELINE_DELAY_0) {
+ CRM_ERR("get device info failed");
+ goto error;
+ } else {
+ CRM_DBG("%x: connected: %s, delay %d",
+ link_info->session_hdl,
+ dev->dev_info.name,
+ dev->dev_info.p_delay);
+ if (dev->dev_info.p_delay >
+ max_delay)
+ max_delay =
+ dev->dev_info.p_delay;
+ }
}
- return ret;
+
+ link_data.link_enable = 1;
+ link_data.link_hdl = link->link_hdl;
+ link_data.crm_cb = &cam_req_mgr_ops;
+ link_data.max_delay = max_delay;
+
+ for (i = 0; i < link_info->num_devices; i++) {
+ dev = &link->l_dev[i];
+
+ link_data.dev_hdl = dev->dev_hdl;
+ /*
+ * For unique pipeline delay table create request
+ * tracking table
+ */
+ if (link->pd_mask & (1 << dev->dev_info.p_delay)) {
+ pd_tbl = __cam_req_mgr_find_pd_tbl(link->req.l_tbl,
+ dev->dev_info.p_delay);
+ if (!pd_tbl) {
+ CRM_ERR("pd %d tbl not found",
+ dev->dev_info.p_delay);
+ rc = -ENXIO;
+ goto error;
+ }
+ } else {
+ pd_tbl = __cam_req_mgr_create_pd_tbl(
+ dev->dev_info.p_delay);
+ if (pd_tbl == NULL) {
+ CRM_ERR("create new pd tbl failed");
+ rc = -ENXIO;
+ goto error;
+ }
+ pd_tbl->pd = dev->dev_info.p_delay;
+ link->pd_mask |= (1 << pd_tbl->pd);
+ /*
+ * Add table to list and also sort list
+ * from max pd to lowest
+ */
+ __cam_req_mgr_add_tbl_to_link(&link->req.l_tbl, pd_tbl);
+ }
+ dev->dev_bit = pd_tbl->dev_count++;
+ dev->pd_tbl = pd_tbl;
+ pd_tbl->dev_mask |= (1 << dev->dev_bit);
+
+ /* Communicate with dev to establish the link */
+ dev->ops->link_setup(&link_data);
+
+ if (link->max_delay < dev->dev_info.p_delay)
+ link->max_delay = dev->dev_info.p_delay;
+ }
+ link->num_devs = link_info->num_devices;
+
+ /* Assign id for pd tables */
+ __cam_req_mgr_tbl_set_id(link->req.l_tbl, &link->req);
+
+ /* At start, expect max pd devices, all are in skip state */
+ __cam_req_mgr_tbl_set_all_skip_cnt(&link->req.l_tbl);
+
+ mutex_unlock(&link->lock);
+ return 0;
+
+error:
+ __cam_req_mgr_destroy_link_info(link);
+ return rc;
}
+/* IOCTLs handling section */
int cam_req_mgr_create_session(
struct cam_req_mgr_session_info *ses_info)
{
- int ret = 0;
- int32_t i;
- int32_t session_hdl;
- struct cam_req_mgr_core_session *cam_session;
+ int rc = 0;
+ int32_t session_hdl;
+ struct cam_req_mgr_core_session *cam_session = NULL;
if (!ses_info) {
- CRM_ERR("NULL session info pointer");
+ CRM_DBG("NULL session info pointer");
return -EINVAL;
}
mutex_lock(&g_crm_core_dev->crm_lock);
cam_session = (struct cam_req_mgr_core_session *)
kzalloc(sizeof(*cam_session), GFP_KERNEL);
if (!cam_session) {
- ret = -ENOMEM;
+ rc = -ENOMEM;
goto end;
}
session_hdl = cam_create_session_hdl((void *)cam_session);
if (session_hdl < 0) {
CRM_ERR("unable to create session_hdl = %x", session_hdl);
- ret = session_hdl;
- goto session_hdl_failed;
+ rc = session_hdl;
+ kfree(cam_session);
+ goto end;
}
ses_info->session_hdl = session_hdl;
+
+ mutex_init(&cam_session->lock);
+ CRM_DBG("LOCK_DBG session lock %pK", &cam_session->lock);
+
+ mutex_lock(&cam_session->lock);
cam_session->session_hdl = session_hdl;
-
- spin_lock_init(&cam_session->lock);
- cam_session->num_active_links = 0;
-
- for (i = 0; i < MAX_LINKS_PER_SESSION; i++) {
- spin_lock_init(&cam_session->links[i].lock);
- cam_session->links[i].link_state = CAM_CRM_LINK_STATE_AVAILABLE;
- INIT_LIST_HEAD(&cam_session->links[i].link_head);
- cam_session->links[i].workq = NULL;
- }
+ cam_session->num_links = 0;
list_add(&cam_session->entry, &g_crm_core_dev->session_head);
-
- mutex_unlock(&g_crm_core_dev->crm_lock);
- return ret;
-
-session_hdl_failed:
- kfree(cam_session);
+ mutex_unlock(&cam_session->lock);
end:
mutex_unlock(&g_crm_core_dev->crm_lock);
- return ret;
+ return rc;
}
int cam_req_mgr_destroy_session(
struct cam_req_mgr_session_info *ses_info)
{
- int ret;
- int32_t i;
- struct cam_req_mgr_core_session *cam_session;
- struct cam_req_mgr_core_link *link = NULL;
+ int rc;
+ struct cam_req_mgr_core_session *cam_session = NULL;
if (!ses_info) {
- CRM_ERR("NULL session info pointer");
+ CRM_DBG("NULL session info pointer");
return -EINVAL;
}
mutex_lock(&g_crm_core_dev->crm_lock);
cam_session = (struct cam_req_mgr_core_session *)
cam_get_device_priv(ses_info->session_hdl);
- if (cam_session == NULL) {
+ if (!cam_session) {
CRM_ERR("failed to get session priv");
- ret = -ENOENT;
+ rc = -ENOENT;
goto end;
}
- spin_lock(&cam_session->lock);
- for (i = 0; i < cam_session->num_active_links; i++) {
- link = &cam_session->links[i];
- CRM_ERR("session %x active_links %d hdl %x connections %d",
+ mutex_lock(&cam_session->lock);
+ if (cam_session->num_links) {
+ CRM_ERR("destroy session %x num_active_links %d",
ses_info->session_hdl,
- cam_session->num_active_links,
- link->link_hdl, link->num_connections);
+ cam_session->num_links);
+ /* @TODO : Go through active links and destroy ? */
}
list_del(&cam_session->entry);
- spin_unlock(&cam_session->lock);
+ mutex_unlock(&cam_session->lock);
+ mutex_destroy(&cam_session->lock);
kfree(cam_session);
- ret = cam_destroy_session_hdl(ses_info->session_hdl);
- if (ret)
- CRM_ERR("unable to destroy session_hdl = %x ret %d",
- ses_info->session_hdl, ret);
+ rc = cam_destroy_session_hdl(ses_info->session_hdl);
+ if (rc < 0)
+ CRM_ERR("unable to destroy session_hdl = %x rc %d",
+ ses_info->session_hdl, rc);
end:
mutex_unlock(&g_crm_core_dev->crm_lock);
- return ret;
-
+ return rc;
}
int cam_req_mgr_link(struct cam_req_mgr_link_info *link_info)
{
- int ret = 0;
- int32_t i, link_hdl;
- char buf[128];
- struct cam_create_dev_hdl root_dev;
- struct cam_req_mgr_core_session *cam_session;
- struct cam_req_mgr_core_link *link;
- struct cam_req_mgr_core_dev_link_setup link_data;
- struct cam_req_mgr_connected_device *l_devices;
- enum cam_pipeline_delay max_delay = CAM_PIPELINE_DELAY_0;
+ int rc = 0;
+ char buf[128];
+ struct cam_create_dev_hdl root_dev;
+ struct cam_req_mgr_core_session *cam_session;
+ struct cam_req_mgr_core_link *link;
if (!link_info) {
- CRM_ERR("NULL pointer");
+ CRM_DBG("NULL pointer");
return -EINVAL;
}
-
if (link_info->num_devices > CAM_REQ_MGR_MAX_HANDLES) {
CRM_ERR("Invalid num devices %d", link_info->num_devices);
return -EINVAL;
}
+ /* session hdl's priv data is cam session struct */
cam_session = (struct cam_req_mgr_core_session *)
cam_get_device_priv(link_info->session_hdl);
if (!cam_session) {
- CRM_ERR("NULL session pointer");
+ CRM_DBG("NULL pointer");
return -EINVAL;
}
- link = cam_req_mgr_pvt_reserve_link(cam_session);
+ mutex_lock(&g_crm_core_dev->crm_lock);
+
+ /* Allocate link struct and map it with session's request queue */
+ link = __cam_req_mgr_reserve_link(cam_session);
if (!link) {
- CRM_ERR("NULL link pointer");
+ CRM_ERR("failed to reserve new link");
+ mutex_unlock(&g_crm_core_dev->crm_lock);
return -EINVAL;
}
+ CRM_DBG("link reserved %pK %x", link, link->link_hdl);
memset(&root_dev, 0, sizeof(struct cam_create_dev_hdl));
root_dev.session_hdl = link_info->session_hdl;
root_dev.priv = (void *)link;
- link_hdl = cam_create_device_hdl(&root_dev);
- if (link_hdl < 0) {
+ mutex_lock(&link->lock);
+ /* Create unique dev handle for link */
+ link->link_hdl = cam_create_device_hdl(&root_dev);
+ if (link->link_hdl < 0) {
CRM_ERR("Insufficient memory to create new device handle");
- ret = link_hdl;
+ mutex_unlock(&link->lock);
+ rc = link->link_hdl;
goto link_hdl_fail;
}
+ mutex_unlock(&link->lock);
+ link_info->link_hdl = link->link_hdl;
- l_devices = cam_req_mgr_pvt_create_subdevs(link_info->num_devices);
- if (!l_devices) {
- ret = -ENOMEM;
+ /* Allocate memory to hold data of all linked devs */
+ rc = __cam_req_mgr_create_subdevs(&link->l_dev,
+ link_info->num_devices);
+ if (rc < 0) {
+ CRM_ERR("Insufficient memory to create new crm subdevs");
goto create_subdev_failed;
}
- for (i = 0; i < link_info->num_devices; i++) {
- l_devices[i].dev_hdl = link_info->dev_hdls[i];
- l_devices[i].parent = (void *)link;
- l_devices[i].ops = (struct cam_req_mgr_kmd_ops *)
- cam_get_device_ops(link_info->dev_hdls[i]);
- link_data.dev_hdl = l_devices[i].dev_hdl;
- l_devices[i].dev_info.dev_hdl = l_devices[i].dev_hdl;
- if (l_devices[i].ops) {
- if (l_devices[i].ops->get_dev_info) {
- ret = l_devices[i].ops->get_dev_info(
- &l_devices[i].dev_info);
- if (ret < 0 ||
- l_devices[i].dev_info.p_delay >=
- CAM_PIPELINE_DELAY_MAX ||
- l_devices[i].dev_info.p_delay <
- CAM_PIPELINE_DELAY_0) {
- CRM_ERR("get device info failed");
- goto error;
- } else {
- CRM_DBG("%x: connected: %s, delay %d",
- link_info->session_hdl,
- l_devices[i].dev_info.name,
- l_devices[i].dev_info.p_delay);
- if (l_devices[i].dev_info.p_delay >
- max_delay)
- max_delay =
- l_devices[i].dev_info.p_delay;
- }
- }
- } else {
- CRM_ERR("FATAL: device ops NULL");
- ret = -ENXIO;
- goto error;
- }
- }
+ /* Using device ops query connected devs, prepare request tables */
+ rc = __cam_req_mgr_setup_link_info(link, link_info);
+ if (rc < 0)
+ goto setup_failed;
- link_data.link_enable = true;
- link_data.link_hdl = link_hdl;
- link_data.crm_cb = &cam_req_mgr_ops;
- link_data.max_delay = max_delay;
-
- /* After getting info about all devices, establish link */
- for (i = 0; i < link_info->num_devices; i++) {
- l_devices[i].dev_hdl = link_info->dev_hdls[i];
- l_devices[i].parent = (void *)link;
- l_devices[i].ops = (struct cam_req_mgr_kmd_ops *)
- cam_get_device_ops(link_info->dev_hdls[i]);
- link_data.dev_hdl = l_devices[i].dev_hdl;
- l_devices[i].dev_info.dev_hdl = l_devices[i].dev_hdl;
- if (l_devices[i].ops) {
- if (l_devices[i].ops->link_setup) {
- ret = l_devices[i].ops->link_setup(&link_data);
- if (ret < 0) {
- /* TODO check handlng of this failure */
- CRM_ERR("link setup failed");
- goto error;
- }
- }
- }
- list_add_tail(&l_devices[i].entry, &link->link_head);
- }
+ mutex_lock(&link->lock);
+ link->state = CAM_CRM_LINK_STATE_READY;
+ mutex_unlock(&link->lock);
/* Create worker for current link */
- snprintf(buf, sizeof(buf), "%x-%x", link_info->session_hdl, link_hdl);
- ret = cam_req_mgr_workq_create(buf, &link->workq);
- if (ret < 0) {
+ snprintf(buf, sizeof(buf), "%x-%x",
+ link_info->session_hdl, link->link_hdl);
+ rc = cam_req_mgr_workq_create(buf, CRM_WORKQ_NUM_TASKS, &link->workq);
+ if (rc < 0) {
CRM_ERR("FATAL: unable to create worker");
- goto error;
+ __cam_req_mgr_destroy_link_info(link);
+ goto setup_failed;
}
- link_info->link_hdl = link_hdl;
- spin_lock(&link->lock);
- link->l_devices = l_devices;
- link->link_hdl = link_hdl;
- link->parent = (void *)cam_session;
- link->num_connections = link_info->num_devices;
- link->link_state = CAM_CRM_LINK_STATE_READY;
- spin_unlock(&link->lock);
+ /* Assign payload to workqueue tasks */
+ rc = __cam_req_mgr_setup_payload(link->workq);
+ if (rc < 0) {
+ __cam_req_mgr_destroy_link_info(link);
+ cam_req_mgr_workq_destroy(&link->workq);
+ goto setup_failed;
+ }
- spin_lock(&cam_session->lock);
- cam_session->num_active_links++;
- spin_unlock(&cam_session->lock);
+ /* Start watchdong timer to detect if camera hw goes into bad state */
+ rc = crm_timer_init(&link->watchdog, CAM_REQ_MGR_WATCHDOG_TIMEOUT,
+ link, &__cam_req_mgr_sof_freeze);
+ if (rc < 0) {
+ kfree(link->workq->task.pool[0].payload);
+ __cam_req_mgr_destroy_link_info(link);
+ cam_req_mgr_workq_destroy(&link->workq);
+ goto setup_failed;
+ }
- return ret;
-
-error:
- cam_req_mgr_pvt_destroy_subdev(&l_devices);
+ mutex_unlock(&g_crm_core_dev->crm_lock);
+ return rc;
+setup_failed:
+ __cam_req_mgr_destroy_subdev(link->l_dev);
create_subdev_failed:
- cam_destroy_device_hdl(link_hdl);
+ cam_destroy_device_hdl(link->link_hdl);
+ link_info->link_hdl = 0;
link_hdl_fail:
- spin_lock(&link->lock);
- link->link_state = CAM_CRM_LINK_STATE_AVAILABLE;
- spin_unlock(&link->lock);
+ mutex_lock(&link->lock);
+ link->state = CAM_CRM_LINK_STATE_AVAILABLE;
+ mutex_unlock(&link->lock);
- return ret;
+ mutex_unlock(&g_crm_core_dev->crm_lock);
+ return rc;
}
int cam_req_mgr_unlink(struct cam_req_mgr_unlink_info *unlink_info)
{
- int ret = 0;
- int32_t i = 0;
+ int rc = 0;
struct cam_req_mgr_core_session *cam_session;
- struct cam_req_mgr_core_link *link;
- struct cam_req_mgr_connected_device *device;
- struct cam_req_mgr_core_dev_link_setup link_data;
+ struct cam_req_mgr_core_link *link;
if (!unlink_info) {
CRM_ERR("NULL pointer");
return -EINVAL;
}
+
+ mutex_lock(&g_crm_core_dev->crm_lock);
+ CRM_DBG("link_hdl %x", unlink_info->link_hdl);
+
+ /* session hdl's priv data is cam session struct */
cam_session = (struct cam_req_mgr_core_session *)
- cam_get_device_priv(unlink_info->session_hdl);
+ cam_get_device_priv(unlink_info->session_hdl);
if (!cam_session) {
CRM_ERR("NULL pointer");
+ mutex_unlock(&g_crm_core_dev->crm_lock);
return -EINVAL;
}
- link = cam_req_mgr_pvt_find_link(cam_session,
- unlink_info->link_hdl);
+ /* link hdl's priv data is core_link struct */
+ link = cam_get_device_priv(unlink_info->link_hdl);
if (!link) {
CRM_ERR("NULL pointer");
+ mutex_unlock(&g_crm_core_dev->crm_lock);
return -EINVAL;
}
+ __cam_req_mgr_print_req_tbl(&link->req);
- ret = cam_destroy_device_hdl(link->link_hdl);
- if (ret < 0) {
- CRM_ERR("error in destroying dev handle %d %x",
- ret, link->link_hdl);
- ret = -EINVAL;
- }
- link_data.link_enable = false;
- link_data.link_hdl = link->link_hdl;
- link_data.crm_cb = NULL;
- for (i = 0; i < link->num_connections; i++) {
- device = &link->l_devices[i];
- link_data.dev_hdl = device->dev_hdl;
- if (device->ops && device->ops->link_setup)
- device->ops->link_setup(&link_data);
- device->dev_hdl = 0;
- device->parent = NULL;
- device->ops = NULL;
- list_del(&device->entry);
- }
- /* Destroy worker of link */
- cam_req_mgr_workq_destroy(link->workq);
- spin_lock(&link->lock);
- link->link_state = CAM_CRM_LINK_STATE_AVAILABLE;
- link->parent = NULL;
- link->num_connections = 0;
- link->link_hdl = 0;
- link->workq = NULL;
- spin_unlock(&link->lock);
+ /* Destroy workq payload data */
+ kfree(link->workq->task.pool[0].payload);
+ link->workq->task.pool[0].payload = NULL;
- spin_lock(&cam_session->lock);
- cam_session->num_active_links--;
- spin_unlock(&cam_session->lock);
+ /* Destroy workq and timer of link */
+ crm_timer_exit(&link->watchdog);
- ret = cam_req_mgr_pvt_destroy_subdev(&link->l_devices);
- if (ret < 0) {
- CRM_ERR("error while destroying subdev link %x",
- link_data.link_hdl);
- ret = -EINVAL;
+ cam_req_mgr_workq_destroy(&link->workq);
+
+ /* Cleanuprequest tables */
+ __cam_req_mgr_destroy_link_info(link);
+
+ /* Free memory holding data of linked devs */
+ __cam_req_mgr_destroy_subdev(link->l_dev);
+
+ /* Destroy the link handle */
+ rc = cam_destroy_device_hdl(unlink_info->link_hdl);
+ if (rc < 0) {
+ CRM_ERR("error while destroying dev handle %d %x",
+ rc, link->link_hdl);
}
- return ret;
+ /* Free curent link and put back into session's free pool of links */
+ __cam_req_mgr_unreserve_link(cam_session, &link);
+ mutex_unlock(&g_crm_core_dev->crm_lock);
+
+ return rc;
}
int cam_req_mgr_schedule_request(
struct cam_req_mgr_sched_request *sched_req)
{
+ int rc = 0;
+ struct crm_workq_task *task = NULL;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_core_session *session = NULL;
+ struct cam_req_mgr_sched_request *sched;
+ struct crm_task_payload *task_data;
+
if (!sched_req) {
- CRM_ERR("NULL pointer");
+ CRM_ERR("csl_req is NULL");
+ rc = -EINVAL;
+ goto end;
+ }
+
+ link = (struct cam_req_mgr_core_link *)
+ cam_get_device_priv(sched_req->link_hdl);
+ if (!link) {
+ CRM_DBG("link ptr NULL %x", sched_req->link_hdl);
+ return -EINVAL;
+ }
+ session = (struct cam_req_mgr_core_session *)link->parent;
+ if (!session) {
+ CRM_WARN("session ptr NULL %x", sched_req->link_hdl);
return -EINVAL;
}
- /* This function handles ioctl, implementation pending */
- return 0;
+ task = cam_req_mgr_workq_get_task(link->workq);
+ if (!task)
+ return -ENOMEM;
+
+ task_data = (struct crm_task_payload *)task->payload;
+ task_data->type = CRM_WORKQ_TASK_SCHED_REQ;
+ sched = (struct cam_req_mgr_sched_request *)&task_data->u;
+ sched->req_id = sched_req->req_id;
+ sched->link_hdl = sched_req->link_hdl;
+ if (session->force_err_recovery == AUTO_RECOVERY) {
+ sched->bubble_enable = sched_req->bubble_enable;
+ } else {
+ sched->bubble_enable =
+ (session->force_err_recovery == FORCE_ENABLE_RECOVERY) ? 1 : 0;
+ }
+ task->process_cb = &cam_req_mgr_process_sched_req;
+ rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0);
+
+ /* Blocking call */
+ init_completion(&link->workq_comp);
+ rc = wait_for_completion_timeout(
+ &link->workq_comp,
+ msecs_to_jiffies(CAM_REQ_MGR_SCHED_REQ_TIMEOUT));
+end:
+ return rc;
}
-int cam_req_mgr_sync_mode(
- struct cam_req_mgr_sync_mode *sync_links)
+int cam_req_mgr_sync_link(
+ struct cam_req_mgr_sync_mode *sync_links)
{
if (!sync_links) {
CRM_ERR("NULL pointer");
@@ -611,15 +1983,70 @@
}
int cam_req_mgr_flush_requests(
- struct cam_req_mgr_flush_info *flush_info)
+ struct cam_req_mgr_flush_info *flush_info)
{
+ int rc = 0;
+ struct crm_workq_task *task = NULL;
+ struct cam_req_mgr_core_link *link = NULL;
+ struct cam_req_mgr_flush_info *flush;
+ struct crm_task_payload *task_data;
+ struct cam_req_mgr_core_session *session = NULL;
+
if (!flush_info) {
- CRM_ERR("NULL pointer");
- return -EINVAL;
+ CRM_ERR("flush req is NULL");
+ rc = -EFAULT;
+ goto end;
+ }
+ if (flush_info->flush_type >= CAM_REQ_MGR_FLUSH_TYPE_MAX) {
+ CRM_ERR("incorrect flush type %x", flush_info->flush_type);
+ rc = -EINVAL;
+ goto end;
}
- /* This function handles ioctl, implementation pending */
- return 0;
+ /* session hdl's priv data is cam session struct */
+ session = (struct cam_req_mgr_core_session *)
+ cam_get_device_priv(flush_info->session_hdl);
+ if (!session) {
+ CRM_ERR("Invalid session %x", flush_info->session_hdl);
+ rc = -EINVAL;
+ goto end;
+ }
+ if (session->num_links <= 0) {
+ CRM_WARN("No active links in session %x",
+ flush_info->session_hdl);
+ goto end;
+ }
+
+ link = (struct cam_req_mgr_core_link *)
+ cam_get_device_priv(flush_info->link_hdl);
+ if (!link) {
+ CRM_DBG("link ptr NULL %x", flush_info->link_hdl);
+ rc = -EINVAL;
+ goto end;
+ }
+
+ task = cam_req_mgr_workq_get_task(link->workq);
+ if (!task) {
+ rc = -ENOMEM;
+ goto end;
+ }
+
+ task_data = (struct crm_task_payload *)task->payload;
+ task_data->type = CRM_WORKQ_TASK_FLUSH_REQ;
+ flush = (struct cam_req_mgr_flush_info *)&task_data->u;
+ flush->req_id = flush_info->req_id;
+ flush->link_hdl = flush_info->link_hdl;
+ flush->flush_type = flush_info->flush_type;
+ task->process_cb = &cam_req_mgr_process_flush_req;
+ rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0);
+
+ /* Blocking call */
+ init_completion(&link->workq_comp);
+ rc = wait_for_completion_timeout(
+ &link->workq_comp,
+ msecs_to_jiffies(CAM_REQ_MGR_SCHED_REQ_TIMEOUT));
+end:
+ return rc;
}
@@ -639,6 +2066,7 @@
CRM_DBG("g_crm_core_dev %pK", g_crm_core_dev);
INIT_LIST_HEAD(&g_crm_core_dev->session_head);
mutex_init(&g_crm_core_dev->crm_lock);
+ cam_req_mgr_debug_register(g_crm_core_dev);
return 0;
}
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h
index 7679f20..889ee9c 100644
--- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h
@@ -14,213 +14,344 @@
#include "cam_req_mgr_interface.h"
#include "cam_req_mgr_core_defs.h"
+#include "cam_req_mgr_timer.h"
-#define CAM_REQ_MGR_MAX_LINKED_DEV 16
+#define CAM_REQ_MGR_MAX_LINKED_DEV 16
+#define MAX_REQ_SLOTS 48
+
+#define CAM_REQ_MGR_WATCHDOG_TIMEOUT 5000
+#define CAM_REQ_MGR_SCHED_REQ_TIMEOUT 1000
+#define CAM_REQ_MGR_SIMULATE_SCHED_REQ 30
+
+#define FORCE_DISABLE_RECOVERY 2
+#define FORCE_ENABLE_RECOVERY 1
+#define AUTO_RECOVERY 0
+
+#define CRM_WORKQ_NUM_TASKS 30
/**
- * enum crm_req_status
- * State machine for life cycle of request in link
- * EMPTY - indicates req slot is empty
- * PENDING - indicates req slot is waiting for reqs from all devs
- * READY - indicates req slot is ready to be sent to devs
- * APPLIED - indicates req slot is sent to devices
- * INVALID - indicates req slot is not in valid state
+ * enum crm_workq_task_type
+ * @codes: to identify which type of task is present
*/
-enum crm_req_status {
- CRM_REQ_STATUS_EMPTY,
- CRM_REQ_STATUS_PENDING,
- CRM_REQ_STATUS_READY,
- CRM_REQ_STATUS_APPLIED,
- CRM_REQ_STATUS_INVALID,
+enum crm_workq_task_type {
+ CRM_WORKQ_TASK_GET_DEV_INFO,
+ CRM_WORKQ_TASK_SETUP_LINK,
+ CRM_WORKQ_TASK_DEV_ADD_REQ,
+ CRM_WORKQ_TASK_APPLY_REQ,
+ CRM_WORKQ_TASK_NOTIFY_SOF,
+ CRM_WORKQ_TASK_NOTIFY_ERR,
+ CRM_WORKQ_TASK_SCHED_REQ,
+ CRM_WORKQ_TASK_FLUSH_REQ,
+ CRM_WORKQ_TASK_INVALID,
+};
+
+/**
+ * struct crm_task_payload
+ * @type : to identify which type of task is present
+ * @u : union of payload of all types of tasks supported
+ * @sched_req : contains info of incoming reqest from CSL to CRM
+ * @flush_info : contains info of cancelled reqest
+ * @dev_req : contains tracking info of available req id at device
+ * @send_req : contains info of apply settings to be sent to devs in link
+ * @apply_req : contains info of which request is applied at device
+ * @notify_sof : contains notification from IFE to CRM about SOF trigger
+ * @notify_err : contains error info happened while processing request
+ * -
+ */
+struct crm_task_payload {
+ enum crm_workq_task_type type;
+ union {
+ struct cam_req_mgr_sched_request sched_req;
+ struct cam_req_mgr_flush_info flush_info;
+ struct cam_req_mgr_add_request dev_req;
+ struct cam_req_mgr_send_request send_req;
+ struct cam_req_mgr_sof_notify notify_sof;
+ struct cam_req_mgr_error_notify notify_err;
+ } u;
+};
+
+/**
+ * enum crm_req_state
+ * State machine for life cycle of request in pd table
+ * EMPTY : indicates req slot is empty
+ * PENDING : indicates req slot is waiting for reqs from all devs
+ * READY : indicates req slot is ready to be sent to devs
+ * INVALID : indicates req slot is not in valid state
+ */
+enum crm_req_state {
+ CRM_REQ_STATE_EMPTY,
+ CRM_REQ_STATE_PENDING,
+ CRM_REQ_STATE_READY,
+ CRM_REQ_STATE_INVALID,
+};
+
+/**
+ * enum crm_slot_status
+ * State machine for life cycle of request in input queue
+ * NO_REQ : empty slot
+ * REQ_ADDED : new entry in slot
+ * INCOMPLETE : waiting for
+ * APPLIED : req is sent to devices
+ * INVALID : invalid state
+ */
+enum crm_slot_status {
+ CRM_SLOT_STATUS_NO_REQ,
+ CRM_SLOT_STATUS_REQ_ADDED,
+ CRM_SLOT_STATUS_REQ_PENDING,
+ CRM_SLOT_STATUS_REQ_APPLIED,
+ CRM_SLOT_STATUS_INVALID,
};
/**
* enum cam_req_mgr_link_state
* State machine for life cycle of link in crm
- * AVAILABLE - indicates link is not in use
- * IDLE - indicates link is reserved but not initialized
- * READY - indicates link is initialized and ready for operation
- * STREAMING - indicates link is receiving triggers and requests
- * BUBBLE_DETECTED - indicates device on link is in bad shape
- * ROLLBACK_STARTED - indicates link had triggered error recovery
- * MAX - indicates link max as invalid
+ * AVAILABLE : link available
+ * IDLE : link initialized but not ready yet
+ * READY : link is ready for use
+ * ERR : link has encountered error
+ * MAX : invalid state
*/
enum cam_req_mgr_link_state {
CAM_CRM_LINK_STATE_AVAILABLE,
CAM_CRM_LINK_STATE_IDLE,
CAM_CRM_LINK_STATE_READY,
- CAM_CRM_LINK_STATE_STREAMING,
- CAM_CRM_LINK_STATE_BUBBLE_DETECTED,
- CAM_CRM_LINK_STATE_ROLLBACK_STARTED,
- CAM_CRM_LINK_STATE_DEVICE_STATE_MAX,
+ CAM_CRM_LINK_STATE_ERR,
+ CAM_CRM_LINK_STATE_MAX,
};
/**
- * struct cam_req_mgr_request_slot
- * @idx: device handle
- * @req_status: state machine for life cycle of a request
- * @request_id: request id value
+ * struct cam_req_mgr_traverse
+ * @idx : slot index
+ * @result : contains which all tables were able to apply successfully
+ * @tbl : pointer of pipeline delay based request table
+ * @apply_data : pointer which various tables will update during traverse
+ * @in_q : input request queue pointer
*/
-struct cam_req_mgr_request_slot {
+struct cam_req_mgr_traverse {
+ int32_t idx;
+ uint32_t result;
+ struct cam_req_mgr_req_tbl *tbl;
+ struct cam_req_mgr_apply *apply_data;
+ struct cam_req_mgr_req_queue *in_q;
+};
+
+/**
+ * struct cam_req_mgr_apply
+ * @idx : corresponding input queue slot index
+ * @pd : pipeline delay of device
+ * @req_id : req id for dev with above pd to process
+ * @skip_idx: skip applying settings when this is set.
+ */
+struct cam_req_mgr_apply {
int32_t idx;
- enum crm_req_status req_status;
- int64_t request_id;
+ int32_t pd;
+ int64_t req_id;
+ int32_t skip_idx;
};
/**
- * struct cam_req_mgr_request_queue
- * @read_index: idx currently being processed
- * @write_index: idx at which incoming req is stored
- * @num_slots: num of req slots i.e. queue depth
- * @req_slot: slots which hold the request info
+ * struct cam_req_mgr_tbl_slot
+ * @idx : slot index
+ * @req_ready_map : mask tracking which all devices have request ready
+ * @state : state machine for life cycle of a slot
*/
-struct cam_req_mgr_request_queue {
- int32_t read_index;
- int32_t write_index;
- uint32_t num_slots;
- struct cam_req_mgr_request_slot *req_slot;
+struct cam_req_mgr_tbl_slot {
+ int32_t idx;
+ uint32_t req_ready_map;
+ enum crm_req_state state;
};
/**
- * struct cam_req_mgr_frame_settings
- * @request_id: request id to apply
- * @frame_id: frame id for debug purpose
+ * struct cam_req_mgr_req_tbl
+ * @id : table indetifier
+ * @pd : pipeline delay of table
+ * @dev_count : num of devices having same pipeline delay
+ * @dev_mask : mask to track which devices are linked
+ * @skip_traverse : to indicate how many traverses need to be dropped
+ * by this table especially in the beginning or bubble recovery
+ * @next : pointer to next pipeline delay request table
+ * @pd_delta : differnce between this table's pipeline delay and next
+ * @num_slots : number of request slots present in the table
+ * @slot : array of slots tracking requests availability at devices
*/
-struct cam_req_mgr_frame_settings {
- int64_t request_id;
- int64_t frame_id;
+struct cam_req_mgr_req_tbl {
+ int32_t id;
+ int32_t pd;
+ int32_t dev_count;
+ int32_t dev_mask;
+ int32_t skip_traverse;
+ struct cam_req_mgr_req_tbl *next;
+ int32_t pd_delta;
+ int32_t num_slots;
+ struct cam_req_mgr_tbl_slot slot[MAX_REQ_SLOTS];
};
/**
- * struct cam_req_mgr_request_table
- * @pipeline_delay: pipeline delay of this req table
- * @l_devices: list of devices belonging to this p_delay
- * @dev_mask: each dev hdl has unique bit assigned, dev mask tracks if all devs
- * received req id packet from UMD to process
+ * struct cam_req_mgr_slot
+ * - Internal Book keeping
+ * @idx : slot index
+ * @skip_idx : if req id in this slot needs to be skipped/not applied
+ * @status : state machine for life cycle of a slot
+ * - members updated due to external events
+ * @recover : if user enabled recovery for this request.
+ * @req_id : mask tracking which all devices have request ready
*/
-struct cam_req_mgr_request_table {
- uint32_t pipeline_delay;
- struct list_head l_devices;
- uint32_t dev_mask;
+struct cam_req_mgr_slot {
+ int32_t idx;
+ int32_t skip_idx;
+ enum crm_slot_status status;
+ int32_t recover;
+ int64_t req_id;
+};
+
+/**
+ * struct cam_req_mgr_req_queue
+ * @num_slots : max num of input queue slots
+ * @slot : request slot holding incoming request id and bubble info.
+ * @rd_idx : indicates slot index currently in process.
+ * @wr_idx : indicates slot index to hold new upcoming req.
+ */
+struct cam_req_mgr_req_queue {
+ int32_t num_slots;
+ struct cam_req_mgr_slot slot[MAX_REQ_SLOTS];
+ int32_t rd_idx;
+ int32_t wr_idx;
+};
+
+/**
+ * struct cam_req_mgr_req_data
+ * @in_q : Poiner to Input request queue
+ * @l_tbl : unique pd request tables.
+ * @num_tbl : how many unique pd value devices are present
+ * @apply_data : Holds information about request id for a request
+ * @lock : mutex lock protecting request data ops.
+ */
+struct cam_req_mgr_req_data {
+ struct cam_req_mgr_req_queue *in_q;
+ struct cam_req_mgr_req_tbl *l_tbl;
+ int32_t num_tbl;
+ struct cam_req_mgr_apply apply_data[CAM_PIPELINE_DELAY_MAX];
+ struct mutex lock;
};
/**
* struct cam_req_mgr_connected_device
- *- Device Properties
- * @dev_hdl: device handle
- * @dev_bit: unique bit assigned to device in link
- * -Device progress status
- * @available_req_id: tracks latest available req id at this device
- * @processing_req_id: tracks request id currently processed
+ * - Device Properties
+ * @dev_hdl : device handle
+ * @dev_bit : unique bit assigned to device in link
* - Device characteristics
- * @dev_info: holds dev characteristics such as pipeline delay, dev name
- * @ops: holds func pointer to call methods on this device
- * @parent: pvt data - Pointer to parent link device its connected with
- * @entry: entry to the list of connected devices in link
+ * @pd_tbl : tracks latest available req id at this device
+ * @dev_info : holds dev characteristics such as pipeline delay, dev name
+ * @ops : holds func pointer to call methods on this device
+ * @parent : pvt data - like link which this dev hdl belongs to
*/
struct cam_req_mgr_connected_device {
- int32_t dev_hdl;
- int64_t dev_bit;
- int64_t available_req_id;
- int64_t processing_req_id;
- struct cam_req_mgr_device_info dev_info;
- struct cam_req_mgr_kmd_ops *ops;
- void *parent;
- struct list_head entry;
+ int32_t dev_hdl;
+ int64_t dev_bit;
+ struct cam_req_mgr_req_tbl *pd_tbl;
+ struct cam_req_mgr_device_info dev_info;
+ struct cam_req_mgr_kmd_ops *ops;
+ void *parent;
};
/**
* struct cam_req_mgr_core_link
- * - Link Properties
- * @link_hdl: Link identifier
- * @num_connections: num of connected devices to this link
- * @max_pipeline_delay: Max of pipeline delay of all connected devs
- * - Input request queue
- * @in_requests: Queue to hold incoming request hints from CSL
- * @workq: Pointer to handle workq related jobs
+ * - Link Properties
+ * @link_hdl : Link identifier
+ * @num_devs : num of connected devices to this link
+ * @max_delay : Max of pipeline delay of all connected devs
+ * @workq : Pointer to handle workq related jobs
+ * @pd_mask : each set bit indicates the device with pd equal to bit
+ * position is available.
* - List of connected devices
- * @l_devices: List of connected devices to this link
- * @fs_list: Holds the request id which each device in link will consume.
- * @req_table: table to keep track of req ids recived at each dev handle
+ * @l_dev : List of connected devices to this link
+ * - Request handling data struct
+ * @req : req data holder.
+ * - Timer
+ * @watchdog : watchdog timer to recover from sof freeze
* - Link private data
- * @link_state: link state cycle
- * @parent: pvt data - like session info
- * @link_head: List head of connected devices
- * @lock: spin lock to guard link data operations
+ * @workq_comp : conditional variable to block user thread for workq to
+ * finish schedule request processing
+ * @state : link state machine
+ * @parent : pvt data - link's parent is session
+ * @lock : mutex lock to guard link data operations
*/
struct cam_req_mgr_core_link {
- int32_t link_hdl;
- int32_t num_connections;
- enum cam_pipeline_delay max_pipeline_delay;
- struct cam_req_mgr_request_queue in_requests;
- struct cam_req_mgr_core_workq *workq;
- struct cam_req_mgr_connected_device *l_devices;
- struct cam_req_mgr_frame_settings fs_list[CAM_REQ_MGR_MAX_LINKED_DEV];
- struct cam_req_mgr_request_table req_table[CAM_PIPELINE_DELAY_MAX];
- enum cam_req_mgr_link_state link_state;
- void *parent;
- struct list_head link_head;
- spinlock_t lock;
+ int32_t link_hdl;
+ int32_t num_devs;
+ enum cam_pipeline_delay max_delay;
+ struct cam_req_mgr_core_workq *workq;
+ int32_t pd_mask;
+ struct cam_req_mgr_connected_device *l_dev;
+ struct cam_req_mgr_req_data req;
+ struct cam_req_mgr_timer *watchdog;
+ struct completion workq_comp;
+ enum cam_req_mgr_link_state state;
+ void *parent;
+ struct mutex lock;
};
/**
* struct cam_req_mgr_core_session
* - Session Properties
- * @session_hdl: session identifier
- * @num_active_links: num of active links for current session
+ * @session_hdl : session identifier
+ * @num_links : num of active links for current session
* - Links of this session
- * @links: pointer to array of links within session
+ * @links : pointer to array of links within session
+ * @in_q : Input request queue one per session
* - Session private data
- * @entry: pvt data - entry in the list of sessions
- * @lock: pvt data - spin lock to guard session data
+ * @entry : pvt data - entry in the list of sessions
+ * @lock : pvt data - spin lock to guard session data
+ * - Debug data
+ * @force_err_recovery : For debugging, we can force bubble recovery
+ * to be always ON or always OFF using debugfs.
*/
struct cam_req_mgr_core_session {
- int32_t session_hdl;
- uint32_t num_active_links;
- struct cam_req_mgr_core_link links[MAX_LINKS_PER_SESSION];
- struct list_head entry;
- spinlock_t lock;
+ int32_t session_hdl;
+ uint32_t num_links;
+ struct cam_req_mgr_core_link *links[MAX_LINKS_PER_SESSION];
+ struct cam_req_mgr_req_queue in_q;
+ struct list_head entry;
+ struct mutex lock;
+ int32_t force_err_recovery;
};
/**
* struct cam_req_mgr_core_device
* - Core camera request manager data struct
- * @session_head: list head holding sessions
- * @crm_lock: mutex lock to protect session creation & destruction
+ * @session_head : list head holding sessions
+ * @crm_lock : mutex lock to protect session creation & destruction
*/
struct cam_req_mgr_core_device {
- struct list_head session_head;
- struct mutex crm_lock;
+ struct list_head session_head;
+ struct mutex crm_lock;
};
-/* cam_req_mgr_dev to cam_req_mgr_core internal functions */
/**
* cam_req_mgr_create_session()
- * @brief: creates session
- * @ses_info: output param for session handle
+ * @brief : creates session
+ * @ses_info : output param for session handle
*
- * Called as part of session creation.
+ * called as part of session creation.
*/
-int cam_req_mgr_create_session(
- struct cam_req_mgr_session_info *ses_info);
+int cam_req_mgr_create_session(struct cam_req_mgr_session_info *ses_info);
/**
* cam_req_mgr_destroy_session()
- * @brief: destroy session
- * @ses_info: session handle info, input param
+ * @brief : destroy session
+ * @ses_info : session handle info, input param
*
* Called as part of session destroy
* return success/failure
*/
-int cam_req_mgr_destroy_session(
- struct cam_req_mgr_session_info *ses_info);
+int cam_req_mgr_destroy_session(struct cam_req_mgr_session_info *ses_info);
/**
* cam_req_mgr_link()
- * @brief: creates a link for a session
- * @link_info: handle and session info to create a link
+ * @brief : creates a link for a session
+ * @link_info : handle and session info to create a link
*
- * Link is formed in a session for multiple devices. It creates
+ * link is formed in a session for multiple devices. it creates
* a unique link handle for the link and is specific to a
* session. Returns link handle
*/
@@ -228,10 +359,10 @@
/**
* cam_req_mgr_unlink()
- * @brief: destroy a link in a session
- * @unlink_info: session and link handle info
+ * @brief : destroy a link in a session
+ * @unlink_info : session and link handle info
*
- * Link is destroyed in a session
+ * link is destroyed in a session
*/
int cam_req_mgr_unlink(struct cam_req_mgr_unlink_info *unlink_info);
@@ -244,11 +375,11 @@
struct cam_req_mgr_sched_request *sched_req);
/**
- * cam_req_mgr_sync_mode()
+ * cam_req_mgr_sync_link()
* @brief: sync for links in a session
* @sync_links: session, links info and master link info
*/
-int cam_req_mgr_sync_mode(struct cam_req_mgr_sync_mode *sync_links);
+int cam_req_mgr_sync_link(struct cam_req_mgr_sync_mode *sync_links);
/**
* cam_req_mgr_flush_requests()
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core_defs.h b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core_defs.h
index cf2fe7f..2a831e8 100644
--- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core_defs.h
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core_defs.h
@@ -15,6 +15,16 @@
#define CRM_TRACE_ENABLE 0
#define CRM_DEBUG_MUTEX 0
+#define SET_SUCCESS_BIT(ret, pd) {\
+ (ret) |= (1 << (pd)); \
+ }
+
+#define SET_FAILURE_BIT(ret, pd) {\
+ (ret) &= (0 << (pd)); \
+ }
+
+#define CRM_GET_REQ_ID(in_q, idx) in_q->slot[idx].req_id
+
#if (CRM_TRACE_ENABLE == 1)
#define CRM_DBG(fmt, args...) do { \
trace_printk("%d: [crm_dbg] "fmt"\n", __LINE__, ##args); \
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_debug.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_debug.c
new file mode 100644
index 0000000..19833d8
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_debug.c
@@ -0,0 +1,139 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "cam_req_mgr_debug.h"
+
+#define MAX_SESS_INFO_LINE_BUFF_LEN 256
+
+static char sess_info_buffer[MAX_SESS_INFO_LINE_BUFF_LEN];
+
+static int cam_req_mgr_debug_set_bubble_recovery(void *data, u64 val)
+{
+ struct cam_req_mgr_core_device *core_dev = data;
+ struct cam_req_mgr_core_session *session;
+ int rc = 0;
+
+ mutex_lock(&core_dev->crm_lock);
+
+ if (!list_empty(&core_dev->session_head)) {
+ list_for_each_entry(session,
+ &core_dev->session_head, entry) {
+ session->force_err_recovery = val;
+ }
+ }
+
+ mutex_unlock(&core_dev->crm_lock);
+
+ return rc;
+}
+
+static int cam_req_mgr_debug_get_bubble_recovery(void *data, u64 *val)
+{
+ struct cam_req_mgr_core_device *core_dev = data;
+ struct cam_req_mgr_core_session *session;
+
+ mutex_lock(&core_dev->crm_lock);
+
+ if (!list_empty(&core_dev->session_head)) {
+ session = list_first_entry(&core_dev->session_head,
+ struct cam_req_mgr_core_session,
+ entry);
+ *val = session->force_err_recovery;
+ }
+ mutex_unlock(&core_dev->crm_lock);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(bubble_recovery, cam_req_mgr_debug_get_bubble_recovery,
+ cam_req_mgr_debug_set_bubble_recovery, "%lld\n");
+
+static int session_info_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static ssize_t session_info_read(struct file *t_file, char *t_char,
+ size_t t_size_t, loff_t *t_loff_t)
+{
+ int i;
+ char *out_buffer = sess_info_buffer;
+ char line_buffer[MAX_SESS_INFO_LINE_BUFF_LEN] = {0};
+ struct cam_req_mgr_core_device *core_dev =
+ (struct cam_req_mgr_core_device *) t_file->private_data;
+ struct cam_req_mgr_core_session *session;
+
+ memset(out_buffer, 0, MAX_SESS_INFO_LINE_BUFF_LEN);
+
+ mutex_lock(&core_dev->crm_lock);
+
+ if (!list_empty(&core_dev->session_head)) {
+ list_for_each_entry(session,
+ &core_dev->session_head, entry) {
+ snprintf(line_buffer, sizeof(line_buffer),
+ "session_hdl = %x \t"
+ "num_links = %d\n",
+ session->session_hdl, session->num_links);
+ strlcat(out_buffer, line_buffer,
+ sizeof(sess_info_buffer));
+ for (i = 0; i < session->num_links; i++) {
+ snprintf(line_buffer, sizeof(line_buffer),
+ "link_hdl[%d] = 0x%x, num_devs connected = %d\n",
+ i, session->links[i]->link_hdl,
+ session->links[i]->num_devs);
+ strlcat(out_buffer, line_buffer,
+ sizeof(sess_info_buffer));
+ }
+ }
+ }
+
+ mutex_unlock(&core_dev->crm_lock);
+
+ return simple_read_from_buffer(t_char, t_size_t,
+ t_loff_t, out_buffer, strlen(out_buffer));
+}
+
+static ssize_t session_info_write(struct file *t_file,
+ const char *t_char, size_t t_size_t, loff_t *t_loff_t)
+{
+ memset(sess_info_buffer, 0, MAX_SESS_INFO_LINE_BUFF_LEN);
+
+ return 0;
+}
+
+static const struct file_operations session_info = {
+ .open = session_info_open,
+ .read = session_info_read,
+ .write = session_info_write,
+};
+
+int cam_req_mgr_debug_register(struct cam_req_mgr_core_device *core_dev)
+{
+ struct dentry *debugfs_root;
+ char dirname[32] = {0};
+
+ snprintf(dirname, sizeof(dirname), "cam_req_mgr");
+ debugfs_root = debugfs_create_dir(dirname, NULL);
+ if (!debugfs_root)
+ return -ENOMEM;
+
+ if (!debugfs_create_file("sessions_info", 0644,
+ debugfs_root, core_dev, &session_info))
+ return -ENOMEM;
+
+ if (!debugfs_create_file("bubble_recovery", 0644,
+ debugfs_root, core_dev, &bubble_recovery))
+ return -ENOMEM;
+
+ return 0;
+}
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_debug.h b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_debug.h
new file mode 100644
index 0000000..82ac764
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_debug.h
@@ -0,0 +1,21 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CAM_REQ_MGR_DEBUG_H_
+#define _CAM_REQ_MGR_DEBUG_H_
+
+#include <linux/debugfs.h>
+#include "cam_req_mgr_core.h"
+
+int cam_req_mgr_debug_register(struct cam_req_mgr_core_device *core_dev);
+
+#endif
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_dev.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_dev.c
index 43b020c6..13affe9 100644
--- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_dev.c
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_dev.c
@@ -326,7 +326,7 @@
return -EFAULT;
}
- rc = cam_req_mgr_sync_mode(&sync_mode);
+ rc = cam_req_mgr_sync_link(&sync_mode);
}
break;
case CAM_REQ_MGR_ALLOC_BUF: {
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_interface.h b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_interface.h
index 174a725..91860f6 100644
--- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_interface.h
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_interface.h
@@ -18,15 +18,14 @@
#include "cam_req_mgr_core_defs.h"
#include "cam_req_mgr_util.h"
-/* Forward declarations */
struct cam_req_mgr_sof_notify;
struct cam_req_mgr_error_notify;
struct cam_req_mgr_add_request;
struct cam_req_mgr_device_info;
struct cam_req_mgr_core_dev_link_setup;
struct cam_req_mgr_apply_request;
-
-/*Ops table for req mgr - kmd communication */
+struct cam_req_mgr_flush_request;
+struct cam_req_mgr_link_evt_data;
/* Request Manager -- camera device driver interface */
/**
@@ -44,21 +43,25 @@
* @brief: cam req mgr to camera device drivers
*
* @cam_req_mgr_get_dev_info: to fetch details about device linked
- * @cam_req_mgr_link_setup: to establish link with device for a session
- * @cam_req_mgr_notify_err: to broadcast error happened on link for request id
- * @cam_req_mgr_apply_req: CRM asks device to apply certain request id.
+ * @cam_req_mgr_link_setup : to establish link with device for a session
+ * @cam_req_mgr_notify_err : to broadcast error happened on link for request id
+ * @cam_req_mgr_apply_req : CRM asks device to apply certain request id.
+ * @cam_req_mgr_flush_req : Flush or cancle request
+ * cam_req_mgr_process_evt : generic events
*/
typedef int (*cam_req_mgr_get_dev_info) (struct cam_req_mgr_device_info *);
typedef int (*cam_req_mgr_link_setup)(
struct cam_req_mgr_core_dev_link_setup *);
typedef int (*cam_req_mgr_apply_req)(struct cam_req_mgr_apply_request *);
+typedef int (*cam_req_mgr_flush_req)(struct cam_req_mgr_flush_request *);
+typedef int (*cam_req_mgr_process_evt)(struct cam_req_mgr_link_evt_data *);
/**
- * @brief: cam_req_mgr_crm_cb - func table
+ * @brief : cam_req_mgr_crm_cb - func table
*
- * @notify_sof: payload for sof indication event
- * @notify_err: payload for different error occurred at device
- * @add_req: pauload to inform which device and what request is received
+ * @notify_sof : payload for sof indication event
+ * @notify_err : payload for different error occurred at device
+ * @add_req : payload to inform which device and what request is received
*/
struct cam_req_mgr_crm_cb {
cam_req_mgr_notify_sof notify_sof;
@@ -67,26 +70,30 @@
};
/**
- * @brief: cam_req_mgr_kmd_ops - func table
+ * @brief : cam_req_mgr_kmd_ops - func table
*
- * @get_dev_info: payload to fetch device details
- * @link_setup: payload to establish link with device
- * @apply_req: payload to apply request id on a device linked
+ * @get_dev_info : payload to fetch device details
+ * @link_setup : payload to establish link with device
+ * @apply_req : payload to apply request id on a device linked
+ * @flush_req : payload to flush request
+ * @process_evt : payload to generic event
*/
struct cam_req_mgr_kmd_ops {
cam_req_mgr_get_dev_info get_dev_info;
cam_req_mgr_link_setup link_setup;
cam_req_mgr_apply_req apply_req;
+ cam_req_mgr_flush_req flush_req;
+ cam_req_mgr_process_evt process_evt;
};
/**
* enum cam_pipeline_delay
- * @brief: enumerator for different pipeline delays in camera
+ * @brief : enumerator for different pipeline delays in camera
*
- * @DELAY_0: device processed settings on same frame
- * @DELAY_1: device processed settings after 1 frame
- * @DELAY_2: device processed settings after 2 frames
- * @DELAY_MAX: maximum supported pipeline delay
+ * @DELAY_0 : device processed settings on same frame
+ * @DELAY_1 : device processed settings after 1 frame
+ * @DELAY_2 : device processed settings after 2 frames
+ * @DELAY_MAX : maximum supported pipeline delay
*/
enum cam_pipeline_delay {
CAM_PIPELINE_DELAY_0,
@@ -97,11 +104,11 @@
/**
* enum cam_req_status
- * @brief: enumerator for request status
+ * @brief : enumerator for request status
*
- * @SUCCESS: device processed settings successfully
- * @FAILED: device processed settings failed
- * @MAX: invalid status value
+ * @SUCCESS : device processed settings successfully
+ * @FAILED : device processed settings failed
+ * @MAX : invalid status value
*/
enum cam_req_status {
CAM_REQ_STATUS_SUCCESS,
@@ -111,15 +118,15 @@
/**
* enum cam_req_mgr_device_error
- * @brief: enumerator for different errors occurred at device
+ * @brief : enumerator for different errors occurred at device
*
- * @NOT_FOUND: settings asked by request manager is not found
- * @BUBBLE: device hit timing issue and is able to recover
- * @FATAL: device is in bad shape and can not recover from error
- * @PAGE_FAULT: Page fault while accessing memory
- * @OVERFLOW: Bus Overflow for IFE/VFE
- * @TIMEOUT: Timeout from cci or bus.
- * @MAX: Invalid error value
+ * @NOT_FOUND : settings asked by request manager is not found
+ * @BUBBLE : device hit timing issue and is able to recover
+ * @FATAL : device is in bad shape and can not recover from error
+ * @PAGE_FAULT : Page fault while accessing memory
+ * @OVERFLOW : Bus Overflow for IFE/VFE
+ * @TIMEOUT : Timeout from cci or bus.
+ * @MAX : Invalid error value
*/
enum cam_req_mgr_device_error {
CRM_KMD_ERR_NOT_FOUND,
@@ -133,17 +140,17 @@
/**
* enum cam_req_mgr_device_id
- * @brief: enumerator for different devices in subsystem
+ * @brief : enumerator for different devices in subsystem
*
- * @CAM_REQ_MGR: request manager itself
- * @SENSOR: sensor device
- * @FLASH: LED flash or dual LED device
- * @ACTUATOR: lens mover
- * @IFE: Image processing device
- * @EXTERNAL_1: third party device
- * @EXTERNAL_2: third party device
- * @EXTERNAL_3: third party device
- * @MAX: invalid device id
+ * @CAM_REQ_MGR : request manager itself
+ * @SENSOR : sensor device
+ * @FLASH : LED flash or dual LED device
+ * @ACTUATOR : lens mover
+ * @IFE : Image processing device
+ * @EXTERNAL_1 : third party device
+ * @EXTERNAL_2 : third party device
+ * @EXTERNAL_3 : third party device
+ * @MAX : invalid device id
*/
enum cam_req_mgr_device_id {
CAM_REQ_MGR_DEVICE,
@@ -158,11 +165,22 @@
};
/* Camera device driver to Req Mgr device interface */
+
+/**
+ * enum cam_req_mgr_link_evt_type
+ * @CAM_REQ_MGR_LINK_EVT_ERR:
+ * @CAM_REQ_MGR_LINK_EVT_MAX:
+ */
+enum cam_req_mgr_link_evt_type {
+ CAM_REQ_MGR_LINK_EVT_ERR,
+ CAM_REQ_MGR_LINK_EVT_MAX,
+};
+
/**
* struct cam_req_mgr_sof_notify
- * @link_hdl: link identifier
- * @dev_hdl: device handle which has sent this req id
- * @frame_id: frame id for internal tracking
+ * @link_hdl : link identifier
+ * @dev_hdl : device handle which has sent this req id
+ * @frame_id : frame id for internal tracking
*/
struct cam_req_mgr_sof_notify {
int32_t link_hdl;
@@ -172,11 +190,10 @@
/**
* struct cam_req_mgr_error_notify
- * @link_hdl: link identifier
- * @dev_hdl: device handle which has sent this req id
- * @req_id: req id which hit error
- * @error: what error device hit while processing this req
- *
+ * @link_hdl : link identifier
+ * @dev_hdl : device handle which has sent this req id
+ * @req_id : req id which hit error
+ * @error : what error device hit while processing this req
*/
struct cam_req_mgr_error_notify {
int32_t link_hdl;
@@ -187,9 +204,9 @@
/**
* struct cam_req_mgr_add_request
- * @link_hdl: link identifier
- * @dev_hdl: device handle which has sent this req id
- * @req_id: req id which device is ready to process
+ * @link_hdl : link identifier
+ * @dev_hdl : device handle which has sent this req id
+ * @req_id : req id which device is ready to process
*
*/
struct cam_req_mgr_add_request {
@@ -202,48 +219,91 @@
/* CRM to KMD devices */
/**
* struct cam_req_mgr_device_info
- * @dev_hdl: Input_param : device handle for reference
- * @name: link link or unlink
- * @dev_id: device id info
- * @p_delay: delay between time settings applied and take effect
+ * @dev_hdl : Input_param : device handle for reference
+ * @name : link link or unlink
+ * @dev_id : device id info
+ * @p_delay : delay between time settings applied and take effect
*
*/
struct cam_req_mgr_device_info {
- int32_t dev_hdl;
- char name[256];
- enum cam_req_mgr_device_id dev_id;
- enum cam_pipeline_delay p_delay;
+ int32_t dev_hdl;
+ char name[256];
+ enum cam_req_mgr_device_id dev_id;
+ enum cam_pipeline_delay p_delay;
};
/**
* struct cam_req_mgr_core_dev_link_setup
- * @link_enable: link link or unlink
- * @link_hdl: link identifier
- * @dev_hdl: device handle for reference
- * @max_delay: max pipeline delay on this link
- * @crm_cb: callback funcs to communicate with req mgr
+ * @link_enable : link link or unlink
+ * @link_hdl : link identifier
+ * @dev_hdl : device handle for reference
+ * @max_delay : max pipeline delay on this link
+ * @crm_cb : callback funcs to communicate with req mgr
*
*/
struct cam_req_mgr_core_dev_link_setup {
- bool link_enable;
- int32_t link_hdl;
- int32_t dev_hdl;
- enum cam_pipeline_delay max_delay;
+ int32_t link_enable;
+ int32_t link_hdl;
+ int32_t dev_hdl;
+ enum cam_pipeline_delay max_delay;
struct cam_req_mgr_crm_cb *crm_cb;
};
/**
* struct cam_req_mgr_apply_request
- * @link_id: link identifier
- * @dev_hdl: device handle for cross check
- * @request_id: request id settings to apply
- * @report_if_bubble: report to crm if failure in applying
+ * @link_hdl : link identifier
+ * @dev_hdl : device handle for cross check
+ * @request_id : request id settings to apply
+ * @report_if_bubble : report to crm if failure in applying
*
*/
struct cam_req_mgr_apply_request {
+ int32_t link_hdl;
+ int32_t dev_hdl;
+ int64_t request_id;
+ int32_t report_if_bubble;
+};
+
+/**
+ * struct cam_req_mgr_flush_request
+ * @link_hdl : link identifier
+ * @dev_hdl : device handle for cross check
+ * @type : cancel request type flush all or a request
+ * @request_id : request id to cancel
+ *
+ */
+struct cam_req_mgr_flush_request {
+ int32_t link_hdl;
+ int32_t dev_hdl;
+ uint32_t type;
+ int64_t req_id;
+};
+
+/**
+ * struct cam_req_mgr_event_data
+ * @link_hdl : link handle
+ * @req_id : request id
+ *
+ */
+struct cam_req_mgr_link_evt_data {
int32_t link_hdl;
int32_t dev_hdl;
- int64_t request_id;
- int32_t report_if_bubble;
+ int64_t req_id;
+
+ enum cam_req_mgr_link_evt_type evt_type;
+ union {
+ enum cam_req_mgr_device_error error;
+ } u;
+};
+
+/**
+ * struct cam_req_mgr_send_request
+ * @link_hdl : link identifier
+ * @idx : slot idx
+ *
+ */
+struct cam_req_mgr_send_request {
+ int32_t link_hdl;
+ struct cam_req_mgr_req_queue *in_q;
};
#endif
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_timer.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_timer.c
new file mode 100644
index 0000000..9da445d
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_timer.c
@@ -0,0 +1,89 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "cam_req_mgr_timer.h"
+
+void crm_timer_reset(struct cam_req_mgr_timer *crm_timer)
+{
+ if (!crm_timer)
+ return;
+ CRM_DBG("Starting timer to fire in %d ms. (jiffies=%lu)\n",
+ crm_timer->expires, jiffies);
+ mod_timer(&crm_timer->sys_timer,
+ (jiffies + msecs_to_jiffies(crm_timer->expires)));
+}
+
+void crm_timer_callback(unsigned long data)
+{
+ struct cam_req_mgr_timer *timer = (struct cam_req_mgr_timer *)data;
+
+ if (!timer) {
+ CRM_ERR("NULL timer");
+ return;
+ }
+ CRM_DBG("timer %pK parent %pK", timer, timer->parent);
+ crm_timer_reset(timer);
+}
+
+void crm_timer_modify(struct cam_req_mgr_timer *crm_timer,
+ int32_t expires)
+{
+ CRM_DBG("new time %d", expires);
+ if (crm_timer) {
+ crm_timer->expires = expires;
+ crm_timer_reset(crm_timer);
+ }
+}
+
+int crm_timer_init(struct cam_req_mgr_timer **timer,
+ int32_t expires, void *parent, void (*timer_cb)(unsigned long))
+{
+ int ret = 0;
+ struct cam_req_mgr_timer *crm_timer = NULL;
+
+ CRM_DBG("init timer %d %pK", expires, *timer);
+ if (*timer == NULL) {
+ crm_timer = (struct cam_req_mgr_timer *)
+ kzalloc(sizeof(struct cam_req_mgr_timer), GFP_KERNEL);
+ if (!crm_timer) {
+ ret = -ENOMEM;
+ goto end;
+ }
+
+ if (timer_cb != NULL)
+ crm_timer->timer_cb = timer_cb;
+ else
+ crm_timer->timer_cb = crm_timer_callback;
+
+ crm_timer->expires = expires;
+ crm_timer->parent = parent;
+ setup_timer(&crm_timer->sys_timer,
+ crm_timer->timer_cb, (unsigned long)crm_timer);
+ crm_timer_reset(crm_timer);
+ *timer = crm_timer;
+ } else {
+ CRM_WARN("Timer already exists!!");
+ ret = -EINVAL;
+ }
+end:
+ return ret;
+}
+void crm_timer_exit(struct cam_req_mgr_timer **crm_timer)
+{
+ CRM_DBG("destroy timer %pK", *crm_timer);
+ if (*crm_timer) {
+ del_timer(&(*crm_timer)->sys_timer);
+ kfree(*crm_timer);
+ *crm_timer = NULL;
+ }
+}
+
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_timer.h b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_timer.h
new file mode 100644
index 0000000..4d600ee
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_timer.h
@@ -0,0 +1,69 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CAM_REQ_MGR_TIMER_H_
+#define _CAM_REQ_MGR_TIMER_H_
+
+#include <linux/slab.h>
+#include <linux/timer.h>
+
+#include "cam_req_mgr_core_defs.h"
+
+/** struct cam_req_mgr_timer
+ * @expires : timeout value for timer
+ * @sys_timer : system timer variable
+ * @parent : priv data - link pointer
+ * @timer_cb : callback func which will be called when timeout expires
+ */
+struct cam_req_mgr_timer {
+ int32_t expires;
+ struct timer_list sys_timer;
+ void *parent;
+ void (*timer_cb)(unsigned long data);
+};
+
+/**
+ * crm_timer_modify()
+ * @brief : allows ser to modify expiry time.
+ * @timer : timer which will be reset to expires values
+ */
+void crm_timer_modify(struct cam_req_mgr_timer *crm_timer,
+ int32_t expires);
+
+/**
+ * crm_timer_reset()
+ * @brief : destroys the timer allocated.
+ * @timer : timer which will be reset to expires values
+ */
+void crm_timer_reset(struct cam_req_mgr_timer *timer);
+
+/**
+ * crm_timer_init()
+ * @brief : create a new general purpose timer.
+ * timer utility takes care of allocating memory and deleting
+ * @timer : double pointer to new timer allocated
+ * @expires : Timeout value to fire callback
+ * @parent : void pointer which caller can use for book keeping
+ * @timer_cb : caller can chose to use its own callback function when
+ * timer fires the timeout. If no value is set timer util
+ * will use default.
+ */
+int crm_timer_init(struct cam_req_mgr_timer **timer,
+ int32_t expires, void *parent, void (*timer_cb)(unsigned long));
+
+/**
+ * crm_timer_exit()
+ * @brief : destroys the timer allocated.
+ * @timer : timer pointer which will be freed
+ */
+void crm_timer_exit(struct cam_req_mgr_timer **timer);
+#endif
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_workq.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_workq.c
index 1f6a97a..f53e41c 100644
--- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_workq.c
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_workq.c
@@ -12,7 +12,7 @@
#include "cam_req_mgr_workq.h"
-/* workqueue's task manager methods */
+
struct crm_workq_task *cam_req_mgr_workq_get_task(
struct cam_req_mgr_core_workq *workq)
{
@@ -21,7 +21,7 @@
if (!workq)
return NULL;
- spin_lock(&workq->task.lock);
+ spin_lock_bh(&workq->lock_bh);
if (list_empty(&workq->task.empty_head))
goto end;
@@ -31,9 +31,9 @@
atomic_sub(1, &workq->task.free_cnt);
list_del_init(&task->entry);
}
-end:
- spin_unlock(&workq->task.lock);
+end:
+ spin_unlock_bh(&workq->lock_bh);
return task;
}
@@ -42,17 +42,20 @@
struct cam_req_mgr_core_workq *workq =
(struct cam_req_mgr_core_workq *)task->parent;
+ spin_lock_bh(&workq->lock_bh);
+ list_del_init(&task->entry);
task->cancel = 0;
task->process_cb = NULL;
task->priv = NULL;
list_add_tail(&task->entry,
&workq->task.empty_head);
atomic_add(1, &workq->task.free_cnt);
+ spin_unlock_bh(&workq->lock_bh);
}
/**
* cam_req_mgr_process_task() - Process the enqueued task
- * @task: pointer to task worker thread shall process
+ * @task: pointer to task workq thread shall process
*/
static int cam_req_mgr_process_task(struct crm_workq_task *task)
{
@@ -62,31 +65,10 @@
return -EINVAL;
workq = (struct cam_req_mgr_core_workq *)task->parent;
-
- switch (task->type) {
- case CRM_WORKQ_TASK_SCHED_REQ:
- case CRM_WORKQ_TASK_DEV_ADD_REQ:
- case CRM_WORKQ_TASK_NOTIFY_SOF:
- case CRM_WORKQ_TASK_NOTIFY_ACK:
- case CRM_WORKQ_TASK_NOTIFY_ERR:
- if (task->process_cb)
- task->process_cb(task->priv, &task->u);
- else
- CRM_WARN("FATAL:no task handler registered for workq!");
- break;
- case CRM_WORKQ_TASK_GET_DEV_INFO:
- case CRM_WORKQ_TASK_SETUP_LINK:
- case CRM_WORKQ_TASK_APPLY_REQ:
- /* These tasks are not expected to be queued to
- * workque at the present
- */
- CRM_DBG("Not supported");
- break;
- case CRM_WORKQ_TASK_INVALID:
- default:
- CRM_ERR("Invalid task type %x", task->type);
- break;
- }
+ if (task->process_cb)
+ task->process_cb(task->priv, task->payload);
+ else
+ CRM_WARN("FATAL:no task handler registered for workq");
cam_req_mgr_workq_put_task(task);
return 0;
@@ -99,8 +81,8 @@
static void cam_req_mgr_process_workq(struct work_struct *w)
{
struct cam_req_mgr_core_workq *workq = NULL;
- struct crm_workq_task *task, *task_save;
-
+ struct crm_workq_task *task, *task_save;
+ int32_t i = CRM_TASK_PRIORITY_0;
if (!w) {
CRM_ERR("NULL task pointer can not schedule");
return;
@@ -108,19 +90,44 @@
workq = (struct cam_req_mgr_core_workq *)
container_of(w, struct cam_req_mgr_core_workq, work);
- list_for_each_entry_safe(task, task_save,
- &workq->task.process_head, entry) {
- atomic_sub(1, &workq->task.pending_cnt);
- spin_lock(&workq->task.lock);
- list_del_init(&task->entry);
- spin_unlock(&workq->task.lock);
- cam_req_mgr_process_task(task);
+ while (i < CRM_TASK_PRIORITY_MAX) {
+ if (!list_empty(&workq->task.process_head[i])) {
+ list_for_each_entry_safe(task, task_save,
+ &workq->task.process_head[i], entry) {
+ atomic_sub(1, &workq->task.pending_cnt);
+ cam_req_mgr_process_task(task);
+ }
+ CRM_DBG("processed task %pK free_cnt %d",
+ task, atomic_read(&workq->task.free_cnt));
+ }
+ i++;
}
- CRM_DBG("processed task %p free_cnt %d",
- task, atomic_read(&workq->task.free_cnt));
}
-int cam_req_mgr_workq_enqueue_task(struct crm_workq_task *task)
+void crm_workq_clear_q(struct cam_req_mgr_core_workq *workq)
+{
+ int32_t i = CRM_TASK_PRIORITY_0;
+ struct crm_workq_task *task, *task_save;
+
+ CRM_DBG("pending_cnt %d",
+ atomic_read(&workq->task.pending_cnt));
+
+ while (i < CRM_TASK_PRIORITY_MAX) {
+ if (!list_empty(&workq->task.process_head[i])) {
+ list_for_each_entry_safe(task, task_save,
+ &workq->task.process_head[i], entry) {
+ cam_req_mgr_workq_put_task(task);
+ CRM_WARN("flush task %pK, %d, cnt %d",
+ task, i, atomic_read(
+ &workq->task.free_cnt));
+ }
+ }
+ i++;
+ }
+}
+
+int cam_req_mgr_workq_enqueue_task(struct crm_workq_task *task,
+ void *priv, int32_t prio)
{
int rc = 0;
struct cam_req_mgr_core_workq *workq = NULL;
@@ -132,31 +139,33 @@
}
workq = (struct cam_req_mgr_core_workq *)task->parent;
if (!workq) {
- CRM_WARN("NULL worker pointer suspect mem corruption");
+ CRM_DBG("NULL workq pointer suspect mem corruption");
rc = -EINVAL;
goto end;
}
if (!workq->job) {
- CRM_WARN("NULL worker pointer suspect mem corruption");
rc = -EINVAL;
goto end;
}
+ spin_lock_bh(&workq->lock_bh);
if (task->cancel == 1) {
cam_req_mgr_workq_put_task(task);
CRM_WARN("task aborted and queued back to pool");
rc = 0;
- spin_unlock(&workq->task.lock);
+ spin_unlock_bh(&workq->lock_bh);
goto end;
}
- spin_lock(&workq->task.lock);
+ task->priv = priv;
+ task->priority =
+ (prio < CRM_TASK_PRIORITY_MAX && prio >= CRM_TASK_PRIORITY_0)
+ ? prio : CRM_TASK_PRIORITY_0;
list_add_tail(&task->entry,
- &workq->task.process_head);
- spin_unlock(&workq->task.lock);
+ &workq->task.process_head[task->priority]);
atomic_add(1, &workq->task.pending_cnt);
- CRM_DBG("enq task %p pending_cnt %d",
+ CRM_DBG("enq task %pK pending_cnt %d",
task, atomic_read(&workq->task.pending_cnt));
-
+ spin_unlock_bh(&workq->lock_bh);
queue_work(workq->job, &workq->work);
@@ -164,7 +173,8 @@
return rc;
}
-int cam_req_mgr_workq_create(char *name, struct cam_req_mgr_core_workq **workq)
+int cam_req_mgr_workq_create(char *name, int32_t num_tasks,
+ struct cam_req_mgr_core_workq **workq)
{
int32_t i;
struct crm_workq_task *task;
@@ -189,20 +199,35 @@
/* Workq attributes initialization */
INIT_WORK(&crm_workq->work, cam_req_mgr_process_workq);
+ spin_lock_init(&crm_workq->lock_bh);
+ CRM_DBG("LOCK_DBG workq %s lock %pK",
+ name, &crm_workq->lock_bh);
/* Task attributes initialization */
- spin_lock_init(&crm_workq->task.lock);
atomic_set(&crm_workq->task.pending_cnt, 0);
atomic_set(&crm_workq->task.free_cnt, 0);
- INIT_LIST_HEAD(&crm_workq->task.process_head);
+ for (i = CRM_TASK_PRIORITY_0; i < CRM_TASK_PRIORITY_MAX; i++)
+ INIT_LIST_HEAD(&crm_workq->task.process_head[i]);
INIT_LIST_HEAD(&crm_workq->task.empty_head);
- memset(crm_workq->task.pool, 0,
- sizeof(struct crm_workq_task) *
- CRM_WORKQ_NUM_TASKS);
- for (i = 0; i < CRM_WORKQ_NUM_TASKS; i++) {
+ crm_workq->task.num_task = num_tasks;
+ crm_workq->task.pool = (struct crm_workq_task *)
+ kzalloc(sizeof(struct crm_workq_task) *
+ crm_workq->task.num_task,
+ GFP_KERNEL);
+ if (!crm_workq->task.pool) {
+ CRM_WARN("Insufficient memory %lu",
+ sizeof(struct crm_workq_task) *
+ crm_workq->task.num_task);
+ kfree(crm_workq);
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < crm_workq->task.num_task; i++) {
task = &crm_workq->task.pool[i];
task->parent = (void *)crm_workq;
/* Put all tasks in free pool */
+ list_add_tail(&task->entry,
+ &crm_workq->task.process_head[CRM_TASK_PRIORITY_0]);
cam_req_mgr_workq_put_task(task);
}
*workq = crm_workq;
@@ -213,15 +238,16 @@
return 0;
}
-void cam_req_mgr_workq_destroy(struct cam_req_mgr_core_workq *crm_workq)
+void cam_req_mgr_workq_destroy(struct cam_req_mgr_core_workq **crm_workq)
{
- CRM_DBG("destroy workque %p", crm_workq);
- if (crm_workq) {
- if (crm_workq->job) {
- destroy_workqueue(crm_workq->job);
- crm_workq->job = NULL;
+ CRM_DBG("destroy workque %pK", crm_workq);
+ if (*crm_workq) {
+ crm_workq_clear_q(*crm_workq);
+ if ((*crm_workq)->job) {
+ destroy_workqueue((*crm_workq)->job);
+ (*crm_workq)->job = NULL;
}
- kfree(crm_workq);
- crm_workq = NULL;
+ kfree(*crm_workq);
+ *crm_workq = NULL;
}
}
diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_workq.h b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_workq.h
index 6b36abc..7d8ca59 100644
--- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_workq.h
+++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_workq.h
@@ -10,8 +10,8 @@
* GNU General Public License for more details.
*/
-#ifndef _CAM_WORKER_H_
-#define _CAM_WORKER_H_
+#ifndef _CAM_REQ_MGR_WORKQ_H_
+#define _CAM_REQ_MGR_WORKQ_H_
#include<linux/kernel.h>
#include<linux/module.h>
@@ -23,99 +23,78 @@
#include "cam_req_mgr_core.h"
-/* Macros */
-#define CRM_WORKQ_NUM_TASKS 30
-
-/**enum crm_workq_task_type
- * @codes: to identify which type of task is present
- */
-enum crm_workq_task_type {
- CRM_WORKQ_TASK_GET_DEV_INFO,
- CRM_WORKQ_TASK_SETUP_LINK,
- CRM_WORKQ_TASK_SCHED_REQ,
- CRM_WORKQ_TASK_DEV_ADD_REQ,
- CRM_WORKQ_TASK_APPLY_REQ,
- CRM_WORKQ_TASK_NOTIFY_SOF,
- CRM_WORKQ_TASK_NOTIFY_ACK,
- CRM_WORKQ_TASK_NOTIFY_ERR,
- CRM_WORKQ_TASK_INVALID,
+/* Task priorities, lower the number higher the priority*/
+enum crm_task_priority {
+ CRM_TASK_PRIORITY_0 = 0,
+ CRM_TASK_PRIORITY_1 = 1,
+ CRM_TASK_PRIORITY_MAX = 2,
};
/** struct crm_workq_task
- * @type: type of task
- * u -
- * @csl_req: contains info of incoming reqest from CSL to CRM
- * @dev_req: contains tracking info of available req id at device
- * @apply_req: contains info of which request is applied at device
- * @notify_sof: contains notification from IFE to CRM about SOF trigger
- * @notify_err: contains error inf happened while processing request
- * @dev_info: contains info about which device is connected with CRM
- * @link_setup: contains info about new link being setup
- * -
- * @process_cb: registered callback called by workq when task enqueued is ready
- * for processing in workq thread context
- * @parent: workq's parent is link which is enqqueing taks to this workq
- * @entry: list head of this list entry is worker's empty_head
- * @cancel: if caller has got free task from pool but wants to abort or put
- * back without using it
- * @priv: when task is enqueuer caller can attach cookie
+ * @priority : caller can assign priority to task based on type.
+ * @payload : depending of user of task this payload type will change
+ * @process_cb : registered callback called by workq when task enqueued is
+ * ready for processing in workq thread context
+ * @parent : workq's parent is link which is enqqueing taks to this workq
+ * @entry : list head of this list entry is worker's empty_head
+ * @cancel : if caller has got free task from pool but wants to abort
+ * or put back without using it
+ * @priv : when task is enqueuer caller can attach priv along which
+ * it will get in process callback
+ * @ret : return value in future to use for blocking calls
*/
struct crm_workq_task {
- enum crm_workq_task_type type;
- union {
- struct cam_req_mgr_sched_request csl_req;
- struct cam_req_mgr_add_request dev_req;
- struct cam_req_mgr_apply_request apply_req;
- struct cam_req_mgr_sof_notify notify_sof;
- struct cam_req_mgr_error_notify notify_err;
- struct cam_req_mgr_device_info dev_info;
- struct cam_req_mgr_core_dev_link_setup link_setup;
- } u;
- int (*process_cb)(void *, void *);
- void *parent;
- struct list_head entry;
- uint8_t cancel;
- void *priv;
+ int32_t priority;
+ void *payload;
+ int32_t (*process_cb)(void *, void *);
+ void *parent;
+ struct list_head entry;
+ uint8_t cancel;
+ void *priv;
+ int32_t ret;
};
-/** struct crm_core_worker
- * @work: work token used by workqueue
- * @job: workqueue internal job struct
- *task -
- * @lock: lock for task structs
- * @pending_cnt: num of tasks pending to be processed
- * @free_cnt: num of free/available tasks
- * @process_head: list head of tasks pending process
- * @empty_head: list head of available tasks which can be used
- * or acquired in order to enqueue a task to workq
- * @pool: pool of tasks used for handling events in workq context
- *@num_task : size of tasks pool
+/** struct cam_req_mgr_core_workq
+ * @work : work token used by workqueue
+ * @job : workqueue internal job struct
+ * task -
+ * @lock : lock for task structs
+ * @free_cnt : num of free/available tasks
+ * @empty_head : list head of available taska which can be used
+ * or acquired in order to enqueue a task to workq
+ * @pool : pool of tasks used for handling events in workq context
+ * @num_task : size of tasks pool
+ * -
*/
struct cam_req_mgr_core_workq {
- struct work_struct work;
- struct workqueue_struct *job;
+ struct work_struct work;
+ struct workqueue_struct *job;
+ spinlock_t lock_bh;
+ /* tasks */
struct {
- spinlock_t lock;
- atomic_t pending_cnt;
- atomic_t free_cnt;
+ struct mutex lock;
+ atomic_t pending_cnt;
+ atomic_t free_cnt;
- struct list_head process_head;
- struct list_head empty_head;
- struct crm_workq_task pool[CRM_WORKQ_NUM_TASKS];
+ struct list_head process_head[CRM_TASK_PRIORITY_MAX];
+ struct list_head empty_head;
+ struct crm_workq_task *pool;
+ uint32_t num_task;
} task;
};
/**
* cam_req_mgr_workq_create()
- * @brief: create a workqueue
- * @name: Name of the workque to be allocated,
- * it is combination of session handle and link handle
- * @workq: Double pointer worker
+ * @brief : create a workqueue
+ * @name : Name of the workque to be allocated, it is combination
+ * of session handle and link handle
+ * @num_task : Num_tasks to be allocated for workq
+ * @workq : Double pointer worker
* This function will allocate and create workqueue and pass
- * the worker pointer to caller.
+ * the workq pointer to caller.
*/
-int cam_req_mgr_workq_create(char *name,
+int cam_req_mgr_workq_create(char *name, int32_t num_tasks,
struct cam_req_mgr_core_workq **workq);
/**
@@ -125,15 +104,18 @@
* this function will destroy workqueue and clean up resources
* associated with worker such as tasks.
*/
-void cam_req_mgr_workq_destroy(struct cam_req_mgr_core_workq *workq);
+void cam_req_mgr_workq_destroy(struct cam_req_mgr_core_workq **workq);
/**
* cam_req_mgr_workq_enqueue_task()
* @brief: Enqueue task in worker queue
- * @task: task to be processed by worker
+ * @task : task to be processed by worker
+ * @priv : clients private data
+ * @prio : task priority
* process callback func
*/
-int cam_req_mgr_workq_enqueue_task(struct crm_workq_task *task);
+int cam_req_mgr_workq_enqueue_task(struct crm_workq_task *task,
+ void *priv, int32_t prio);
/**
* cam_req_mgr_workq_get_task()
diff --git a/drivers/media/platform/msm/camera/cam_sync/cam_sync_util.c b/drivers/media/platform/msm/camera/cam_sync/cam_sync_util.c
index 4f5bf87..ecc62c8 100644
--- a/drivers/media/platform/msm/camera/cam_sync/cam_sync_util.c
+++ b/drivers/media/platform/msm/camera/cam_sync/cam_sync_util.c
@@ -57,6 +57,48 @@
return 0;
}
+uint32_t cam_sync_util_get_group_object_state(struct sync_table_row *table,
+ uint32_t *sync_objs,
+ uint32_t num_objs)
+{
+ int i;
+ struct sync_table_row *child_row = NULL;
+ int success_count = 0;
+ int active_count = 0;
+
+ if (!table || !sync_objs)
+ return CAM_SYNC_STATE_SIGNALED_ERROR;
+
+ /*
+ * We need to arrive at the state of the merged object based on
+ * counts of error, active and success states of all children objects
+ */
+ for (i = 0; i < num_objs; i++) {
+ child_row = table + sync_objs[i];
+ switch (child_row->state) {
+ case CAM_SYNC_STATE_SIGNALED_ERROR:
+ return CAM_SYNC_STATE_SIGNALED_ERROR;
+ case CAM_SYNC_STATE_SIGNALED_SUCCESS:
+ success_count++;
+ break;
+ case CAM_SYNC_STATE_ACTIVE:
+ active_count++;
+ break;
+ default:
+ pr_err("Invalid state of child object during merge\n");
+ return CAM_SYNC_STATE_SIGNALED_ERROR;
+ }
+ }
+
+ if (active_count)
+ return CAM_SYNC_STATE_ACTIVE;
+
+ if (success_count == num_objs)
+ return CAM_SYNC_STATE_SIGNALED_SUCCESS;
+
+ return CAM_SYNC_STATE_SIGNALED_ERROR;
+}
+
int cam_sync_init_group_object(struct sync_table_row *table,
uint32_t idx,
uint32_t *sync_objs,
@@ -113,12 +155,16 @@
row->type = CAM_SYNC_TYPE_GROUP;
row->sync_id = idx;
- row->state = CAM_SYNC_STATE_ACTIVE;
+ row->state = cam_sync_util_get_group_object_state(table,
+ sync_objs, num_objs);
row->remaining = num_objs;
init_completion(&row->signaled);
INIT_LIST_HEAD(&row->callback_list);
INIT_LIST_HEAD(&row->user_payload_list);
+ if (row->state != CAM_SYNC_STATE_ACTIVE)
+ complete_all(&row->signaled);
+
spin_unlock_bh(&sync_dev->row_spinlocks[idx]);
return 0;
}
@@ -208,6 +254,11 @@
int i;
struct sync_table_row *row = NULL;
+ if (num_objs <= 1) {
+ pr_err("Single object merge is not allowed\n");
+ return -EINVAL;
+ }
+
for (i = 0; i < num_objs; i++) {
row = sync_dev->sync_table + sync_obj[i];
spin_lock_bh(&sync_dev->row_spinlocks[sync_obj[i]]);
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c
index 8bd5d4d..30fda07 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c
@@ -25,6 +25,7 @@
#include <linux/msm-bus-board.h>
#include <linux/regulator/consumer.h>
#include <linux/dma-direction.h>
+#include <linux/sde_rsc.h>
#include <soc/qcom/scm.h>
#include <soc/qcom/secure_buffer.h>
#include <asm/cacheflush.h>
@@ -293,7 +294,7 @@
SDEROT_DBG("core_clk %lu\n", total_clk_rate);
ATRACE_INT("core_clk", total_clk_rate);
- sde_rotator_set_clk_rate(mgr, total_clk_rate, SDE_ROTATOR_CLK_ROT_CORE);
+ sde_rotator_set_clk_rate(mgr, total_clk_rate, SDE_ROTATOR_CLK_MDSS_ROT);
return 0;
}
@@ -318,8 +319,13 @@
if (mgr->ops_hw_pre_pmevent)
mgr->ops_hw_pre_pmevent(mgr, on);
- ret = sde_rot_enable_vreg(mgr->module_power.vreg_config,
- mgr->module_power.num_vreg, on);
+ if (mgr->rsc_client)
+ ret = sde_rsc_client_state_update(mgr->rsc_client,
+ on ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE,
+ NULL, -1);
+ else
+ ret = sde_rot_enable_vreg(mgr->module_power.vreg_config,
+ mgr->module_power.num_vreg, on);
if (ret) {
SDEROT_WARN("Rotator regulator failed to %s\n",
on ? "enable" : "disable");
@@ -406,13 +412,13 @@
if (ret)
goto error_mdss_axi;
ret = sde_rotator_enable_clk(mgr,
- SDE_ROTATOR_CLK_ROT_CORE);
- if (ret)
- goto error_rot_core;
- ret = sde_rotator_enable_clk(mgr,
SDE_ROTATOR_CLK_MDSS_ROT);
if (ret)
goto error_mdss_rot;
+ ret = sde_rotator_enable_clk(mgr,
+ SDE_ROTATOR_CLK_MDSS_ROT_SUB);
+ if (ret)
+ goto error_rot_sub;
/* Active+Sleep */
msm_bus_scale_client_update_context(
@@ -420,8 +426,9 @@
mgr->data_bus.curr_bw_uc_idx);
trace_rot_bw_ao_as_context(0);
} else {
+ sde_rotator_disable_clk(mgr,
+ SDE_ROTATOR_CLK_MDSS_ROT_SUB);
sde_rotator_disable_clk(mgr, SDE_ROTATOR_CLK_MDSS_ROT);
- sde_rotator_disable_clk(mgr, SDE_ROTATOR_CLK_ROT_CORE);
sde_rotator_disable_clk(mgr, SDE_ROTATOR_CLK_MDSS_AXI);
sde_rotator_disable_clk(mgr, SDE_ROTATOR_CLK_MDSS_AHB);
sde_rotator_disable_clk(mgr, SDE_ROTATOR_CLK_GCC_AXI);
@@ -437,9 +444,9 @@
}
return ret;
+error_rot_sub:
+ sde_rotator_disable_clk(mgr, SDE_ROTATOR_CLK_MDSS_ROT);
error_mdss_rot:
- sde_rotator_disable_clk(mgr, SDE_ROTATOR_CLK_ROT_CORE);
-error_rot_core:
sde_rotator_disable_clk(mgr, SDE_ROTATOR_CLK_MDSS_AXI);
error_mdss_axi:
sde_rotator_disable_clk(mgr, SDE_ROTATOR_CLK_MDSS_AHB);
@@ -550,6 +557,12 @@
if (!input)
dir = DMA_FROM_DEVICE;
+ if (buffer->plane_count > SDE_ROT_MAX_PLANES) {
+ SDEROT_ERR("buffer plane_count exceeds MAX_PLANE limit:%d\n",
+ buffer->plane_count);
+ return -EINVAL;
+ }
+
data->sbuf = buffer->sbuf;
data->scid = buffer->scid;
data->writeback = buffer->writeback;
@@ -2730,11 +2743,19 @@
sde_rotator_search_dt_clk(pdev, mgr, "axi_clk",
SDE_ROTATOR_CLK_MDSS_AXI, true) ||
sde_rotator_search_dt_clk(pdev, mgr, "rot_core_clk",
- SDE_ROTATOR_CLK_ROT_CORE, true) ||
- sde_rotator_search_dt_clk(pdev, mgr, "rot_clk",
- SDE_ROTATOR_CLK_MDSS_ROT, true))
+ SDE_ROTATOR_CLK_MDSS_ROT, false))
rc = -EINVAL;
+ /*
+ * If 'MDSS_ROT' is already present, place 'rot_clk' under
+ * MDSS_ROT_SUB. Otherwise, place it directly into MDSS_ROT.
+ */
+ if (sde_rotator_get_clk(mgr, SDE_ROTATOR_CLK_MDSS_ROT))
+ rc = sde_rotator_search_dt_clk(pdev, mgr, "rot_clk",
+ SDE_ROTATOR_CLK_MDSS_ROT_SUB, true);
+ else
+ rc = sde_rotator_search_dt_clk(pdev, mgr, "rot_clk",
+ SDE_ROTATOR_CLK_MDSS_ROT, true);
clk_err:
return rc;
}
@@ -2765,9 +2786,21 @@
{
int ret;
- ret = sde_rotator_get_dt_vreg_data(&pdev->dev, &mgr->module_power);
- if (ret)
+ mgr->rsc_client = sde_rsc_client_create(
+ SDE_RSC_INDEX, "sde_rotator_core", false);
+ if (IS_ERR(mgr->rsc_client)) {
+ ret = PTR_ERR(mgr->rsc_client);
+ pr_err("rsc client create returned %d\n", ret);
+ mgr->rsc_client = NULL;
return ret;
+ }
+
+ if (!mgr->rsc_client) {
+ ret = sde_rotator_get_dt_vreg_data(
+ &pdev->dev, &mgr->module_power);
+ if (ret)
+ return ret;
+ }
ret = sde_rotator_register_clk(pdev, mgr);
if (ret)
@@ -2787,9 +2820,15 @@
{
struct platform_device *pdev = mgr->pdev;
- sde_rotator_put_dt_vreg_data(&pdev->dev, &mgr->module_power);
sde_rotator_unregister_clk(mgr);
sde_rotator_bus_scale_unregister(mgr);
+
+ if (mgr->rsc_client) {
+ sde_rsc_client_destroy(mgr->rsc_client);
+ mgr->rsc_client = NULL;
+ } else {
+ sde_rotator_put_dt_vreg_data(&pdev->dev, &mgr->module_power);
+ }
}
int sde_rotator_core_init(struct sde_rot_mgr **pmgr,
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.h b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.h
index 819f57b..0051e96 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.h
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.h
@@ -125,7 +125,7 @@
enum sde_rotator_clk_type {
SDE_ROTATOR_CLK_MDSS_AHB,
SDE_ROTATOR_CLK_MDSS_AXI,
- SDE_ROTATOR_CLK_ROT_CORE,
+ SDE_ROTATOR_CLK_MDSS_ROT_SUB,
SDE_ROTATOR_CLK_MDSS_ROT,
SDE_ROTATOR_CLK_MNOC_AHB,
SDE_ROTATOR_CLK_GCC_AHB,
@@ -373,6 +373,7 @@
* @reg_bus: register bus configuration state
* @module_power: power/clock configuration state
* @regulator_enable: true if foot switch is enabled; false otherwise
+ * @rsc_client: pointer to rsc client handle
* @res_ref_cnt: reference count of how many times resource is requested
* @rot_enable_clk_cnt: reference count of how many times clock is requested
* @rot_clk: array of rotator and periphery clocks
@@ -417,6 +418,8 @@
struct sde_module_power module_power;
bool regulator_enable;
+ struct sde_rsc_client *rsc_client;
+
int res_ref_cnt;
int rot_enable_clk_cnt;
struct sde_rot_clk *rot_clk;
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c
index 15ecc10..90b7194 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c
@@ -438,6 +438,8 @@
{
struct sde_rotator_ctx *ctx = vb2_get_drv_priv(q);
struct sde_rotator_device *rot_dev = ctx->rot_dev;
+ struct sde_rotator_request *request;
+ struct list_head *curr, *next;
int i;
int ret;
@@ -458,6 +460,21 @@
sde_rot_mgr_lock(rot_dev->mgr);
sde_rotator_cancel_all_requests(rot_dev->mgr, ctx->private);
sde_rot_mgr_unlock(rot_dev->mgr);
+ list_for_each_safe(curr, next, &ctx->pending_list) {
+ request = container_of(curr, struct sde_rotator_request,
+ list);
+
+ SDEDEV_DBG(rot_dev->dev, "cancel request s:%d\n",
+ ctx->session_id);
+ mutex_unlock(q->lock);
+ cancel_work_sync(&request->submit_work);
+ cancel_work_sync(&request->retire_work);
+ mutex_lock(q->lock);
+ spin_lock(&ctx->list_lock);
+ list_del_init(&request->list);
+ list_add_tail(&request->list, &ctx->retired_list);
+ spin_unlock(&ctx->list_lock);
+ }
}
sde_rotator_return_all_buffers(q, VB2_BUF_STATE_ERROR);
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
index 2672f1e..c147b0b 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
@@ -52,8 +52,8 @@
/* default stream buffer headroom in lines */
#define DEFAULT_SBUF_HEADROOM 20
-#define DEFAULT_UBWC_MALSIZE 1
-#define DEFAULT_UBWC_SWIZZLE 1
+#define DEFAULT_UBWC_MALSIZE 0
+#define DEFAULT_UBWC_SWIZZLE 0
#define DEFAULT_MAXLINEWIDTH 4096
@@ -3082,9 +3082,9 @@
goto error_hw_rev_init;
/* set rotator CBCR to shutoff memory/periphery on clock off.*/
- clk_set_flags(mgr->rot_clk[SDE_ROTATOR_CLK_ROT_CORE].clk,
+ clk_set_flags(mgr->rot_clk[SDE_ROTATOR_CLK_MDSS_ROT].clk,
CLKFLAG_NORETAIN_MEM);
- clk_set_flags(mgr->rot_clk[SDE_ROTATOR_CLK_ROT_CORE].clk,
+ clk_set_flags(mgr->rot_clk[SDE_ROTATOR_CLK_MDSS_ROT].clk,
CLKFLAG_NORETAIN_PERIPH);
mdata->sde_rot_hw = rot;
diff --git a/drivers/media/platform/msm/vidc/hfi_packetization.c b/drivers/media/platform/msm/vidc/hfi_packetization.c
index 6c49ff5..6601c9a 100644
--- a/drivers/media/platform/msm/vidc/hfi_packetization.c
+++ b/drivers/media/platform/msm/vidc/hfi_packetization.c
@@ -920,6 +920,8 @@
pkt->session_id = hash32_ptr(session);
pkt->num_properties = 1;
+ dprintk(VIDC_DBG, "Setting HAL Property = 0x%x\n", ptype);
+
switch (ptype) {
case HAL_CONFIG_FRAME_RATE:
{
@@ -1478,22 +1480,22 @@
pkt->size += sizeof(u32) + sizeof(struct hfi_enable);
break;
}
- case HAL_PARAM_VENC_H264_VUI_TIMING_INFO:
+ case HAL_PARAM_VENC_VUI_TIMING_INFO:
{
- struct hfi_h264_vui_timing_info *hfi;
- struct hal_h264_vui_timing_info *timing_info = pdata;
+ struct hfi_vui_timing_info *hfi;
+ struct hal_vui_timing_info *timing_info = pdata;
pkt->rg_property_data[0] =
- HFI_PROPERTY_PARAM_VENC_H264_VUI_TIMING_INFO;
+ HFI_PROPERTY_PARAM_VENC_VUI_TIMING_INFO;
- hfi = (struct hfi_h264_vui_timing_info *)&pkt->
+ hfi = (struct hfi_vui_timing_info *)&pkt->
rg_property_data[1];
hfi->enable = timing_info->enable;
hfi->fixed_frame_rate = timing_info->fixed_frame_rate;
hfi->time_scale = timing_info->time_scale;
pkt->size += sizeof(u32) +
- sizeof(struct hfi_h264_vui_timing_info);
+ sizeof(struct hfi_vui_timing_info);
break;
}
case HAL_CONFIG_VPE_DEINTERLACE:
diff --git a/drivers/media/platform/msm/vidc/msm_v4l2_vidc.c b/drivers/media/platform/msm/vidc/msm_v4l2_vidc.c
index c82db74..c5c4269 100644
--- a/drivers/media/platform/msm/vidc/msm_v4l2_vidc.c
+++ b/drivers/media/platform/msm/vidc/msm_v4l2_vidc.c
@@ -135,6 +135,14 @@
return msm_vidc_s_ext_ctrl((void *)vidc_inst, a);
}
+int msm_v4l2_g_ext_ctrl(struct file *file, void *fh,
+ struct v4l2_ext_controls *a)
+{
+ struct msm_vidc_inst *vidc_inst = get_vidc_inst(file, fh);
+
+ return msm_vidc_g_ext_ctrl((void *)vidc_inst, a);
+}
+
int msm_v4l2_reqbufs(struct file *file, void *fh,
struct v4l2_requestbuffers *b)
{
@@ -250,6 +258,7 @@
.vidioc_g_ctrl = msm_v4l2_g_ctrl,
.vidioc_queryctrl = msm_v4l2_queryctrl,
.vidioc_s_ext_ctrls = msm_v4l2_s_ext_ctrl,
+ .vidioc_g_ext_ctrls = msm_v4l2_g_ext_ctrl,
.vidioc_subscribe_event = msm_v4l2_subscribe_event,
.vidioc_unsubscribe_event = msm_v4l2_unsubscribe_event,
.vidioc_decoder_cmd = msm_v4l2_decoder_cmd,
diff --git a/drivers/media/platform/msm/vidc/msm_vdec.c b/drivers/media/platform/msm/vidc/msm_vdec.c
index 3d3b7e9..a86c677 100644
--- a/drivers/media/platform/msm/vidc/msm_vdec.c
+++ b/drivers/media/platform/msm/vidc/msm_vdec.c
@@ -23,7 +23,6 @@
#define MIN_NUM_THUMBNAIL_MODE_CAPTURE_BUFFERS MIN_NUM_CAPTURE_BUFFERS
#define DEFAULT_VIDEO_CONCEAL_COLOR_BLACK 0x8010
#define MB_SIZE_IN_PIXEL (16 * 16)
-#define MAX_OPERATING_FRAME_RATE (300 << 16)
#define OPERATING_FRAME_RATE_STEP (1 << 16)
static const char *const mpeg_video_stream_format[] = {
@@ -360,7 +359,7 @@
.name = "Set Decoder Operating rate",
.type = V4L2_CTRL_TYPE_INTEGER,
.minimum = 0,
- .maximum = MAX_OPERATING_FRAME_RATE,
+ .maximum = INT_MAX,
.default_value = 0,
.step = OPERATING_FRAME_RATE_STEP,
},
@@ -368,17 +367,6 @@
#define NUM_CTRLS ARRAY_SIZE(msm_vdec_ctrls)
-static u32 get_frame_size_nv12(int plane,
- u32 height, u32 width)
-{
- return VENUS_BUFFER_SIZE(COLOR_FMT_NV12, width, height);
-}
-
-static u32 get_frame_size_nv12_ubwc(int plane, u32 height, u32 width)
-{
- return VENUS_BUFFER_SIZE(COLOR_FMT_NV12_UBWC, width, height);
-}
-
static u32 get_frame_size_compressed_full_yuv(int plane,
u32 max_mbs_per_frame, u32 size_per_mb)
{
@@ -391,11 +379,6 @@
return (max_mbs_per_frame * size_per_mb * 3/2)/2;
}
-static u32 get_frame_size_nv12_ubwc_10bit(int plane, u32 height, u32 width)
-{
- return VENUS_BUFFER_SIZE(COLOR_FMT_NV12_BPP10_UBWC, width, height);
-}
-
static u32 get_frame_size(struct msm_vidc_inst *inst,
const struct msm_vidc_format *fmt,
int fmt_type, int plane)
@@ -446,7 +429,7 @@
.name = "UBWC YCbCr Semiplanar 4:2:0 10bit",
.description = "UBWC Y/CbCr 4:2:0 10bit",
.fourcc = V4L2_PIX_FMT_NV12_TP10_UBWC,
- .get_frame_size = get_frame_size_nv12_ubwc_10bit,
+ .get_frame_size = get_frame_size_tp10_ubwc,
.type = CAPTURE_PORT,
},
{
@@ -681,7 +664,7 @@
inst->bufq[OUTPUT_PORT].num_planes = 1;
inst->bufq[CAPTURE_PORT].num_planes = 1;
inst->prop.fps = DEFAULT_FPS;
- inst->operating_rate = 0;
+ inst->clk_data.operating_rate = 0;
memcpy(&inst->fmts[OUTPUT_PORT], &vdec_formats[2],
sizeof(struct msm_vidc_format));
memcpy(&inst->fmts[CAPTURE_PORT], &vdec_formats[0],
@@ -968,8 +951,12 @@
case V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE:
dprintk(VIDC_DBG,
"inst(%pK) operating rate changed from %d to %d\n",
- inst, inst->operating_rate >> 16, ctrl->val >> 16);
- inst->operating_rate = ctrl->val;
+ inst, inst->clk_data.operating_rate >> 16,
+ ctrl->val >> 16);
+ inst->clk_data.operating_rate = ctrl->val;
+
+ msm_vidc_update_operating_rate(inst);
+
break;
default:
break;
@@ -980,8 +967,8 @@
if (!rc && property_id) {
dprintk(VIDC_DBG,
- "Control: HAL property=%#x,ctrl: id=%#x,value=%#x\n",
- property_id, ctrl->id, ctrl->val);
+ "Control: Name = %s, ID = 0x%x Value = %d\n",
+ ctrl->name, ctrl->id, ctrl->val);
rc = call_hfi_op(hdev, session_set_property, (void *)
inst->session, property_id, pdata);
}
diff --git a/drivers/media/platform/msm/vidc/msm_venc.c b/drivers/media/platform/msm/vidc/msm_venc.c
index 91d657d..006cd49 100644
--- a/drivers/media/platform/msm/vidc/msm_venc.c
+++ b/drivers/media/platform/msm/vidc/msm_venc.c
@@ -23,7 +23,6 @@
#define DEFAULT_BIT_RATE 64000
#define BIT_RATE_STEP 100
#define DEFAULT_FRAME_RATE 15
-#define MAX_OPERATING_FRAME_RATE (300 << 16)
#define OPERATING_FRAME_RATE_STEP (1 << 16)
#define MAX_SLICE_BYTE_SIZE ((MAX_BIT_RATE)>>3)
#define MIN_SLICE_BYTE_SIZE 512
@@ -878,7 +877,7 @@
.name = "Set Encoder Operating rate",
.type = V4L2_CTRL_TYPE_INTEGER,
.minimum = 0,
- .maximum = MAX_OPERATING_FRAME_RATE,
+ .maximum = INT_MAX,
.default_value = 0,
.step = OPERATING_FRAME_RATE_STEP,
},
@@ -989,31 +988,20 @@
(1 << V4L2_CID_MPEG_VIDC_VIDEO_IFRAME_SIZE_UNLIMITED)),
.qmenu = iframe_sizes,
},
+ {
+ .id = V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
+ .name = "Frame Rate based Rate Control",
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .minimum = 0,
+ .maximum = 1,
+ .default_value = 0,
+ .step = 1,
+ },
};
#define NUM_CTRLS ARRAY_SIZE(msm_venc_ctrls)
-static u32 get_frame_size_nv12(int plane, u32 height, u32 width)
-{
- return VENUS_BUFFER_SIZE(COLOR_FMT_NV12, width, height);
-}
-
-static u32 get_frame_size_nv12_ubwc(int plane, u32 height, u32 width)
-{
- return VENUS_BUFFER_SIZE(COLOR_FMT_NV12_UBWC, width, height);
-}
-
-static u32 get_frame_size_rgba(int plane, u32 height, u32 width)
-{
- return VENUS_BUFFER_SIZE(COLOR_FMT_RGBA8888, width, height);
-}
-
-static u32 get_frame_size_nv21(int plane, u32 height, u32 width)
-{
- return VENUS_BUFFER_SIZE(COLOR_FMT_NV21, width, height);
-}
-
static u32 get_frame_size_compressed(int plane, u32 height, u32 width)
{
int sz = ALIGN(height, 32) * ALIGN(width, 32) * 3 / 2;
@@ -1071,6 +1059,13 @@
.get_frame_size = get_frame_size_nv21,
.type = OUTPUT_PORT,
},
+ {
+ .name = "TP10 UBWC 4:2:0",
+ .description = "TP10 UBWC 4:2:0",
+ .fourcc = V4L2_PIX_FMT_NV12_TP10_UBWC,
+ .get_frame_size = get_frame_size_tp10_ubwc,
+ .type = OUTPUT_PORT,
+ },
};
static int msm_venc_set_csc(struct msm_vidc_inst *inst);
@@ -1145,6 +1140,7 @@
int max_hierp_layers;
int baselayerid = 0;
struct hal_video_signal_info signal_info = {0};
+ struct hal_vui_timing_info vui_timing_info = {0};
enum hal_iframesize_type iframesize_type = HAL_IFRAMESIZE_TYPE_DEFAULT;
if (!inst || !inst->core || !inst->core->device) {
@@ -1233,9 +1229,9 @@
{
property_id = HAL_CONFIG_VENC_TARGET_BITRATE;
bitrate.bit_rate = ctrl->val;
- bitrate.layer_id = 0;
+ bitrate.layer_id = MSM_VIDC_ALL_LAYER_ID;
pdata = &bitrate;
- inst->bitrate = ctrl->val;
+ inst->clk_data.bitrate = ctrl->val;
break;
}
case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK:
@@ -1257,7 +1253,7 @@
property_id = HAL_CONFIG_VENC_MAX_BITRATE;
bitrate.bit_rate = ctrl->val;
- bitrate.layer_id = 0;
+ bitrate.layer_id = MSM_VIDC_ALL_LAYER_ID;
pdata = &bitrate;
break;
}
@@ -1747,8 +1743,12 @@
case V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE:
dprintk(VIDC_DBG,
"inst(%pK) operating rate changed from %d to %d\n",
- inst, inst->operating_rate >> 16, ctrl->val >> 16);
- inst->operating_rate = ctrl->val;
+ inst, inst->clk_data.operating_rate >> 16,
+ ctrl->val >> 16);
+ inst->clk_data.operating_rate = ctrl->val;
+
+ msm_vidc_update_operating_rate(inst);
+
break;
case V4L2_CID_MPEG_VIDC_VIDEO_VENC_BITRATE_TYPE:
{
@@ -1831,6 +1831,7 @@
else
enable.enable = 0;
pdata = &enable;
+ inst->clk_data.low_latency_mode = (bool) enable.enable;
break;
}
case V4L2_CID_MPEG_VIDC_VIDEO_H264_TRANSFORM_8x8:
@@ -1858,6 +1859,43 @@
ctrl->val);
pdata = &iframesize_type;
break;
+ case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
+ {
+ property_id = HAL_PARAM_VENC_DISABLE_RC_TIMESTAMP;
+ enable.enable = ctrl->val;
+ pdata = &enable;
+ break;
+ }
+ case V4L2_CID_MPEG_VIDC_VIDEO_VUI_TIMING_INFO:
+ {
+ struct v4l2_ctrl *rc_mode;
+ bool cfr = false;
+
+ property_id = HAL_PARAM_VENC_VUI_TIMING_INFO;
+ pdata = &vui_timing_info;
+
+ if (ctrl->val != V4L2_MPEG_VIDC_VIDEO_VUI_TIMING_INFO_ENABLED) {
+ vui_timing_info.enable = 0;
+ break;
+ }
+
+ rc_mode = TRY_GET_CTRL(V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL);
+
+ switch (rc_mode->val) {
+ case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR:
+ case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_CBR_CFR:
+ case V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR:
+ cfr = true;
+ break;
+ default:
+ cfr = false;
+ }
+
+ vui_timing_info.enable = 1;
+ vui_timing_info.fixed_frame_rate = cfr;
+ vui_timing_info.time_scale = NSEC_PER_SEC;
+ break;
+ }
default:
dprintk(VIDC_ERR, "Unsupported index: %x\n", ctrl->id);
rc = -ENOTSUPP;
@@ -1868,9 +1906,9 @@
#undef TRY_GET_CTRL
if (!rc && property_id) {
- dprintk(VIDC_DBG, "Control: HAL property=%x,ctrl_value=%d\n",
- property_id,
- ctrl->val);
+ dprintk(VIDC_DBG,
+ "Control: Name = %s, ID = 0x%x Value = %d\n",
+ ctrl->name, ctrl->id, ctrl->val);
rc = call_hfi_op(hdev, session_set_property,
(void *)inst->session, property_id, pdata);
}
@@ -1967,6 +2005,7 @@
/* Enable QP for all frame types by default */
qp.enable = 7;
qp_range.layer_id = control[i].value;
+ bitrate.layer_id = control[i].value;
i++;
while (i < ctrl->count) {
switch (control[i].id) {
@@ -2083,7 +2122,7 @@
/* To start with, both ports are 1 plane each */
inst->bufq[OUTPUT_PORT].num_planes = 1;
inst->bufq[CAPTURE_PORT].num_planes = 1;
- inst->operating_rate = 0;
+ inst->clk_data.operating_rate = 0;
memcpy(&inst->fmts[CAPTURE_PORT], &venc_formats[4],
sizeof(struct msm_vidc_format));
diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c
index e071037..576809b 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc.c
@@ -28,6 +28,8 @@
static int try_get_ctrl(struct msm_vidc_inst *inst,
struct v4l2_ctrl *ctrl);
+static int msm_vidc_get_count(struct msm_vidc_inst *inst,
+ struct v4l2_ctrl *ctrl);
static int get_poll_flags(void *instance)
{
@@ -274,6 +276,40 @@
}
EXPORT_SYMBOL(msm_vidc_g_ctrl);
+int msm_vidc_g_ext_ctrl(void *instance, struct v4l2_ext_controls *control)
+{
+ struct msm_vidc_inst *inst = instance;
+ struct v4l2_ext_control *ext_control;
+ struct v4l2_ctrl ctrl;
+ int i = 0, rc = 0;
+
+ if (!inst || !control)
+ return -EINVAL;
+
+ ext_control = control->controls;
+
+ for (i = 0; i < control->count; i++) {
+ switch (ext_control[i].id) {
+ case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE:
+ case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:
+ ctrl.id = ext_control[i].id;
+ ctrl.val = ext_control[i].value;
+
+ msm_vidc_get_count(inst, &ctrl);
+ ext_control->value = ctrl.val;
+ break;
+ default:
+ dprintk(VIDC_ERR,
+ "This control %x is not supported yet\n",
+ ext_control[i].id);
+ rc = -EINVAL;
+ break;
+ }
+ }
+ return rc;
+}
+EXPORT_SYMBOL(msm_vidc_g_ext_ctrl);
+
int msm_vidc_s_ext_ctrl(void *instance, struct v4l2_ext_controls *control)
{
struct msm_vidc_inst *inst = instance;
@@ -1187,6 +1223,8 @@
buf_count.buffer_type = type;
buf_count.buffer_count_actual = act_count;
buf_count.buffer_count_min_host = host_count;
+ dprintk(VIDC_DBG, "%s : Act count = %d Host count = %d\n",
+ __func__, act_count, host_count);
rc = call_hfi_op(hdev, session_set_property,
inst->session, HAL_PARAM_BUFFER_COUNT_ACTUAL, &buf_count);
if (rc)
@@ -1433,7 +1471,9 @@
"Failed to move inst: %pK to start done state\n", inst);
goto fail_start;
}
- msm_dcvs_init(inst);
+
+ msm_clock_data_reset(inst);
+
if (msm_comm_get_stream_output_mode(inst) ==
HAL_VIDEO_DECODER_SECONDARY) {
rc = msm_comm_queue_output_buffers(inst);
@@ -1519,6 +1559,9 @@
dprintk(VIDC_ERR,
"Failed to move inst: %pK to state %d\n",
inst, MSM_VIDC_RELEASE_RESOURCES_DONE);
+
+ msm_clock_data_reset(inst);
+
return rc;
}
@@ -1839,33 +1882,52 @@
static int try_get_ctrl(struct msm_vidc_inst *inst, struct v4l2_ctrl *ctrl)
{
int rc = 0;
-
- /*
- * HACK: unlock the control prior to querying the hardware. Otherwise
- * lower level code that attempts to do g_ctrl() will end up deadlocking
- * us.
- */
+ struct hal_buffer_requirements *bufreq = NULL;
+ enum hal_buffer buffer_type;
switch (ctrl->id) {
case V4L2_CID_MPEG_VIDEO_H264_PROFILE:
case V4L2_CID_MPEG_VIDC_VIDEO_VP8_PROFILE_LEVEL:
case V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_PROFILE:
+ case V4L2_CID_MPEG_VIDC_VIDEO_HEVC_PROFILE:
ctrl->val = inst->profile;
- break;
+ break;
case V4L2_CID_MPEG_VIDEO_H264_LEVEL:
case V4L2_CID_MPEG_VIDC_VIDEO_MPEG2_LEVEL:
+ case V4L2_CID_MPEG_VIDC_VIDEO_HEVC_TIER_LEVEL:
ctrl->val = inst->level;
- break;
+ break;
case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE:
ctrl->val = inst->entropy_mode;
- break;
+ break;
case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE:
+ if (inst->in_reconfig)
+ msm_comm_try_get_bufreqs(inst);
+
+ buffer_type = msm_comm_get_hal_output_buffer(inst);
+ bufreq = get_buff_req_buffer(inst,
+ buffer_type);
+ if (!bufreq) {
+ dprintk(VIDC_ERR,
+ "Failed to find bufreqs for buffer type = %d\n",
+ buffer_type);
+ return -EINVAL;
+ }
+ ctrl->val = bufreq->buffer_count_min_host;
+ break;
case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:
- rc = msm_vidc_get_count(inst, ctrl);
+ bufreq = get_buff_req_buffer(inst, HAL_BUFFER_INPUT);
+ if (!bufreq) {
+ dprintk(VIDC_ERR,
+ "Failed to find bufreqs for buffer type = %d\n",
+ HAL_BUFFER_INPUT);
+ return -EINVAL;
+ }
+ ctrl->val = bufreq->buffer_count_min_host;
break;
default:
/*
@@ -1873,7 +1935,7 @@
* modify ctrl->value
*/
break;
-}
+ }
return rc;
}
@@ -1971,10 +2033,11 @@
inst->session_type = session_type;
inst->state = MSM_VIDC_CORE_UNINIT_DONE;
inst->core = core;
- inst->freq = 0;
- inst->core_id = VIDC_CORE_ID_DEFAULT;
+ inst->clk_data.min_freq = 0;
+ inst->clk_data.curr_freq = 0;
+ inst->clk_data.bitrate = 0;
+ inst->clk_data.core_id = VIDC_CORE_ID_DEFAULT;
inst->bit_depth = MSM_VIDC_BIT_DEPTH_8;
- inst->bitrate = 0;
inst->pic_struct = MSM_VIDC_PIC_STRUCT_PROGRESSIVE;
inst->colour_space = MSM_VIDC_BT601_6_525;
inst->profile = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
@@ -2031,12 +2094,15 @@
goto fail_init;
}
+ msm_dcvs_try_enable(inst);
if (msm_vidc_check_for_inst_overload(core)) {
dprintk(VIDC_ERR,
"Instance count reached Max limit, rejecting session");
goto fail_init;
}
+ msm_comm_scale_clocks_and_bus(inst);
+
inst->debugfs_root =
msm_vidc_debugfs_init_inst(inst, core->debugfs_root);
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
index d43ae5a..b80aa08 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
@@ -23,17 +23,12 @@
struct msm_vidc_inst *inst = NULL;
struct vidc_bus_vote_data *vote_data = NULL;
- if (!core) {
+ if (!core || !core->device) {
dprintk(VIDC_ERR, "%s Invalid args: %pK\n", __func__, core);
return -EINVAL;
}
hdev = core->device;
- if (!hdev) {
- dprintk(VIDC_ERR, "%s Invalid device handle: %pK\n",
- __func__, hdev);
- return -EINVAL;
- }
mutex_lock(&core->lock);
list_for_each_entry(inst, &core->instances, list)
@@ -65,12 +60,17 @@
vote_data[i].height = max(inst->prop.height[CAPTURE_PORT],
inst->prop.height[OUTPUT_PORT]);
- if (inst->operating_rate)
- vote_data[i].fps = (inst->operating_rate >> 16) ?
- inst->operating_rate >> 16 : 1;
+ if (inst->clk_data.operating_rate)
+ vote_data[i].fps =
+ (inst->clk_data.operating_rate >> 16) ?
+ inst->clk_data.operating_rate >> 16 : 1;
else
vote_data[i].fps = inst->prop.fps;
+ if (!msm_vidc_clock_scaling ||
+ inst->clk_data.buffer_counter < DCVS_FTB_WINDOW)
+ vote_data[i].power_mode = VIDC_POWER_TURBO;
+
/*
* TODO: support for OBP-DBP split mode hasn't been yet
* implemented, once it is, this part of code needs to be
@@ -126,18 +126,19 @@
int buffers_outside_fw = 0;
struct msm_vidc_core *core;
struct hal_buffer_requirements *output_buf_req;
- struct dcvs_stats *dcvs;
+ struct clock_data *dcvs;
if (!inst || !inst->core || !inst->core->device) {
dprintk(VIDC_ERR, "%s Invalid params\n", __func__);
return -EINVAL;
}
- if (!inst->dcvs_mode) {
+
+ if (!inst->clk_data.dcvs_mode) {
dprintk(VIDC_DBG, "DCVS is not enabled\n");
return 0;
}
- dcvs = &inst->dcvs;
+ dcvs = &inst->clk_data;
core = inst->core;
mutex_lock(&inst->lock);
@@ -210,7 +211,7 @@
}
mutex_unlock(&inst->freqs.lock);
- inst->dcvs.buffer_counter++;
+ inst->clk_data.buffer_counter++;
}
@@ -227,12 +228,13 @@
/* If current requirement is within DCVS limits, try DCVS. */
- if (freq < inst->dcvs.load_high) {
+ if (freq < inst->clk_data.load_high) {
dprintk(VIDC_DBG, "Calling DCVS now\n");
// TODO calling DCVS here may reduce the residency. Re-visit.
msm_dcvs_scale_clocks(inst);
- freq = inst->dcvs.load;
+ freq = inst->clk_data.load;
}
+ dprintk(VIDC_PROF, "%s Inst %pK : Freq = %lu\n", __func__, inst, freq);
return freq;
}
@@ -274,9 +276,10 @@
unsigned long freq = 0;
unsigned long vpp_cycles = 0, vsp_cycles = 0;
u32 vpp_cycles_per_mb;
- u32 mbs_per_frame;
+ u32 mbs_per_second;
- mbs_per_frame = msm_dcvs_get_mbs_per_frame(inst);
+ mbs_per_second = msm_comm_get_inst_load(inst,
+ LOAD_CALC_NO_QUIRKS);
/*
* Calculate vpp, vsp cycles separately for encoder and decoder.
@@ -286,17 +289,17 @@
if (inst->session_type == MSM_VIDC_ENCODER) {
vpp_cycles_per_mb = inst->flags & VIDC_LOW_POWER ?
- inst->entry->low_power_cycles :
- inst->entry->vpp_cycles;
+ inst->clk_data.entry->low_power_cycles :
+ inst->clk_data.entry->vpp_cycles;
- vsp_cycles = mbs_per_frame * inst->entry->vsp_cycles;
+ vsp_cycles = mbs_per_second * inst->clk_data.entry->vsp_cycles;
/* 10 / 7 is overhead factor */
- vsp_cycles += (inst->bitrate * 10) / 7;
+ vsp_cycles += (inst->clk_data.bitrate * 10) / 7;
} else if (inst->session_type == MSM_VIDC_DECODER) {
- vpp_cycles = mbs_per_frame * inst->entry->vpp_cycles;
+ vpp_cycles = mbs_per_second * inst->clk_data.entry->vpp_cycles;
- vsp_cycles = mbs_per_frame * inst->entry->vsp_cycles;
+ vsp_cycles = mbs_per_second * inst->clk_data.entry->vsp_cycles;
/* 10 / 7 is overhead factor */
vsp_cycles += (inst->prop.fps * filled_len * 8 * 10) / 7;
@@ -306,6 +309,8 @@
return freq;
}
+ dprintk(VIDC_PROF, "%s Inst %pK : Freq = %lu\n", __func__, inst, freq);
+
freq = max(vpp_cycles, vsp_cycles);
return freq;
@@ -321,7 +326,7 @@
hdev = core->device;
allowed_clks_tbl = core->resources.allowed_clks_tbl;
- if (!hdev || !allowed_clks_tbl) {
+ if (!allowed_clks_tbl) {
dprintk(VIDC_ERR,
"%s Invalid parameters\n", __func__);
return -EINVAL;
@@ -329,35 +334,104 @@
mutex_lock(&core->lock);
list_for_each_entry(temp, &core->instances, list) {
- freq += temp->freq;
+ freq += temp->clk_data.curr_freq;
}
for (i = core->resources.allowed_clks_tbl_size - 1; i >= 0; i--) {
rate = allowed_clks_tbl[i].clock_rate;
if (rate >= freq)
break;
}
+ core->min_freq = freq;
+ core->curr_freq = rate;
mutex_unlock(&core->lock);
- core->freq = rate;
- dprintk(VIDC_PROF, "Voting for freq = %lu", freq);
+ dprintk(VIDC_PROF, "Min freq = %lu Current Freq = %lu\n",
+ core->min_freq, core->curr_freq);
rc = call_hfi_op(hdev, scale_clocks,
- hdev->hfi_device_data, rate);
+ hdev->hfi_device_data, core->curr_freq);
return rc;
}
-static unsigned long msm_vidc_max_freq(struct msm_vidc_inst *inst)
+static unsigned long msm_vidc_max_freq(struct msm_vidc_core *core)
{
struct allowed_clock_rates_table *allowed_clks_tbl = NULL;
unsigned long freq = 0;
- allowed_clks_tbl = inst->core->resources.allowed_clks_tbl;
+ allowed_clks_tbl = core->resources.allowed_clks_tbl;
freq = allowed_clks_tbl[0].clock_rate;
dprintk(VIDC_PROF, "Max rate = %lu", freq);
return freq;
}
+int msm_vidc_update_operating_rate(struct msm_vidc_inst *inst)
+{
+ struct v4l2_ctrl *ctrl = NULL;
+ struct msm_vidc_inst *temp;
+ struct msm_vidc_core *core;
+ unsigned long max_freq, freq_left, ops_left, load, cycles, freq = 0;
+ unsigned long mbs_per_frame;
+
+ if (!inst || !inst->core) {
+ dprintk(VIDC_ERR, "%s Invalid args\n", __func__);
+ return -EINVAL;
+ }
+ core = inst->core;
+
+ mutex_lock(&core->lock);
+ max_freq = msm_vidc_max_freq(core);
+ list_for_each_entry(temp, &core->instances, list) {
+ if (temp == inst ||
+ temp->state < MSM_VIDC_START_DONE ||
+ temp->state >= MSM_VIDC_RELEASE_RESOURCES_DONE)
+ continue;
+
+ freq += temp->clk_data.min_freq;
+ }
+
+ freq_left = max_freq - freq;
+
+ list_for_each_entry(temp, &core->instances, list) {
+
+ mbs_per_frame = msm_dcvs_get_mbs_per_frame(inst);
+ cycles = temp->clk_data.entry->vpp_cycles;
+ if (inst->session_type == MSM_VIDC_ENCODER)
+ cycles = temp->flags & VIDC_LOW_POWER ?
+ inst->clk_data.entry->low_power_cycles :
+ cycles;
+
+ load = cycles * mbs_per_frame;
+
+ ops_left = load ? (freq_left / load) : 0;
+ /* Convert remaining operating rate to Q16 format */
+ ops_left = ops_left << 16;
+
+ ctrl = v4l2_ctrl_find(&temp->ctrl_handler,
+ V4L2_CID_MPEG_VIDC_VIDEO_OPERATING_RATE);
+ if (ctrl) {
+ dprintk(VIDC_DBG,
+ "%s: Before Range = %lld --> %lld\n",
+ ctrl->name, ctrl->minimum, ctrl->maximum);
+ dprintk(VIDC_DBG,
+ "%s: Before Def value = %lld Cur val = %d\n",
+ ctrl->name, ctrl->default_value, ctrl->val);
+ v4l2_ctrl_modify_range(ctrl, ctrl->minimum,
+ ctrl->val + ops_left, ctrl->step,
+ ctrl->minimum);
+ dprintk(VIDC_DBG,
+ "%s: Updated Range = %lld --> %lld\n",
+ ctrl->name, ctrl->minimum, ctrl->maximum);
+ dprintk(VIDC_DBG,
+ "%s: Updated Def value = %lld Cur val = %d\n",
+ ctrl->name, ctrl->default_value, ctrl->val);
+ }
+ }
+ mutex_unlock(&core->lock);
+
+ return 0;
+}
+
int msm_comm_scale_clocks(struct msm_vidc_inst *inst)
{
struct vb2_buf_entry *temp, *next;
@@ -365,9 +439,10 @@
u32 filled_len = 0;
ion_phys_addr_t device_addr = 0;
- if (inst->dcvs.buffer_counter < DCVS_FTB_WINDOW) {
- freq = msm_vidc_max_freq(inst);
- goto decision_done;
+ if (!inst || !inst->core) {
+ dprintk(VIDC_ERR, "%s Invalid args: Inst = %pK\n",
+ __func__, inst);
+ return -EINVAL;
}
mutex_lock(&inst->pendingq.lock);
@@ -381,7 +456,7 @@
mutex_unlock(&inst->pendingq.lock);
if (!filled_len || !device_addr) {
- freq = inst->freq;
+ dprintk(VIDC_PROF, "No Change in frequency\n");
goto decision_done;
}
@@ -391,8 +466,15 @@
freq = msm_vidc_adjust_freq(inst);
+ inst->clk_data.min_freq = freq;
+
+ if (inst->clk_data.buffer_counter < DCVS_FTB_WINDOW ||
+ !msm_vidc_clock_scaling)
+ inst->clk_data.curr_freq = msm_vidc_max_freq(inst->core);
+ else
+ inst->clk_data.curr_freq = freq;
+
decision_done:
- inst->freq = freq;
msm_vidc_set_clocks(inst->core);
return 0;
}
@@ -422,29 +504,29 @@
int msm_dcvs_try_enable(struct msm_vidc_inst *inst)
{
- bool force_disable = false;
-
if (!inst) {
dprintk(VIDC_ERR, "%s: Invalid args: %p\n", __func__, inst);
return -EINVAL;
}
- force_disable = inst->session_type == MSM_VIDC_ENCODER ?
- !msm_vidc_enc_dcvs_mode :
- !msm_vidc_dec_dcvs_mode;
-
- if (force_disable || inst->flags & VIDC_THUMBNAIL) {
- dprintk(VIDC_PROF, "Thumbnail sessions don't need DCVS : %pK\n",
- inst);
- inst->dcvs.extra_capture_buffer_count = 0;
- inst->dcvs.extra_output_buffer_count = 0;
+ if (!msm_vidc_clock_scaling ||
+ inst->flags & VIDC_THUMBNAIL ||
+ inst->clk_data.low_latency_mode) {
+ dprintk(VIDC_PROF,
+ "This session doesn't need DCVS : %pK\n",
+ inst);
+ inst->clk_data.extra_capture_buffer_count = 0;
+ inst->clk_data.extra_output_buffer_count = 0;
+ inst->clk_data.dcvs_mode = false;
return false;
}
- inst->dcvs_mode = true;
+ inst->clk_data.dcvs_mode = true;
// TODO : Update with proper number based on on-target tuning.
- inst->dcvs.extra_capture_buffer_count = DCVS_DEC_EXTRA_OUTPUT_BUFFERS;
- inst->dcvs.extra_output_buffer_count = DCVS_DEC_EXTRA_OUTPUT_BUFFERS;
+ inst->clk_data.extra_capture_buffer_count =
+ DCVS_DEC_EXTRA_OUTPUT_BUFFERS;
+ inst->clk_data.extra_output_buffer_count =
+ DCVS_DEC_EXTRA_OUTPUT_BUFFERS;
return true;
}
@@ -482,6 +564,12 @@
struct clock_profile_entry *entry = NULL;
int fourcc;
+ if (!inst || !inst->core) {
+ dprintk(VIDC_ERR, "%s Invalid args: Inst = %pK\n",
+ __func__, inst);
+ return -EINVAL;
+ }
+
clk_freq_tbl = &inst->core->resources.clock_freq_tbl;
fourcc = inst->session_type == MSM_VIDC_DECODER ?
inst->fmts[OUTPUT_PORT].fourcc :
@@ -498,7 +586,7 @@
inst->session_type);
if (matched) {
- inst->entry = entry;
+ inst->clk_data.entry = entry;
break;
}
}
@@ -512,7 +600,7 @@
return rc;
}
-static inline void msm_dcvs_print_dcvs_stats(struct dcvs_stats *dcvs)
+static inline void msm_dcvs_print_dcvs_stats(struct clock_data *dcvs)
{
dprintk(VIDC_DBG,
"DCVS: Load_Low %d, Load High %d\n",
@@ -524,31 +612,31 @@
dcvs->min_threshold, dcvs->max_threshold);
}
-void msm_dcvs_init(struct msm_vidc_inst *inst)
+void msm_clock_data_reset(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
- int i = 0;
+ int i = 0, rc = 0;
struct allowed_clock_rates_table *allowed_clks_tbl = NULL;
u64 total_freq = 0, rate = 0, load;
int cycles;
- struct dcvs_stats *dcvs;
+ struct clock_data *dcvs;
dprintk(VIDC_DBG, "Init DCVS Load\n");
if (!inst || !inst->core) {
- dprintk(VIDC_ERR, "%s Invalid args: %pK\n", __func__, inst);
+ dprintk(VIDC_ERR, "%s Invalid args: Inst = %pK\n",
+ __func__, inst);
return;
}
core = inst->core;
- dcvs = &inst->dcvs;
- inst->dcvs = (struct dcvs_stats){0};
+ dcvs = &inst->clk_data;
load = msm_comm_get_inst_load(inst, LOAD_CALC_NO_QUIRKS);
- cycles = inst->entry->vpp_cycles;
+ cycles = inst->clk_data.entry->vpp_cycles;
allowed_clks_tbl = core->resources.allowed_clks_tbl;
if (inst->session_type == MSM_VIDC_ENCODER) {
cycles = inst->flags & VIDC_LOW_POWER ?
- inst->entry->low_power_cycles :
+ inst->clk_data.entry->low_power_cycles :
cycles;
dcvs->buffer_type = HAL_BUFFER_INPUT;
@@ -573,7 +661,17 @@
dcvs->load = dcvs->load_high = rate;
dcvs->load_low = allowed_clks_tbl[i+1].clock_rate;
+ inst->clk_data.buffer_counter = 0;
+
msm_dcvs_print_dcvs_stats(dcvs);
+
+ msm_vidc_update_operating_rate(inst);
+
+ rc = msm_comm_scale_clocks_and_bus(inst);
+
+ if (rc)
+ dprintk(VIDC_ERR, "%s Failed to scale Clocks and Bus\n",
+ __func__);
}
int msm_vidc_get_extra_buff_count(struct msm_vidc_inst *inst,
@@ -585,23 +683,26 @@
}
return buffer_type == HAL_BUFFER_INPUT ?
- inst->dcvs.extra_output_buffer_count :
- inst->dcvs.extra_capture_buffer_count;
+ inst->clk_data.extra_output_buffer_count :
+ inst->clk_data.extra_capture_buffer_count;
}
int msm_vidc_decide_work_mode(struct msm_vidc_inst *inst)
{
int rc = 0;
- bool low_latency_mode;
struct hfi_device *hdev;
struct hal_video_work_mode pdata;
struct hal_enable latency;
- hdev = inst->core->device;
+ if (!inst || !inst->core || !inst->core->device) {
+ dprintk(VIDC_ERR,
+ "%s Invalid args: Inst = %pK\n",
+ __func__, inst);
+ return -EINVAL;
+ }
- low_latency_mode = msm_comm_g_ctrl_for_id(inst,
- V4L2_CID_MPEG_VIDC_VIDEO_LOWLATENCY_MODE);
- if (low_latency_mode) {
+ hdev = inst->core->device;
+ if (inst->clk_data.low_latency_mode) {
pdata.video_work_mode = VIDC_WORK_MODE_1;
goto decision_done;
}
@@ -636,7 +737,7 @@
decision_done:
- inst->work_mode = pdata.video_work_mode;
+ inst->clk_data.work_mode = pdata.video_work_mode;
rc = call_hfi_op(hdev, session_set_property,
(void *)inst->session, HAL_PARAM_VIDEO_WORK_MODE,
(void *)&pdata);
@@ -646,7 +747,8 @@
/* For WORK_MODE_1, set Low Latency mode by default to HW. */
- if (inst->work_mode == VIDC_WORK_MODE_1) {
+ if (inst->session_type == MSM_VIDC_ENCODER &&
+ inst->clk_data.work_mode == VIDC_WORK_MODE_1) {
latency.enable = 1;
rc = call_hfi_op(hdev, session_set_property,
(void *)inst->session, HAL_PARAM_VENC_LOW_LATENCY,
@@ -675,8 +777,8 @@
return 0;
}
mbs_per_frame = msm_dcvs_get_mbs_per_frame(inst);
- if (inst->core->resources.max_hq_mbs_per_frame > mbs_per_frame ||
- inst->core->resources.max_hq_fps > inst->prop.fps) {
+ if (mbs_per_frame >= inst->core->resources.max_hq_mbs_per_frame ||
+ inst->prop.fps >= inst->core->resources.max_hq_fps) {
enable = true;
}
@@ -692,9 +794,12 @@
__func__, inst);
goto fail_power_mode_set;
}
- inst->flags |= VIDC_LOW_POWER;
- dprintk(VIDC_PROF, "Power Save Mode set for inst: %pK\n", inst);
+ inst->flags = enable ?
+ inst->flags | VIDC_LOW_POWER :
+ inst->flags & ~VIDC_LOW_POWER;
+ dprintk(VIDC_PROF,
+ "Power Save Mode for inst: %pK Enable = %d\n", inst, enable);
fail_power_mode_set:
return rc;
}
@@ -704,15 +809,10 @@
{
struct msm_vidc_inst *inst = NULL;
- if (!core) {
- dprintk(VIDC_ERR, "Invalid args: %pK\n", core);
- return -EINVAL;
- }
-
dprintk(VIDC_PROF, "Core %d : Moving all inst to LP mode\n", core_id);
mutex_lock(&core->lock);
list_for_each_entry(inst, &core->instances, list) {
- if (inst->core_id == core_id &&
+ if (inst->clk_data.core_id == core_id &&
inst->session_type == MSM_VIDC_ENCODER)
msm_vidc_power_save_mode_enable(inst, true);
}
@@ -731,19 +831,19 @@
list_for_each_entry(inst, &core->instances, list) {
u32 cycles, lp_cycles;
- if (!inst->core_id && core_id)
+ if (!(inst->clk_data.core_id & core_id))
continue;
if (inst->session_type == MSM_VIDC_DECODER) {
- cycles = lp_cycles = inst->entry->vpp_cycles;
+ cycles = lp_cycles = inst->clk_data.entry->vpp_cycles;
} else if (inst->session_type == MSM_VIDC_ENCODER) {
lp_mode |= inst->flags & VIDC_LOW_POWER;
cycles = lp_mode ?
- inst->entry->low_power_cycles :
- inst->entry->vpp_cycles;
+ inst->clk_data.entry->low_power_cycles :
+ inst->clk_data.entry->vpp_cycles;
} else {
continue;
}
- if (inst->core_id == 3)
+ if (inst->clk_data.core_id == 3)
cycles = cycles / 2;
current_inst_mbs_per_sec = msm_comm_get_inst_load(inst,
@@ -768,10 +868,17 @@
min_load = 0, min_lp_load = 0;
u32 min_core_id, min_lp_core_id;
+ if (!inst || !inst->core || !inst->core->device) {
+ dprintk(VIDC_ERR,
+ "%s Invalid args: Inst = %pK\n",
+ __func__, inst);
+ return -EINVAL;
+ }
+
core = inst->core;
hdev = core->device;
- max_freq = msm_vidc_max_freq(inst);
- inst->core_id = 0;
+ max_freq = msm_vidc_max_freq(inst->core);
+ inst->clk_data.core_id = 0;
core0_load = get_core_load(core, VIDC_CORE_ID_1, false);
core1_load = get_core_load(core, VIDC_CORE_ID_2, false);
@@ -786,11 +893,11 @@
VIDC_CORE_ID_1 : VIDC_CORE_ID_2;
lp_cycles = inst->session_type == MSM_VIDC_ENCODER ?
- inst->entry->low_power_cycles :
- inst->entry->vpp_cycles;
+ inst->clk_data.entry->low_power_cycles :
+ inst->clk_data.entry->vpp_cycles;
current_inst_load = msm_comm_get_inst_load(inst, LOAD_CALC_NO_QUIRKS) *
- inst->entry->vpp_cycles;
+ inst->clk_data.entry->vpp_cycles;
current_inst_lp_load = msm_comm_get_inst_load(inst,
LOAD_CALC_NO_QUIRKS) * lp_cycles;
@@ -814,7 +921,7 @@
if (inst->session_type == MSM_VIDC_ENCODER && hier_mode) {
if (current_inst_load / 2 + core0_load <= max_freq &&
current_inst_load / 2 + core1_load <= max_freq) {
- inst->core_id = VIDC_CORE_ID_3;
+ inst->clk_data.core_id = VIDC_CORE_ID_3;
msm_vidc_power_save_mode_enable(inst, false);
goto decision_done;
}
@@ -825,32 +932,32 @@
core0_lp_load <= max_freq &&
current_inst_lp_load / 2 +
core1_lp_load <= max_freq) {
- inst->core_id = VIDC_CORE_ID_3;
+ inst->clk_data.core_id = VIDC_CORE_ID_3;
msm_vidc_power_save_mode_enable(inst, true);
goto decision_done;
}
}
if (current_inst_load + min_load < max_freq) {
- inst->core_id = min_core_id;
+ inst->clk_data.core_id = min_core_id;
dprintk(VIDC_DBG,
"Selected normally : Core ID = %d\n",
- inst->core_id);
+ inst->clk_data.core_id);
msm_vidc_power_save_mode_enable(inst, false);
} else if (current_inst_lp_load + min_load < max_freq) {
/* Move current instance to LP and return */
- inst->core_id = min_core_id;
+ inst->clk_data.core_id = min_core_id;
dprintk(VIDC_DBG,
"Selected by moving current to LP : Core ID = %d\n",
- inst->core_id);
+ inst->clk_data.core_id);
msm_vidc_power_save_mode_enable(inst, true);
} else if (current_inst_lp_load + min_lp_load < max_freq) {
/* Move all instances to LP mode and return */
- inst->core_id = min_lp_core_id;
+ inst->clk_data.core_id = min_lp_core_id;
dprintk(VIDC_DBG,
"Moved all inst's to LP: Core ID = %d\n",
- inst->core_id);
+ inst->clk_data.core_id);
msm_vidc_move_core_to_power_save_mode(core, min_lp_core_id);
} else {
rc = -EINVAL;
@@ -860,7 +967,7 @@
}
decision_done:
- core_info.video_core_enable_mask = inst->core_id;
+ core_info.video_core_enable_mask = inst->clk_data.core_id;
rc = call_hfi_op(hdev, session_set_property,
(void *)inst->session,
@@ -874,3 +981,4 @@
return rc;
}
+
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_clocks.h b/drivers/media/platform/msm/vidc/msm_vidc_clocks.h
index d01f074..fe4822b 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_clocks.h
+++ b/drivers/media/platform/msm/vidc/msm_vidc_clocks.h
@@ -31,7 +31,8 @@
/* Considering one safeguard buffer */
#define DCVS_BUFFER_SAFEGUARD (DCVS_DEC_EXTRA_OUTPUT_BUFFERS - 1)
-void msm_dcvs_init(struct msm_vidc_inst *inst);
+void msm_clock_data_reset(struct msm_vidc_inst *inst);
+int msm_vidc_update_operating_rate(struct msm_vidc_inst *inst);
int msm_vidc_get_extra_buff_count(struct msm_vidc_inst *inst,
enum hal_buffer buffer_type);
int msm_dcvs_try_enable(struct msm_vidc_inst *inst);
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.c b/drivers/media/platform/msm/vidc/msm_vidc_common.c
index 853edf5..0efe93b 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_common.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_common.c
@@ -584,9 +584,9 @@
capture_port_mbs = NUM_MBS_PER_FRAME(inst->prop.width[CAPTURE_PORT],
inst->prop.height[CAPTURE_PORT]);
- if (inst->operating_rate) {
- fps = (inst->operating_rate >> 16) ?
- inst->operating_rate >> 16 : 1;
+ if (inst->clk_data.operating_rate) {
+ fps = (inst->clk_data.operating_rate >> 16) ?
+ inst->clk_data.operating_rate >> 16 : 1;
/*
* Check if operating rate is less than fps.
* If Yes, then use fps to scale clocks
@@ -2510,7 +2510,7 @@
}
tl = msm_comm_vidc_thermal_level(vidc_driver->thermal_level);
- freq = core->freq;
+ freq = core->curr_freq;
is_turbo = is_core_turbo(core, freq);
dprintk(VIDC_DBG,
@@ -4094,9 +4094,8 @@
dprintk(VIDC_DBG, "%15s %8s %8s %8s %8s\n",
"buffer type", "count", "mincount_host", "mincount_fw", "size");
for (i = 0; i < HAL_BUFFER_MAX; i++) {
- struct hal_buffer_requirements req = hprop.buf_req.buffer[i];
+ struct hal_buffer_requirements req = inst->buff_req.buffer[i];
- inst->buff_req.buffer[i] = req;
if (req.buffer_type != HAL_BUFFER_NONE) {
dprintk(VIDC_DBG, "%15s %8d %8d %8d %8d\n",
get_buffer_name(req.buffer_type),
@@ -4738,9 +4737,9 @@
return 0;
}
- // Finish FLUSH As Soon As Possible.
- inst->dcvs.buffer_counter = 0;
- msm_comm_scale_clocks_and_bus(inst);
+ /* Finish FLUSH As Soon As Possible. */
+
+ msm_clock_data_reset(inst);
msm_comm_flush_dynamic_buffers(inst);
@@ -5474,7 +5473,7 @@
}
core = inst->core;
- dprintk(VIDC_ERR, "Venus core frequency = %lu", core->freq);
+ dprintk(VIDC_ERR, "Venus core frequency = %lu", core->curr_freq);
mutex_lock(&core->lock);
dprintk(VIDC_ERR, "Printing instance info that caused Error\n");
msm_comm_print_inst_info(inst);
@@ -5520,3 +5519,28 @@
mutex_unlock(&inst->lock);
return rc;
}
+
+u32 get_frame_size_nv12(int plane, u32 height, u32 width)
+{
+ return VENUS_BUFFER_SIZE(COLOR_FMT_NV12, width, height);
+}
+
+u32 get_frame_size_nv12_ubwc(int plane, u32 height, u32 width)
+{
+ return VENUS_BUFFER_SIZE(COLOR_FMT_NV12_UBWC, width, height);
+}
+
+u32 get_frame_size_rgba(int plane, u32 height, u32 width)
+{
+ return VENUS_BUFFER_SIZE(COLOR_FMT_RGBA8888, width, height);
+}
+
+u32 get_frame_size_nv21(int plane, u32 height, u32 width)
+{
+ return VENUS_BUFFER_SIZE(COLOR_FMT_NV21, width, height);
+}
+
+u32 get_frame_size_tp10_ubwc(int plane, u32 height, u32 width)
+{
+ return VENUS_BUFFER_SIZE(COLOR_FMT_NV12_BPP10_UBWC, width, height);
+}
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.h b/drivers/media/platform/msm/vidc/msm_vidc_common.h
index 9c7eec5..098063d 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_common.h
+++ b/drivers/media/platform/msm/vidc/msm_vidc_common.h
@@ -98,4 +98,9 @@
int msm_comm_v4l2_to_hal(int id, int value);
int msm_comm_hal_to_v4l2(int id, int value);
int msm_comm_session_continue(void *instance);
+u32 get_frame_size_nv12(int plane, u32 height, u32 width);
+u32 get_frame_size_nv12_ubwc(int plane, u32 height, u32 width);
+u32 get_frame_size_rgba(int plane, u32 height, u32 width);
+u32 get_frame_size_nv21(int plane, u32 height, u32 width);
+u32 get_frame_size_tp10_ubwc(int plane, u32 height, u32 width);
#endif
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_debug.c b/drivers/media/platform/msm/vidc/msm_vidc_debug.c
index 15ee8a8..f62c132 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_debug.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_debug.c
@@ -26,12 +26,10 @@
int msm_vidc_fw_low_power_mode = 1;
int msm_vidc_hw_rsp_timeout = 2000;
bool msm_vidc_fw_coverage = !true;
-bool msm_vidc_dec_dcvs_mode = true;
-bool msm_vidc_enc_dcvs_mode = true;
bool msm_vidc_sys_idle_indicator = !true;
int msm_vidc_firmware_unload_delay = 15000;
bool msm_vidc_thermal_mitigation_disabled = !true;
-bool msm_vidc_bitrate_clock_scaling = true;
+bool msm_vidc_clock_scaling = true;
bool msm_vidc_debug_timeout = !true;
#define MAX_DBG_BUF_SIZE 4096
@@ -174,8 +172,6 @@
__debugfs_create(x32, "fw_level", &msm_vidc_fw_debug) &&
__debugfs_create(u32, "fw_debug_mode", &msm_vidc_fw_debug_mode) &&
__debugfs_create(bool, "fw_coverage", &msm_vidc_fw_coverage) &&
- __debugfs_create(bool, "dcvs_dec_mode", &msm_vidc_dec_dcvs_mode) &&
- __debugfs_create(bool, "dcvs_enc_mode", &msm_vidc_enc_dcvs_mode) &&
__debugfs_create(u32, "fw_low_power_mode",
&msm_vidc_fw_low_power_mode) &&
__debugfs_create(u32, "debug_output", &msm_vidc_debug_out) &&
@@ -186,8 +182,8 @@
&msm_vidc_firmware_unload_delay) &&
__debugfs_create(bool, "disable_thermal_mitigation",
&msm_vidc_thermal_mitigation_disabled) &&
- __debugfs_create(bool, "bitrate_clock_scaling",
- &msm_vidc_bitrate_clock_scaling) &&
+ __debugfs_create(bool, "clock_scaling",
+ &msm_vidc_clock_scaling) &&
__debugfs_create(bool, "debug_timeout",
&msm_vidc_debug_timeout);
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_debug.h b/drivers/media/platform/msm/vidc/msm_vidc_debug.h
index cf5ce22..f5c8e5a 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_debug.h
+++ b/drivers/media/platform/msm/vidc/msm_vidc_debug.h
@@ -59,12 +59,10 @@
extern int msm_vidc_fw_low_power_mode;
extern int msm_vidc_hw_rsp_timeout;
extern bool msm_vidc_fw_coverage;
-extern bool msm_vidc_dec_dcvs_mode;
-extern bool msm_vidc_enc_dcvs_mode;
extern bool msm_vidc_sys_idle_indicator;
extern int msm_vidc_firmware_unload_delay;
extern bool msm_vidc_thermal_mitigation_disabled;
-extern bool msm_vidc_bitrate_clock_scaling;
+extern bool msm_vidc_clock_scaling;
extern bool msm_vidc_debug_timeout;
#define VIDC_MSG_PRIO2STRING(__level) ({ \
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_internal.h b/drivers/media/platform/msm/vidc/msm_vidc_internal.h
index 53bc068..37bccbd 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_internal.h
+++ b/drivers/media/platform/msm/vidc/msm_vidc_internal.h
@@ -52,7 +52,7 @@
/* Maintains the number of FTB's between each FBD over a window */
-#define DCVS_FTB_WINDOW 32
+#define DCVS_FTB_WINDOW 16
#define V4L2_EVENT_VIDC_BASE 10
@@ -205,7 +205,7 @@
int ebd;
};
-struct dcvs_stats {
+struct clock_data {
int buffer_counter;
int load;
int load_low;
@@ -215,6 +215,15 @@
unsigned int extra_capture_buffer_count;
unsigned int extra_output_buffer_count;
enum hal_buffer buffer_type;
+ bool dcvs_mode;
+ unsigned long bitrate;
+ unsigned long min_freq;
+ unsigned long curr_freq;
+ u32 operating_rate;
+ struct clock_profile_entry *entry;
+ u32 core_id;
+ enum hal_work_mode work_mode;
+ bool low_latency_mode;
};
struct profile_data {
@@ -259,7 +268,8 @@
struct msm_vidc_capability *capabilities;
struct delayed_work fw_unload_work;
bool smmu_fault_handled;
- unsigned long freq;
+ unsigned long min_freq;
+ unsigned long curr_freq;
};
struct msm_vidc_inst {
@@ -293,28 +303,21 @@
void *priv;
struct msm_vidc_debug debug;
struct buf_count count;
- struct dcvs_stats dcvs;
+ struct clock_data clk_data;
enum msm_vidc_modes flags;
struct msm_vidc_capability capability;
u32 buffer_size_limit;
enum buffer_mode_type buffer_mode_set[MAX_PORT_NUM];
struct v4l2_ctrl **ctrls;
- bool dcvs_mode;
enum msm_vidc_pixel_depth bit_depth;
struct kref kref;
- unsigned long bitrate;
- unsigned long freq;
u32 buffers_held_in_driver;
atomic_t in_flush;
u32 pic_struct;
u32 colour_space;
- u32 operating_rate;
u32 profile;
u32 level;
u32 entropy_mode;
- struct clock_profile_entry *entry;
- u32 core_id;
- enum hal_work_mode work_mode;
};
extern struct msm_vidc_drv *vidc_driver;
diff --git a/drivers/media/platform/msm/vidc/vidc_hfi_api.h b/drivers/media/platform/msm/vidc/vidc_hfi_api.h
index 8752378..474c2fb6 100644
--- a/drivers/media/platform/msm/vidc/vidc_hfi_api.h
+++ b/drivers/media/platform/msm/vidc/vidc_hfi_api.h
@@ -187,7 +187,7 @@
HAL_PARAM_VDEC_SYNC_FRAME_DECODE,
HAL_PARAM_VENC_H264_ENTROPY_CABAC_MODEL,
HAL_CONFIG_VENC_MAX_BITRATE,
- HAL_PARAM_VENC_H264_VUI_TIMING_INFO,
+ HAL_PARAM_VENC_VUI_TIMING_INFO,
HAL_PARAM_VENC_GENERATE_AUDNAL,
HAL_PARAM_BUFFER_ALLOC_MODE,
HAL_PARAM_VDEC_FRAME_ASSEMBLY,
@@ -813,7 +813,7 @@
};
-struct hal_h264_vui_timing_info {
+struct hal_vui_timing_info {
u32 enable;
u32 fixed_frame_rate;
u32 time_scale;
@@ -1036,7 +1036,7 @@
struct hal_codec_supported codec_supported;
struct hal_multi_view_select multi_view_select;
struct hal_timestamp_scale timestamp_scale;
- struct hal_h264_vui_timing_info h264_vui_timing_info;
+ struct hal_vui_timing_info vui_timing_info;
struct hal_preserve_text_quality preserve_text_quality;
struct hal_buffer_info buffer_info;
struct hal_buffer_alloc_mode buffer_alloc_mode;
diff --git a/drivers/media/platform/msm/vidc/vidc_hfi_helper.h b/drivers/media/platform/msm/vidc/vidc_hfi_helper.h
index 77164be..81b4d91 100644
--- a/drivers/media/platform/msm/vidc/vidc_hfi_helper.h
+++ b/drivers/media/platform/msm/vidc/vidc_hfi_helper.h
@@ -283,7 +283,7 @@
(HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01C)
#define HFI_PROPERTY_PARAM_VENC_VIDEO_SIGNAL_INFO \
(HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01D)
-#define HFI_PROPERTY_PARAM_VENC_H264_VUI_TIMING_INFO \
+#define HFI_PROPERTY_PARAM_VENC_VUI_TIMING_INFO \
(HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x01E)
#define HFI_PROPERTY_PARAM_VENC_LOW_LATENCY_MODE \
(HFI_PROPERTY_PARAM_VENC_COMMON_START + 0x022)
@@ -589,7 +589,7 @@
u32 matrix_coeffs;
};
-struct hfi_h264_vui_timing_info {
+struct hfi_vui_timing_info {
u32 enable;
u32 fixed_frame_rate;
u32 time_scale;
diff --git a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
index bacecbd..f37d64c 100644
--- a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
+++ b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
@@ -45,27 +45,36 @@
compat_caddr_t bitmap;
};
-static int get_v4l2_window32(struct v4l2_window *kp, struct v4l2_window32 __user *up)
+static int get_v4l2_window32(struct v4l2_window __user *kp,
+ struct v4l2_window32 __user *up)
{
+ u32 clipcount = 0;
+
if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_window32)) ||
- copy_from_user(&kp->w, &up->w, sizeof(up->w)) ||
- get_user(kp->field, &up->field) ||
- get_user(kp->chromakey, &up->chromakey) ||
- get_user(kp->clipcount, &up->clipcount))
+ !access_ok(VERIFY_WRITE, kp, sizeof(struct v4l2_window)) ||
+ copy_in_user(&kp->w, &up->w, sizeof(up->w)) ||
+ copy_in_user(&kp->field, &up->field, sizeof(up->field)) ||
+ copy_in_user(&kp->chromakey, &up->chromakey,
+ sizeof(up->chromakey)) ||
+ copy_in_user(&kp->clipcount, &up->clipcount,
+ sizeof(up->clipcount)))
return -EFAULT;
- if (kp->clipcount > 2048)
+ if (get_user(clipcount, &kp->clipcount))
+ return -EFAULT;
+ if (clipcount > 2048)
return -EINVAL;
- if (kp->clipcount) {
+ if (clipcount) {
struct v4l2_clip32 __user *uclips;
struct v4l2_clip __user *kclips;
- int n = kp->clipcount;
+ int n = clipcount;
compat_caddr_t p;
if (get_user(p, &up->clips))
return -EFAULT;
uclips = compat_ptr(p);
kclips = compat_alloc_user_space(n * sizeof(struct v4l2_clip));
- kp->clips = kclips;
+ if (put_user(kclips, &kp->clips))
+ return -EFAULT;
while (--n >= 0) {
if (copy_in_user(&kclips->c, &uclips->c, sizeof(uclips->c)))
return -EFAULT;
@@ -74,89 +83,106 @@
uclips += 1;
kclips += 1;
}
- } else
- kp->clips = NULL;
- return 0;
-}
-
-static int put_v4l2_window32(struct v4l2_window *kp, struct v4l2_window32 __user *up)
-{
- if (copy_to_user(&up->w, &kp->w, sizeof(kp->w)) ||
- put_user(kp->field, &up->field) ||
- put_user(kp->chromakey, &up->chromakey) ||
- put_user(kp->clipcount, &up->clipcount))
+ } else {
+ if (put_user(NULL, &kp->clips))
return -EFAULT;
+ }
return 0;
}
-static inline int get_v4l2_pix_format(struct v4l2_pix_format *kp, struct v4l2_pix_format __user *up)
+static int put_v4l2_window32(struct v4l2_window __user *kp,
+ struct v4l2_window32 __user *up)
{
- if (copy_from_user(kp, up, sizeof(struct v4l2_pix_format)))
+ if (copy_in_user(&up->w, &kp->w, sizeof(up->w)) ||
+ copy_in_user(&up->field, &kp->field, sizeof(up->field)) ||
+ copy_in_user(&up->chromakey, &kp->chromakey,
+ sizeof(up->chromakey)) ||
+ copy_in_user(&up->clipcount, &kp->clipcount,
+ sizeof(up->clipcount)))
return -EFAULT;
return 0;
}
-static inline int get_v4l2_pix_format_mplane(struct v4l2_pix_format_mplane *kp,
+static inline int get_v4l2_pix_format(struct v4l2_pix_format __user *kp,
+ struct v4l2_pix_format __user *up)
+{
+ if (copy_in_user(kp, up, sizeof(struct v4l2_pix_format)))
+ return -EFAULT;
+ return 0;
+}
+
+static inline int get_v4l2_pix_format_mplane(
+ struct v4l2_pix_format_mplane __user *kp,
struct v4l2_pix_format_mplane __user *up)
{
- if (copy_from_user(kp, up, sizeof(struct v4l2_pix_format_mplane)))
+ if (copy_in_user(kp, up, sizeof(struct v4l2_pix_format_mplane)))
return -EFAULT;
return 0;
}
-static inline int put_v4l2_pix_format(struct v4l2_pix_format *kp, struct v4l2_pix_format __user *up)
+static inline int put_v4l2_pix_format(struct v4l2_pix_format __user *kp,
+ struct v4l2_pix_format __user *up)
{
- if (copy_to_user(up, kp, sizeof(struct v4l2_pix_format)))
+ if (copy_in_user(up, kp, sizeof(struct v4l2_pix_format)))
return -EFAULT;
return 0;
}
-static inline int put_v4l2_pix_format_mplane(struct v4l2_pix_format_mplane *kp,
+static inline int put_v4l2_pix_format_mplane(
+ struct v4l2_pix_format_mplane __user *kp,
struct v4l2_pix_format_mplane __user *up)
{
- if (copy_to_user(up, kp, sizeof(struct v4l2_pix_format_mplane)))
+ if (copy_in_user(up, kp, sizeof(struct v4l2_pix_format_mplane)))
return -EFAULT;
return 0;
}
-static inline int get_v4l2_vbi_format(struct v4l2_vbi_format *kp, struct v4l2_vbi_format __user *up)
+static inline int get_v4l2_vbi_format(struct v4l2_vbi_format __user *kp,
+ struct v4l2_vbi_format __user *up)
{
- if (copy_from_user(kp, up, sizeof(struct v4l2_vbi_format)))
+ if (copy_in_user(kp, up, sizeof(struct v4l2_vbi_format)))
return -EFAULT;
return 0;
}
-static inline int put_v4l2_vbi_format(struct v4l2_vbi_format *kp, struct v4l2_vbi_format __user *up)
+static inline int put_v4l2_vbi_format(struct v4l2_vbi_format __user *kp,
+ struct v4l2_vbi_format __user *up)
{
- if (copy_to_user(up, kp, sizeof(struct v4l2_vbi_format)))
+ if (copy_in_user(up, kp, sizeof(struct v4l2_vbi_format)))
return -EFAULT;
return 0;
}
-static inline int get_v4l2_sliced_vbi_format(struct v4l2_sliced_vbi_format *kp, struct v4l2_sliced_vbi_format __user *up)
+static inline int get_v4l2_sliced_vbi_format(
+ struct v4l2_sliced_vbi_format __user *kp,
+ struct v4l2_sliced_vbi_format __user *up)
{
- if (copy_from_user(kp, up, sizeof(struct v4l2_sliced_vbi_format)))
+ if (copy_in_user(kp, up, sizeof(struct v4l2_sliced_vbi_format)))
return -EFAULT;
return 0;
}
-static inline int put_v4l2_sliced_vbi_format(struct v4l2_sliced_vbi_format *kp, struct v4l2_sliced_vbi_format __user *up)
+static inline int put_v4l2_sliced_vbi_format(
+ struct v4l2_sliced_vbi_format __user *kp,
+ struct v4l2_sliced_vbi_format __user *up)
{
- if (copy_to_user(up, kp, sizeof(struct v4l2_sliced_vbi_format)))
+ if (copy_in_user(up, kp, sizeof(struct v4l2_sliced_vbi_format)))
return -EFAULT;
return 0;
}
-static inline int get_v4l2_sdr_format(struct v4l2_sdr_format *kp, struct v4l2_sdr_format __user *up)
+static inline int get_v4l2_sdr_format(struct v4l2_sdr_format __user *kp,
+ struct v4l2_sdr_format __user *up)
{
- if (copy_from_user(kp, up, sizeof(struct v4l2_sdr_format)))
+ if (copy_in_user(kp, up, sizeof(struct v4l2_sdr_format)))
return -EFAULT;
return 0;
}
-static inline int put_v4l2_sdr_format(struct v4l2_sdr_format *kp, struct v4l2_sdr_format __user *up)
+static inline int put_v4l2_sdr_format(struct v4l2_sdr_format __user *kp,
+ struct v4l2_sdr_format __user *up)
{
- if (copy_to_user(up, kp, sizeof(struct v4l2_sdr_format)))
+ if (copy_in_user(up, kp, sizeof(struct v4l2_sdr_format)))
return -EFAULT;
return 0;
}
@@ -191,12 +217,17 @@
__u32 reserved[8];
};
-static int __get_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __user *up)
+static int __get_v4l2_format32(struct v4l2_format __user *kp,
+ struct v4l2_format32 __user *up)
{
- if (get_user(kp->type, &up->type))
+ u32 type;
+
+ if (copy_in_user(&kp->type, &up->type, sizeof(up->type)))
return -EFAULT;
- switch (kp->type) {
+ if (get_user(type, &kp->type))
+ return -EFAULT;
+ switch (type) {
case V4L2_BUF_TYPE_VIDEO_CAPTURE:
case V4L2_BUF_TYPE_VIDEO_OUTPUT:
return get_v4l2_pix_format(&kp->fmt.pix, &up->fmt.pix);
@@ -223,27 +254,39 @@
}
}
-static int get_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __user *up)
+static int get_v4l2_format32(struct v4l2_format __user *kp,
+ struct v4l2_format32 __user *up)
{
- if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_format32)))
+ if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_format32)) ||
+ !access_ok(VERIFY_WRITE, kp, sizeof(struct v4l2_format)))
return -EFAULT;
return __get_v4l2_format32(kp, up);
}
-static int get_v4l2_create32(struct v4l2_create_buffers *kp, struct v4l2_create_buffers32 __user *up)
+static int get_v4l2_create32(struct v4l2_create_buffers __user *kp,
+ struct v4l2_create_buffers32 __user *up)
{
if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_create_buffers32)) ||
- copy_from_user(kp, up, offsetof(struct v4l2_create_buffers32, format)))
+ !access_ok(VERIFY_WRITE, kp,
+ sizeof(struct v4l2_create_buffers)) ||
+ copy_in_user(kp, up,
+ offsetof(struct v4l2_create_buffers32, format)))
return -EFAULT;
return __get_v4l2_format32(&kp->format, &up->format);
}
-static int __put_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __user *up)
+static int __put_v4l2_format32(struct v4l2_format __user *kp,
+ struct v4l2_format32 __user *up)
{
- if (put_user(kp->type, &up->type))
+ u32 type;
+
+ if (copy_in_user(&up->type, &kp->type, sizeof(up->type)))
return -EFAULT;
- switch (kp->type) {
+ if (get_user(type, &kp->type))
+ return -EFAULT;
+
+ switch (type) {
case V4L2_BUF_TYPE_VIDEO_CAPTURE:
case V4L2_BUF_TYPE_VIDEO_OUTPUT:
return put_v4l2_pix_format(&kp->fmt.pix, &up->fmt.pix);
@@ -270,18 +313,24 @@
}
}
-static int put_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __user *up)
+static int put_v4l2_format32(struct v4l2_format __user *kp,
+ struct v4l2_format32 __user *up)
{
- if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_format32)))
+ if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_format32)) ||
+ !access_ok(VERIFY_READ, kp, sizeof(struct v4l2_format)))
return -EFAULT;
return __put_v4l2_format32(kp, up);
}
-static int put_v4l2_create32(struct v4l2_create_buffers *kp, struct v4l2_create_buffers32 __user *up)
+static int put_v4l2_create32(struct v4l2_create_buffers __user *kp,
+ struct v4l2_create_buffers32 __user *up)
{
if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_create_buffers32)) ||
- copy_to_user(up, kp, offsetof(struct v4l2_create_buffers32, format)) ||
- copy_to_user(up->reserved, kp->reserved, sizeof(kp->reserved)))
+ !access_ok(VERIFY_READ, kp,
+ sizeof(struct v4l2_create_buffers)) ||
+ copy_in_user(up, kp,
+ offsetof(struct v4l2_create_buffers32, format)) ||
+ copy_in_user(up->reserved, kp->reserved, sizeof(up->reserved)))
return -EFAULT;
return __put_v4l2_format32(&kp->format, &up->format);
}
@@ -295,24 +344,30 @@
__u32 reserved[4];
};
-static int get_v4l2_standard32(struct v4l2_standard *kp, struct v4l2_standard32 __user *up)
+static int get_v4l2_standard32(struct v4l2_standard __user *kp,
+ struct v4l2_standard32 __user *up)
{
/* other fields are not set by the user, nor used by the driver */
if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_standard32)) ||
- get_user(kp->index, &up->index))
+ !access_ok(VERIFY_WRITE, kp, sizeof(struct v4l2_standard)) ||
+ copy_in_user(&kp->index, &up->index, sizeof(up->index)))
return -EFAULT;
return 0;
}
-static int put_v4l2_standard32(struct v4l2_standard *kp, struct v4l2_standard32 __user *up)
+static int put_v4l2_standard32(struct v4l2_standard __user *kp,
+ struct v4l2_standard32 __user *up)
{
if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_standard32)) ||
- put_user(kp->index, &up->index) ||
- put_user(kp->id, &up->id) ||
- copy_to_user(up->name, kp->name, 24) ||
- copy_to_user(&up->frameperiod, &kp->frameperiod, sizeof(kp->frameperiod)) ||
- put_user(kp->framelines, &up->framelines) ||
- copy_to_user(up->reserved, kp->reserved, 4 * sizeof(__u32)))
+ !access_ok(VERIFY_READ, kp, sizeof(struct v4l2_standard)) ||
+ copy_in_user(&up->index, &kp->index, sizeof(up->index)) ||
+ copy_in_user(&up->id, &kp->id, sizeof(up->id)) ||
+ copy_in_user(up->name, kp->name, 24) ||
+ copy_in_user(&up->frameperiod, &kp->frameperiod,
+ sizeof(up->frameperiod)) ||
+ copy_in_user(&up->framelines, &kp->framelines,
+ sizeof(up->framelines)) ||
+ copy_in_user(up->reserved, kp->reserved, 4 * sizeof(__u32)))
return -EFAULT;
return 0;
}
@@ -360,6 +415,10 @@
if (copy_in_user(up, up32, 2 * sizeof(__u32)) ||
copy_in_user(&up->data_offset, &up32->data_offset,
+ sizeof(__u32)) ||
+ copy_in_user(up->reserved, up32->reserved,
+ sizeof(up->reserved)) ||
+ copy_in_user(&up->length, &up32->length,
sizeof(__u32)))
return -EFAULT;
@@ -386,7 +445,9 @@
{
if (copy_in_user(up32, up, 2 * sizeof(__u32)) ||
copy_in_user(&up32->data_offset, &up->data_offset,
- sizeof(__u32)))
+ sizeof(__u32)) ||
+ copy_in_user(up32->reserved, up->reserved,
+ sizeof(up32->reserved)))
return -EFAULT;
/* For MMAP, driver might've set up the offset, so copy it back.
@@ -404,34 +465,48 @@
return 0;
}
-static int get_v4l2_buffer32(struct v4l2_buffer *kp, struct v4l2_buffer32 __user *up)
+static int get_v4l2_buffer32(struct v4l2_buffer __user *kp,
+ struct v4l2_buffer32 __user *up)
{
struct v4l2_plane32 __user *uplane32;
struct v4l2_plane __user *uplane;
compat_caddr_t p;
int num_planes;
+ struct timeval time;
+ u32 plane_count, memory, type;
int ret;
if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_buffer32)) ||
- get_user(kp->index, &up->index) ||
- get_user(kp->type, &up->type) ||
- get_user(kp->flags, &up->flags) ||
- get_user(kp->memory, &up->memory) ||
- get_user(kp->length, &up->length))
+ !access_ok(VERIFY_WRITE, kp, sizeof(struct v4l2_buffer)) ||
+ copy_in_user(&kp->index, &up->index, sizeof(up->index)) ||
+ copy_in_user(&kp->type, &up->type, sizeof(up->type)) ||
+ copy_in_user(&kp->flags, &up->flags, sizeof(up->flags)) ||
+ copy_in_user(&kp->memory, &up->memory, sizeof(up->memory)) ||
+ copy_in_user(&kp->length, &up->length, sizeof(up->length)))
return -EFAULT;
- if (V4L2_TYPE_IS_OUTPUT(kp->type))
- if (get_user(kp->bytesused, &up->bytesused) ||
- get_user(kp->field, &up->field) ||
- get_user(kp->timestamp.tv_sec, &up->timestamp.tv_sec) ||
- get_user(kp->timestamp.tv_usec,
- &up->timestamp.tv_usec))
+ if (get_user(type, &kp->type))
+ return -EFAULT;
+ if (V4L2_TYPE_IS_OUTPUT(type))
+ if (copy_in_user(&kp->bytesused, &up->bytesused,
+ sizeof(up->bytesused)) ||
+ copy_in_user(&kp->field, &up->field,
+ sizeof(up->field)) ||
+ get_user(time.tv_sec, &up->timestamp.tv_sec) ||
+ get_user(time.tv_usec, &up->timestamp.tv_usec) ||
+ put_user(time.tv_sec, &kp->timestamp.tv_sec) ||
+ put_user(time.tv_usec, &kp->timestamp.tv_usec))
return -EFAULT;
- if (V4L2_TYPE_IS_MULTIPLANAR(kp->type)) {
- num_planes = kp->length;
+ if (get_user(memory, &kp->memory))
+ return -EFAULT;
+ if (V4L2_TYPE_IS_MULTIPLANAR(type)) {
+ if (get_user(plane_count, &kp->length))
+ return -EFAULT;
+ num_planes = plane_count;
if (num_planes == 0) {
- kp->m.planes = NULL;
+ if (put_user(NULL, &kp->m.planes))
+ return -EFAULT;
/* num_planes == 0 is legal, e.g. when userspace doesn't
* need planes array on DQBUF*/
return 0;
@@ -449,37 +524,43 @@
* by passing a very big num_planes value */
uplane = compat_alloc_user_space(num_planes *
sizeof(struct v4l2_plane));
- kp->m.planes = (__force struct v4l2_plane *)uplane;
+ if (put_user(uplane, &kp->m.planes))
+ return -EFAULT;
while (--num_planes >= 0) {
- ret = get_v4l2_plane32(uplane, uplane32, kp->memory);
+ ret = get_v4l2_plane32(uplane, uplane32, memory);
if (ret)
return ret;
++uplane;
++uplane32;
}
} else {
- switch (kp->memory) {
+ switch (memory) {
case V4L2_MEMORY_MMAP:
- if (get_user(kp->m.offset, &up->m.offset))
+ if (copy_in_user(&kp->m.offset, &up->m.offset,
+ sizeof(up->m.offset)))
return -EFAULT;
break;
case V4L2_MEMORY_USERPTR:
{
compat_long_t tmp;
+ unsigned long userptr;
if (get_user(tmp, &up->m.userptr))
return -EFAULT;
- kp->m.userptr = (unsigned long)compat_ptr(tmp);
+ userptr = (unsigned long)compat_ptr(tmp);
+ put_user(userptr, &kp->m.userptr);
}
break;
case V4L2_MEMORY_OVERLAY:
- if (get_user(kp->m.offset, &up->m.offset))
+ if (copy_in_user(&kp->m.offset, &up->m.offset,
+ sizeof(up->m.offset)))
return -EFAULT;
break;
case V4L2_MEMORY_DMABUF:
- if (get_user(kp->m.fd, &up->m.fd))
+ if (copy_in_user(&kp->m.fd, &up->m.fd,
+ sizeof(up->m.fd)))
return -EFAULT;
break;
}
@@ -488,65 +569,86 @@
return 0;
}
-static int put_v4l2_buffer32(struct v4l2_buffer *kp, struct v4l2_buffer32 __user *up)
+static int put_v4l2_buffer32(struct v4l2_buffer __user *kp,
+ struct v4l2_buffer32 __user *up)
{
struct v4l2_plane32 __user *uplane32;
struct v4l2_plane __user *uplane;
compat_caddr_t p;
int num_planes;
int ret;
+ struct timeval time;
+ u32 memory, type, length;
if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_buffer32)) ||
- put_user(kp->index, &up->index) ||
- put_user(kp->type, &up->type) ||
- put_user(kp->flags, &up->flags) ||
- put_user(kp->memory, &up->memory))
- return -EFAULT;
+ !access_ok(VERIFY_READ, kp, sizeof(struct v4l2_buffer)) ||
+ copy_in_user(&up->index, &kp->index, sizeof(up->index)) ||
+ copy_in_user(&up->type, &kp->type, sizeof(up->type)) ||
+ copy_in_user(&up->flags, &kp->flags, sizeof(up->flags)) ||
+ copy_in_user(&up->memory, &kp->memory, sizeof(up->memory)))
+ return -EFAULT;
- if (put_user(kp->bytesused, &up->bytesused) ||
- put_user(kp->field, &up->field) ||
- put_user(kp->timestamp.tv_sec, &up->timestamp.tv_sec) ||
- put_user(kp->timestamp.tv_usec, &up->timestamp.tv_usec) ||
- copy_to_user(&up->timecode, &kp->timecode, sizeof(struct v4l2_timecode)) ||
- put_user(kp->sequence, &up->sequence) ||
- put_user(kp->reserved2, &up->reserved2) ||
- put_user(kp->reserved, &up->reserved) ||
- put_user(kp->length, &up->length))
- return -EFAULT;
+ if (copy_in_user(&up->bytesused, &kp->bytesused,
+ sizeof(up->bytesused)) ||
+ copy_in_user(&up->field, &kp->field, sizeof(up->field)) ||
+ get_user(time.tv_sec, &kp->timestamp.tv_sec) ||
+ get_user(time.tv_usec, &kp->timestamp.tv_usec) ||
+ put_user(time.tv_sec, &up->timestamp.tv_sec) ||
+ put_user(time.tv_usec, &up->timestamp.tv_usec) ||
+ copy_in_user(&up->timecode, &kp->timecode,
+ sizeof(struct v4l2_timecode)) ||
+ copy_in_user(&up->sequence, &kp->sequence,
+ sizeof(up->sequence)) ||
+ copy_in_user(&up->reserved2, &kp->reserved2,
+ sizeof(up->reserved2)) ||
+ copy_in_user(&up->reserved, &kp->reserved,
+ sizeof(up->reserved)) ||
+ copy_in_user(&up->length, &kp->length, sizeof(up->length)))
+ return -EFAULT;
- if (V4L2_TYPE_IS_MULTIPLANAR(kp->type)) {
- num_planes = kp->length;
+ if (get_user(type, &kp->type) ||
+ get_user(memory, &kp->memory) ||
+ get_user(length, &kp->length))
+ return -EINVAL;
+
+ if (V4L2_TYPE_IS_MULTIPLANAR(type)) {
+ num_planes = length;
if (num_planes == 0)
return 0;
- uplane = (__force struct v4l2_plane __user *)kp->m.planes;
+ if (get_user(uplane, &kp->m.planes))
+ return -EFAULT;
if (get_user(p, &up->m.planes))
return -EFAULT;
uplane32 = compat_ptr(p);
while (--num_planes >= 0) {
- ret = put_v4l2_plane32(uplane, uplane32, kp->memory);
+ ret = put_v4l2_plane32(uplane, uplane32, memory);
if (ret)
return ret;
++uplane;
++uplane32;
}
} else {
- switch (kp->memory) {
+ switch (memory) {
case V4L2_MEMORY_MMAP:
- if (put_user(kp->m.offset, &up->m.offset))
+ if (copy_in_user(&up->m.offset, &kp->m.offset,
+ sizeof(up->m.offset)))
return -EFAULT;
break;
case V4L2_MEMORY_USERPTR:
- if (put_user(kp->m.userptr, &up->m.userptr))
+ if (copy_in_user(&up->m.userptr, &kp->m.userptr,
+ sizeof(up->m.userptr)))
return -EFAULT;
break;
case V4L2_MEMORY_OVERLAY:
- if (put_user(kp->m.offset, &up->m.offset))
+ if (copy_in_user(&up->m.offset, &kp->m.offset,
+ sizeof(up->m.offset)))
return -EFAULT;
break;
case V4L2_MEMORY_DMABUF:
- if (put_user(kp->m.fd, &up->m.fd))
+ if (copy_in_user(&up->m.fd, &kp->m.fd,
+ sizeof(up->m.fd)))
return -EFAULT;
break;
}
@@ -571,29 +673,39 @@
} fmt;
};
-static int get_v4l2_framebuffer32(struct v4l2_framebuffer *kp, struct v4l2_framebuffer32 __user *up)
+static int get_v4l2_framebuffer32(struct v4l2_framebuffer __user *kp,
+ struct v4l2_framebuffer32 __user *up)
{
u32 tmp;
if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_framebuffer32)) ||
+ !access_ok(VERIFY_WRITE, kp,
+ sizeof(struct v4l2_framebuffer)) ||
get_user(tmp, &up->base) ||
- get_user(kp->capability, &up->capability) ||
- get_user(kp->flags, &up->flags) ||
- copy_from_user(&kp->fmt, &up->fmt, sizeof(up->fmt)))
+ put_user(compat_ptr(tmp), &kp->base) ||
+ copy_in_user(&kp->capability, &up->capability,
+ sizeof(up->capability)) ||
+ copy_in_user(&kp->flags, &up->flags, sizeof(up->flags)) ||
+ copy_in_user(&kp->fmt, &up->fmt, sizeof(up->fmt)))
return -EFAULT;
- kp->base = (__force void *)compat_ptr(tmp);
+
return 0;
}
-static int put_v4l2_framebuffer32(struct v4l2_framebuffer *kp, struct v4l2_framebuffer32 __user *up)
+static int put_v4l2_framebuffer32(struct v4l2_framebuffer __user *kp,
+ struct v4l2_framebuffer32 __user *up)
{
- u32 tmp = (u32)((unsigned long)kp->base);
+ unsigned long base;
if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_framebuffer32)) ||
- put_user(tmp, &up->base) ||
- put_user(kp->capability, &up->capability) ||
- put_user(kp->flags, &up->flags) ||
- copy_to_user(&up->fmt, &kp->fmt, sizeof(up->fmt)))
+ !access_ok(VERIFY_READ, kp,
+ sizeof(struct v4l2_framebuffer)) ||
+ copy_from_user(&base, &kp->base, sizeof(base)) ||
+ put_user((u32)base, &up->base) ||
+ copy_in_user(&up->capability, &kp->capability,
+ sizeof(up->capability)) ||
+ copy_in_user(&up->flags, &kp->flags, sizeof(up->flags)) ||
+ copy_in_user(&up->fmt, &kp->fmt, sizeof(up->fmt)))
return -EFAULT;
return 0;
}
@@ -611,16 +723,18 @@
/* The 64-bit v4l2_input struct has extra padding at the end of the struct.
Otherwise it is identical to the 32-bit version. */
-static inline int get_v4l2_input32(struct v4l2_input *kp, struct v4l2_input32 __user *up)
+static inline int get_v4l2_input32(struct v4l2_input __user *kp,
+ struct v4l2_input32 __user *up)
{
- if (copy_from_user(kp, up, sizeof(struct v4l2_input32)))
+ if (copy_in_user(kp, up, sizeof(struct v4l2_input32)))
return -EFAULT;
return 0;
}
-static inline int put_v4l2_input32(struct v4l2_input *kp, struct v4l2_input32 __user *up)
+static inline int put_v4l2_input32(struct v4l2_input __user *kp,
+ struct v4l2_input32 __user *up)
{
- if (copy_to_user(up, kp, sizeof(struct v4l2_input32)))
+ if (copy_in_user(up, kp, sizeof(struct v4l2_input32)))
return -EFAULT;
return 0;
}
@@ -661,23 +775,33 @@
}
}
-static int get_v4l2_ext_controls32(struct v4l2_ext_controls *kp, struct v4l2_ext_controls32 __user *up)
+static int get_v4l2_ext_controls32(struct v4l2_ext_controls __user *kp,
+ struct v4l2_ext_controls32 __user *up)
{
struct v4l2_ext_control32 __user *ucontrols;
struct v4l2_ext_control __user *kcontrols;
int n;
compat_caddr_t p;
+ u32 count;
if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_ext_controls32)) ||
- get_user(kp->which, &up->which) ||
- get_user(kp->count, &up->count) ||
- get_user(kp->error_idx, &up->error_idx) ||
- copy_from_user(kp->reserved, up->reserved,
- sizeof(kp->reserved)))
+ !access_ok(VERIFY_WRITE, kp,
+ sizeof(struct v4l2_ext_controls)) ||
+ copy_in_user(&kp->which, &up->which,
+ sizeof(up->which)) ||
+ copy_in_user(&kp->count, &up->count, sizeof(up->count)) ||
+ copy_in_user(&kp->error_idx, &up->error_idx,
+ sizeof(up->error_idx)) ||
+ copy_in_user(kp->reserved, up->reserved,
+ sizeof(up->reserved)))
return -EFAULT;
- n = kp->count;
+
+ if (get_user(count, &kp->count))
+ return -EFAULT;
+ n = count;
if (n == 0) {
- kp->controls = NULL;
+ if (put_user(NULL, &kp->controls))
+ return -EINVAL;
return 0;
}
if (get_user(p, &up->controls))
@@ -687,7 +811,9 @@
n * sizeof(struct v4l2_ext_control32)))
return -EFAULT;
kcontrols = compat_alloc_user_space(n * sizeof(struct v4l2_ext_control));
- kp->controls = (__force struct v4l2_ext_control *)kcontrols;
+ if (put_user(kcontrols, &kp->controls))
+ return -EFAULT;
+
while (--n >= 0) {
u32 id;
@@ -710,23 +836,33 @@
return 0;
}
-static int put_v4l2_ext_controls32(struct v4l2_ext_controls *kp, struct v4l2_ext_controls32 __user *up)
+static int put_v4l2_ext_controls32(struct v4l2_ext_controls __user *kp,
+ struct v4l2_ext_controls32 __user *up)
{
struct v4l2_ext_control32 __user *ucontrols;
- struct v4l2_ext_control __user *kcontrols =
- (__force struct v4l2_ext_control __user *)kp->controls;
- int n = kp->count;
+ struct v4l2_ext_control __user *kcontrols;
+ int n;
+ u32 count;
compat_caddr_t p;
if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_ext_controls32)) ||
- put_user(kp->which, &up->which) ||
- put_user(kp->count, &up->count) ||
- put_user(kp->error_idx, &up->error_idx) ||
- copy_to_user(up->reserved, kp->reserved, sizeof(up->reserved)))
+ !access_ok(VERIFY_READ, kp,
+ sizeof(struct v4l2_ext_controls)) ||
+ copy_in_user(&up->which, &kp->which,
+ sizeof(up->which)) ||
+ copy_in_user(&up->count, &kp->count,
+ sizeof(up->count)) ||
+ copy_in_user(&up->error_idx, &kp->error_idx,
+ sizeof(up->error_idx)) ||
+ copy_in_user(up->reserved, kp->reserved,
+ sizeof(up->reserved)) ||
+ get_user(count, &kp->count) ||
+ get_user(kcontrols, &kp->controls))
return -EFAULT;
- if (!kp->count)
+ if (!count)
return 0;
+ n = count;
if (get_user(p, &up->controls))
return -EFAULT;
ucontrols = compat_ptr(p);
@@ -766,16 +902,22 @@
__u32 reserved[8];
};
-static int put_v4l2_event32(struct v4l2_event *kp, struct v4l2_event32 __user *up)
+static int put_v4l2_event32(struct v4l2_event __user *kp,
+ struct v4l2_event32 __user *up)
{
+ struct timespec ts;
if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_event32)) ||
- put_user(kp->type, &up->type) ||
- copy_to_user(&up->u, &kp->u, sizeof(kp->u)) ||
- put_user(kp->pending, &up->pending) ||
- put_user(kp->sequence, &up->sequence) ||
- compat_put_timespec(&kp->timestamp, &up->timestamp) ||
- put_user(kp->id, &up->id) ||
- copy_to_user(up->reserved, kp->reserved, 8 * sizeof(__u32)))
+ !access_ok(VERIFY_READ, kp, sizeof(struct v4l2_event)) ||
+ copy_in_user(&up->type, &kp->type, sizeof(up->type)) ||
+ copy_in_user(&up->u, &kp->u, sizeof(up->u)) ||
+ copy_in_user(&up->pending, &kp->pending,
+ sizeof(up->pending)) ||
+ copy_in_user(&up->sequence, &kp->sequence,
+ sizeof(up->sequence)) ||
+ copy_from_user(&ts, &kp->timestamp, sizeof(ts)) ||
+ compat_put_timespec(&ts, &up->timestamp) ||
+ copy_in_user(&up->id, &kp->id, sizeof(up->id)) ||
+ copy_in_user(up->reserved, kp->reserved, 8 * sizeof(__u32)))
return -EFAULT;
return 0;
}
@@ -788,31 +930,39 @@
compat_caddr_t edid;
};
-static int get_v4l2_edid32(struct v4l2_edid *kp, struct v4l2_edid32 __user *up)
+static int get_v4l2_edid32(struct v4l2_edid __user *kp,
+ struct v4l2_edid32 __user *up)
{
u32 tmp;
if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_edid32)) ||
- get_user(kp->pad, &up->pad) ||
- get_user(kp->start_block, &up->start_block) ||
- get_user(kp->blocks, &up->blocks) ||
+ !access_ok(VERIFY_WRITE, kp, sizeof(struct v4l2_edid)) ||
+ copy_in_user(&kp->pad, &up->pad, sizeof(up->pad)) ||
+ copy_in_user(&kp->start_block, &up->start_block,
+ sizeof(up->start_block)) ||
+ copy_in_user(&kp->blocks, &up->blocks, sizeof(up->blocks)) ||
get_user(tmp, &up->edid) ||
- copy_from_user(kp->reserved, up->reserved, sizeof(kp->reserved)))
+ put_user(compat_ptr(tmp), &kp->edid) ||
+ copy_in_user(kp->reserved, up->reserved,
+ sizeof(kp->reserved)))
return -EFAULT;
- kp->edid = (__force u8 *)compat_ptr(tmp);
return 0;
}
-static int put_v4l2_edid32(struct v4l2_edid *kp, struct v4l2_edid32 __user *up)
+static int put_v4l2_edid32(struct v4l2_edid __user *kp,
+ struct v4l2_edid32 __user *up)
{
- u32 tmp = (u32)((unsigned long)kp->edid);
+ unsigned long ptr;
if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_edid32)) ||
- put_user(kp->pad, &up->pad) ||
- put_user(kp->start_block, &up->start_block) ||
- put_user(kp->blocks, &up->blocks) ||
- put_user(tmp, &up->edid) ||
- copy_to_user(up->reserved, kp->reserved, sizeof(up->reserved)))
+ !access_ok(VERIFY_READ, kp, sizeof(struct v4l2_edid)) ||
+ copy_in_user(&up->pad, &kp->pad, sizeof(up->pad)) ||
+ copy_in_user(&up->start_block, &kp->start_block,
+ sizeof(up->start_block)) ||
+ copy_in_user(&up->blocks, &kp->blocks, sizeof(up->blocks)) ||
+ copy_from_user(&ptr, &kp->edid, sizeof(ptr)) ||
+ put_user((u32)ptr, &up->edid) ||
+ copy_in_user(up->reserved, kp->reserved, sizeof(up->reserved)))
return -EFAULT;
return 0;
}
@@ -859,11 +1009,16 @@
struct v4l2_edid v2edid;
unsigned long vx;
int vi;
- } karg;
+ } *karg;
void __user *up = compat_ptr(arg);
int compatible_arg = 1;
long err = 0;
+ karg = compat_alloc_user_space(sizeof(*karg));
+ if (karg == NULL) {
+ return -EFAULT;
+ }
+
/* First, convert the command. */
switch (cmd) {
case VIDIOC_G_FMT32: cmd = VIDIOC_G_FMT; break;
@@ -899,7 +1054,8 @@
case VIDIOC_STREAMOFF:
case VIDIOC_S_INPUT:
case VIDIOC_S_OUTPUT:
- err = get_user(karg.vi, (s32 __user *)up);
+ err = copy_in_user(&karg->vi, (s32 __user *)up,
+ sizeof(karg->vi));
compatible_arg = 0;
break;
@@ -910,19 +1066,19 @@
case VIDIOC_G_EDID:
case VIDIOC_S_EDID:
- err = get_v4l2_edid32(&karg.v2edid, up);
+ err = get_v4l2_edid32(&karg->v2edid, up);
compatible_arg = 0;
break;
case VIDIOC_G_FMT:
case VIDIOC_S_FMT:
case VIDIOC_TRY_FMT:
- err = get_v4l2_format32(&karg.v2f, up);
+ err = get_v4l2_format32(&karg->v2f, up);
compatible_arg = 0;
break;
case VIDIOC_CREATE_BUFS:
- err = get_v4l2_create32(&karg.v2crt, up);
+ err = get_v4l2_create32(&karg->v2crt, up);
compatible_arg = 0;
break;
@@ -930,12 +1086,12 @@
case VIDIOC_QUERYBUF:
case VIDIOC_QBUF:
case VIDIOC_DQBUF:
- err = get_v4l2_buffer32(&karg.v2b, up);
+ err = get_v4l2_buffer32(&karg->v2b, up);
compatible_arg = 0;
break;
case VIDIOC_S_FBUF:
- err = get_v4l2_framebuffer32(&karg.v2fb, up);
+ err = get_v4l2_framebuffer32(&karg->v2fb, up);
compatible_arg = 0;
break;
@@ -944,19 +1100,19 @@
break;
case VIDIOC_ENUMSTD:
- err = get_v4l2_standard32(&karg.v2s, up);
+ err = get_v4l2_standard32(&karg->v2s, up);
compatible_arg = 0;
break;
case VIDIOC_ENUMINPUT:
- err = get_v4l2_input32(&karg.v2i, up);
+ err = get_v4l2_input32(&karg->v2i, up);
compatible_arg = 0;
break;
case VIDIOC_G_EXT_CTRLS:
case VIDIOC_S_EXT_CTRLS:
case VIDIOC_TRY_EXT_CTRLS:
- err = get_v4l2_ext_controls32(&karg.v2ecs, up);
+ err = get_v4l2_ext_controls32(&karg->v2ecs, up);
compatible_arg = 0;
break;
case VIDIOC_DQEVENT:
@@ -969,11 +1125,7 @@
if (compatible_arg)
err = native_ioctl(file, cmd, (unsigned long)up);
else {
- mm_segment_t old_fs = get_fs();
-
- set_fs(KERNEL_DS);
- err = native_ioctl(file, cmd, (unsigned long)&karg);
- set_fs(old_fs);
+ err = native_ioctl(file, cmd, (unsigned long)karg);
}
/* Special case: even after an error we need to put the
@@ -983,7 +1135,7 @@
case VIDIOC_G_EXT_CTRLS:
case VIDIOC_S_EXT_CTRLS:
case VIDIOC_TRY_EXT_CTRLS:
- if (put_v4l2_ext_controls32(&karg.v2ecs, up))
+ if (put_v4l2_ext_controls32(&karg->v2ecs, up))
err = -EFAULT;
break;
}
@@ -995,44 +1147,44 @@
case VIDIOC_S_OUTPUT:
case VIDIOC_G_INPUT:
case VIDIOC_G_OUTPUT:
- err = put_user(((s32)karg.vi), (s32 __user *)up);
+ err = copy_in_user(up, &karg->vi, sizeof(s32));
break;
case VIDIOC_G_FBUF:
- err = put_v4l2_framebuffer32(&karg.v2fb, up);
+ err = put_v4l2_framebuffer32(&karg->v2fb, up);
break;
case VIDIOC_DQEVENT:
- err = put_v4l2_event32(&karg.v2ev, up);
+ err = put_v4l2_event32(&karg->v2ev, up);
break;
case VIDIOC_G_EDID:
case VIDIOC_S_EDID:
- err = put_v4l2_edid32(&karg.v2edid, up);
+ err = put_v4l2_edid32(&karg->v2edid, up);
break;
case VIDIOC_G_FMT:
case VIDIOC_S_FMT:
case VIDIOC_TRY_FMT:
- err = put_v4l2_format32(&karg.v2f, up);
+ err = put_v4l2_format32(&karg->v2f, up);
break;
case VIDIOC_CREATE_BUFS:
- err = put_v4l2_create32(&karg.v2crt, up);
+ err = put_v4l2_create32(&karg->v2crt, up);
break;
case VIDIOC_QUERYBUF:
case VIDIOC_QBUF:
case VIDIOC_DQBUF:
- err = put_v4l2_buffer32(&karg.v2b, up);
+ err = put_v4l2_buffer32(&karg->v2b, up);
break;
case VIDIOC_ENUMSTD:
- err = put_v4l2_standard32(&karg.v2s, up);
+ err = put_v4l2_standard32(&karg->v2s, up);
break;
case VIDIOC_ENUMINPUT:
- err = put_v4l2_input32(&karg.v2i, up);
+ err = put_v4l2_input32(&karg->v2i, up);
break;
}
return err;
diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
index adc2147..0898414 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls.c
@@ -337,6 +337,7 @@
"4.2",
"5",
"5.1",
+ "5.2",
NULL,
};
static const char * const h264_loop_filter[] = {
@@ -363,6 +364,7 @@
"Scalable High Intra",
"Stereo High",
"Multiview High",
+ "Constrained High",
NULL,
};
static const char * const vui_sar_idc[] = {
diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index 2c02d2d..877c4d1 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -5869,7 +5869,8 @@
* It will return false if it is GPCE based crypto instance or
* ICE is setup properly
*/
- if (qseecom_enable_ice_setup(create_key_req.usage))
+ ret = qseecom_enable_ice_setup(create_key_req.usage);
+ if (ret)
goto free_buf;
do {
@@ -5998,7 +5999,8 @@
* It will return false if it is GPCE based crypto instance or
* ICE is setup properly
*/
- if (qseecom_enable_ice_setup(wipe_key_req.usage))
+ ret = qseecom_enable_ice_setup(wipe_key_req.usage);
+ if (ret)
goto free_buf;
ret = __qseecom_set_clear_ce_key(data, wipe_key_req.usage,
diff --git a/drivers/misc/uid_sys_stats.c b/drivers/misc/uid_sys_stats.c
index 3bc7d4e..127a052 100644
--- a/drivers/misc/uid_sys_stats.c
+++ b/drivers/misc/uid_sys_stats.c
@@ -96,9 +96,11 @@
{
struct uid_entry *uid_entry;
struct task_struct *task, *temp;
+ struct user_namespace *user_ns = current_user_ns();
cputime_t utime;
cputime_t stime;
unsigned long bkt;
+ uid_t uid;
rt_mutex_lock(&uid_lock);
@@ -109,14 +111,13 @@
read_lock(&tasklist_lock);
do_each_thread(temp, task) {
- uid_entry = find_or_register_uid(from_kuid_munged(
- current_user_ns(), task_uid(task)));
+ uid = from_kuid_munged(user_ns, task_uid(task));
+ uid_entry = find_or_register_uid(uid);
if (!uid_entry) {
read_unlock(&tasklist_lock);
rt_mutex_unlock(&uid_lock);
pr_err("%s: failed to find the uid_entry for uid %d\n",
- __func__, from_kuid_munged(current_user_ns(),
- task_uid(task)));
+ __func__, uid);
return -ENOMEM;
}
task_cputime_adjusted(task, &utime, &stime);
diff --git a/drivers/net/can/usb/gs_usb.c b/drivers/net/can/usb/gs_usb.c
index a0dabd4..7ab24c5 100644
--- a/drivers/net/can/usb/gs_usb.c
+++ b/drivers/net/can/usb/gs_usb.c
@@ -740,13 +740,18 @@
static int gs_usb_set_identify(struct net_device *netdev, bool do_identify)
{
struct gs_can *dev = netdev_priv(netdev);
- struct gs_identify_mode imode;
+ struct gs_identify_mode *imode;
int rc;
+ imode = kmalloc(sizeof(*imode), GFP_KERNEL);
+
+ if (!imode)
+ return -ENOMEM;
+
if (do_identify)
- imode.mode = GS_CAN_IDENTIFY_ON;
+ imode->mode = GS_CAN_IDENTIFY_ON;
else
- imode.mode = GS_CAN_IDENTIFY_OFF;
+ imode->mode = GS_CAN_IDENTIFY_OFF;
rc = usb_control_msg(interface_to_usbdev(dev->iface),
usb_sndctrlpipe(interface_to_usbdev(dev->iface),
@@ -756,10 +761,12 @@
USB_RECIP_INTERFACE,
dev->channel,
0,
- &imode,
- sizeof(imode),
+ imode,
+ sizeof(*imode),
100);
+ kfree(imode);
+
return (rc > 0) ? 0 : rc;
}
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h
index 81d8e3b..21ce0b7 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h
@@ -82,7 +82,7 @@
#define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) <= U16_MAX)
#define MLX5_UMR_ALIGN (2048)
-#define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
+#define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256)
#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
#define MLX5E_DEFAULT_LRO_TIMEOUT 32
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c
index 90e81ae..e034dbc 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c
@@ -563,6 +563,7 @@
int idx = 0;
int err = 0;
+ info->data = MAX_NUM_OF_ETHTOOL_RULES;
while ((!err || err == -ENOENT) && idx < info->rule_cnt) {
err = mlx5e_ethtool_get_flow(priv, info, location);
if (!err)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag.c
index 5595724..b5d5519 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lag.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag.c
@@ -294,7 +294,7 @@
struct netdev_notifier_changeupper_info *info)
{
struct net_device *upper = info->upper_dev, *ndev_tmp;
- struct netdev_lag_upper_info *lag_upper_info;
+ struct netdev_lag_upper_info *lag_upper_info = NULL;
bool is_bonded;
int bond_status = 0;
int num_slaves = 0;
@@ -303,7 +303,8 @@
if (!netif_is_lag_master(upper))
return 0;
- lag_upper_info = info->upper_info;
+ if (info->linking)
+ lag_upper_info = info->upper_info;
/* The event may still be of interest if the slave does not belong to
* us, but is enslaved to a master which has one or more of our netdevs
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c
index 7a196a0..d776db7 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c
@@ -966,7 +966,7 @@
if (err) {
dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
FW_INIT_TIMEOUT_MILI);
- goto out_err;
+ goto err_cmd_cleanup;
}
err = mlx5_core_enable_hca(dev, 0);
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index 1a92de7..a2d218b 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -1059,12 +1059,70 @@
.get_mdio_data = sh_get_mdio,
};
+/* free Tx skb function */
+static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
+{
+ struct sh_eth_private *mdp = netdev_priv(ndev);
+ struct sh_eth_txdesc *txdesc;
+ int free_num = 0;
+ int entry;
+ bool sent;
+
+ for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
+ entry = mdp->dirty_tx % mdp->num_tx_ring;
+ txdesc = &mdp->tx_ring[entry];
+ sent = !(txdesc->status & cpu_to_le32(TD_TACT));
+ if (sent_only && !sent)
+ break;
+ /* TACT bit must be checked before all the following reads */
+ dma_rmb();
+ netif_info(mdp, tx_done, ndev,
+ "tx entry %d status 0x%08x\n",
+ entry, le32_to_cpu(txdesc->status));
+ /* Free the original skb. */
+ if (mdp->tx_skbuff[entry]) {
+ dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
+ le32_to_cpu(txdesc->len) >> 16,
+ DMA_TO_DEVICE);
+ dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
+ mdp->tx_skbuff[entry] = NULL;
+ free_num++;
+ }
+ txdesc->status = cpu_to_le32(TD_TFP);
+ if (entry >= mdp->num_tx_ring - 1)
+ txdesc->status |= cpu_to_le32(TD_TDLE);
+
+ if (sent) {
+ ndev->stats.tx_packets++;
+ ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
+ }
+ }
+ return free_num;
+}
+
/* free skb and descriptor buffer */
static void sh_eth_ring_free(struct net_device *ndev)
{
struct sh_eth_private *mdp = netdev_priv(ndev);
int ringsize, i;
+ if (mdp->rx_ring) {
+ for (i = 0; i < mdp->num_rx_ring; i++) {
+ if (mdp->rx_skbuff[i]) {
+ struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
+
+ dma_unmap_single(&ndev->dev,
+ le32_to_cpu(rxdesc->addr),
+ ALIGN(mdp->rx_buf_sz, 32),
+ DMA_FROM_DEVICE);
+ }
+ }
+ ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
+ dma_free_coherent(NULL, ringsize, mdp->rx_ring,
+ mdp->rx_desc_dma);
+ mdp->rx_ring = NULL;
+ }
+
/* Free Rx skb ringbuffer */
if (mdp->rx_skbuff) {
for (i = 0; i < mdp->num_rx_ring; i++)
@@ -1073,27 +1131,18 @@
kfree(mdp->rx_skbuff);
mdp->rx_skbuff = NULL;
- /* Free Tx skb ringbuffer */
- if (mdp->tx_skbuff) {
- for (i = 0; i < mdp->num_tx_ring; i++)
- dev_kfree_skb(mdp->tx_skbuff[i]);
- }
- kfree(mdp->tx_skbuff);
- mdp->tx_skbuff = NULL;
-
- if (mdp->rx_ring) {
- ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
- dma_free_coherent(NULL, ringsize, mdp->rx_ring,
- mdp->rx_desc_dma);
- mdp->rx_ring = NULL;
- }
-
if (mdp->tx_ring) {
+ sh_eth_tx_free(ndev, false);
+
ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
dma_free_coherent(NULL, ringsize, mdp->tx_ring,
mdp->tx_desc_dma);
mdp->tx_ring = NULL;
}
+
+ /* Free Tx skb ringbuffer */
+ kfree(mdp->tx_skbuff);
+ mdp->tx_skbuff = NULL;
}
/* format skb and descriptor buffer */
@@ -1341,43 +1390,6 @@
update_mac_address(ndev);
}
-/* free Tx skb function */
-static int sh_eth_txfree(struct net_device *ndev)
-{
- struct sh_eth_private *mdp = netdev_priv(ndev);
- struct sh_eth_txdesc *txdesc;
- int free_num = 0;
- int entry;
-
- for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
- entry = mdp->dirty_tx % mdp->num_tx_ring;
- txdesc = &mdp->tx_ring[entry];
- if (txdesc->status & cpu_to_le32(TD_TACT))
- break;
- /* TACT bit must be checked before all the following reads */
- dma_rmb();
- netif_info(mdp, tx_done, ndev,
- "tx entry %d status 0x%08x\n",
- entry, le32_to_cpu(txdesc->status));
- /* Free the original skb. */
- if (mdp->tx_skbuff[entry]) {
- dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
- le32_to_cpu(txdesc->len) >> 16,
- DMA_TO_DEVICE);
- dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
- mdp->tx_skbuff[entry] = NULL;
- free_num++;
- }
- txdesc->status = cpu_to_le32(TD_TFP);
- if (entry >= mdp->num_tx_ring - 1)
- txdesc->status |= cpu_to_le32(TD_TDLE);
-
- ndev->stats.tx_packets++;
- ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
- }
- return free_num;
-}
-
/* Packet receive function */
static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
{
@@ -1620,7 +1632,7 @@
intr_status, mdp->cur_tx, mdp->dirty_tx,
(u32)ndev->state, edtrr);
/* dirty buffer free */
- sh_eth_txfree(ndev);
+ sh_eth_tx_free(ndev, true);
/* SH7712 BUG */
if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
@@ -1679,7 +1691,7 @@
/* Clear Tx interrupts */
sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
- sh_eth_txfree(ndev);
+ sh_eth_tx_free(ndev, true);
netif_wake_queue(ndev);
}
@@ -2307,7 +2319,7 @@
spin_lock_irqsave(&mdp->lock, flags);
if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
- if (!sh_eth_txfree(ndev)) {
+ if (!sh_eth_tx_free(ndev, true)) {
netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
netif_stop_queue(ndev);
spin_unlock_irqrestore(&mdp->lock, flags);
diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c
index d2e61e0..f7c6a40 100644
--- a/drivers/net/macsec.c
+++ b/drivers/net/macsec.c
@@ -2709,7 +2709,7 @@
}
#define MACSEC_FEATURES \
- (NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST)
+ (NETIF_F_SG | NETIF_F_HIGHDMA)
static struct lock_class_key macsec_netdev_addr_lock_key;
static int macsec_dev_init(struct net_device *dev)
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index 26d6f0b..dc8ccac 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -1140,6 +1140,7 @@
static void macvlan_port_destroy(struct net_device *dev)
{
struct macvlan_port *port = macvlan_port_get_rtnl(dev);
+ struct sk_buff *skb;
dev->priv_flags &= ~IFF_MACVLAN_PORT;
netdev_rx_handler_unregister(dev);
@@ -1148,7 +1149,15 @@
* but we need to cancel it and purge left skbs if any.
*/
cancel_work_sync(&port->bc_work);
- __skb_queue_purge(&port->bc_queue);
+
+ while ((skb = __skb_dequeue(&port->bc_queue))) {
+ const struct macvlan_dev *src = MACVLAN_SKB_CB(skb)->src;
+
+ if (src)
+ dev_put(src->dev);
+
+ kfree_skb(skb);
+ }
kfree_rcu(port, rcu);
}
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
index 7a240fc..4865221 100644
--- a/drivers/net/phy/dp83640.c
+++ b/drivers/net/phy/dp83640.c
@@ -1438,8 +1438,6 @@
skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
skb_queue_tail(&dp83640->rx_queue, skb);
schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
- } else {
- netif_rx_ni(skb);
}
return true;
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 201ffa5..a9be26f 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -552,16 +552,18 @@
EXPORT_SYMBOL(phy_mii_ioctl);
/**
- * phy_start_aneg - start auto-negotiation for this PHY device
+ * phy_start_aneg_priv - start auto-negotiation for this PHY device
* @phydev: the phy_device struct
+ * @sync: indicate whether we should wait for the workqueue cancelation
*
* Description: Sanitizes the settings (if we're not autonegotiating
* them), and then calls the driver's config_aneg function.
* If the PHYCONTROL Layer is operating, we change the state to
* reflect the beginning of Auto-negotiation or forcing.
*/
-int phy_start_aneg(struct phy_device *phydev)
+static int phy_start_aneg_priv(struct phy_device *phydev, bool sync)
{
+ bool trigger = 0;
int err;
mutex_lock(&phydev->lock);
@@ -586,10 +588,40 @@
}
}
+ /* Re-schedule a PHY state machine to check PHY status because
+ * negotiation may already be done and aneg interrupt may not be
+ * generated.
+ */
+ if (phy_interrupt_is_valid(phydev) && (phydev->state == PHY_AN)) {
+ err = phy_aneg_done(phydev);
+ if (err > 0) {
+ trigger = true;
+ err = 0;
+ }
+ }
+
out_unlock:
mutex_unlock(&phydev->lock);
+
+ if (trigger)
+ phy_trigger_machine(phydev, sync);
+
return err;
}
+
+/**
+ * phy_start_aneg - start auto-negotiation for this PHY device
+ * @phydev: the phy_device struct
+ *
+ * Description: Sanitizes the settings (if we're not autonegotiating
+ * them), and then calls the driver's config_aneg function.
+ * If the PHYCONTROL Layer is operating, we change the state to
+ * reflect the beginning of Auto-negotiation or forcing.
+ */
+int phy_start_aneg(struct phy_device *phydev)
+{
+ return phy_start_aneg_priv(phydev, true);
+}
EXPORT_SYMBOL(phy_start_aneg);
/**
@@ -617,7 +649,7 @@
* state machine runs.
*/
-static void phy_trigger_machine(struct phy_device *phydev, bool sync)
+void phy_trigger_machine(struct phy_device *phydev, bool sync)
{
if (sync)
cancel_delayed_work_sync(&phydev->state_queue);
@@ -639,7 +671,7 @@
cancel_delayed_work_sync(&phydev->state_queue);
mutex_lock(&phydev->lock);
- if (phydev->state > PHY_UP)
+ if (phydev->state > PHY_UP && phydev->state != PHY_HALTED)
phydev->state = PHY_UP;
mutex_unlock(&phydev->lock);
}
@@ -1100,7 +1132,7 @@
mutex_unlock(&phydev->lock);
if (needs_aneg)
- err = phy_start_aneg(phydev);
+ err = phy_start_aneg_priv(phydev, false);
else if (do_suspend)
phy_suspend(phydev);
diff --git a/drivers/net/ppp/pppolac.c b/drivers/net/ppp/pppolac.c
index 0184c96..3a45cf8 100644
--- a/drivers/net/ppp/pppolac.c
+++ b/drivers/net/ppp/pppolac.c
@@ -206,7 +206,9 @@
while ((skb = skb_dequeue(&delivery_queue))) {
struct sock *sk_udp = skb->sk;
struct kvec iov = {.iov_base = skb->data, .iov_len = skb->len};
- struct msghdr msg = { 0 };
+ struct msghdr msg = {
+ .msg_flags = MSG_NOSIGNAL | MSG_DONTWAIT,
+ };
iov_iter_kvec(&msg.msg_iter, WRITE | ITER_KVEC, &iov, 1,
skb->len);
diff --git a/drivers/net/ppp/pppopns.c b/drivers/net/ppp/pppopns.c
index d9e0603..cdb4fa1 100644
--- a/drivers/net/ppp/pppopns.c
+++ b/drivers/net/ppp/pppopns.c
@@ -189,7 +189,9 @@
while ((skb = skb_dequeue(&delivery_queue))) {
struct sock *sk_raw = skb->sk;
struct kvec iov = {.iov_base = skb->data, .iov_len = skb->len};
- struct msghdr msg = { 0 };
+ struct msghdr msg = {
+ .msg_flags = MSG_NOSIGNAL | MSG_DONTWAIT,
+ };
iov_iter_kvec(&msg.msg_iter, WRITE | ITER_KVEC, &iov, 1,
skb->len);
diff --git a/drivers/net/vrf.c b/drivers/net/vrf.c
index a2afb8e..80ef486 100644
--- a/drivers/net/vrf.c
+++ b/drivers/net/vrf.c
@@ -1124,7 +1124,7 @@
goto nla_put_failure;
/* rule only needs to appear once */
- nlh->nlmsg_flags &= NLM_F_EXCL;
+ nlh->nlmsg_flags |= NLM_F_EXCL;
frh = nlmsg_data(nlh);
memset(frh, 0, sizeof(*frh));
diff --git a/drivers/net/wireless/ath/wil6210/cfg80211.c b/drivers/net/wireless/ath/wil6210/cfg80211.c
index 6c68fd9..4e111cb 100644
--- a/drivers/net/wireless/ath/wil6210/cfg80211.c
+++ b/drivers/net/wireless/ath/wil6210/cfg80211.c
@@ -474,22 +474,23 @@
}
mutex_unlock(&wil->p2p_wdev_mutex);
- /* social scan on P2P_DEVICE is handled as p2p search */
- if (wdev->iftype == NL80211_IFTYPE_P2P_DEVICE &&
- wil_p2p_is_social_scan(request)) {
+ if (wdev->iftype == NL80211_IFTYPE_P2P_DEVICE) {
if (!wil->p2p.p2p_dev_started) {
wil_err(wil, "P2P search requested on stopped P2P device\n");
rc = -EIO;
goto out;
}
- wil->scan_request = request;
- wil->radio_wdev = wdev;
- rc = wil_p2p_search(wil, request);
- if (rc) {
- wil->radio_wdev = wil_to_wdev(wil);
- wil->scan_request = NULL;
+ /* social scan on P2P_DEVICE is handled as p2p search */
+ if (wil_p2p_is_social_scan(request)) {
+ wil->scan_request = request;
+ wil->radio_wdev = wdev;
+ rc = wil_p2p_search(wil, request);
+ if (rc) {
+ wil->radio_wdev = wil_to_wdev(wil);
+ wil->scan_request = NULL;
+ }
+ goto out;
}
- goto out;
}
(void)wil_p2p_stop_discovery(wil);
@@ -499,9 +500,9 @@
for (i = 0; i < request->n_ssids; i++) {
wil_dbg_misc(wil, "SSID[%d]", i);
- print_hex_dump_bytes("SSID ", DUMP_PREFIX_OFFSET,
- request->ssids[i].ssid,
- request->ssids[i].ssid_len);
+ wil_hex_dump_misc("SSID ", DUMP_PREFIX_OFFSET, 16, 1,
+ request->ssids[i].ssid,
+ request->ssids[i].ssid_len, true);
}
if (request->n_ssids)
@@ -538,8 +539,8 @@
}
if (request->ie_len)
- print_hex_dump_bytes("Scan IE ", DUMP_PREFIX_OFFSET,
- request->ie, request->ie_len);
+ wil_hex_dump_misc("Scan IE ", DUMP_PREFIX_OFFSET, 16, 1,
+ request->ie, request->ie_len, true);
else
wil_dbg_misc(wil, "Scan has no IE's\n");
@@ -763,6 +764,8 @@
rc = wmi_send(wil, WMI_CONNECT_CMDID, &conn, sizeof(conn));
if (rc == 0) {
netif_carrier_on(ndev);
+ wil6210_bus_request(wil, WIL_MAX_BUS_REQUEST_KBPS);
+ wil->bss = bss;
/* Connect can take lots of time */
mod_timer(&wil->connect_timer,
jiffies + msecs_to_jiffies(2000));
@@ -791,6 +794,7 @@
return 0;
}
+ wil->locally_generated_disc = true;
rc = wmi_call(wil, WMI_DISCONNECT_CMDID, NULL, 0,
WMI_DISCONNECT_EVENTID, NULL, 0,
WIL6210_DISCONNECT_TO_MS);
@@ -844,7 +848,8 @@
*/
wil_dbg_misc(wil, "mgmt_tx\n");
- print_hex_dump_bytes("mgmt tx frame ", DUMP_PREFIX_OFFSET, buf, len);
+ wil_hex_dump_misc("mgmt tx frame ", DUMP_PREFIX_OFFSET, 16, 1, buf,
+ len, true);
cmd = kmalloc(sizeof(*cmd) + len, GFP_KERNEL);
if (!cmd) {
@@ -1177,18 +1182,18 @@
static void wil_print_bcon_data(struct cfg80211_beacon_data *b)
{
- print_hex_dump_bytes("head ", DUMP_PREFIX_OFFSET,
- b->head, b->head_len);
- print_hex_dump_bytes("tail ", DUMP_PREFIX_OFFSET,
- b->tail, b->tail_len);
- print_hex_dump_bytes("BCON IE ", DUMP_PREFIX_OFFSET,
- b->beacon_ies, b->beacon_ies_len);
- print_hex_dump_bytes("PROBE ", DUMP_PREFIX_OFFSET,
- b->probe_resp, b->probe_resp_len);
- print_hex_dump_bytes("PROBE IE ", DUMP_PREFIX_OFFSET,
- b->proberesp_ies, b->proberesp_ies_len);
- print_hex_dump_bytes("ASSOC IE ", DUMP_PREFIX_OFFSET,
- b->assocresp_ies, b->assocresp_ies_len);
+ wil_hex_dump_misc("head ", DUMP_PREFIX_OFFSET, 16, 1,
+ b->head, b->head_len, true);
+ wil_hex_dump_misc("tail ", DUMP_PREFIX_OFFSET, 16, 1,
+ b->tail, b->tail_len, true);
+ wil_hex_dump_misc("BCON IE ", DUMP_PREFIX_OFFSET, 16, 1,
+ b->beacon_ies, b->beacon_ies_len, true);
+ wil_hex_dump_misc("PROBE ", DUMP_PREFIX_OFFSET, 16, 1,
+ b->probe_resp, b->probe_resp_len, true);
+ wil_hex_dump_misc("PROBE IE ", DUMP_PREFIX_OFFSET, 16, 1,
+ b->proberesp_ies, b->proberesp_ies_len, true);
+ wil_hex_dump_misc("ASSOC IE ", DUMP_PREFIX_OFFSET, 16, 1,
+ b->assocresp_ies, b->assocresp_ies_len, true);
}
/* internal functions for device reset and starting AP */
@@ -1282,6 +1287,7 @@
wil->pbss = pbss;
netif_carrier_on(ndev);
+ wil6210_bus_request(wil, WIL_MAX_BUS_REQUEST_KBPS);
rc = wmi_pcp_start(wil, bi, wmi_nettype, chan, hidden_ssid, is_go);
if (rc)
@@ -1297,6 +1303,7 @@
wmi_pcp_stop(wil);
err_pcp_start:
netif_carrier_off(ndev);
+ wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS);
out:
mutex_unlock(&wil->mutex);
return rc;
@@ -1382,8 +1389,8 @@
wil_dbg_misc(wil, "BI %d DTIM %d\n", info->beacon_interval,
info->dtim_period);
wil_dbg_misc(wil, "PBSS %d\n", info->pbss);
- print_hex_dump_bytes("SSID ", DUMP_PREFIX_OFFSET,
- info->ssid, info->ssid_len);
+ wil_hex_dump_misc("SSID ", DUMP_PREFIX_OFFSET, 16, 1,
+ info->ssid, info->ssid_len, true);
wil_print_bcon_data(bcon);
wil_print_crypto(wil, crypto);
@@ -1403,6 +1410,7 @@
wil_dbg_misc(wil, "stop_ap\n");
netif_carrier_off(ndev);
+ wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS);
wil_set_recovery_state(wil, fw_recovery_idle);
mutex_lock(&wil->mutex);
diff --git a/drivers/net/wireless/ath/wil6210/debugfs.c b/drivers/net/wireless/ath/wil6210/debugfs.c
index 3e8cdf1..5648ebb 100644
--- a/drivers/net/wireless/ath/wil6210/debugfs.c
+++ b/drivers/net/wireless/ath/wil6210/debugfs.c
@@ -524,9 +524,8 @@
if (!buf)
return -ENOMEM;
- wil_memcpy_fromio_halp_vote(wil_blob->wil, buf,
- (const volatile void __iomem *)
- wil_blob->blob.data + pos, count);
+ wil_memcpy_fromio_32(buf, (const void __iomem *)
+ wil_blob->blob.data + pos, count);
ret = copy_to_user(user_buf, buf, count);
kfree(buf);
diff --git a/drivers/net/wireless/ath/wil6210/main.c b/drivers/net/wireless/ath/wil6210/main.c
index 2c48419..36959a3 100644
--- a/drivers/net/wireless/ath/wil6210/main.c
+++ b/drivers/net/wireless/ath/wil6210/main.c
@@ -30,8 +30,8 @@
module_param(debug_fw, bool, 0444);
MODULE_PARM_DESC(debug_fw, " do not perform card reset. For FW debug");
-static bool oob_mode;
-module_param(oob_mode, bool, 0444);
+static u8 oob_mode;
+module_param(oob_mode, byte, 0444);
MODULE_PARM_DESC(oob_mode,
" enable out of the box (OOB) mode in FW, for diagnostics and certification");
@@ -135,14 +135,6 @@
*d++ = __raw_readl(s++);
}
-void wil_memcpy_fromio_halp_vote(struct wil6210_priv *wil, void *dst,
- const volatile void __iomem *src, size_t count)
-{
- wil_halp_vote(wil);
- wil_memcpy_fromio_32(dst, src, count);
- wil_halp_unvote(wil);
-}
-
void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
size_t count)
{
@@ -153,15 +145,6 @@
__raw_writel(*s++, d++);
}
-void wil_memcpy_toio_halp_vote(struct wil6210_priv *wil,
- volatile void __iomem *dst,
- const void *src, size_t count)
-{
- wil_halp_vote(wil);
- wil_memcpy_toio_32(dst, src, count);
- wil_halp_unvote(wil);
-}
-
static void wil_disconnect_cid(struct wil6210_priv *wil, int cid,
u16 reason_code, bool from_event)
__acquires(&sta->tid_rx_lock) __releases(&sta->tid_rx_lock)
@@ -274,15 +257,20 @@
wil_bcast_fini(wil);
wil_update_net_queues_bh(wil, NULL, true);
netif_carrier_off(ndev);
+ wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS);
if (test_bit(wil_status_fwconnected, wil->status)) {
clear_bit(wil_status_fwconnected, wil->status);
cfg80211_disconnected(ndev, reason_code,
- NULL, 0, false, GFP_KERNEL);
+ NULL, 0,
+ wil->locally_generated_disc,
+ GFP_KERNEL);
+ wil->locally_generated_disc = false;
} else if (test_bit(wil_status_fwconnecting, wil->status)) {
cfg80211_connect_result(ndev, bssid, NULL, 0, NULL, 0,
WLAN_STATUS_UNSPECIFIED_FAILURE,
GFP_KERNEL);
+ wil->bss = NULL;
}
clear_bit(wil_status_fwconnecting, wil->status);
break;
@@ -304,10 +292,34 @@
{
struct wil6210_priv *wil = container_of(work,
struct wil6210_priv, disconnect_worker);
+ struct net_device *ndev = wil_to_ndev(wil);
+ int rc;
+ struct {
+ struct wmi_cmd_hdr wmi;
+ struct wmi_disconnect_event evt;
+ } __packed reply;
- mutex_lock(&wil->mutex);
- _wil6210_disconnect(wil, NULL, WLAN_REASON_UNSPECIFIED, false);
- mutex_unlock(&wil->mutex);
+ if (test_bit(wil_status_fwconnected, wil->status))
+ /* connect succeeded after all */
+ return;
+
+ if (!test_bit(wil_status_fwconnecting, wil->status))
+ /* already disconnected */
+ return;
+
+ rc = wmi_call(wil, WMI_DISCONNECT_CMDID, NULL, 0,
+ WMI_DISCONNECT_EVENTID, &reply, sizeof(reply),
+ WIL6210_DISCONNECT_TO_MS);
+ if (rc) {
+ wil_err(wil, "disconnect error %d\n", rc);
+ return;
+ }
+
+ wil_update_net_queues_bh(wil, NULL, true);
+ netif_carrier_off(ndev);
+ cfg80211_connect_result(ndev, NULL, NULL, 0, NULL, 0,
+ WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_KERNEL);
+ clear_bit(wil_status_fwconnecting, wil->status);
}
static void wil_connect_timer_fn(ulong x)
@@ -557,6 +569,12 @@
return -EAGAIN;
}
+void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps)
+{
+ if (wil->platform_ops.bus_request)
+ wil->platform_ops.bus_request(wil->platform_handle, kbps);
+}
+
/**
* wil6210_disconnect - disconnect one connection
* @wil: driver context
@@ -610,13 +628,25 @@
wil_w(wil, RGF_USER_USER_CPU_0, 1);
}
-static void wil_set_oob_mode(struct wil6210_priv *wil, bool enable)
+static void wil_set_oob_mode(struct wil6210_priv *wil, u8 mode)
{
- wil_info(wil, "enable=%d\n", enable);
- if (enable)
+ wil_info(wil, "oob_mode to %d\n", mode);
+ switch (mode) {
+ case 0:
+ wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE |
+ BIT_USER_OOB_R2_MODE);
+ break;
+ case 1:
+ wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_R2_MODE);
wil_s(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE);
- else
+ break;
+ case 2:
wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE);
+ wil_s(wil, RGF_USER_USAGE_6, BIT_USER_OOB_R2_MODE);
+ break;
+ default:
+ wil_err(wil, "invalid oob_mode: %d\n", mode);
+ }
}
static int wil_target_reset(struct wil6210_priv *wil)
@@ -1073,9 +1103,7 @@
napi_enable(&wil->napi_tx);
set_bit(wil_status_napi_en, wil->status);
- if (wil->platform_ops.bus_request)
- wil->platform_ops.bus_request(wil->platform_handle,
- WIL_MAX_BUS_REQUEST_KBPS);
+ wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS);
return 0;
}
@@ -1099,8 +1127,7 @@
set_bit(wil_status_resetting, wil->status);
- if (wil->platform_ops.bus_request)
- wil->platform_ops.bus_request(wil->platform_handle, 0);
+ wil6210_bus_request(wil, 0);
wil_disable_irq(wil);
if (test_and_clear_bit(wil_status_napi_en, wil->status)) {
@@ -1163,6 +1190,7 @@
wil->halp.ref_cnt);
if (++wil->halp.ref_cnt == 1) {
+ reinit_completion(&wil->halp.comp);
wil6210_set_halp(wil);
rc = wait_for_completion_timeout(&wil->halp.comp, to_jiffies);
if (!rc) {
diff --git a/drivers/net/wireless/ath/wil6210/pm.c b/drivers/net/wireless/ath/wil6210/pm.c
index 7260bef..2ae4fe8 100644
--- a/drivers/net/wireless/ath/wil6210/pm.c
+++ b/drivers/net/wireless/ath/wil6210/pm.c
@@ -71,6 +71,11 @@
wil_dbg_pm(wil, "suspend: %s\n", is_runtime ? "runtime" : "system");
+ if (test_bit(wil_status_suspended, wil->status)) {
+ wil_dbg_pm(wil, "trying to suspend while suspended\n");
+ return 0;
+ }
+
/* if netif up, hardware is alive, shut it down */
if (ndev->flags & IFF_UP) {
rc = wil_down(wil);
@@ -86,10 +91,14 @@
if (wil->platform_ops.suspend) {
rc = wil->platform_ops.suspend(wil->platform_handle);
- if (rc)
+ if (rc) {
wil_enable_irq(wil);
+ goto out;
+ }
}
+ set_bit(wil_status_suspended, wil->status);
+
out:
wil_dbg_pm(wil, "suspend: %s => %d\n",
is_runtime ? "runtime" : "system", rc);
@@ -117,10 +126,13 @@
/* if netif up, bring hardware up
* During open(), IFF_UP set after actual device method
- * invocation. This prevent recursive call to wil_up()
+ * invocation. This prevent recursive call to wil_up().
+ * wil_status_suspended will be cleared in wil_reset
*/
if (ndev->flags & IFF_UP)
rc = wil_up(wil);
+ else
+ clear_bit(wil_status_suspended, wil->status);
out:
wil_dbg_pm(wil, "resume: %s => %d\n",
diff --git a/drivers/net/wireless/ath/wil6210/wil6210.h b/drivers/net/wireless/ath/wil6210/wil6210.h
index 4bccef3..734449d 100644
--- a/drivers/net/wireless/ath/wil6210/wil6210.h
+++ b/drivers/net/wireless/ath/wil6210/wil6210.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
+ * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -41,6 +41,7 @@
#define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw" /* code Sparrow D0 */
#define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */
+#define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */
#define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */
/**
@@ -140,6 +141,7 @@
#define RGF_USER_USAGE_1 (0x880004)
#define RGF_USER_USAGE_6 (0x880018)
#define BIT_USER_OOB_MODE BIT(31)
+ #define BIT_USER_OOB_R2_MODE BIT(30)
#define RGF_USER_USAGE_8 (0x880020)
#define BIT_USER_PREVENT_DEEP_SLEEP BIT(0)
#define BIT_USER_SUPPORT_T_POWER_ON_0 BIT(1)
@@ -413,6 +415,7 @@
wil_status_irqen, /* FIXME: interrupts enabled - for debug */
wil_status_napi_en, /* NAPI enabled protected by wil->mutex */
wil_status_resetting, /* reset in progress */
+ wil_status_suspended, /* suspend completed, device is suspended */
wil_status_last /* keep last */
};
@@ -616,6 +619,8 @@
u16 channel; /* relevant in AP mode */
int sinfo_gen;
u32 ap_isolate; /* no intra-BSS communication */
+ struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */
+ int locally_generated_disc; /* relevant in STA mode */
/* interrupt moderation */
u32 tx_max_burst_duration;
u32 tx_interframe_timeout;
@@ -771,6 +776,12 @@
print_hex_dump_debug("DBG[ WMI]" prefix_str,\
prefix_type, rowsize, \
groupsize, buf, len, ascii)
+
+#define wil_hex_dump_misc(prefix_str, prefix_type, rowsize, \
+ groupsize, buf, len, ascii) \
+ print_hex_dump_debug("DBG[MISC]" prefix_str,\
+ prefix_type, rowsize, \
+ groupsize, buf, len, ascii)
#else /* defined(CONFIG_DYNAMIC_DEBUG) */
static inline
void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize,
@@ -783,18 +794,18 @@
int groupsize, const void *buf, size_t len, bool ascii)
{
}
+
+static inline
+void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize,
+ int groupsize, const void *buf, size_t len, bool ascii)
+{
+}
#endif /* defined(CONFIG_DYNAMIC_DEBUG) */
void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
size_t count);
void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
size_t count);
-void wil_memcpy_fromio_halp_vote(struct wil6210_priv *wil, void *dst,
- const volatile void __iomem *src,
- size_t count);
-void wil_memcpy_toio_halp_vote(struct wil6210_priv *wil,
- volatile void __iomem *dst,
- const void *src, size_t count);
void *wil_if_alloc(struct device *dev);
void wil_if_free(struct wil6210_priv *wil);
@@ -910,7 +921,7 @@
u8 type);
int wmi_abort_scan(struct wil6210_priv *wil);
void wil_abort_scan(struct wil6210_priv *wil, bool sync);
-
+void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps);
void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid,
u16 reason_code, bool from_event);
void wil_probe_client_flush(struct wil6210_priv *wil);
diff --git a/drivers/net/wireless/ath/wil6210/wmi.c b/drivers/net/wireless/ath/wil6210/wmi.c
index 0ede7f7..31d6ab9 100644
--- a/drivers/net/wireless/ath/wil6210/wmi.c
+++ b/drivers/net/wireless/ath/wil6210/wmi.c
@@ -566,6 +566,7 @@
(wdev->iftype == NL80211_IFTYPE_P2P_CLIENT)) {
if (rc) {
netif_carrier_off(ndev);
+ wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS);
wil_err(wil, "cfg80211_connect_result with failure\n");
cfg80211_connect_result(ndev, evt->bssid, NULL, 0,
NULL, 0,
@@ -573,12 +574,16 @@
GFP_KERNEL);
goto out;
} else {
- cfg80211_connect_result(ndev, evt->bssid,
- assoc_req_ie, assoc_req_ielen,
- assoc_resp_ie, assoc_resp_ielen,
- WLAN_STATUS_SUCCESS,
- GFP_KERNEL);
+ struct wiphy *wiphy = wil_to_wiphy(wil);
+
+ cfg80211_ref_bss(wiphy, wil->bss);
+ cfg80211_connect_bss(ndev, evt->bssid, wil->bss,
+ assoc_req_ie, assoc_req_ielen,
+ assoc_resp_ie, assoc_resp_ielen,
+ WLAN_STATUS_SUCCESS, GFP_KERNEL,
+ NL80211_TIMEOUT_UNSPECIFIED);
}
+ wil->bss = NULL;
} else if ((wdev->iftype == NL80211_IFTYPE_AP) ||
(wdev->iftype == NL80211_IFTYPE_P2P_GO)) {
if (rc) {
@@ -1524,6 +1529,7 @@
wil_dbg_wmi(wil, "disconnect_sta: (%pM, reason %d)\n", mac, reason);
+ wil->locally_generated_disc = true;
if (del_sta) {
ether_addr_copy(del_sta_cmd.dst_mac, mac);
rc = wmi_call(wil, WMI_DEL_STA_CMDID, &del_sta_cmd,
@@ -1765,14 +1771,19 @@
void wmi_event_flush(struct wil6210_priv *wil)
{
+ ulong flags;
struct pending_wmi_event *evt, *t;
wil_dbg_wmi(wil, "event_flush\n");
+ spin_lock_irqsave(&wil->wmi_ev_lock, flags);
+
list_for_each_entry_safe(evt, t, &wil->pending_wmi_ev, list) {
list_del(&evt->list);
kfree(evt);
}
+
+ spin_unlock_irqrestore(&wil->wmi_ev_lock, flags);
}
static bool wmi_evt_call_handler(struct wil6210_priv *wil, int id,
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 6555eb7..6ae8964 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -120,6 +120,20 @@
If unsure, say N.
+config PCI_MSM
+ bool "MSM PCIe Controller driver"
+ depends on ARCH_QCOM && PCI
+ select PCI_DOMAINS
+ select PCI_DOMAINS_GENERIC
+ select PCI_MSI
+ help
+ Enables the PCIe functionality by configuring PCIe core on
+ MSM chipset and by enabling the ARM PCI framework extension.
+ The PCIe core is essential for communication between the host
+ and an endpoint.
+
+ If unsure, say N.
+
config PCI_LABEL
def_bool y if (DMI || ACPI)
select NLS
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c
index 6523cb0..a0fa943 100644
--- a/drivers/pci/host/pci-msm.c
+++ b/drivers/pci/host/pci-msm.c
@@ -27,11 +27,11 @@
#include <linux/iommu.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
-#include <linux/regulator/rpm-smd-regulator.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/of_gpio.h>
-#include <linux/clk/msm-clk.h>
+#include <linux/clk/qcom.h>
#include <linux/reset.h>
#include <linux/msm-bus.h>
#include <linux/msm-bus-board.h>
@@ -48,170 +48,27 @@
#include <linux/ipc_logging.h>
#include <linux/msm_pcie.h>
-#ifdef CONFIG_ARCH_MDMCALIFORNIUM
#define PCIE_VENDOR_ID_RCP 0x17cb
-#define PCIE_DEVICE_ID_RCP 0x0302
-
-#define PCIE20_L1SUB_CONTROL1 0x158
-#define PCIE20_PARF_DBI_BASE_ADDR 0x350
-#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358
-
-#define TX_BASE 0x200
-#define RX_BASE 0x400
-#define PCS_BASE 0x800
-#define PCS_MISC_BASE 0x600
-
-#elif defined(CONFIG_ARCH_MSM8998)
-#define PCIE_VENDOR_ID_RCP 0x17cb
-#define PCIE_DEVICE_ID_RCP 0x0105
+#define PCIE_DEVICE_ID_RCP 0x0106
#define PCIE20_L1SUB_CONTROL1 0x1E4
#define PCIE20_PARF_DBI_BASE_ADDR 0x350
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358
-#define TX_BASE 0
-#define RX_BASE 0
#define PCS_BASE 0x800
-#define PCS_MISC_BASE 0
-#else
-#define PCIE_VENDOR_ID_RCP 0x17cb
-#define PCIE_DEVICE_ID_RCP 0x0104
-
-#define PCIE20_L1SUB_CONTROL1 0x158
-#define PCIE20_PARF_DBI_BASE_ADDR 0x168
-#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
-
-#define TX_BASE 0x1000
-#define RX_BASE 0x1200
-#define PCS_BASE 0x1400
-#define PCS_MISC_BASE 0
-#endif
-
-#define TX(n, m) (TX_BASE + n * m * 0x1000)
-#define RX(n, m) (RX_BASE + n * m * 0x1000)
#define PCS_PORT(n, m) (PCS_BASE + n * m * 0x1000)
-#define PCS_MISC_PORT(n, m) (PCS_MISC_BASE + n * m * 0x1000)
-
-#define QSERDES_COM_BG_TIMER 0x00C
-#define QSERDES_COM_SSC_EN_CENTER 0x010
-#define QSERDES_COM_SSC_ADJ_PER1 0x014
-#define QSERDES_COM_SSC_ADJ_PER2 0x018
-#define QSERDES_COM_SSC_PER1 0x01C
-#define QSERDES_COM_SSC_PER2 0x020
-#define QSERDES_COM_SSC_STEP_SIZE1 0x024
-#define QSERDES_COM_SSC_STEP_SIZE2 0x028
-#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
-#define QSERDES_COM_CLK_ENABLE1 0x038
-#define QSERDES_COM_SYS_CLK_CTRL 0x03C
-#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
-#define QSERDES_COM_PLL_IVCO 0x048
-#define QSERDES_COM_LOCK_CMP1_MODE0 0x04C
-#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
-#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
-#define QSERDES_COM_BG_TRIM 0x070
-#define QSERDES_COM_CLK_EP_DIV 0x074
-#define QSERDES_COM_CP_CTRL_MODE0 0x078
-#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
-#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
-#define QSERDES_COM_SYSCLK_EN_SEL 0x0AC
-#define QSERDES_COM_RESETSM_CNTRL 0x0B4
-#define QSERDES_COM_RESTRIM_CTRL 0x0BC
-#define QSERDES_COM_RESCODE_DIV_NUM 0x0C4
-#define QSERDES_COM_LOCK_CMP_EN 0x0C8
-#define QSERDES_COM_DEC_START_MODE0 0x0D0
-#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0DC
-#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0E0
-#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0E4
-#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
-#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10C
-#define QSERDES_COM_VCO_TUNE_CTRL 0x124
-#define QSERDES_COM_VCO_TUNE_MAP 0x128
-#define QSERDES_COM_VCO_TUNE1_MODE0 0x12C
-#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
-#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
-#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
-#define QSERDES_COM_BG_CTRL 0x170
-#define QSERDES_COM_CLK_SELECT 0x174
-#define QSERDES_COM_HSCLK_SEL 0x178
-#define QSERDES_COM_CORECLK_DIV 0x184
-#define QSERDES_COM_CORE_CLK_EN 0x18C
-#define QSERDES_COM_C_READY_STATUS 0x190
-#define QSERDES_COM_CMN_CONFIG 0x194
-#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19C
-#define QSERDES_COM_DEBUG_BUS0 0x1A0
-#define QSERDES_COM_DEBUG_BUS1 0x1A4
-#define QSERDES_COM_DEBUG_BUS2 0x1A8
-#define QSERDES_COM_DEBUG_BUS3 0x1AC
-#define QSERDES_COM_DEBUG_BUS_SEL 0x1B0
-
-#define QSERDES_TX_N_RES_CODE_LANE_OFFSET(n, m) (TX(n, m) + 0x4C)
-#define QSERDES_TX_N_DEBUG_BUS_SEL(n, m) (TX(n, m) + 0x64)
-#define QSERDES_TX_N_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN(n, m) (TX(n, m) + 0x68)
-#define QSERDES_TX_N_LANE_MODE(n, m) (TX(n, m) + 0x94)
-#define QSERDES_TX_N_RCV_DETECT_LVL_2(n, m) (TX(n, m) + 0xAC)
-
-#define QSERDES_RX_N_UCDR_SO_GAIN_HALF(n, m) (RX(n, m) + 0x010)
-#define QSERDES_RX_N_UCDR_SO_GAIN(n, m) (RX(n, m) + 0x01C)
-#define QSERDES_RX_N_UCDR_SO_SATURATION_AND_ENABLE(n, m) (RX(n, m) + 0x048)
-#define QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL2(n, m) (RX(n, m) + 0x0D8)
-#define QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL3(n, m) (RX(n, m) + 0x0DC)
-#define QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL4(n, m) (RX(n, m) + 0x0E0)
-#define QSERDES_RX_N_SIGDET_ENABLES(n, m) (RX(n, m) + 0x110)
-#define QSERDES_RX_N_SIGDET_DEGLITCH_CNTRL(n, m) (RX(n, m) + 0x11C)
-#define QSERDES_RX_N_SIGDET_LVL(n, m) (RX(n, m) + 0x118)
-#define QSERDES_RX_N_RX_BAND(n, m) (RX(n, m) + 0x120)
-
-#define PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x00)
-#define PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x04)
-#define PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x08)
-#define PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(n, m) (PCS_MISC_PORT(n, m) + 0x0C)
-#define PCIE_MISC_N_DEBUG_BUS_0_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x14)
-#define PCIE_MISC_N_DEBUG_BUS_1_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x18)
-#define PCIE_MISC_N_DEBUG_BUS_2_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x1C)
-#define PCIE_MISC_N_DEBUG_BUS_3_STATUS(n, m) (PCS_MISC_PORT(n, m) + 0x20)
#define PCIE_N_SW_RESET(n, m) (PCS_PORT(n, m) + 0x00)
#define PCIE_N_POWER_DOWN_CONTROL(n, m) (PCS_PORT(n, m) + 0x04)
-#define PCIE_N_START_CONTROL(n, m) (PCS_PORT(n, m) + 0x08)
-#define PCIE_N_TXDEEMPH_M6DB_V0(n, m) (PCS_PORT(n, m) + 0x24)
-#define PCIE_N_TXDEEMPH_M3P5DB_V0(n, m) (PCS_PORT(n, m) + 0x28)
-#define PCIE_N_ENDPOINT_REFCLK_DRIVE(n, m) (PCS_PORT(n, m) + 0x54)
-#define PCIE_N_RX_IDLE_DTCT_CNTRL(n, m) (PCS_PORT(n, m) + 0x58)
-#define PCIE_N_POWER_STATE_CONFIG1(n, m) (PCS_PORT(n, m) + 0x60)
-#define PCIE_N_POWER_STATE_CONFIG4(n, m) (PCS_PORT(n, m) + 0x6C)
-#define PCIE_N_PWRUP_RESET_DLY_TIME_AUXCLK(n, m) (PCS_PORT(n, m) + 0xA0)
-#define PCIE_N_LP_WAKEUP_DLY_TIME_AUXCLK(n, m) (PCS_PORT(n, m) + 0xA4)
-#define PCIE_N_PLL_LOCK_CHK_DLY_TIME(n, m) (PCS_PORT(n, m) + 0xA8)
-#define PCIE_N_TEST_CONTROL4(n, m) (PCS_PORT(n, m) + 0x11C)
-#define PCIE_N_TEST_CONTROL5(n, m) (PCS_PORT(n, m) + 0x120)
-#define PCIE_N_TEST_CONTROL6(n, m) (PCS_PORT(n, m) + 0x124)
-#define PCIE_N_TEST_CONTROL7(n, m) (PCS_PORT(n, m) + 0x128)
#define PCIE_N_PCS_STATUS(n, m) (PCS_PORT(n, m) + 0x174)
-#define PCIE_N_DEBUG_BUS_0_STATUS(n, m) (PCS_PORT(n, m) + 0x198)
-#define PCIE_N_DEBUG_BUS_1_STATUS(n, m) (PCS_PORT(n, m) + 0x19C)
-#define PCIE_N_DEBUG_BUS_2_STATUS(n, m) (PCS_PORT(n, m) + 0x1A0)
-#define PCIE_N_DEBUG_BUS_3_STATUS(n, m) (PCS_PORT(n, m) + 0x1A4)
-#define PCIE_N_LP_WAKEUP_DLY_TIME_AUXCLK_MSB(n, m) (PCS_PORT(n, m) + 0x1A8)
-#define PCIE_N_OSC_DTCT_ACTIONS(n, m) (PCS_PORT(n, m) + 0x1AC)
-#define PCIE_N_SIGDET_CNTRL(n, m) (PCS_PORT(n, m) + 0x1B0)
-#define PCIE_N_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB(n, m) (PCS_PORT(n, m) + 0x1DC)
-#define PCIE_N_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB(n, m) (PCS_PORT(n, m) + 0x1E0)
#define PCIE_COM_SW_RESET 0x400
#define PCIE_COM_POWER_DOWN_CONTROL 0x404
-#define PCIE_COM_START_CONTROL 0x408
-#define PCIE_COM_DEBUG_BUS_BYTE0_INDEX 0x438
-#define PCIE_COM_DEBUG_BUS_BYTE1_INDEX 0x43C
-#define PCIE_COM_DEBUG_BUS_BYTE2_INDEX 0x440
-#define PCIE_COM_DEBUG_BUS_BYTE3_INDEX 0x444
#define PCIE_COM_PCS_READY_STATUS 0x448
-#define PCIE_COM_DEBUG_BUS_0_STATUS 0x45C
-#define PCIE_COM_DEBUG_BUS_1_STATUS 0x460
-#define PCIE_COM_DEBUG_BUS_2_STATUS 0x464
-#define PCIE_COM_DEBUG_BUS_3_STATUS 0x468
#define PCIE20_PARF_SYS_CTRL 0x00
+#define PCIE20_PARF_PM_CTRL 0x20
#define PCIE20_PARF_PM_STTS 0x24
#define PCIE20_PARF_PCS_DEEMPH 0x34
#define PCIE20_PARF_PCS_SWING 0x38
@@ -228,6 +85,7 @@
#define PCIE20_PARF_SID_OFFSET 0x234
#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
#define PCIE20_PARF_BDF_TRANSLATE_N 0x250
+#define PCIE20_PARF_DEVICE_TYPE 0x1000
#define PCIE20_ELBI_VERSION 0x00
#define PCIE20_ELBI_SYS_CTRL 0x04
@@ -300,7 +158,7 @@
#define MAX_PROP_SIZE 32
#define MAX_RC_NAME_LEN 15
#define MSM_PCIE_MAX_VREG 4
-#define MSM_PCIE_MAX_CLK 9
+#define MSM_PCIE_MAX_CLK 12
#define MSM_PCIE_MAX_PIPE_CLK 1
#define MAX_RC_NUM 3
#define MAX_DEVICE_NUM 20
@@ -314,7 +172,7 @@
#define PCIE_CLEAR 0xDEADBEEF
#define PCIE_LINK_DOWN 0xFFFFFFFF
-#define MSM_PCIE_MAX_RESET 4
+#define MSM_PCIE_MAX_RESET 5
#define MSM_PCIE_MAX_PIPE_RESET 1
#define MSM_PCIE_MSI_PHY 0xa0000000
@@ -629,7 +487,6 @@
uint32_t wr_halt_size;
uint32_t cpl_timeout;
uint32_t current_bdf;
- short current_short_bdf;
uint32_t perst_delay_us_min;
uint32_t perst_delay_us_max;
uint32_t tlp_rd_size;
@@ -734,18 +591,21 @@
static struct msm_pcie_reset_info_t
msm_pcie_reset_info[MAX_RC_NUM][MSM_PCIE_MAX_RESET] = {
{
+ {NULL, "pcie_0_core_reset", false},
{NULL, "pcie_phy_reset", false},
{NULL, "pcie_phy_com_reset", false},
{NULL, "pcie_phy_nocsr_com_phy_reset", false},
{NULL, "pcie_0_phy_reset", false}
},
{
+ {NULL, "pcie_1_core_reset", false},
{NULL, "pcie_phy_reset", false},
{NULL, "pcie_phy_com_reset", false},
{NULL, "pcie_phy_nocsr_com_phy_reset", false},
{NULL, "pcie_1_phy_reset", false}
},
{
+ {NULL, "pcie_2_core_reset", false},
{NULL, "pcie_phy_reset", false},
{NULL, "pcie_phy_com_reset", false},
{NULL, "pcie_phy_nocsr_com_phy_reset", false},
@@ -778,6 +638,9 @@
{NULL, "pcie_0_slv_axi_clk", 0, true, true},
{NULL, "pcie_0_ldo", 0, false, true},
{NULL, "pcie_0_smmu_clk", 0, false, false},
+ {NULL, "pcie_0_slv_q2a_axi_clk", 0, false, false},
+ {NULL, "pcie_phy_refgen_clk", 0, false, false},
+ {NULL, "pcie_tbu_clk", 0, false, false},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false}
},
@@ -789,6 +652,9 @@
{NULL, "pcie_1_slv_axi_clk", 0, true, true},
{NULL, "pcie_1_ldo", 0, false, true},
{NULL, "pcie_1_smmu_clk", 0, false, false},
+ {NULL, "pcie_1_slv_q2a_axi_clk", 0, false, false},
+ {NULL, "pcie_phy_refgen_clk", 0, false, false},
+ {NULL, "pcie_tbu_clk", 0, false, false},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false}
},
@@ -800,6 +666,9 @@
{NULL, "pcie_2_slv_axi_clk", 0, true, true},
{NULL, "pcie_2_ldo", 0, false, true},
{NULL, "pcie_2_smmu_clk", 0, false, false},
+ {NULL, "pcie_2_slv_q2a_axi_clk", 0, false, false},
+ {NULL, "pcie_phy_refgen_clk", 0, false, false},
+ {NULL, "pcie_tbu_clk", 0, false, false},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false}
}
@@ -860,6 +729,8 @@
{"msi_28", 0}, {"msi_29", 0}, {"msi_30", 0}, {"msi_31", 0}
};
+static int msm_pcie_config_device(struct pci_dev *dev, void *pdev);
+
#ifdef CONFIG_ARM
#define PCIE_BUS_PRIV_DATA(bus) \
(((struct pci_sys_data *)bus->sysdata)->private_data)
@@ -938,393 +809,9 @@
dev->rc_idx, info->name);
}
-#if defined(CONFIG_ARCH_FSM9010)
-#define PCIE20_PARF_PHY_STTS 0x3c
-#define PCIE2_PHY_RESET_CTRL 0x44
-#define PCIE20_PARF_PHY_REFCLK_CTRL2 0xa0
-#define PCIE20_PARF_PHY_REFCLK_CTRL3 0xa4
-#define PCIE20_PARF_PCS_SWING_CTRL1 0x88
-#define PCIE20_PARF_PCS_SWING_CTRL2 0x8c
-#define PCIE20_PARF_PCS_DEEMPH1 0x74
-#define PCIE20_PARF_PCS_DEEMPH2 0x78
-#define PCIE20_PARF_PCS_DEEMPH3 0x7c
-#define PCIE20_PARF_CONFIGBITS 0x84
-#define PCIE20_PARF_PHY_CTRL3 0x94
-#define PCIE20_PARF_PCS_CTRL 0x80
-
-#define TX_AMP_VAL 127
-#define PHY_RX0_EQ_GEN1_VAL 0
-#define PHY_RX0_EQ_GEN2_VAL 4
-#define TX_DEEMPH_GEN1_VAL 24
-#define TX_DEEMPH_GEN2_3_5DB_VAL 24
-#define TX_DEEMPH_GEN2_6DB_VAL 34
-#define PHY_TX0_TERM_OFFST_VAL 0
-
-static inline void pcie_phy_dump(struct msm_pcie_dev_t *dev)
-{
-}
-
-static inline void pcie20_phy_reset(struct msm_pcie_dev_t *dev, uint32_t assert)
-{
- msm_pcie_write_reg_field(dev->phy, PCIE2_PHY_RESET_CTRL,
- BIT(0), (assert) ? 1 : 0);
-}
-
-static void pcie_phy_init(struct msm_pcie_dev_t *dev)
-{
- PCIE_DBG(dev, "RC%d: Initializing 28LP SNS phy - 100MHz\n",
- dev->rc_idx);
-
- /* De-assert Phy SW Reset */
- pcie20_phy_reset(dev, 1);
-
- /* Program SSP ENABLE */
- if (readl_relaxed(dev->phy + PCIE20_PARF_PHY_REFCLK_CTRL2) & BIT(0))
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PHY_REFCLK_CTRL2,
- BIT(0), 0);
- if ((readl_relaxed(dev->phy + PCIE20_PARF_PHY_REFCLK_CTRL3) &
- BIT(0)) == 0)
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PHY_REFCLK_CTRL3,
- BIT(0), 1);
- /* Program Tx Amplitude */
- if ((readl_relaxed(dev->phy + PCIE20_PARF_PCS_SWING_CTRL1) &
- (BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) !=
- TX_AMP_VAL)
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_SWING_CTRL1,
- BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0),
- TX_AMP_VAL);
- if ((readl_relaxed(dev->phy + PCIE20_PARF_PCS_SWING_CTRL2) &
- (BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) !=
- TX_AMP_VAL)
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_SWING_CTRL2,
- BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0),
- TX_AMP_VAL);
- /* Program De-Emphasis */
- if ((readl_relaxed(dev->phy + PCIE20_PARF_PCS_DEEMPH1) &
- (BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) !=
- TX_DEEMPH_GEN2_6DB_VAL)
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_DEEMPH1,
- BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0),
- TX_DEEMPH_GEN2_6DB_VAL);
-
- if ((readl_relaxed(dev->phy + PCIE20_PARF_PCS_DEEMPH2) &
- (BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) !=
- TX_DEEMPH_GEN2_3_5DB_VAL)
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_DEEMPH2,
- BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0),
- TX_DEEMPH_GEN2_3_5DB_VAL);
-
- if ((readl_relaxed(dev->phy + PCIE20_PARF_PCS_DEEMPH3) &
- (BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) !=
- TX_DEEMPH_GEN1_VAL)
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_DEEMPH3,
- BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0),
- TX_DEEMPH_GEN1_VAL);
-
- /* Program Rx_Eq */
- if ((readl_relaxed(dev->phy + PCIE20_PARF_CONFIGBITS) &
- (BIT(2)|BIT(1)|BIT(0))) != PHY_RX0_EQ_GEN1_VAL)
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_CONFIGBITS,
- BIT(2)|BIT(1)|BIT(0), PHY_RX0_EQ_GEN1_VAL);
-
- /* Program Tx0_term_offset */
- if ((readl_relaxed(dev->phy + PCIE20_PARF_PHY_CTRL3) &
- (BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0))) !=
- PHY_TX0_TERM_OFFST_VAL)
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PHY_CTRL3,
- BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0),
- PHY_TX0_TERM_OFFST_VAL);
-
- /* Program REF_CLK source */
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PHY_REFCLK_CTRL2, BIT(1),
- (dev->ext_ref_clk) ? 1 : 0);
- /* disable Tx2Rx Loopback */
- if (readl_relaxed(dev->phy + PCIE20_PARF_PCS_CTRL) & BIT(1))
- msm_pcie_write_reg_field(dev->phy, PCIE20_PARF_PCS_CTRL,
- BIT(1), 0);
- /* De-assert Phy SW Reset */
- pcie20_phy_reset(dev, 0);
-}
-
-static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev)
-{
-
- /* read PCIE20_PARF_PHY_STTS twice */
- readl_relaxed(dev->phy + PCIE20_PARF_PHY_STTS);
- if (readl_relaxed(dev->phy + PCIE20_PARF_PHY_STTS) & BIT(0))
- return false;
- else
- return true;
-}
-#else
-static void pcie_phy_dump_test_cntrl(struct msm_pcie_dev_t *dev,
- u32 cntrl4_val, u32 cntrl5_val,
- u32 cntrl6_val, u32 cntrl7_val)
-{
- msm_pcie_write_reg(dev->phy,
- PCIE_N_TEST_CONTROL4(dev->rc_idx, dev->common_phy), cntrl4_val);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_TEST_CONTROL5(dev->rc_idx, dev->common_phy), cntrl5_val);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_TEST_CONTROL6(dev->rc_idx, dev->common_phy), cntrl6_val);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_TEST_CONTROL7(dev->rc_idx, dev->common_phy), cntrl7_val);
-
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_N_TEST_CONTROL4: 0x%x\n", dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_N_TEST_CONTROL4(dev->rc_idx,
- dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_N_TEST_CONTROL5: 0x%x\n", dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_N_TEST_CONTROL5(dev->rc_idx,
- dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_N_TEST_CONTROL6: 0x%x\n", dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_N_TEST_CONTROL6(dev->rc_idx,
- dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_N_TEST_CONTROL7: 0x%x\n", dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_N_TEST_CONTROL7(dev->rc_idx,
- dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_N_DEBUG_BUS_0_STATUS: 0x%x\n", dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_N_DEBUG_BUS_0_STATUS(dev->rc_idx,
- dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_N_DEBUG_BUS_1_STATUS: 0x%x\n", dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_N_DEBUG_BUS_1_STATUS(dev->rc_idx,
- dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_N_DEBUG_BUS_2_STATUS: 0x%x\n", dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_N_DEBUG_BUS_2_STATUS(dev->rc_idx,
- dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_N_DEBUG_BUS_3_STATUS: 0x%x\n\n", dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_N_DEBUG_BUS_3_STATUS(dev->rc_idx,
- dev->common_phy)));
-}
-
static void pcie_phy_dump(struct msm_pcie_dev_t *dev)
{
int i, size;
- u32 write_val;
-
- if (dev->phy_ver >= 0x20) {
- PCIE_DUMP(dev, "PCIe: RC%d PHY dump is not supported\n",
- dev->rc_idx);
- return;
- }
-
- PCIE_DUMP(dev, "PCIe: RC%d PHY testbus\n", dev->rc_idx);
-
- pcie_phy_dump_test_cntrl(dev, 0x18, 0x19, 0x1A, 0x1B);
- pcie_phy_dump_test_cntrl(dev, 0x1C, 0x1D, 0x1E, 0x1F);
- pcie_phy_dump_test_cntrl(dev, 0x20, 0x21, 0x22, 0x23);
-
- for (i = 0; i < 3; i++) {
- write_val = 0x1 + i;
- msm_pcie_write_reg(dev->phy,
- QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx,
- dev->common_phy), write_val);
- PCIE_DUMP(dev,
- "PCIe: RC%d QSERDES_TX_N_DEBUG_BUS_SEL: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx,
- dev->common_phy)));
-
- pcie_phy_dump_test_cntrl(dev, 0x30, 0x31, 0x32, 0x33);
- }
-
- pcie_phy_dump_test_cntrl(dev, 0, 0, 0, 0);
-
- if (dev->phy_ver >= 0x10 && dev->phy_ver < 0x20) {
- pcie_phy_dump_test_cntrl(dev, 0x01, 0x02, 0x03, 0x0A);
- pcie_phy_dump_test_cntrl(dev, 0x0E, 0x0F, 0x12, 0x13);
- pcie_phy_dump_test_cntrl(dev, 0, 0, 0, 0);
-
- for (i = 0; i < 8; i += 4) {
- write_val = 0x1 + i;
- msm_pcie_write_reg(dev->phy,
- PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(dev->rc_idx,
- dev->common_phy), write_val);
- msm_pcie_write_reg(dev->phy,
- PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(dev->rc_idx,
- dev->common_phy), write_val + 1);
- msm_pcie_write_reg(dev->phy,
- PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(dev->rc_idx,
- dev->common_phy), write_val + 2);
- msm_pcie_write_reg(dev->phy,
- PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(dev->rc_idx,
- dev->common_phy), write_val + 3);
-
- PCIE_DUMP(dev,
- "PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(
- dev->rc_idx, dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(
- dev->rc_idx, dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(
- dev->rc_idx, dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d to PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(
- dev->rc_idx, dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_0_STATUS: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_MISC_N_DEBUG_BUS_0_STATUS(
- dev->rc_idx, dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_1_STATUS: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_MISC_N_DEBUG_BUS_1_STATUS(
- dev->rc_idx, dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_2_STATUS: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_MISC_N_DEBUG_BUS_2_STATUS(
- dev->rc_idx, dev->common_phy)));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_MISC_N_DEBUG_BUS_3_STATUS: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_MISC_N_DEBUG_BUS_3_STATUS(
- dev->rc_idx, dev->common_phy)));
- }
-
- msm_pcie_write_reg(dev->phy,
- PCIE_MISC_N_DEBUG_BUS_BYTE0_INDEX(
- dev->rc_idx, dev->common_phy), 0);
- msm_pcie_write_reg(dev->phy,
- PCIE_MISC_N_DEBUG_BUS_BYTE1_INDEX(
- dev->rc_idx, dev->common_phy), 0);
- msm_pcie_write_reg(dev->phy,
- PCIE_MISC_N_DEBUG_BUS_BYTE2_INDEX(
- dev->rc_idx, dev->common_phy), 0);
- msm_pcie_write_reg(dev->phy,
- PCIE_MISC_N_DEBUG_BUS_BYTE3_INDEX(
- dev->rc_idx, dev->common_phy), 0);
- }
-
- for (i = 0; i < 2; i++) {
- write_val = 0x2 + i;
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_DEBUG_BUS_SEL,
- write_val);
-
- PCIE_DUMP(dev,
- "PCIe: RC%d to QSERDES_COM_DEBUG_BUS_SEL: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS_SEL));
- PCIE_DUMP(dev,
- "PCIe: RC%d QSERDES_COM_DEBUG_BUS0: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS0));
- PCIE_DUMP(dev,
- "PCIe: RC%d QSERDES_COM_DEBUG_BUS1: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS1));
- PCIE_DUMP(dev,
- "PCIe: RC%d QSERDES_COM_DEBUG_BUS2: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS2));
- PCIE_DUMP(dev,
- "PCIe: RC%d QSERDES_COM_DEBUG_BUS3: 0x%x\n\n",
- dev->rc_idx,
- readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS3));
- }
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_DEBUG_BUS_SEL, 0);
-
- if (dev->common_phy) {
- msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE0_INDEX,
- 0x01);
- msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE1_INDEX,
- 0x02);
- msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE2_INDEX,
- 0x03);
- msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE3_INDEX,
- 0x04);
-
- PCIE_DUMP(dev,
- "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE0_INDEX: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_COM_DEBUG_BUS_BYTE0_INDEX));
- PCIE_DUMP(dev,
- "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE1_INDEX: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_COM_DEBUG_BUS_BYTE1_INDEX));
- PCIE_DUMP(dev,
- "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE2_INDEX: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_COM_DEBUG_BUS_BYTE2_INDEX));
- PCIE_DUMP(dev,
- "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE3_INDEX: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_COM_DEBUG_BUS_BYTE3_INDEX));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_COM_DEBUG_BUS_0_STATUS: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_COM_DEBUG_BUS_0_STATUS));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_COM_DEBUG_BUS_1_STATUS: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_COM_DEBUG_BUS_1_STATUS));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_COM_DEBUG_BUS_2_STATUS: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_COM_DEBUG_BUS_2_STATUS));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_COM_DEBUG_BUS_3_STATUS: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_COM_DEBUG_BUS_3_STATUS));
-
- msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE0_INDEX,
- 0x05);
-
- PCIE_DUMP(dev,
- "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE0_INDEX: 0x%x\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_COM_DEBUG_BUS_BYTE0_INDEX));
- PCIE_DUMP(dev,
- "PCIe: RC%d PCIE_COM_DEBUG_BUS_0_STATUS: 0x%x\n\n",
- dev->rc_idx,
- readl_relaxed(dev->phy +
- PCIE_COM_DEBUG_BUS_0_STATUS));
- }
size = resource_size(dev->res[MSM_PCIE_RES_PHY].resource);
for (i = 0; i < size; i += 32) {
@@ -1342,181 +829,6 @@
}
}
-#ifdef CONFIG_ARCH_MDMCALIFORNIUM
-static void pcie_phy_init(struct msm_pcie_dev_t *dev)
-{
- u8 common_phy;
-
- PCIE_DBG(dev,
- "RC%d: Initializing MDM 14nm QMP phy - 19.2MHz with Common Mode Clock (SSC ON)\n",
- dev->rc_idx);
-
- if (dev->common_phy)
- common_phy = 1;
- else
- common_phy = 0;
-
- msm_pcie_write_reg(dev->phy,
- PCIE_N_SW_RESET(dev->rc_idx, common_phy),
- 0x01);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, common_phy),
- 0x03);
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_ENABLE1, 0x10);
-
- msm_pcie_write_reg(dev->phy,
- QSERDES_TX_N_LANE_MODE(dev->rc_idx, common_phy), 0x06);
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP_EN, 0x01);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_MAP, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER1, 0xFF);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER2, 0x1F);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_TRIM, 0x0F);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_IVCO, 0x0F);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_HSCLK_SEL, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SVS_MODE_CLK_SEL, 0x01);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CORE_CLK_EN, 0x20);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CORECLK_DIV, 0x0A);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_TIMER, 0x09);
-
- if (dev->tcsr) {
- PCIE_DBG(dev, "RC%d: TCSR PHY clock scheme is 0x%x\n",
- dev->rc_idx, readl_relaxed(dev->tcsr));
-
- if (readl_relaxed(dev->tcsr) & (BIT(1) | BIT(0)))
- msm_pcie_write_reg(dev->phy,
- QSERDES_COM_SYSCLK_EN_SEL, 0x0A);
- else
- msm_pcie_write_reg(dev->phy,
- QSERDES_COM_SYSCLK_EN_SEL, 0x04);
- }
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_DEC_START_MODE0, 0x82);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP3_MODE0, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP2_MODE0, 0x0D);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP1_MODE0, 0x04);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_SELECT, 0x33);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SYS_CLK_CTRL, 0x02);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1F);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CP_CTRL_MODE0, 0x0B);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_RCTRL_MODE0, 0x16);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CCTRL_MODE0, 0x28);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80);
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_EN_CENTER, 0x01);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_PER1, 0x31);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_PER2, 0x01);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_ADJ_PER1, 0x02);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_ADJ_PER2, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_STEP_SIZE1, 0x2f);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_STEP_SIZE2, 0x19);
-
- msm_pcie_write_reg(dev->phy,
- QSERDES_TX_N_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN(dev->rc_idx,
- common_phy), 0x45);
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CMN_CONFIG, 0x06);
-
- msm_pcie_write_reg(dev->phy,
- QSERDES_TX_N_RES_CODE_LANE_OFFSET(dev->rc_idx, common_phy),
- 0x02);
- msm_pcie_write_reg(dev->phy,
- QSERDES_TX_N_RCV_DETECT_LVL_2(dev->rc_idx, common_phy),
- 0x12);
-
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_SIGDET_ENABLES(dev->rc_idx, common_phy),
- 0x1C);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_SIGDET_DEGLITCH_CNTRL(dev->rc_idx, common_phy),
- 0x14);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL2(dev->rc_idx, common_phy),
- 0x01);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL3(dev->rc_idx, common_phy),
- 0x00);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL4(dev->rc_idx, common_phy),
- 0xDB);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_UCDR_SO_SATURATION_AND_ENABLE(dev->rc_idx,
- common_phy),
- 0x4B);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_UCDR_SO_GAIN(dev->rc_idx, common_phy),
- 0x04);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_UCDR_SO_GAIN_HALF(dev->rc_idx, common_phy),
- 0x04);
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_EP_DIV, 0x19);
-
- msm_pcie_write_reg(dev->phy,
- PCIE_N_ENDPOINT_REFCLK_DRIVE(dev->rc_idx, common_phy),
- 0x04);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_OSC_DTCT_ACTIONS(dev->rc_idx, common_phy),
- 0x00);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_PWRUP_RESET_DLY_TIME_AUXCLK(dev->rc_idx, common_phy),
- 0x40);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB(dev->rc_idx, common_phy),
- 0x00);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB(dev->rc_idx, common_phy),
- 0x40);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_LP_WAKEUP_DLY_TIME_AUXCLK_MSB(dev->rc_idx, common_phy),
- 0x00);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_LP_WAKEUP_DLY_TIME_AUXCLK(dev->rc_idx, common_phy),
- 0x40);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_PLL_LOCK_CHK_DLY_TIME(dev->rc_idx, common_phy),
- 0x73);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_SIGDET_LVL(dev->rc_idx, common_phy),
- 0x99);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_TXDEEMPH_M6DB_V0(dev->rc_idx, common_phy),
- 0x15);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_TXDEEMPH_M3P5DB_V0(dev->rc_idx, common_phy),
- 0x0E);
-
- msm_pcie_write_reg(dev->phy,
- PCIE_N_SIGDET_CNTRL(dev->rc_idx, common_phy),
- 0x07);
-
- msm_pcie_write_reg(dev->phy,
- PCIE_N_SW_RESET(dev->rc_idx, common_phy),
- 0x00);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_START_CONTROL(dev->rc_idx, common_phy),
- 0x03);
-}
-
-static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev)
-{
-}
-
-static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev)
-{
- if (readl_relaxed(dev->phy +
- PCIE_N_PCS_STATUS(dev->rc_idx, dev->common_phy)) & BIT(6))
- return false;
- else
- return true;
-}
-#else
static void pcie_phy_init(struct msm_pcie_dev_t *dev)
{
int i;
@@ -1538,64 +850,6 @@
phy_seq->delay + 1);
phy_seq++;
}
- return;
- }
-
- if (dev->common_phy)
- msm_pcie_write_reg(dev->phy, PCIE_COM_POWER_DOWN_CONTROL, 0x01);
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1C);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_ENABLE1, 0x10);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_SELECT, 0x33);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CMN_CONFIG, 0x06);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP_EN, 0x42);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_MAP, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER1, 0xFF);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER2, 0x1F);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_HSCLK_SEL, 0x01);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SVS_MODE_CLK_SEL, 0x01);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CORE_CLK_EN, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CORECLK_DIV, 0x0A);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_TIMER, 0x09);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_DEC_START_MODE0, 0x82);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP3_MODE0, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP2_MODE0, 0x1A);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP1_MODE0, 0x0A);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_SELECT, 0x33);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SYS_CLK_CTRL, 0x02);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1F);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_EN_SEL, 0x04);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CP_CTRL_MODE0, 0x0B);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_RCTRL_MODE0, 0x16);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CCTRL_MODE0, 0x28);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_EN_CENTER, 0x01);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_PER1, 0x31);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_PER2, 0x01);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_ADJ_PER1, 0x02);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_ADJ_PER2, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_STEP_SIZE1, 0x2f);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_STEP_SIZE2, 0x19);
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_RESCODE_DIV_NUM, 0x15);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_TRIM, 0x0F);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_IVCO, 0x0F);
-
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_EP_DIV, 0x19);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_ENABLE1, 0x10);
-
- if (dev->phy_ver == 0x3) {
- msm_pcie_write_reg(dev->phy, QSERDES_COM_HSCLK_SEL, 0x00);
- msm_pcie_write_reg(dev->phy, QSERDES_COM_RESCODE_DIV_NUM, 0x40);
- }
-
- if (dev->common_phy) {
- msm_pcie_write_reg(dev->phy, PCIE_COM_SW_RESET, 0x00);
- msm_pcie_write_reg(dev->phy, PCIE_COM_START_CONTROL, 0x03);
}
}
@@ -1603,18 +857,9 @@
{
int i;
struct msm_pcie_phy_info_t *phy_seq;
- u8 common_phy;
-
- if (dev->phy_ver >= 0x20)
- return;
PCIE_DBG(dev, "RC%d: Initializing PCIe PHY Port\n", dev->rc_idx);
- if (dev->common_phy)
- common_phy = 1;
- else
- common_phy = 0;
-
if (dev->port_phy_sequence) {
i = dev->port_phy_len;
phy_seq = dev->port_phy_sequence;
@@ -1627,93 +872,8 @@
phy_seq->delay + 1);
phy_seq++;
}
- return;
}
- msm_pcie_write_reg(dev->phy,
- QSERDES_TX_N_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN(dev->rc_idx,
- common_phy), 0x45);
- msm_pcie_write_reg(dev->phy,
- QSERDES_TX_N_LANE_MODE(dev->rc_idx, common_phy),
- 0x06);
-
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_SIGDET_ENABLES(dev->rc_idx, common_phy),
- 0x1C);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_SIGDET_LVL(dev->rc_idx, common_phy),
- 0x17);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL2(dev->rc_idx, common_phy),
- 0x01);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL3(dev->rc_idx, common_phy),
- 0x00);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL4(dev->rc_idx, common_phy),
- 0xDB);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_RX_BAND(dev->rc_idx, common_phy),
- 0x18);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_UCDR_SO_GAIN(dev->rc_idx, common_phy),
- 0x04);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_UCDR_SO_GAIN_HALF(dev->rc_idx, common_phy),
- 0x04);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_RX_IDLE_DTCT_CNTRL(dev->rc_idx, common_phy),
- 0x4C);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_PWRUP_RESET_DLY_TIME_AUXCLK(dev->rc_idx, common_phy),
- 0x00);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_LP_WAKEUP_DLY_TIME_AUXCLK(dev->rc_idx, common_phy),
- 0x01);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_PLL_LOCK_CHK_DLY_TIME(dev->rc_idx, common_phy),
- 0x05);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_UCDR_SO_SATURATION_AND_ENABLE(dev->rc_idx,
- common_phy), 0x4B);
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_SIGDET_DEGLITCH_CNTRL(dev->rc_idx, common_phy),
- 0x14);
-
- msm_pcie_write_reg(dev->phy,
- PCIE_N_ENDPOINT_REFCLK_DRIVE(dev->rc_idx, common_phy),
- 0x05);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, common_phy),
- 0x02);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_POWER_STATE_CONFIG4(dev->rc_idx, common_phy),
- 0x00);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_POWER_STATE_CONFIG1(dev->rc_idx, common_phy),
- 0xA3);
-
- if (dev->phy_ver == 0x3) {
- msm_pcie_write_reg(dev->phy,
- QSERDES_RX_N_SIGDET_LVL(dev->rc_idx, common_phy),
- 0x19);
-
- msm_pcie_write_reg(dev->phy,
- PCIE_N_TXDEEMPH_M3P5DB_V0(dev->rc_idx, common_phy),
- 0x0E);
- }
-
- msm_pcie_write_reg(dev->phy,
- PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, common_phy),
- 0x03);
- usleep_range(POWER_DOWN_DELAY_US_MIN, POWER_DOWN_DELAY_US_MAX);
-
- msm_pcie_write_reg(dev->phy,
- PCIE_N_SW_RESET(dev->rc_idx, common_phy),
- 0x00);
- msm_pcie_write_reg(dev->phy,
- PCIE_N_START_CONTROL(dev->rc_idx, common_phy),
- 0x0A);
}
static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev)
@@ -1732,8 +892,6 @@
else
return true;
}
-#endif
-#endif
static int msm_pcie_restore_sec_config(struct msm_pcie_dev_t *dev)
{
@@ -1975,8 +1133,6 @@
dev->msi_gicm_base);
PCIE_DBG_FS(dev, "bus_client: %d\n",
dev->bus_client);
- PCIE_DBG_FS(dev, "current short bdf: %d\n",
- dev->current_short_bdf);
PCIE_DBG_FS(dev, "smmu does %s exist\n",
dev->smmu_exist ? "" : "not");
PCIE_DBG_FS(dev, "smmu_sid_base: 0x%x\n",
@@ -3512,8 +2668,8 @@
dev->rc_idx,
dev->vreg[i].name);
regulator_set_voltage(hdl,
- RPM_REGULATOR_CORNER_NONE,
- INT_MAX);
+ RPMH_REGULATOR_LEVEL_OFF,
+ RPMH_REGULATOR_LEVEL_MAX);
}
}
@@ -3542,8 +2698,8 @@
dev->rc_idx,
dev->vreg[i].name);
regulator_set_voltage(dev->vreg[i].hdl,
- RPM_REGULATOR_CORNER_NONE,
- INT_MAX);
+ RPMH_REGULATOR_LEVEL_OFF,
+ RPMH_REGULATOR_LEVEL_MAX);
}
}
}
@@ -3645,6 +2801,19 @@
for (i = 0; i < MSM_PCIE_MAX_RESET; i++) {
reset_info = &dev->reset[i];
if (reset_info->hdl) {
+ rc = reset_control_assert(reset_info->hdl);
+ if (rc)
+ PCIE_ERR(dev,
+ "PCIe: RC%d failed to assert reset for %s.\n",
+ dev->rc_idx, reset_info->name);
+ else
+ PCIE_DBG2(dev,
+ "PCIe: RC%d successfully asserted reset for %s.\n",
+ dev->rc_idx, reset_info->name);
+
+ /* add a 1ms delay to ensure the reset is asserted */
+ usleep_range(1000, 1005);
+
rc = reset_control_deassert(reset_info->hdl);
if (rc)
PCIE_ERR(dev,
@@ -3749,6 +2918,19 @@
for (i = 0; i < MSM_PCIE_MAX_PIPE_RESET; i++) {
pipe_reset_info = &dev->pipe_reset[i];
if (pipe_reset_info->hdl) {
+ rc = reset_control_assert(pipe_reset_info->hdl);
+ if (rc)
+ PCIE_ERR(dev,
+ "PCIe: RC%d failed to assert pipe reset for %s.\n",
+ dev->rc_idx, pipe_reset_info->name);
+ else
+ PCIE_DBG2(dev,
+ "PCIe: RC%d successfully asserted pipe reset for %s.\n",
+ dev->rc_idx, pipe_reset_info->name);
+
+ /* add a 1ms delay to ensure the reset is asserted */
+ usleep_range(1000, 1005);
+
rc = reset_control_deassert(
pipe_reset_info->hdl);
if (rc)
@@ -3802,8 +2984,6 @@
static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev)
{
- int i;
-
PCIE_DBG(dev, "RC%d\n", dev->rc_idx);
/*
@@ -3859,27 +3039,6 @@
PCIE_DBG(dev, "RC's PCIE20_CAP_DEVCTRLSTATUS:0x%x\n",
readl_relaxed(dev->dm_core + PCIE20_CAP_DEVCTRLSTATUS));
}
-
- /* configure SMMU registers */
- if (dev->smmu_exist) {
- msm_pcie_write_reg(dev->parf,
- PCIE20_PARF_BDF_TRANSLATE_CFG, 0);
- msm_pcie_write_reg(dev->parf,
- PCIE20_PARF_SID_OFFSET, 0);
-
- if (dev->enumerated) {
- for (i = 0; i < MAX_DEVICE_NUM; i++) {
- if (dev->pcidev_table[i].dev &&
- dev->pcidev_table[i].short_bdf) {
- msm_pcie_write_reg(dev->parf,
- PCIE20_PARF_BDF_TRANSLATE_N +
- dev->pcidev_table[i].short_bdf
- * 4,
- dev->pcidev_table[i].bdf >> 16);
- }
- }
- }
- }
}
static void msm_pcie_config_link_state(struct msm_pcie_dev_t *dev)
@@ -4527,6 +3686,13 @@
msm_pcie_restore_sec_config(dev);
}
+ /* configure PCIe to RC mode */
+ msm_pcie_write_reg(dev->parf, PCIE20_PARF_DEVICE_TYPE, 0x4);
+
+ /* enable l1 mode, clear bit 5 (REQ_NOT_ENTR_L1) */
+ if (dev->l1_supported)
+ msm_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0);
+
/* enable PCIe clocks and resets */
msm_pcie_write_mask(dev->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
@@ -4688,6 +3854,9 @@
msm_pcie_config_link_state(dev);
+ if (dev->enumerated)
+ pci_walk_bus(dev->dev->bus, &msm_pcie_config_device, dev);
+
dev->link_status = MSM_PCIE_LINK_ENABLED;
dev->power_on = true;
dev->suspending = false;
@@ -4935,106 +4104,41 @@
return ret;
}
-int msm_pcie_configure_sid(struct device *dev, u32 *sid, int *domain)
+static void msm_pcie_configure_sid(struct msm_pcie_dev_t *pcie_dev,
+ struct pci_dev *dev)
{
- struct pci_dev *pcidev;
- struct msm_pcie_dev_t *pcie_dev;
- struct pci_bus *bus;
- int i;
+ u32 offset;
+ u32 sid;
u32 bdf;
+ int ret;
- if (!dev) {
- pr_err("%s: PCIe: endpoint device passed in is NULL\n",
- __func__);
- return MSM_PCIE_ERROR;
- }
-
- pcidev = to_pci_dev(dev);
- if (!pcidev) {
- pr_err("%s: PCIe: PCI device of endpoint is NULL\n",
- __func__);
- return MSM_PCIE_ERROR;
- }
-
- bus = pcidev->bus;
- if (!bus) {
- pr_err("%s: PCIe: Bus of PCI device is NULL\n",
- __func__);
- return MSM_PCIE_ERROR;
- }
-
- while (!pci_is_root_bus(bus))
- bus = bus->parent;
-
- pcie_dev = (struct msm_pcie_dev_t *)(bus->sysdata);
- if (!pcie_dev) {
- pr_err("%s: PCIe: Could not get PCIe structure\n",
- __func__);
- return MSM_PCIE_ERROR;
- }
-
- if (!pcie_dev->smmu_exist) {
+ ret = iommu_fwspec_get_id(&dev->dev, &sid);
+ if (ret) {
PCIE_DBG(pcie_dev,
- "PCIe: RC:%d: smmu does not exist\n",
+ "PCIe: RC%d: Device does not have a SID\n",
pcie_dev->rc_idx);
- return MSM_PCIE_ERROR;
- }
-
- PCIE_DBG(pcie_dev, "PCIe: RC%d: device address is: %p\n",
- pcie_dev->rc_idx, dev);
- PCIE_DBG(pcie_dev, "PCIe: RC%d: PCI device address is: %p\n",
- pcie_dev->rc_idx, pcidev);
-
- *domain = pcie_dev->rc_idx;
-
- if (pcie_dev->current_short_bdf < (MAX_SHORT_BDF_NUM - 1)) {
- pcie_dev->current_short_bdf++;
- } else {
- PCIE_ERR(pcie_dev,
- "PCIe: RC%d: No more short BDF left\n",
- pcie_dev->rc_idx);
- return MSM_PCIE_ERROR;
- }
-
- bdf = BDF_OFFSET(pcidev->bus->number, pcidev->devfn);
-
- for (i = 0; i < MAX_DEVICE_NUM; i++) {
- if (pcie_dev->pcidev_table[i].bdf == bdf) {
- *sid = pcie_dev->smmu_sid_base +
- ((pcie_dev->rc_idx << 4) |
- pcie_dev->current_short_bdf);
-
- msm_pcie_write_reg(pcie_dev->parf,
- PCIE20_PARF_BDF_TRANSLATE_N +
- pcie_dev->current_short_bdf * 4,
- bdf >> 16);
-
- pcie_dev->pcidev_table[i].sid = *sid;
- pcie_dev->pcidev_table[i].short_bdf =
- pcie_dev->current_short_bdf;
- break;
- }
- }
-
- if (i == MAX_DEVICE_NUM) {
- pcie_dev->current_short_bdf--;
- PCIE_ERR(pcie_dev,
- "PCIe: RC%d could not find BDF:%d\n",
- pcie_dev->rc_idx, bdf);
- return MSM_PCIE_ERROR;
+ return;
}
PCIE_DBG(pcie_dev,
- "PCIe: RC%d: Device: %02x:%02x.%01x received SID %d\n",
- pcie_dev->rc_idx,
- bdf >> 24,
- bdf >> 19 & 0x1f,
- bdf >> 16 & 0x07,
- *sid);
+ "PCIe: RC%d: Device SID: 0x%x\n",
+ pcie_dev->rc_idx, sid);
- return 0;
+ bdf = BDF_OFFSET(dev->bus->number, dev->devfn);
+ offset = (sid - pcie_dev->smmu_sid_base) * 4;
+
+ if (offset >= MAX_SHORT_BDF_NUM * 4) {
+ PCIE_ERR(pcie_dev,
+ "PCIe: RC%d: Invalid SID offset: 0x%x. Should be less than 0x%x\n",
+ pcie_dev->rc_idx, offset, MAX_SHORT_BDF_NUM * 4);
+ return;
+ }
+
+ msm_pcie_write_reg(pcie_dev->parf, PCIE20_PARF_BDF_TRANSLATE_CFG, 0);
+ msm_pcie_write_reg(pcie_dev->parf, PCIE20_PARF_SID_OFFSET, 0);
+ msm_pcie_write_reg(pcie_dev->parf,
+ PCIE20_PARF_BDF_TRANSLATE_N + offset, bdf >> 16);
}
-EXPORT_SYMBOL(msm_pcie_configure_sid);
int msm_pcie_enumerate(u32 rc_idx)
{
@@ -6138,6 +5242,28 @@
disable_irq(dev->wake_n);
}
+static int msm_pcie_config_device(struct pci_dev *dev, void *pdev)
+{
+ struct msm_pcie_dev_t *pcie_dev = (struct msm_pcie_dev_t *)pdev;
+ u8 busnr = dev->bus->number;
+ u8 slot = PCI_SLOT(dev->devfn);
+ u8 func = PCI_FUNC(dev->devfn);
+
+ PCIE_DBG(pcie_dev, "PCIe: RC%d: configure PCI device %02x:%02x.%01x\n",
+ pcie_dev->rc_idx, busnr, slot, func);
+
+ msm_pcie_configure_sid(pcie_dev, dev);
+
+ return 0;
+}
+
+/* Hook to setup PCI device during PCI framework scan */
+int pcibios_add_device(struct pci_dev *dev)
+{
+ struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev->bus);
+
+ return msm_pcie_config_device(dev, pcie_dev);
+}
static int msm_pcie_probe(struct platform_device *pdev)
{
@@ -6413,7 +5539,6 @@
msm_pcie_dev[rc_idx].wake_counter = 0;
msm_pcie_dev[rc_idx].aer_enable = true;
msm_pcie_dev[rc_idx].power_on = false;
- msm_pcie_dev[rc_idx].current_short_bdf = 0;
msm_pcie_dev[rc_idx].use_msi = false;
msm_pcie_dev[rc_idx].use_pinctrl = false;
msm_pcie_dev[rc_idx].linkdown_panic = false;
@@ -6764,12 +5889,12 @@
PCIE_DBG(pcie_dev, "RC%d: PM_Enter_L23 is NOT received\n",
pcie_dev->rc_idx);
- msm_pcie_disable(pcie_dev, PM_PIPE_CLK | PM_CLK | PM_VREG);
-
if (pcie_dev->use_pinctrl && pcie_dev->pins_sleep)
pinctrl_select_state(pcie_dev->pinctrl,
pcie_dev->pins_sleep);
+ msm_pcie_disable(pcie_dev, PM_PIPE_CLK | PM_CLK | PM_VREG);
+
PCIE_DBG(pcie_dev, "RC%d: exit\n", pcie_dev->rc_idx);
return ret;
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 67adf58..30c31a8 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -526,7 +526,6 @@
msm_mux_reserved30,
msm_mux_qup11,
msm_mux_qup14,
- msm_mux_phase_flag3,
msm_mux_reserved96,
msm_mux_ldo_en,
msm_mux_reserved97,
@@ -543,17 +542,13 @@
msm_mux_phase_flag5,
msm_mux_reserved103,
msm_mux_reserved104,
- msm_mux_pcie1_forceon,
msm_mux_uim2_data,
msm_mux_qup13,
msm_mux_reserved105,
- msm_mux_pcie1_pwren,
msm_mux_uim2_clk,
msm_mux_reserved106,
- msm_mux_pcie1_auxen,
msm_mux_uim2_reset,
msm_mux_reserved107,
- msm_mux_pcie1_button,
msm_mux_uim2_present,
msm_mux_reserved108,
msm_mux_uim1_data,
@@ -564,7 +559,6 @@
msm_mux_reserved111,
msm_mux_uim1_present,
msm_mux_reserved112,
- msm_mux_pcie1_prsnt2,
msm_mux_uim_batt,
msm_mux_edp_hot,
msm_mux_reserved113,
@@ -587,7 +581,6 @@
msm_mux_reserved123,
msm_mux_reserved124,
msm_mux_reserved125,
- msm_mux_sd_card,
msm_mux_reserved126,
msm_mux_reserved127,
msm_mux_reserved128,
@@ -647,7 +640,6 @@
msm_mux_reserved42,
msm_mux_reserved43,
msm_mux_reserved44,
- msm_mux_bt_reset,
msm_mux_qup6,
msm_mux_reserved45,
msm_mux_reserved46,
@@ -672,7 +664,6 @@
msm_mux_gcc_gp1,
msm_mux_phase_flag18,
msm_mux_reserved57,
- msm_mux_ssc_irq,
msm_mux_phase_flag19,
msm_mux_reserved58,
msm_mux_phase_flag20,
@@ -731,10 +722,8 @@
msm_mux_reserved82,
msm_mux_reserved83,
msm_mux_reserved84,
- msm_mux_pcie1_pwrfault,
msm_mux_qup5,
msm_mux_reserved85,
- msm_mux_pcie1_mrl,
msm_mux_reserved86,
msm_mux_reserved87,
msm_mux_reserved88,
@@ -772,6 +761,7 @@
msm_mux_reserved95,
msm_mux_tsif2_sync,
msm_mux_sdc40,
+ msm_mux_phase_flag3,
msm_mux_NA,
};
@@ -781,19 +771,24 @@
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
- "gpio36", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
- "gpio44", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51",
- "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio64",
- "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
- "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "gpio81",
- "gpio82", "gpio83", "gpio84", "gpio87", "gpio88", "gpio89", "gpio90",
- "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97",
- "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103",
- "gpio109", "gpio110", "gpio111", "gpio112", "gpio114", "gpio115",
- "gpio116", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
- "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
- "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
- "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149",
};
static const char * const qup0_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3",
@@ -1075,9 +1070,6 @@
static const char * const qup14_groups[] = {
"gpio31", "gpio32", "gpio33", "gpio34",
};
-static const char * const phase_flag3_groups[] = {
- "gpio96",
-};
static const char * const reserved96_groups[] = {
"gpio96",
};
@@ -1109,7 +1101,7 @@
"gpio101",
};
static const char * const pci_e1_groups[] = {
- "gpio102", "gpio103", "gpio104",
+ "gpio102", "gpio103",
};
static const char * const prng_rosc_groups[] = {
"gpio102",
@@ -1126,9 +1118,6 @@
static const char * const reserved104_groups[] = {
"gpio104",
};
-static const char * const pcie1_forceon_groups[] = {
- "gpio105",
-};
static const char * const uim2_data_groups[] = {
"gpio105",
};
@@ -1138,27 +1127,18 @@
static const char * const reserved105_groups[] = {
"gpio105",
};
-static const char * const pcie1_pwren_groups[] = {
- "gpio106",
-};
static const char * const uim2_clk_groups[] = {
"gpio106",
};
static const char * const reserved106_groups[] = {
"gpio106",
};
-static const char * const pcie1_auxen_groups[] = {
- "gpio107",
-};
static const char * const uim2_reset_groups[] = {
"gpio107",
};
static const char * const reserved107_groups[] = {
"gpio107",
};
-static const char * const pcie1_button_groups[] = {
- "gpio108",
-};
static const char * const uim2_present_groups[] = {
"gpio108",
};
@@ -1189,9 +1169,6 @@
static const char * const reserved112_groups[] = {
"gpio112",
};
-static const char * const pcie1_prsnt2_groups[] = {
- "gpio113",
-};
static const char * const uim_batt_groups[] = {
"gpio113",
};
@@ -1259,9 +1236,6 @@
static const char * const reserved125_groups[] = {
"gpio125",
};
-static const char * const sd_card_groups[] = {
- "gpio126",
-};
static const char * const reserved126_groups[] = {
"gpio126",
};
@@ -1380,7 +1354,7 @@
"gpio34",
};
static const char * const pci_e0_groups[] = {
- "gpio35", "gpio36", "gpio37",
+ "gpio35", "gpio36",
};
static const char * const jitter_bist_groups[] = {
"gpio35",
@@ -1439,9 +1413,6 @@
static const char * const reserved44_groups[] = {
"gpio44",
};
-static const char * const bt_reset_groups[] = {
- "gpio45",
-};
static const char * const qup6_groups[] = {
"gpio45", "gpio46", "gpio47", "gpio48",
};
@@ -1514,11 +1485,6 @@
static const char * const reserved57_groups[] = {
"gpio57",
};
-static const char * const ssc_irq_groups[] = {
- "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio78",
- "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", "gpio120",
- "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
-};
static const char * const phase_flag19_groups[] = {
"gpio58",
};
@@ -1693,18 +1659,12 @@
static const char * const reserved84_groups[] = {
"gpio84",
};
-static const char * const pcie1_pwrfault_groups[] = {
- "gpio85",
-};
static const char * const qup5_groups[] = {
"gpio85", "gpio86", "gpio87", "gpio88",
};
static const char * const reserved85_groups[] = {
"gpio85",
};
-static const char * const pcie1_mrl_groups[] = {
- "gpio86",
-};
static const char * const reserved86_groups[] = {
"gpio86",
};
@@ -1816,6 +1776,9 @@
static const char * const sdc40_groups[] = {
"gpio96",
};
+static const char * const phase_flag3_groups[] = {
+ "gpio96",
+};
static const struct msm_function sdm845_functions[] = {
FUNCTION(gpio),
@@ -1912,7 +1875,6 @@
FUNCTION(reserved30),
FUNCTION(qup11),
FUNCTION(qup14),
- FUNCTION(phase_flag3),
FUNCTION(reserved96),
FUNCTION(ldo_en),
FUNCTION(reserved97),
@@ -1929,17 +1891,13 @@
FUNCTION(phase_flag5),
FUNCTION(reserved103),
FUNCTION(reserved104),
- FUNCTION(pcie1_forceon),
FUNCTION(uim2_data),
FUNCTION(qup13),
FUNCTION(reserved105),
- FUNCTION(pcie1_pwren),
FUNCTION(uim2_clk),
FUNCTION(reserved106),
- FUNCTION(pcie1_auxen),
FUNCTION(uim2_reset),
FUNCTION(reserved107),
- FUNCTION(pcie1_button),
FUNCTION(uim2_present),
FUNCTION(reserved108),
FUNCTION(uim1_data),
@@ -1950,7 +1908,6 @@
FUNCTION(reserved111),
FUNCTION(uim1_present),
FUNCTION(reserved112),
- FUNCTION(pcie1_prsnt2),
FUNCTION(uim_batt),
FUNCTION(edp_hot),
FUNCTION(reserved113),
@@ -1973,7 +1930,6 @@
FUNCTION(reserved123),
FUNCTION(reserved124),
FUNCTION(reserved125),
- FUNCTION(sd_card),
FUNCTION(reserved126),
FUNCTION(reserved127),
FUNCTION(reserved128),
@@ -2033,7 +1989,6 @@
FUNCTION(reserved42),
FUNCTION(reserved43),
FUNCTION(reserved44),
- FUNCTION(bt_reset),
FUNCTION(qup6),
FUNCTION(reserved45),
FUNCTION(reserved46),
@@ -2058,7 +2013,6 @@
FUNCTION(gcc_gp1),
FUNCTION(phase_flag18),
FUNCTION(reserved57),
- FUNCTION(ssc_irq),
FUNCTION(phase_flag19),
FUNCTION(reserved58),
FUNCTION(phase_flag20),
@@ -2117,10 +2071,8 @@
FUNCTION(reserved82),
FUNCTION(reserved83),
FUNCTION(reserved84),
- FUNCTION(pcie1_pwrfault),
FUNCTION(qup5),
FUNCTION(reserved85),
- FUNCTION(pcie1_mrl),
FUNCTION(reserved86),
FUNCTION(reserved87),
FUNCTION(reserved88),
@@ -2158,6 +2110,7 @@
FUNCTION(reserved95),
FUNCTION(tsif2_sync),
FUNCTION(sdc40),
+ FUNCTION(phase_flag3),
};
static const struct msm_pingroup sdm845_groups[] = {
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa.c b/drivers/platform/msm/ipa/ipa_v2/ipa.c
index af4d4c8..f5d8227 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa.c
@@ -3546,16 +3546,32 @@
ipa_ctx->curr_ipa_clk_rate = clk_rate;
IPADBG("setting clock rate to %u\n", ipa_ctx->curr_ipa_clk_rate);
if (ipa_ctx->ipa_active_clients.cnt > 0) {
+ struct ipa_active_client_logging_info log_info;
+
+ /*
+ * clk_set_rate should be called with unlocked lock to allow
+ * clients to get a reference to IPA clock synchronously.
+ * Hold a reference to IPA clock here to make sure clock
+ * state does not change during set_rate.
+ */
+ IPA_ACTIVE_CLIENTS_PREP_SIMPLE(log_info);
+ ipa_ctx->ipa_active_clients.cnt++;
+ ipa2_active_clients_log_inc(&log_info, false);
+ ipa_active_clients_unlock();
+
clk_set_rate(ipa_clk, ipa_ctx->curr_ipa_clk_rate);
if (ipa_ctx->ipa_hw_mode != IPA_HW_MODE_VIRTUAL)
if (msm_bus_scale_client_update_request(
ipa_ctx->ipa_bus_hdl, ipa_get_bus_vote()))
WARN_ON(1);
+ /* remove the vote added here */
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
} else {
IPADBG("clocks are gated, not setting rate\n");
+ ipa_active_clients_unlock();
}
- ipa_active_clients_unlock();
IPADBG("Done\n");
+
return 0;
}
@@ -3679,6 +3695,7 @@
* pipe will be unsuspended as part of
* enabling IPA clocks
*/
+ mutex_lock(&ipa_ctx->sps_pm.sps_pm_lock);
if (!atomic_read(
&ipa_ctx->sps_pm.dec_clients)
) {
@@ -3691,6 +3708,7 @@
1);
ipa_sps_process_irq_schedule_rel();
}
+ mutex_unlock(&ipa_ctx->sps_pm.sps_pm_lock);
} else {
resource = ipa2_get_rm_resource_from_ep(i);
res = ipa_rm_request_resource_with_timer(
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c b/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c
index e474a40..b60c7a6 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -1480,17 +1480,24 @@
void ipa_delete_dflt_flt_rules(u32 ipa_ep_idx)
{
+ struct ipa_flt_tbl *tbl;
struct ipa_ep_context *ep = &ipa_ctx->ep[ipa_ep_idx];
mutex_lock(&ipa_ctx->lock);
if (ep->dflt_flt4_rule_hdl) {
+ tbl = &ipa_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v4];
__ipa_del_flt_rule(ep->dflt_flt4_rule_hdl);
ipa_ctx->ctrl->ipa_commit_flt(IPA_IP_v4);
+ /* Reset the sticky flag. */
+ tbl->sticky_rear = false;
ep->dflt_flt4_rule_hdl = 0;
}
if (ep->dflt_flt6_rule_hdl) {
+ tbl = &ipa_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v6];
__ipa_del_flt_rule(ep->dflt_flt6_rule_hdl);
ipa_ctx->ctrl->ipa_commit_flt(IPA_IP_v6);
+ /* Reset the sticky flag. */
+ tbl->sticky_rear = false;
ep->dflt_flt6_rule_hdl = 0;
}
mutex_unlock(&ipa_ctx->lock);
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_i.h b/drivers/platform/msm/ipa/ipa_v2/ipa_i.h
index cd575fe..5568f8b 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_i.h
@@ -51,6 +51,7 @@
#define IPA_UC_FINISH_MAX 6
#define IPA_UC_WAIT_MIN_SLEEP 1000
#define IPA_UC_WAII_MAX_SLEEP 1200
+#define IPA_BAM_STOP_MAX_RETRY 10
#define IPA_MAX_STATUS_STAT_NUM 30
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_uc.c b/drivers/platform/msm/ipa/ipa_v2/ipa_uc.c
index 01eea36..9a3c146 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_uc.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_uc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -591,6 +591,7 @@
{
int index;
union IpaHwCpuCmdCompletedResponseData_t uc_rsp;
+ int retries = 0;
mutex_lock(&ipa_ctx->uc_ctx.uc_lock);
@@ -600,6 +601,7 @@
return -EBADF;
}
+send_cmd:
init_completion(&ipa_ctx->uc_ctx.uc_completion);
ipa_ctx->uc_ctx.uc_sram_mmio->cmdParams = cmd;
@@ -659,6 +661,19 @@
}
if (ipa_ctx->uc_ctx.uc_status != expected_status) {
+ if (IPA_HW_2_CPU_WDI_RX_FSM_TRANSITION_ERROR ==
+ ipa_ctx->uc_ctx.uc_status) {
+ retries++;
+ if (retries == IPA_BAM_STOP_MAX_RETRY) {
+ IPAERR("Failed after %d tries\n", retries);
+ } else {
+ /* sleep for short period to flush IPA */
+ usleep_range(IPA_UC_WAIT_MIN_SLEEP,
+ IPA_UC_WAII_MAX_SLEEP);
+ goto send_cmd;
+ }
+ }
+
IPAERR("Recevied status %u, Expected status %u\n",
ipa_ctx->uc_ctx.uc_status, expected_status);
ipa_ctx->uc_ctx.pending_cmd = -1;
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_uc_offload_i.h b/drivers/platform/msm/ipa/ipa_v2/ipa_uc_offload_i.h
index 3bec471..a98d602 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_uc_offload_i.h
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_uc_offload_i.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -441,7 +441,7 @@
/**
- * enum ipa_hw_2_cpu_cmd_resp_status - Values that represent
+ * enum ipa_hw_2_cpu_offload_cmd_resp_status - Values that represent
* offload related command response status to be sent to CPU.
*/
enum ipa_hw_2_cpu_offload_cmd_resp_status {
@@ -478,6 +478,47 @@
};
/**
+ * enum ipa_hw_2_cpu_cmd_resp_status - Values that represent WDI related
+ * command response status to be sent to CPU.
+ */
+enum ipa_hw_2_cpu_cmd_resp_status {
+ IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 0),
+ IPA_HW_2_CPU_MAX_WDI_TX_CHANNELS =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 1),
+ IPA_HW_2_CPU_WDI_CE_RING_OVERRUN_POSSIBILITY =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 2),
+ IPA_HW_2_CPU_WDI_CE_RING_SET_UP_FAILURE =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 3),
+ IPA_HW_2_CPU_WDI_CE_RING_PARAMS_UNALIGNED =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 4),
+ IPA_HW_2_CPU_WDI_COMP_RING_OVERRUN_POSSIBILITY =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 5),
+ IPA_HW_2_CPU_WDI_COMP_RING_SET_UP_FAILURE =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 6),
+ IPA_HW_2_CPU_WDI_COMP_RING_PARAMS_UNALIGNED =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 7),
+ IPA_HW_2_CPU_WDI_UNKNOWN_TX_CHANNEL =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 8),
+ IPA_HW_2_CPU_WDI_TX_INVALID_FSM_TRANSITION =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 9),
+ IPA_HW_2_CPU_WDI_TX_FSM_TRANSITION_ERROR =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 10),
+ IPA_HW_2_CPU_MAX_WDI_RX_CHANNELS =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 11),
+ IPA_HW_2_CPU_WDI_RX_RING_PARAMS_UNALIGNED =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 12),
+ IPA_HW_2_CPU_WDI_RX_RING_SET_UP_FAILURE =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 13),
+ IPA_HW_2_CPU_WDI_UNKNOWN_RX_CHANNEL =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 14),
+ IPA_HW_2_CPU_WDI_RX_INVALID_FSM_TRANSITION =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 15),
+ IPA_HW_2_CPU_WDI_RX_FSM_TRANSITION_ERROR =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 16),
+};
+
+/**
* struct IpaHwSetUpCmd -
*
*
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_uc_wdi.c b/drivers/platform/msm/ipa/ipa_v2/ipa_uc_wdi.c
index 128674a..b7815cb 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_uc_wdi.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_uc_wdi.c
@@ -111,47 +111,6 @@
};
/**
- * enum ipa_hw_2_cpu_cmd_resp_status - Values that represent WDI related
- * command response status to be sent to CPU.
- */
-enum ipa_hw_2_cpu_cmd_resp_status {
- IPA_HW_2_CPU_WDI_CMD_STATUS_SUCCESS =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 0),
- IPA_HW_2_CPU_MAX_WDI_TX_CHANNELS =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 1),
- IPA_HW_2_CPU_WDI_CE_RING_OVERRUN_POSSIBILITY =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 2),
- IPA_HW_2_CPU_WDI_CE_RING_SET_UP_FAILURE =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 3),
- IPA_HW_2_CPU_WDI_CE_RING_PARAMS_UNALIGNED =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 4),
- IPA_HW_2_CPU_WDI_COMP_RING_OVERRUN_POSSIBILITY =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 5),
- IPA_HW_2_CPU_WDI_COMP_RING_SET_UP_FAILURE =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 6),
- IPA_HW_2_CPU_WDI_COMP_RING_PARAMS_UNALIGNED =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 7),
- IPA_HW_2_CPU_WDI_UNKNOWN_TX_CHANNEL =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 8),
- IPA_HW_2_CPU_WDI_TX_INVALID_FSM_TRANSITION =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 9),
- IPA_HW_2_CPU_WDI_TX_FSM_TRANSITION_ERROR =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 10),
- IPA_HW_2_CPU_MAX_WDI_RX_CHANNELS =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 11),
- IPA_HW_2_CPU_WDI_RX_RING_PARAMS_UNALIGNED =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 12),
- IPA_HW_2_CPU_WDI_RX_RING_SET_UP_FAILURE =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 13),
- IPA_HW_2_CPU_WDI_UNKNOWN_RX_CHANNEL =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 14),
- IPA_HW_2_CPU_WDI_RX_INVALID_FSM_TRANSITION =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 15),
- IPA_HW_2_CPU_WDI_RX_FSM_TRANSITION_ERROR =
- FEATURE_ENUM_VAL(IPA_HW_FEATURE_WDI, 16),
-};
-
-/**
* enum ipa_hw_wdi_errors - WDI specific error types.
* @IPA_HW_WDI_ERROR_NONE : No error persists
* @IPA_HW_WDI_CHANNEL_ERROR : Error is specific to channel
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c
index 83fd2b2..862b147 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c
@@ -3569,16 +3569,32 @@
ipa3_ctx->curr_ipa_clk_rate = clk_rate;
IPADBG_LOW("setting clock rate to %u\n", ipa3_ctx->curr_ipa_clk_rate);
if (ipa3_ctx->ipa3_active_clients.cnt > 0) {
+ struct ipa_active_client_logging_info log_info;
+
+ /*
+ * clk_set_rate should be called with unlocked lock to allow
+ * clients to get a reference to IPA clock synchronously.
+ * Hold a reference to IPA clock here to make sure clock
+ * state does not change during set_rate.
+ */
+ IPA_ACTIVE_CLIENTS_PREP_SIMPLE(log_info);
+ ipa3_ctx->ipa3_active_clients.cnt++;
+ ipa3_active_clients_log_inc(&log_info, false);
+ ipa3_active_clients_unlock();
+
if (ipa3_clk)
clk_set_rate(ipa3_clk, ipa3_ctx->curr_ipa_clk_rate);
if (msm_bus_scale_client_update_request(ipa3_ctx->ipa_bus_hdl,
ipa3_get_bus_vote()))
WARN_ON(1);
+ /* remove the vote added here */
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
} else {
IPADBG_LOW("clocks are gated, not setting rate\n");
+ ipa3_active_clients_unlock();
}
- ipa3_active_clients_unlock();
IPADBG_LOW("Done\n");
+
return 0;
}
@@ -3620,6 +3636,8 @@
* pipe will be unsuspended as part of
* enabling IPA clocks
*/
+ mutex_lock(&ipa3_ctx->transport_pm.
+ transport_pm_mutex);
if (!atomic_read(
&ipa3_ctx->transport_pm.dec_clients)
) {
@@ -3632,6 +3650,8 @@
1);
ipa3_process_irq_schedule_rel();
}
+ mutex_unlock(&ipa3_ctx->transport_pm.
+ transport_pm_mutex);
} else {
resource = ipa3_get_rm_resource_from_ep(i);
res =
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
index 9d25e4a..89dd274 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
@@ -1004,6 +1004,7 @@
struct ipa3_ep_context *ep;
int empty;
int result;
+ int i;
if (clnt_hdl >= ipa3_ctx->ipa_num_pipes ||
ipa3_ctx->ep[clnt_hdl].valid == 0) {
@@ -1038,7 +1039,17 @@
if (IPA_CLIENT_IS_CONS(ep->client))
cancel_delayed_work_sync(&ep->sys->replenish_rx_work);
flush_workqueue(ep->sys->wq);
- result = ipa3_stop_gsi_channel(clnt_hdl);
+ /* channel stop might fail on timeout if IPA is busy */
+ for (i = 0; i < IPA_GSI_CHANNEL_STOP_MAX_RETRY; i++) {
+ result = ipa3_stop_gsi_channel(clnt_hdl);
+ if (result == GSI_STATUS_SUCCESS)
+ break;
+
+ if (result != -GSI_STATUS_AGAIN &&
+ result != -GSI_STATUS_TIMED_OUT)
+ break;
+ }
+
if (result != GSI_STATUS_SUCCESS) {
IPAERR("GSI stop chan err: %d.\n", result);
ipa_assert();
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c
index 0cc1206..ff763c4 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c
@@ -1389,16 +1389,23 @@
void ipa3_delete_dflt_flt_rules(u32 ipa_ep_idx)
{
struct ipa3_ep_context *ep = &ipa3_ctx->ep[ipa_ep_idx];
+ struct ipa3_flt_tbl *tbl;
mutex_lock(&ipa3_ctx->lock);
if (ep->dflt_flt4_rule_hdl) {
+ tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v4];
__ipa_del_flt_rule(ep->dflt_flt4_rule_hdl);
ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v4);
+ /* Reset the sticky flag. */
+ tbl->sticky_rear = false;
ep->dflt_flt4_rule_hdl = 0;
}
if (ep->dflt_flt6_rule_hdl) {
+ tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v6];
__ipa_del_flt_rule(ep->dflt_flt6_rule_hdl);
ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v6);
+ /* Reset the sticky flag. */
+ tbl->sticky_rear = false;
ep->dflt_flt6_rule_hdl = 0;
}
mutex_unlock(&ipa3_ctx->lock);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
index 19c3de4a..73738bf 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
@@ -53,6 +53,8 @@
static bool workqueues_stopped;
static bool ipa3_modem_init_cmplt;
static bool first_time_handshake;
+struct mutex ipa3_qmi_lock;
+
/* QMI A5 service */
static struct msg_desc ipa3_indication_reg_req_desc = {
@@ -610,12 +612,17 @@
req->filter_spec_ex_list_len);
}
- /* cache the qmi_filter_request */
- memcpy(&(ipa3_qmi_ctx->ipa_install_fltr_rule_req_msg_cache[
- ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_msg]),
- req, sizeof(struct ipa_install_fltr_rule_req_msg_v01));
- ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_msg++;
- ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_msg %= 10;
+ mutex_lock(&ipa3_qmi_lock);
+ if (ipa3_qmi_ctx != NULL) {
+ /* cache the qmi_filter_request */
+ memcpy(&(ipa3_qmi_ctx->ipa_install_fltr_rule_req_msg_cache[
+ ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_msg]),
+ req,
+ sizeof(struct ipa_install_fltr_rule_req_msg_v01));
+ ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_msg++;
+ ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_msg %= 10;
+ }
+ mutex_unlock(&ipa3_qmi_lock);
req_desc.max_msg_len = QMI_IPA_INSTALL_FILTER_RULE_REQ_MAX_MSG_LEN_V01;
req_desc.msg_id = QMI_IPA_INSTALL_FILTER_RULE_REQ_V01;
@@ -655,12 +662,17 @@
req->filter_spec_ex_list_len);
}
- /* cache the qmi_filter_request */
- memcpy(&(ipa3_qmi_ctx->ipa_install_fltr_rule_req_ex_msg_cache[
- ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg]),
- req, sizeof(struct ipa_install_fltr_rule_req_ex_msg_v01));
- ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg++;
- ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg %= 10;
+ mutex_lock(&ipa3_qmi_lock);
+ if (ipa3_qmi_ctx != NULL) {
+ /* cache the qmi_filter_request */
+ memcpy(&(ipa3_qmi_ctx->ipa_install_fltr_rule_req_ex_msg_cache[
+ ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg]),
+ req,
+ sizeof(struct ipa_install_fltr_rule_req_ex_msg_v01));
+ ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg++;
+ ipa3_qmi_ctx->num_ipa_install_fltr_rule_req_ex_msg %= 10;
+ }
+ mutex_unlock(&ipa3_qmi_lock);
req_desc.max_msg_len =
QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_MAX_MSG_LEN_V01;
@@ -796,12 +808,17 @@
return -EINVAL;
}
- /* cache the qmi_filter_request */
- memcpy(&(ipa3_qmi_ctx->ipa_fltr_installed_notif_req_msg_cache[
- ipa3_qmi_ctx->num_ipa_fltr_installed_notif_req_msg]),
- req, sizeof(struct ipa_fltr_installed_notif_req_msg_v01));
- ipa3_qmi_ctx->num_ipa_fltr_installed_notif_req_msg++;
- ipa3_qmi_ctx->num_ipa_fltr_installed_notif_req_msg %= 10;
+ mutex_lock(&ipa3_qmi_lock);
+ if (ipa3_qmi_ctx != NULL) {
+ /* cache the qmi_filter_request */
+ memcpy(&(ipa3_qmi_ctx->ipa_fltr_installed_notif_req_msg_cache[
+ ipa3_qmi_ctx->num_ipa_fltr_installed_notif_req_msg]),
+ req,
+ sizeof(struct ipa_fltr_installed_notif_req_msg_v01));
+ ipa3_qmi_ctx->num_ipa_fltr_installed_notif_req_msg++;
+ ipa3_qmi_ctx->num_ipa_fltr_installed_notif_req_msg %= 10;
+ }
+ mutex_unlock(&ipa3_qmi_lock);
req_desc.max_msg_len =
QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_MAX_MSG_LEN_V01;
@@ -1339,3 +1356,13 @@
resp.resp.error, "ipa_stop_data_usage_quota_req_msg_v01");
}
+void ipa3_qmi_init(void)
+{
+ mutex_init(&ipa3_qmi_lock);
+}
+
+void ipa3_qmi_cleanup(void)
+{
+ mutex_destroy(&ipa3_qmi_lock);
+}
+
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h
index 4fde261..6cd82f8 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.h
@@ -204,6 +204,10 @@
void ipa3_q6_handshake_complete(bool ssr_bootup);
+void ipa3_qmi_init(void);
+
+void ipa3_qmi_cleanup(void);
+
#else /* CONFIG_RMNET_IPA3 */
static inline int ipa3_qmi_service_init(uint32_t wan_platform_type)
@@ -316,6 +320,14 @@
static inline void ipa3_q6_handshake_complete(bool ssr_bootup) { }
+static inline void ipa3_qmi_init(void)
+{
+}
+
+static inline void ipa3_qmi_cleanup(void)
+{
+}
+
#endif /* CONFIG_RMNET_IPA3 */
#endif /* IPA_QMI_SERVICE_H */
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index 5a38db3..f066d94 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -4352,21 +4352,30 @@
memset(&mem, 0, sizeof(mem));
- for (i = 0; i < IPA_GSI_CHANNEL_STOP_MAX_RETRY; i++) {
- IPADBG("Calling gsi_stop_channel\n");
+ if (IPA_CLIENT_IS_PROD(ep->client)) {
+ IPADBG("Calling gsi_stop_channel ch:%lu\n",
+ ep->gsi_chan_hdl);
res = gsi_stop_channel(ep->gsi_chan_hdl);
- IPADBG("gsi_stop_channel returned %d\n", res);
+ IPADBG("gsi_stop_channel ch: %lu returned %d\n",
+ ep->gsi_chan_hdl, res);
+ goto end_sequence;
+ }
+
+ for (i = 0; i < IPA_GSI_CHANNEL_STOP_MAX_RETRY; i++) {
+ IPADBG("Calling gsi_stop_channel ch:%lu\n",
+ ep->gsi_chan_hdl);
+ res = gsi_stop_channel(ep->gsi_chan_hdl);
+ IPADBG("gsi_stop_channel ch: %lu returned %d\n",
+ ep->gsi_chan_hdl, res);
if (res != -GSI_STATUS_AGAIN && res != -GSI_STATUS_TIMED_OUT)
goto end_sequence;
- if (IPA_CLIENT_IS_CONS(ep->client)) {
- IPADBG("Inject a DMA_TASK with 1B packet to IPA\n");
- /* Send a 1B packet DMA_TASK to IPA and try again */
- res = ipa3_inject_dma_task_for_gsi();
- if (res) {
- IPAERR("Failed to inject DMA TASk for GSI\n");
- goto end_sequence;
- }
+ IPADBG("Inject a DMA_TASK with 1B packet to IPA\n");
+ /* Send a 1B packet DMA_TASK to IPA and try again */
+ res = ipa3_inject_dma_task_for_gsi();
+ if (res) {
+ IPAERR("Failed to inject DMA TASk for GSI\n");
+ goto end_sequence;
}
/* sleep for short period to flush IPA */
diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
index 56e7718..a15bd04 100644
--- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
@@ -3206,6 +3206,9 @@
mutex_init(&rmnet_ipa3_ctx->pipe_handle_guard);
rmnet_ipa3_ctx->ipa3_to_apps_hdl = -1;
rmnet_ipa3_ctx->apps_to_ipa3_hdl = -1;
+
+ ipa3_qmi_init();
+
/* Register for Modem SSR */
rmnet_ipa3_ctx->subsys_notify_handle = subsys_notif_register_notifier(
SUBSYS_MODEM,
@@ -3219,7 +3222,7 @@
static void __exit ipa3_wwan_cleanup(void)
{
int ret;
-
+ ipa3_qmi_cleanup();
mutex_destroy(&rmnet_ipa3_ctx->pipe_handle_guard);
ret = subsys_notif_unregister_notifier(
rmnet_ipa3_ctx->subsys_notify_handle, &ipa3_ssr_notifier);
diff --git a/drivers/platform/msm/msm_11ad/msm_11ad.c b/drivers/platform/msm/msm_11ad/msm_11ad.c
index 47da1b3..5595b7b 100644
--- a/drivers/platform/msm/msm_11ad/msm_11ad.c
+++ b/drivers/platform/msm/msm_11ad/msm_11ad.c
@@ -36,7 +36,7 @@
#define WIGIG_VENDOR (0x1ae9)
#define WIGIG_DEVICE (0x0310)
-#define SMMU_BASE 0x10000000 /* Device address range base */
+#define SMMU_BASE 0x20000000 /* Device address range base */
#define SMMU_SIZE ((SZ_1G * 4ULL) - SMMU_BASE)
#define WIGIG_ENABLE_DELAY 50
@@ -93,9 +93,12 @@
/* SMMU */
bool use_smmu; /* have SMMU enabled? */
- int smmu_bypass;
+ int smmu_s1_en;
int smmu_fast_map;
+ int smmu_coherent;
struct dma_iommu_mapping *mapping;
+ u32 smmu_base;
+ u32 smmu_size;
/* bus frequency scaling */
struct msm_bus_scale_pdata *bus_scale;
@@ -638,15 +641,20 @@
{
int atomic_ctx = 1;
int rc;
+ int force_pt_coherent = 1;
+ int smmu_bypass = !ctx->smmu_s1_en;
+ dma_addr_t iova_base = 0;
+ dma_addr_t iova_end = ctx->smmu_base + ctx->smmu_size - 1;
+ struct iommu_domain_geometry geometry;
if (!ctx->use_smmu)
return 0;
- dev_info(ctx->dev, "Initialize SMMU, bypass = %d, fastmap = %d\n",
- ctx->smmu_bypass, ctx->smmu_fast_map);
+ dev_info(ctx->dev, "Initialize SMMU, bypass=%d, fastmap=%d, coherent=%d\n",
+ smmu_bypass, ctx->smmu_fast_map, ctx->smmu_coherent);
ctx->mapping = arm_iommu_create_mapping(&platform_bus_type,
- SMMU_BASE, SMMU_SIZE);
+ ctx->smmu_base, ctx->smmu_size);
if (IS_ERR_OR_NULL(ctx->mapping)) {
rc = PTR_ERR(ctx->mapping) ?: -ENODEV;
dev_err(ctx->dev, "Failed to create IOMMU mapping (%d)\n", rc);
@@ -662,23 +670,50 @@
goto release_mapping;
}
- if (ctx->smmu_bypass) {
+ if (smmu_bypass) {
rc = iommu_domain_set_attr(ctx->mapping->domain,
DOMAIN_ATTR_S1_BYPASS,
- &ctx->smmu_bypass);
+ &smmu_bypass);
if (rc) {
dev_err(ctx->dev, "Set bypass attribute to SMMU failed (%d)\n",
rc);
goto release_mapping;
}
- } else if (ctx->smmu_fast_map) {
- rc = iommu_domain_set_attr(ctx->mapping->domain,
- DOMAIN_ATTR_FAST,
- &ctx->smmu_fast_map);
- if (rc) {
- dev_err(ctx->dev, "Set fast attribute to SMMU failed (%d)\n",
- rc);
- goto release_mapping;
+ } else {
+ /* Set dma-coherent and page table coherency */
+ if (ctx->smmu_coherent) {
+ arch_setup_dma_ops(&ctx->pcidev->dev, 0, 0, NULL, true);
+ rc = iommu_domain_set_attr(ctx->mapping->domain,
+ DOMAIN_ATTR_PAGE_TABLE_FORCE_COHERENT,
+ &force_pt_coherent);
+ if (rc) {
+ dev_err(ctx->dev,
+ "Set SMMU PAGE_TABLE_FORCE_COHERENT attr failed (%d)\n",
+ rc);
+ goto release_mapping;
+ }
+ }
+
+ if (ctx->smmu_fast_map) {
+ rc = iommu_domain_set_attr(ctx->mapping->domain,
+ DOMAIN_ATTR_FAST,
+ &ctx->smmu_fast_map);
+ if (rc) {
+ dev_err(ctx->dev, "Set fast attribute to SMMU failed (%d)\n",
+ rc);
+ goto release_mapping;
+ }
+ memset(&geometry, 0, sizeof(geometry));
+ geometry.aperture_start = iova_base;
+ geometry.aperture_end = iova_end;
+ rc = iommu_domain_set_attr(ctx->mapping->domain,
+ DOMAIN_ATTR_GEOMETRY,
+ &geometry);
+ if (rc) {
+ dev_err(ctx->dev, "Set geometry attribute to SMMU failed (%d)\n",
+ rc);
+ goto release_mapping;
+ }
}
}
@@ -900,6 +935,7 @@
struct device_node *of_node = dev->of_node;
struct device_node *rc_node;
struct pci_dev *pcidev = NULL;
+ u32 smmu_mapping[2];
int rc;
u32 val;
@@ -954,8 +990,27 @@
ctx->use_smmu = of_property_read_bool(of_node, "qcom,smmu-support");
ctx->bus_scale = msm_bus_cl_get_pdata(pdev);
- ctx->smmu_bypass = 1;
- ctx->smmu_fast_map = 0;
+ ctx->smmu_s1_en = of_property_read_bool(of_node, "qcom,smmu-s1-en");
+ if (ctx->smmu_s1_en) {
+ ctx->smmu_fast_map = of_property_read_bool(
+ of_node, "qcom,smmu-fast-map");
+ ctx->smmu_coherent = of_property_read_bool(
+ of_node, "qcom,smmu-coherent");
+ }
+ rc = of_property_read_u32_array(dev->of_node, "qcom,smmu-mapping",
+ smmu_mapping, 2);
+ if (rc) {
+ dev_err(ctx->dev,
+ "Failed to read base/size smmu addresses %d, fallback to default\n",
+ rc);
+ ctx->smmu_base = SMMU_BASE;
+ ctx->smmu_size = SMMU_SIZE;
+ } else {
+ ctx->smmu_base = smmu_mapping[0];
+ ctx->smmu_size = smmu_mapping[1];
+ }
+ dev_dbg(ctx->dev, "smmu_base=0x%x smmu_sise=0x%x\n",
+ ctx->smmu_base, ctx->smmu_size);
/*== execute ==*/
/* turn device on */
diff --git a/drivers/power/supply/qcom/Kconfig b/drivers/power/supply/qcom/Kconfig
index 79ea712..362375f 100644
--- a/drivers/power/supply/qcom/Kconfig
+++ b/drivers/power/supply/qcom/Kconfig
@@ -20,6 +20,16 @@
The driver reports the charger status via the power supply framework.
A charger status change triggers an IRQ via the device STAT pin.
+config SMB1355_SLAVE_CHARGER
+ tristate "SMB1355 Slave Battery Charger"
+ depends on MFD_I2C_PMIC
+ help
+ Say Y to include support for SMB1355 Battery Charger.
+ SMB1355 is a single phase 5A battery charger.
+ The driver supports charger enable/disable.
+ The driver reports the charger status via the power supply framework.
+ A charger status change triggers an IRQ via the device STAT pin.
+
config SMB1351_USB_CHARGER
tristate "smb1351 usb charger (with VBUS detection)"
depends on I2C
diff --git a/drivers/power/supply/qcom/Makefile b/drivers/power/supply/qcom/Makefile
index 171444f..bc19b24 100644
--- a/drivers/power/supply/qcom/Makefile
+++ b/drivers/power/supply/qcom/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_QPNP_FG_GEN3) += qpnp-fg-gen3.o fg-memif.o fg-util.o
obj-$(CONFIG_SMB135X_CHARGER) += smb135x-charger.o pmic-voter.o
+obj-$(CONFIG_SMB1355_SLAVE_CHARGER) += smb1355-charger.o pmic-voter.o
obj-$(CONFIG_SMB1351_USB_CHARGER) += smb1351-charger.o pmic-voter.o battery.o
obj-$(CONFIG_QPNP_SMB2) += qpnp-smb2.o smb-lib.o pmic-voter.o storm-watch.o battery.o
obj-$(CONFIG_SMB138X_CHARGER) += smb138x-charger.o smb-lib.o pmic-voter.o storm-watch.o battery.o
diff --git a/drivers/power/supply/qcom/smb1355-charger.c b/drivers/power/supply/qcom/smb1355-charger.c
new file mode 100644
index 0000000..d5fff74
--- /dev/null
+++ b/drivers/power/supply/qcom/smb1355-charger.c
@@ -0,0 +1,675 @@
+/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "SMB1355: %s: " fmt, __func__
+
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/qpnp/qpnp-revid.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/power_supply.h>
+#include <linux/pmic-voter.h>
+
+#define SMB1355_DEFAULT_FCC_UA 1000000
+
+/* SMB1355 registers, different than mentioned in smb-reg.h */
+
+#define CHGR_BASE 0x1000
+#define BATIF_BASE 0x1200
+#define USBIN_BASE 0x1300
+#define MISC_BASE 0x1600
+
+#define BATTERY_STATUS_2_REG (CHGR_BASE + 0x0B)
+#define DISABLE_CHARGING_BIT BIT(3)
+
+#define BATTERY_STATUS_3_REG (CHGR_BASE + 0x0C)
+#define BATT_GT_PRE_TO_FAST_BIT BIT(4)
+#define ENABLE_CHARGING_BIT BIT(3)
+
+#define CHGR_CFG2_REG (CHGR_BASE + 0x51)
+#define CHG_EN_SRC_BIT BIT(7)
+#define CHG_EN_POLARITY_BIT BIT(6)
+
+#define CFG_REG (CHGR_BASE + 0x53)
+#define CHG_OPTION_PIN_TRIM_BIT BIT(7)
+#define BATN_SNS_CFG_BIT BIT(4)
+#define CFG_TAPER_DIS_AFVC_BIT BIT(3)
+#define BATFET_SHUTDOWN_CFG_BIT BIT(2)
+#define VDISCHG_EN_CFG_BIT BIT(1)
+#define VCHG_EN_CFG_BIT BIT(0)
+
+#define FAST_CHARGE_CURRENT_CFG_REG (CHGR_BASE + 0x61)
+#define FAST_CHARGE_CURRENT_SETTING_MASK GENMASK(7, 0)
+
+#define CHGR_BATTOV_CFG_REG (CHGR_BASE + 0x70)
+#define BATTOV_SETTING_MASK GENMASK(7, 0)
+
+#define BARK_BITE_WDOG_PET_REG (MISC_BASE + 0x43)
+#define BARK_BITE_WDOG_PET_BIT BIT(0)
+
+#define WD_CFG_REG (MISC_BASE + 0x51)
+#define WATCHDOG_TRIGGER_AFP_EN_BIT BIT(7)
+#define BARK_WDOG_INT_EN_BIT BIT(6)
+#define BITE_WDOG_INT_EN_BIT BIT(5)
+#define WDOG_IRQ_SFT_BIT BIT(2)
+#define WDOG_TIMER_EN_ON_PLUGIN_BIT BIT(1)
+#define WDOG_TIMER_EN_BIT BIT(0)
+
+#define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x53)
+#define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7)
+#define SNARL_WDOG_TIMEOUT_MASK GENMASK(6, 4)
+#define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2)
+#define BITE_WDOG_TIMEOUT_MASK GENMASK(1, 0)
+
+struct smb_chg_param {
+ const char *name;
+ u16 reg;
+ int min_u;
+ int max_u;
+ int step_u;
+};
+
+struct smb_params {
+ struct smb_chg_param fcc;
+ struct smb_chg_param ov;
+};
+
+static struct smb_params v1_params = {
+ .fcc = {
+ .name = "fast charge current",
+ .reg = FAST_CHARGE_CURRENT_CFG_REG,
+ .min_u = 0,
+ .max_u = 6000000,
+ .step_u = 25000,
+ },
+ .ov = {
+ .name = "battery over voltage",
+ .reg = CHGR_BATTOV_CFG_REG,
+ .min_u = 2450000,
+ .max_u = 5000000,
+ .step_u = 10000,
+ },
+};
+
+struct smb_irq_info {
+ const char *name;
+ const irq_handler_t handler;
+ const bool wake;
+ int irq;
+};
+
+struct smb1355 {
+ struct device *dev;
+ char *name;
+ struct regmap *regmap;
+
+ struct smb_params param;
+
+ struct mutex write_lock;
+
+ struct power_supply *parallel_psy;
+ struct pmic_revid_data *pmic_rev_id;
+};
+
+static bool is_secure(struct smb1355 *chip, int addr)
+{
+ /* assume everything above 0xA0 is secure */
+ return (addr & 0xFF) >= 0xA0;
+}
+
+static int smb1355_read(struct smb1355 *chip, u16 addr, u8 *val)
+{
+ unsigned int temp;
+ int rc;
+
+ rc = regmap_read(chip->regmap, addr, &temp);
+ if (rc >= 0)
+ *val = (u8)temp;
+
+ return rc;
+}
+
+static int smb1355_masked_write(struct smb1355 *chip, u16 addr, u8 mask, u8 val)
+{
+ int rc;
+
+ mutex_lock(&chip->write_lock);
+ if (is_secure(chip, addr)) {
+ rc = regmap_write(chip->regmap, (addr & 0xFF00) | 0xD0, 0xA5);
+ if (rc < 0)
+ goto unlock;
+ }
+
+ rc = regmap_update_bits(chip->regmap, addr, mask, val);
+
+unlock:
+ mutex_unlock(&chip->write_lock);
+ return rc;
+}
+
+static int smb1355_write(struct smb1355 *chip, u16 addr, u8 val)
+{
+ int rc;
+
+ mutex_lock(&chip->write_lock);
+
+ if (is_secure(chip, addr)) {
+ rc = regmap_write(chip->regmap, (addr & ~(0xFF)) | 0xD0, 0xA5);
+ if (rc < 0)
+ goto unlock;
+ }
+
+ rc = regmap_write(chip->regmap, addr, val);
+
+unlock:
+ mutex_unlock(&chip->write_lock);
+ return rc;
+}
+
+static int smb1355_set_charge_param(struct smb1355 *chip,
+ struct smb_chg_param *param, int val_u)
+{
+ int rc;
+ u8 val_raw;
+
+ if (val_u > param->max_u || val_u < param->min_u) {
+ pr_err("%s: %d is out of range [%d, %d]\n",
+ param->name, val_u, param->min_u, param->max_u);
+ return -EINVAL;
+ }
+
+ val_raw = (val_u - param->min_u) / param->step_u;
+
+ rc = smb1355_write(chip, param->reg, val_raw);
+ if (rc < 0) {
+ pr_err("%s: Couldn't write 0x%02x to 0x%04x rc=%d\n",
+ param->name, val_raw, param->reg, rc);
+ return rc;
+ }
+
+ return rc;
+}
+
+static int smb1355_get_charge_param(struct smb1355 *chip,
+ struct smb_chg_param *param, int *val_u)
+{
+ int rc;
+ u8 val_raw;
+
+ rc = smb1355_read(chip, param->reg, &val_raw);
+ if (rc < 0) {
+ pr_err("%s: Couldn't read from 0x%04x rc=%d\n",
+ param->name, param->reg, rc);
+ return rc;
+ }
+
+ *val_u = val_raw * param->step_u + param->min_u;
+
+ return rc;
+}
+
+static irqreturn_t smb1355_handle_chg_state_change(int irq, void *data)
+{
+ struct smb1355 *chip = data;
+
+ if (chip->parallel_psy)
+ power_supply_changed(chip->parallel_psy);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t smb1355_handle_wdog_bark(int irq, void *data)
+{
+ struct smb1355 *chip = data;
+ int rc;
+
+ rc = smb1355_write(chip, BARK_BITE_WDOG_PET_REG,
+ BARK_BITE_WDOG_PET_BIT);
+ if (rc < 0)
+ pr_err("Couldn't pet the dog rc=%d\n", rc);
+
+ return IRQ_HANDLED;
+}
+
+/*****************************
+ * PARALLEL PSY REGISTRATION *
+ *****************************/
+
+static enum power_supply_property smb1355_parallel_props[] = {
+ POWER_SUPPLY_PROP_CHARGE_TYPE,
+ POWER_SUPPLY_PROP_CHARGING_ENABLED,
+ POWER_SUPPLY_PROP_PIN_ENABLED,
+ POWER_SUPPLY_PROP_INPUT_SUSPEND,
+ POWER_SUPPLY_PROP_VOLTAGE_MAX,
+ POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX,
+ POWER_SUPPLY_PROP_MODEL_NAME,
+};
+
+static int smb1355_get_prop_batt_charge_type(struct smb1355 *chip,
+ union power_supply_propval *val)
+{
+ int rc;
+ u8 stat;
+
+ rc = smb1355_read(chip, BATTERY_STATUS_3_REG, &stat);
+ if (rc < 0) {
+ pr_err("Couldn't read SMB1355_BATTERY_STATUS_3 rc=%d\n", rc);
+ return rc;
+ }
+
+ if (stat & ENABLE_CHARGING_BIT) {
+ if (stat & BATT_GT_PRE_TO_FAST_BIT)
+ val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST;
+ else
+ val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
+ } else {
+ val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE;
+ }
+
+ return rc;
+}
+
+static int smb1355_get_parallel_charging(struct smb1355 *chip, int *disabled)
+{
+ int rc;
+ u8 cfg2;
+
+ rc = smb1355_read(chip, CHGR_CFG2_REG, &cfg2);
+ if (rc < 0) {
+ pr_err("Couldn't read en_cmg_reg rc=%d\n", rc);
+ return rc;
+ }
+
+ if (cfg2 & CHG_EN_SRC_BIT)
+ *disabled = 0;
+ else
+ *disabled = 1;
+
+ return 0;
+}
+
+static int smb1355_parallel_get_prop(struct power_supply *psy,
+ enum power_supply_property prop,
+ union power_supply_propval *val)
+{
+ struct smb1355 *chip = power_supply_get_drvdata(psy);
+ u8 stat;
+ int rc = 0;
+
+ switch (prop) {
+ case POWER_SUPPLY_PROP_CHARGE_TYPE:
+ rc = smb1355_get_prop_batt_charge_type(chip, val);
+ break;
+ case POWER_SUPPLY_PROP_CHARGING_ENABLED:
+ rc = smb1355_read(chip, BATTERY_STATUS_3_REG, &stat);
+ if (rc >= 0)
+ val->intval = (bool)(stat & ENABLE_CHARGING_BIT);
+ break;
+ case POWER_SUPPLY_PROP_PIN_ENABLED:
+ rc = smb1355_read(chip, BATTERY_STATUS_2_REG, &stat);
+ if (rc >= 0)
+ val->intval = !(stat & DISABLE_CHARGING_BIT);
+ break;
+ case POWER_SUPPLY_PROP_INPUT_SUSPEND:
+ rc = smb1355_get_parallel_charging(chip, &val->intval);
+ break;
+ case POWER_SUPPLY_PROP_VOLTAGE_MAX:
+ rc = smb1355_get_charge_param(chip, &chip->param.ov,
+ &val->intval);
+ break;
+ case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
+ rc = smb1355_get_charge_param(chip, &chip->param.fcc,
+ &val->intval);
+ break;
+ case POWER_SUPPLY_PROP_MODEL_NAME:
+ val->strval = chip->name;
+ break;
+ case POWER_SUPPLY_PROP_PARALLEL_MODE:
+ val->intval = POWER_SUPPLY_PL_USBMID_USBMID;
+ break;
+ default:
+ pr_err_ratelimited("parallel psy get prop %d not supported\n",
+ prop);
+ return -EINVAL;
+ }
+
+ if (rc < 0) {
+ pr_debug("Couldn't get prop %d rc = %d\n", prop, rc);
+ return -ENODATA;
+ }
+
+ return rc;
+}
+
+static int smb1355_set_parallel_charging(struct smb1355 *chip, bool disable)
+{
+ int rc;
+
+ rc = smb1355_masked_write(chip, WD_CFG_REG, WDOG_TIMER_EN_BIT,
+ disable ? 0 : WDOG_TIMER_EN_BIT);
+ if (rc < 0) {
+ pr_err("Couldn't %s watchdog rc=%d\n",
+ disable ? "disable" : "enable", rc);
+ disable = true;
+ }
+
+ /*
+ * Configure charge enable for high polarity and
+ * When disabling charging set it to cmd register control(cmd bit=0)
+ * When enabling charging set it to pin control
+ */
+ rc = smb1355_masked_write(chip, CHGR_CFG2_REG,
+ CHG_EN_POLARITY_BIT | CHG_EN_SRC_BIT,
+ disable ? 0 : CHG_EN_SRC_BIT);
+ if (rc < 0) {
+ pr_err("Couldn't configure charge enable source rc=%d\n", rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static int smb1355_parallel_set_prop(struct power_supply *psy,
+ enum power_supply_property prop,
+ const union power_supply_propval *val)
+{
+ struct smb1355 *chip = power_supply_get_drvdata(psy);
+ int rc = 0;
+
+ switch (prop) {
+ case POWER_SUPPLY_PROP_INPUT_SUSPEND:
+ rc = smb1355_set_parallel_charging(chip, (bool)val->intval);
+ break;
+ case POWER_SUPPLY_PROP_VOLTAGE_MAX:
+ rc = smb1355_set_charge_param(chip, &chip->param.ov,
+ val->intval);
+ break;
+ case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
+ rc = smb1355_set_charge_param(chip, &chip->param.fcc,
+ val->intval);
+ break;
+ default:
+ pr_debug("parallel power supply set prop %d not supported\n",
+ prop);
+ return -EINVAL;
+ }
+
+ return rc;
+}
+
+static int smb1355_parallel_prop_is_writeable(struct power_supply *psy,
+ enum power_supply_property prop)
+{
+ return 0;
+}
+
+static struct power_supply_desc parallel_psy_desc = {
+ .name = "parallel",
+ .type = POWER_SUPPLY_TYPE_PARALLEL,
+ .properties = smb1355_parallel_props,
+ .num_properties = ARRAY_SIZE(smb1355_parallel_props),
+ .get_property = smb1355_parallel_get_prop,
+ .set_property = smb1355_parallel_set_prop,
+ .property_is_writeable = smb1355_parallel_prop_is_writeable,
+};
+
+static int smb1355_init_parallel_psy(struct smb1355 *chip)
+{
+ struct power_supply_config parallel_cfg = {};
+
+ parallel_cfg.drv_data = chip;
+ parallel_cfg.of_node = chip->dev->of_node;
+
+ /* change to smb1355's property list */
+ parallel_psy_desc.properties = smb1355_parallel_props;
+ parallel_psy_desc.num_properties = ARRAY_SIZE(smb1355_parallel_props);
+ chip->parallel_psy = devm_power_supply_register(chip->dev,
+ ¶llel_psy_desc,
+ ¶llel_cfg);
+ if (IS_ERR(chip->parallel_psy)) {
+ pr_err("Couldn't register parallel power supply\n");
+ return PTR_ERR(chip->parallel_psy);
+ }
+
+ return 0;
+}
+
+/***************************
+ * HARDWARE INITIALIZATION *
+ ***************************/
+
+static int smb1355_init_hw(struct smb1355 *chip)
+{
+ int rc;
+
+ /* enable watchdog bark and bite interrupts, and disable the watchdog */
+ rc = smb1355_masked_write(chip, WD_CFG_REG, WDOG_TIMER_EN_BIT
+ | WDOG_TIMER_EN_ON_PLUGIN_BIT | BITE_WDOG_INT_EN_BIT
+ | BARK_WDOG_INT_EN_BIT,
+ BITE_WDOG_INT_EN_BIT | BARK_WDOG_INT_EN_BIT);
+ if (rc < 0) {
+ pr_err("Couldn't configure the watchdog rc=%d\n", rc);
+ return rc;
+ }
+
+ /* disable charging when watchdog bites */
+ rc = smb1355_masked_write(chip, SNARL_BARK_BITE_WD_CFG_REG,
+ BITE_WDOG_DISABLE_CHARGING_CFG_BIT,
+ BITE_WDOG_DISABLE_CHARGING_CFG_BIT);
+ if (rc < 0) {
+ pr_err("Couldn't configure the watchdog bite rc=%d\n", rc);
+ return rc;
+ }
+
+ /* disable parallel charging path */
+ rc = smb1355_set_parallel_charging(chip, true);
+ if (rc < 0) {
+ pr_err("Couldn't disable parallel path rc=%d\n", rc);
+ return rc;
+ }
+
+ /* initialize FCC to 0 */
+ rc = smb1355_set_charge_param(chip, &chip->param.fcc, 0);
+ if (rc < 0) {
+ pr_err("Couldn't set 0 FCC rc=%d\n", rc);
+ return rc;
+ }
+
+ /* enable parallel current sensing */
+ rc = smb1355_masked_write(chip, CFG_REG,
+ VCHG_EN_CFG_BIT, VCHG_EN_CFG_BIT);
+ if (rc < 0) {
+ pr_err("Couldn't enable parallel current sensing rc=%d\n",
+ rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+/**************************
+ * INTERRUPT REGISTRATION *
+ **************************/
+static struct smb_irq_info smb1355_irqs[] = {
+ [0] = {
+ .name = "wdog-bark",
+ .handler = smb1355_handle_wdog_bark,
+ },
+ [1] = {
+ .name = "chg-state-change",
+ .handler = smb1355_handle_chg_state_change,
+ .wake = true,
+ },
+};
+
+static int smb1355_get_irq_index_byname(const char *irq_name)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(smb1355_irqs); i++) {
+ if (strcmp(smb1355_irqs[i].name, irq_name) == 0)
+ return i;
+ }
+
+ return -ENOENT;
+}
+
+static int smb1355_request_interrupt(struct smb1355 *chip,
+ struct device_node *node,
+ const char *irq_name)
+{
+ int rc = 0, irq, irq_index;
+
+ irq = of_irq_get_byname(node, irq_name);
+ if (irq < 0) {
+ pr_err("Couldn't get irq %s byname\n", irq_name);
+ return irq;
+ }
+
+ irq_index = smb1355_get_irq_index_byname(irq_name);
+ if (irq_index < 0) {
+ pr_err("%s is not a defined irq\n", irq_name);
+ return irq_index;
+ }
+
+ if (!smb1355_irqs[irq_index].handler)
+ return 0;
+
+ rc = devm_request_threaded_irq(chip->dev, irq, NULL,
+ smb1355_irqs[irq_index].handler,
+ IRQF_ONESHOT, irq_name, chip);
+ if (rc < 0) {
+ pr_err("Couldn't request irq %d rc=%d\n", irq, rc);
+ return rc;
+ }
+
+ if (smb1355_irqs[irq_index].wake)
+ enable_irq_wake(irq);
+
+ return rc;
+}
+
+static int smb1355_request_interrupts(struct smb1355 *chip)
+{
+ struct device_node *node = chip->dev->of_node;
+ struct device_node *child;
+ int rc = 0;
+ const char *name;
+ struct property *prop;
+
+ for_each_available_child_of_node(node, child) {
+ of_property_for_each_string(child, "interrupt-names",
+ prop, name) {
+ rc = smb1355_request_interrupt(chip, child, name);
+ if (rc < 0) {
+ pr_err("Couldn't request interrupt %s rc=%d\n",
+ name, rc);
+ return rc;
+ }
+ }
+ }
+
+ return rc;
+}
+
+/*********
+ * PROBE *
+ *********/
+static const struct of_device_id match_table[] = {
+ {
+ .compatible = "qcom,smb1355",
+ },
+ { },
+};
+
+static int smb1355_probe(struct platform_device *pdev)
+{
+ struct smb1355 *chip;
+ const struct of_device_id *id;
+ int rc = 0;
+
+ chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->dev = &pdev->dev;
+ chip->param = v1_params;
+ chip->name = "smb1355";
+ mutex_init(&chip->write_lock);
+
+ chip->regmap = dev_get_regmap(chip->dev->parent, NULL);
+ if (!chip->regmap) {
+ pr_err("parent regmap is missing\n");
+ return -EINVAL;
+ }
+
+ id = of_match_device(of_match_ptr(match_table), chip->dev);
+ if (!id) {
+ pr_err("Couldn't find a matching device\n");
+ return -ENODEV;
+ }
+
+ platform_set_drvdata(pdev, chip);
+
+ rc = smb1355_init_hw(chip);
+ if (rc < 0) {
+ pr_err("Couldn't initialize hardware rc=%d\n", rc);
+ goto cleanup;
+ }
+
+ rc = smb1355_init_parallel_psy(chip);
+ if (rc < 0) {
+ pr_err("Couldn't initialize parallel psy rc=%d\n", rc);
+ goto cleanup;
+ }
+
+ rc = smb1355_request_interrupts(chip);
+ if (rc < 0) {
+ pr_err("Couldn't request interrupts rc=%d\n", rc);
+ goto cleanup;
+ }
+
+ pr_info("%s probed successfully\n", chip->name);
+ return rc;
+
+cleanup:
+ platform_set_drvdata(pdev, NULL);
+ return rc;
+}
+
+static int smb1355_remove(struct platform_device *pdev)
+{
+ platform_set_drvdata(pdev, NULL);
+ return 0;
+}
+
+static struct platform_driver smb1355_driver = {
+ .driver = {
+ .name = "qcom,smb1355-charger",
+ .owner = THIS_MODULE,
+ .of_match_table = match_table,
+ },
+ .probe = smb1355_probe,
+ .remove = smb1355_remove,
+};
+module_platform_driver(smb1355_driver);
+
+MODULE_DESCRIPTION("QPNP SMB1355 Charger Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/regulator/cpr3-regulator.c b/drivers/regulator/cpr3-regulator.c
index 9566e24..c45fb0d 100644
--- a/drivers/regulator/cpr3-regulator.c
+++ b/drivers/regulator/cpr3-regulator.c
@@ -177,6 +177,7 @@
#define CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN BIT(27)
#define CPR4_REG_MISC 0x700
+#define CPR4_MISC_RESET_STEP_QUOT_LOOP_EN BIT(2)
#define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK GENMASK(23, 20)
#define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT 20
#define CPR4_MISC_TEMP_SENSOR_ID_START_MASK GENMASK(27, 24)
@@ -723,6 +724,11 @@
int thread_id = 0;
u64 temp;
+ if (ctrl->reset_step_quot_loop_en)
+ cpr3_masked_write(ctrl, CPR4_REG_MISC,
+ CPR4_MISC_RESET_STEP_QUOT_LOOP_EN,
+ CPR4_MISC_RESET_STEP_QUOT_LOOP_EN);
+
if (ctrl->supports_hw_closed_loop) {
if (ctrl->saw_use_unit_mV)
pmic_step_size = ctrl->step_volt / 1000;
@@ -1355,6 +1361,11 @@
}
}
+ if (ctrl->reset_step_quot_loop_en)
+ cpr3_masked_write(ctrl, CPR4_REG_MISC,
+ CPR4_MISC_RESET_STEP_QUOT_LOOP_EN,
+ CPR4_MISC_RESET_STEP_QUOT_LOOP_EN);
+
if (ctrl->saw_use_unit_mV)
pmic_step_size = ctrl->step_volt / 1000;
cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
diff --git a/drivers/regulator/cpr3-regulator.h b/drivers/regulator/cpr3-regulator.h
index 570ddfc..8535020 100644
--- a/drivers/regulator/cpr3-regulator.h
+++ b/drivers/regulator/cpr3-regulator.h
@@ -756,6 +756,12 @@
* @panic_notifier: Notifier block registered to global panic notifier list.
* @support_ldo300_vreg: Boolean value which indicates that this CPR controller
* manages an underlying LDO regulator of type LDO300.
+ * @reset_step_quot_loop_en: Boolean value which indicates that this CPR
+ * controller should be configured to reset step_quot on
+ * each loop_en = 0 transition. This configuration allows
+ * the CPR controller to first use the default step_quot
+ * and then later switch to the run-time calibrated
+ * step_quot.
*
* This structure contains both configuration and runtime state data. The
* elements cpr_allowed_sw, use_hw_closed_loop, aggr_corner, cpr_enabled,
@@ -866,6 +872,7 @@
struct cpr3_panic_regs_info *panic_regs_info;
struct notifier_block panic_notifier;
bool support_ldo300_vreg;
+ bool reset_step_quot_loop_en;
};
/* Used for rounding voltages to the closest physically available set point. */
diff --git a/drivers/regulator/cpr3-util.c b/drivers/regulator/cpr3-util.c
index 648d396..3035155 100644
--- a/drivers/regulator/cpr3-util.c
+++ b/drivers/regulator/cpr3-util.c
@@ -1224,6 +1224,14 @@
}
/*
+ * Reset step_quot to default on each loop_en = 0 transition is
+ * optional.
+ */
+ ctrl->reset_step_quot_loop_en
+ = of_property_read_bool(ctrl->dev->of_node,
+ "qcom,cpr-reset-step-quot-loop-en");
+
+ /*
* Regulator device handles are not necessary for CPRh controllers
* since communication with the regulators is completely managed
* in hardware.
diff --git a/drivers/scsi/storvsc_drv.c b/drivers/scsi/storvsc_drv.c
index 3f218f5..c5ab1b0 100644
--- a/drivers/scsi/storvsc_drv.c
+++ b/drivers/scsi/storvsc_drv.c
@@ -400,8 +400,6 @@
*/
static int storvsc_timeout = 180;
-static int msft_blist_flags = BLIST_TRY_VPD_PAGES;
-
#if IS_ENABLED(CONFIG_SCSI_FC_ATTRS)
static struct scsi_transport_template *fc_transport_template;
#endif
@@ -1283,6 +1281,22 @@
return ret;
}
+static int storvsc_device_alloc(struct scsi_device *sdevice)
+{
+ /*
+ * Set blist flag to permit the reading of the VPD pages even when
+ * the target may claim SPC-2 compliance. MSFT targets currently
+ * claim SPC-2 compliance while they implement post SPC-2 features.
+ * With this flag we can correctly handle WRITE_SAME_16 issues.
+ *
+ * Hypervisor reports SCSI_UNKNOWN type for DVD ROM device but
+ * still supports REPORT LUN.
+ */
+ sdevice->sdev_bflags = BLIST_REPORTLUN2 | BLIST_TRY_VPD_PAGES;
+
+ return 0;
+}
+
static int storvsc_device_configure(struct scsi_device *sdevice)
{
@@ -1298,14 +1312,6 @@
sdevice->no_write_same = 1;
/*
- * Add blist flags to permit the reading of the VPD pages even when
- * the target may claim SPC-2 compliance. MSFT targets currently
- * claim SPC-2 compliance while they implement post SPC-2 features.
- * With this patch we can correctly handle WRITE_SAME_16 issues.
- */
- sdevice->sdev_bflags |= msft_blist_flags;
-
- /*
* If the host is WIN8 or WIN8 R2, claim conformance to SPC-3
* if the device is a MSFT virtual device. If the host is
* WIN10 or newer, allow write_same.
@@ -1569,6 +1575,7 @@
.eh_host_reset_handler = storvsc_host_reset_handler,
.proc_name = "storvsc_host",
.eh_timed_out = storvsc_eh_timed_out,
+ .slave_alloc = storvsc_device_alloc,
.slave_configure = storvsc_device_configure,
.cmd_per_lun = 255,
.this_id = -1,
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 69e3032..3311380 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -655,3 +655,11 @@
memory location. These messages provide statistical information about
the low power modes that RPM enters. The drivers outputs the message
via a debugfs node.
+
+config QCOM_FORCE_WDOG_BITE_ON_PANIC
+ bool "QCOM force watchdog bite"
+ depends on QCOM_WATCHDOG_V2
+ help
+ This forces a watchdog bite when the device restarts due to a
+ kernel panic. On certain MSM SoCs, this provides us
+ additional debugging information.
diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c
index 0c2ba4d..5cc04c0 100644
--- a/drivers/soc/qcom/cmd-db.c
+++ b/drivers/soc/qcom/cmd-db.c
@@ -241,18 +241,28 @@
static int cmd_db_dev_probe(struct platform_device *pdev)
{
- struct resource *res;
+ struct resource res;
+ void __iomem *dict;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
+ dict = of_iomap(pdev->dev.of_node, 0);
+ if (!dict) {
cmd_db_status = -ENOMEM;
goto failed;
}
- start_addr = devm_ioremap_resource(&pdev->dev, res);
+ /*
+ * Read start address and size of the command DB address from
+ * shared dictionary location
+ */
+ res.start = readl_relaxed(dict);
+ res.end = res.start + readl_relaxed(dict + 0x4);
+ res.flags = IORESOURCE_MEM;
+ iounmap(dict);
- cmd_db_header = devm_kzalloc(&pdev->dev, sizeof(*cmd_db_header),
- GFP_KERNEL);
+ start_addr = devm_ioremap_resource(&pdev->dev, &res);
+
+ cmd_db_header = devm_kzalloc(&pdev->dev,
+ sizeof(*cmd_db_header), GFP_KERNEL);
if (!cmd_db_header) {
cmd_db_status = -ENOMEM;
diff --git a/drivers/soc/qcom/glink_private.h b/drivers/soc/qcom/glink_private.h
index c837bd8..9810207 100644
--- a/drivers/soc/qcom/glink_private.h
+++ b/drivers/soc/qcom/glink_private.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -700,6 +700,7 @@
* edge: The G-Link edge name for the channel associated with
* this callback data
* do_cleanup_data: Structure containing the G-Link SSR do_cleanup message.
+ * cb_kref: Kref object to maintain cb_data reference.
*/
struct ssr_notify_data {
bool tx_done;
@@ -707,6 +708,7 @@
bool responded;
const char *edge;
struct do_cleanup_msg *do_cleanup_data;
+ struct kref cb_kref;
};
/**
@@ -741,6 +743,7 @@
int notify_list_len;
bool link_up;
spinlock_t link_up_lock;
+ spinlock_t cb_lock;
};
/**
diff --git a/drivers/soc/qcom/glink_ssr.c b/drivers/soc/qcom/glink_ssr.c
index b24598a..4737288 100644
--- a/drivers/soc/qcom/glink_ssr.c
+++ b/drivers/soc/qcom/glink_ssr.c
@@ -115,6 +115,44 @@
static atomic_t responses_remaining = ATOMIC_INIT(0);
static wait_queue_head_t waitqueue;
+/**
+ * cb_data_release() - Free cb_data and set to NULL
+ * @kref_ptr: pointer to kref.
+ *
+ * This function releses cb_data.
+ */
+static inline void cb_data_release(struct kref *kref_ptr)
+{
+ struct ssr_notify_data *cb_data;
+
+ cb_data = container_of(kref_ptr, struct ssr_notify_data, cb_kref);
+ kfree(cb_data);
+}
+
+/**
+ * check_and_get_cb_data() - Try to get reference to kref of cb_data
+ * @ss_info: pointer to subsystem info structure.
+ *
+ * Return: NULL is cb_data is NULL, pointer to cb_data otherwise
+ */
+static struct ssr_notify_data *check_and_get_cb_data(
+ struct subsys_info *ss_info)
+{
+ struct ssr_notify_data *cb_data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ss_info->cb_lock, flags);
+ if (ss_info->cb_data == NULL) {
+ GLINK_SSR_LOG("<SSR> %s: cb_data is NULL\n", __func__);
+ spin_unlock_irqrestore(&ss_info->cb_lock, flags);
+ return 0;
+ }
+ kref_get(&ss_info->cb_data->cb_kref);
+ cb_data = ss_info->cb_data;
+ spin_unlock_irqrestore(&ss_info->cb_lock, flags);
+ return cb_data;
+}
+
static void rx_done_cb_worker(struct work_struct *work)
{
struct rx_done_ch_work *rx_done_work =
@@ -340,8 +378,10 @@
if (WARN_ON(!ss_info->cb_data))
return;
- kfree(ss_info->cb_data);
+ spin_lock_irqsave(&ss_info->cb_lock, flags);
+ kref_put(&ss_info->cb_data->cb_kref, cb_data_release);
ss_info->cb_data = NULL;
+ spin_unlock_irqrestore(&ss_info->cb_lock, flags);
kfree(close_work);
}
@@ -508,13 +548,18 @@
return -ENODEV;
}
handle = ss_info_channel->handle;
- ss_leaf_entry->cb_data = ss_info_channel->cb_data;
+ ss_leaf_entry->cb_data = check_and_get_cb_data(
+ ss_info_channel);
+ if (!ss_leaf_entry->cb_data) {
+ GLINK_SSR_LOG("<SSR> %s: CB data is NULL\n", __func__);
+ atomic_dec(&responses_remaining);
+ continue;
+ }
spin_lock_irqsave(&ss_info->link_up_lock, flags);
if (IS_ERR_OR_NULL(ss_info_channel->handle) ||
- !ss_info_channel->cb_data ||
!ss_info_channel->link_up ||
- ss_info_channel->cb_data->event
+ ss_leaf_entry->cb_data->event
!= GLINK_CONNECTED) {
GLINK_SSR_LOG(
@@ -527,6 +572,8 @@
spin_unlock_irqrestore(&ss_info->link_up_lock, flags);
atomic_dec(&responses_remaining);
+ kref_put(&ss_leaf_entry->cb_data->cb_kref,
+ cb_data_release);
continue;
}
spin_unlock_irqrestore(&ss_info->link_up_lock, flags);
@@ -537,6 +584,8 @@
GLINK_SSR_ERR(
"%s %s: Could not allocate do_cleanup_msg\n",
"<SSR>", __func__);
+ kref_put(&ss_leaf_entry->cb_data->cb_kref,
+ cb_data_release);
return -ENOMEM;
}
@@ -568,6 +617,8 @@
__func__);
}
atomic_dec(&responses_remaining);
+ kref_put(&ss_leaf_entry->cb_data->cb_kref,
+ cb_data_release);
continue;
}
@@ -597,10 +648,12 @@
__func__);
}
atomic_dec(&responses_remaining);
+ kref_put(&ss_leaf_entry->cb_data->cb_kref,
+ cb_data_release);
continue;
}
-
sequence_number++;
+ kref_put(&ss_leaf_entry->cb_data->cb_kref, cb_data_release);
}
wait_ret = wait_event_timeout(waitqueue,
@@ -609,6 +662,21 @@
list_for_each_entry(ss_leaf_entry, &ss_info->notify_list,
notify_list_node) {
+ ss_info_channel =
+ get_info_for_subsystem(ss_leaf_entry->ssr_name);
+ if (ss_info_channel == NULL) {
+ GLINK_SSR_ERR(
+ "<SSR> %s: unable to find subsystem name\n",
+ __func__);
+ continue;
+ }
+
+ ss_leaf_entry->cb_data = check_and_get_cb_data(
+ ss_info_channel);
+ if (!ss_leaf_entry->cb_data) {
+ GLINK_SSR_LOG("<SSR> %s: CB data is NULL\n", __func__);
+ continue;
+ }
if (!wait_ret && !IS_ERR_OR_NULL(ss_leaf_entry->cb_data)
&& !ss_leaf_entry->cb_data->responded) {
GLINK_SSR_ERR("%s %s: Subsystem %s %s\n",
@@ -627,6 +695,7 @@
if (!IS_ERR_OR_NULL(ss_leaf_entry->cb_data))
ss_leaf_entry->cb_data->responded = false;
+ kref_put(&ss_leaf_entry->cb_data->cb_kref, cb_data_release);
}
complete(¬ifications_successful_complete);
return 0;
@@ -645,6 +714,7 @@
struct glink_open_config open_cfg;
struct ssr_notify_data *cb_data = NULL;
void *handle = NULL;
+ unsigned long flags;
if (!ss_info) {
GLINK_SSR_ERR("<SSR> %s: ss_info structure invalid\n",
@@ -661,7 +731,10 @@
cb_data->responded = false;
cb_data->event = GLINK_SSR_EVENT_INIT;
cb_data->edge = ss_info->edge;
+ spin_lock_irqsave(&ss_info->cb_lock, flags);
ss_info->cb_data = cb_data;
+ kref_init(&cb_data->cb_kref);
+ spin_unlock_irqrestore(&ss_info->cb_lock, flags);
memset(&open_cfg, 0, sizeof(struct glink_open_config));
@@ -877,6 +950,7 @@
ss_info->link_state_handle = NULL;
ss_info->cb_data = NULL;
spin_lock_init(&ss_info->link_up_lock);
+ spin_lock_init(&ss_info->cb_lock);
nb = kmalloc(sizeof(struct restart_notifier_block), GFP_KERNEL);
if (!nb) {
diff --git a/drivers/soc/qcom/msm_bus/msm_bus_fabric_rpmh.c b/drivers/soc/qcom/msm_bus/msm_bus_fabric_rpmh.c
index 91d6349..c950367 100644
--- a/drivers/soc/qcom/msm_bus/msm_bus_fabric_rpmh.c
+++ b/drivers/soc/qcom/msm_bus/msm_bus_fabric_rpmh.c
@@ -337,8 +337,8 @@
tcs_cmd_gen(cur_bcm, &cmdlist_active[k],
cur_bcm->node_vec[ACTIVE_CTX].vec_a,
cur_bcm->node_vec[ACTIVE_CTX].vec_b, commit);
- k++;
last_tcs = k;
+ k++;
cur_bcm->updated = true;
}
}
diff --git a/drivers/soc/qcom/pil-msa.c b/drivers/soc/qcom/pil-msa.c
index fb3d7d9..c5ba279 100644
--- a/drivers/soc/qcom/pil-msa.c
+++ b/drivers/soc/qcom/pil-msa.c
@@ -75,6 +75,10 @@
#define MSS_RESTART_ID 0xA
#define MSS_MAGIC 0XAABADEAD
+
+#define MSS_PDC_OFFSET 8
+#define MSS_PDC_MASK BIT(MSS_PDC_OFFSET)
+
enum scm_cmd {
PAS_MEM_SETUP_CMD = 2,
};
@@ -204,6 +208,33 @@
clk_disable_unprepare(drv->ahb_clk);
}
+static void pil_mss_pdc_sync(struct q6v5_data *drv, bool pdc_sync)
+{
+ u32 val = 0;
+
+ if (drv->pdc_sync) {
+ val = readl_relaxed(drv->pdc_sync);
+ if (pdc_sync)
+ val |= MSS_PDC_MASK;
+ else
+ val &= ~MSS_PDC_MASK;
+ writel_relaxed(val, drv->pdc_sync);
+ /* Ensure PDC is written before next write */
+ wmb();
+ udelay(2);
+ }
+}
+
+static void pil_mss_alt_reset(struct q6v5_data *drv, u32 val)
+{
+ if (drv->alt_reset) {
+ writel_relaxed(val, drv->alt_reset);
+ /* Ensure alt reset is written before restart reg */
+ wmb();
+ udelay(2);
+ }
+}
+
static int pil_mss_restart_reg(struct q6v5_data *drv, u32 mss_restart)
{
int ret = 0;
@@ -235,6 +266,32 @@
return ret;
}
+static int pil_mss_assert_resets(struct q6v5_data *drv)
+{
+ int ret = 0;
+
+ pil_mss_pdc_sync(drv, 1);
+ pil_mss_alt_reset(drv, 1);
+ ret = pil_mss_restart_reg(drv, true);
+
+ return ret;
+}
+
+static int pil_mss_deassert_resets(struct q6v5_data *drv)
+{
+ int ret = 0;
+
+ ret = pil_mss_restart_reg(drv, 0);
+ if (ret)
+ return ret;
+ /* Wait 6 32kHz sleep cycles for reset */
+ udelay(200);
+ pil_mss_alt_reset(drv, 0);
+ pil_mss_pdc_sync(drv, false);
+
+ return ret;
+}
+
static int pil_msa_wait_for_mba_ready(struct q6v5_data *drv)
{
struct device *dev = drv->desc.dev;
@@ -304,7 +361,10 @@
ret);
}
- ret = pil_mss_restart_reg(drv, 1);
+ pil_mss_assert_resets(drv);
+ /* Wait 6 32kHz sleep cycles for reset */
+ udelay(200);
+ ret = pil_mss_deassert_resets(drv);
if (drv->is_booted) {
pil_mss_disable_clks(drv);
@@ -450,6 +510,7 @@
{
struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
phys_addr_t start_addr = pil_get_entry_addr(pil);
+ u32 debug_val;
int ret;
if (drv->mba_dp_phys)
@@ -463,15 +524,22 @@
if (ret)
goto err_power;
- /* Deassert reset to subsystem and wait for propagation */
- ret = pil_mss_restart_reg(drv, 0);
- if (ret)
- goto err_restart;
-
ret = pil_mss_enable_clks(drv);
if (ret)
goto err_clks;
+ /* Save state of modem debug register before full reset */
+ debug_val = readl_relaxed(drv->reg_base + QDSP6SS_DBG_CFG);
+
+ /* Assert reset to subsystem */
+ pil_mss_assert_resets(drv);
+ /* Wait 6 32kHz sleep cycles for reset */
+ udelay(200);
+ ret = pil_mss_deassert_resets(drv);
+ if (ret)
+ goto err_restart;
+
+ writel_relaxed(debug_val, drv->reg_base + QDSP6SS_DBG_CFG);
if (modem_dbg_cfg)
writel_relaxed(modem_dbg_cfg, drv->reg_base + QDSP6SS_DBG_CFG);
@@ -519,12 +587,11 @@
err_q6v5_reset:
modem_log_rmb_regs(drv->rmb_base);
+err_restart:
pil_mss_disable_clks(drv);
if (drv->ahb_clk_vote)
clk_disable_unprepare(drv->ahb_clk);
err_clks:
- pil_mss_restart_reg(drv, 1);
-err_restart:
pil_mss_power_down(drv);
err_power:
return ret;
diff --git a/drivers/soc/qcom/pil-q6v5-mss.c b/drivers/soc/qcom/pil-q6v5-mss.c
index bbde4b6..df0c609c 100644
--- a/drivers/soc/qcom/pil-q6v5-mss.c
+++ b/drivers/soc/qcom/pil-q6v5-mss.c
@@ -284,6 +284,20 @@
if (!q6->restart_reg)
return -ENOMEM;
+ q6->pdc_sync = NULL;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pdc_sync");
+ if (res) {
+ q6->pdc_sync = devm_ioremap(&pdev->dev,
+ res->start, resource_size(res));
+ }
+
+ q6->alt_reset = NULL;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "alt_reset");
+ if (res) {
+ q6->alt_reset = devm_ioremap(&pdev->dev,
+ res->start, resource_size(res));
+ }
+
q6->vreg = NULL;
prop = of_find_property(pdev->dev.of_node, "vdd_mss-supply", NULL);
diff --git a/drivers/soc/qcom/pil-q6v5.h b/drivers/soc/qcom/pil-q6v5.h
index 1725253..9b4c811 100644
--- a/drivers/soc/qcom/pil-q6v5.h
+++ b/drivers/soc/qcom/pil-q6v5.h
@@ -44,6 +44,8 @@
void __iomem *axi_halt_mss;
void __iomem *axi_halt_nc;
void __iomem *restart_reg;
+ void __iomem *pdc_sync;
+ void __iomem *alt_reset;
struct regulator *vreg;
struct regulator *vreg_cx;
struct regulator *vreg_mx;
diff --git a/drivers/soc/qcom/qdsp6v2/Makefile b/drivers/soc/qcom/qdsp6v2/Makefile
index 8c5b0d0..b2cf03c 100644
--- a/drivers/soc/qcom/qdsp6v2/Makefile
+++ b/drivers/soc/qcom/qdsp6v2/Makefile
@@ -1,7 +1,7 @@
-obj-$(CONFIG_MSM_QDSP6_APRV2) += apr.o apr_v2.o apr_tal.o voice_svc.o
-obj-$(CONFIG_MSM_QDSP6_APRV3) += apr.o apr_v3.o apr_tal.o voice_svc.o
-obj-$(CONFIG_MSM_QDSP6_APRV2_GLINK) += apr.o apr_v2.o apr_tal_glink.o voice_svc.o
-obj-$(CONFIG_MSM_QDSP6_APRV3_GLINK) += apr.o apr_v3.o apr_tal_glink.o voice_svc.o
+obj-$(CONFIG_MSM_QDSP6_APRV2) += apr.o apr_v2.o apr_tal.o
+obj-$(CONFIG_MSM_QDSP6_APRV3) += apr.o apr_v3.o apr_tal.o
+obj-$(CONFIG_MSM_QDSP6_APRV2_GLINK) += apr.o apr_v2.o apr_tal_glink.o
+obj-$(CONFIG_MSM_QDSP6_APRV3_GLINK) += apr.o apr_v3.o apr_tal_glink.o
obj-$(CONFIG_SND_SOC_MSM_QDSP6V2_INTF) += msm_audio_ion.o
obj-$(CONFIG_MSM_ADSP_LOADER) += adsp-loader.o
obj-$(CONFIG_MSM_QDSP6_SSR) += audio_ssr.o
diff --git a/drivers/soc/qcom/qdsp6v2/voice_svc.c b/drivers/soc/qcom/qdsp6v2/voice_svc.c
deleted file mode 100644
index f3b1b83..0000000
--- a/drivers/soc/qcom/qdsp6v2/voice_svc.c
+++ /dev/null
@@ -1,837 +0,0 @@
-/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/cdev.h>
-#include <linux/qdsp6v2/apr_tal.h>
-#include <linux/qdsp6v2/apr.h>
-#include <sound/voice_svc.h>
-
-#define MINOR_NUMBER 1
-#define APR_MAX_RESPONSE 10
-#define TIMEOUT_MS 1000
-
-#define MAX(a, b) ((a) >= (b) ? (a) : (b))
-
-struct voice_svc_device {
- struct cdev *cdev;
- struct device *dev;
- int major;
-};
-
-struct voice_svc_prvt {
- void *apr_q6_mvm;
- void *apr_q6_cvs;
- uint16_t response_count;
- struct list_head response_queue;
- wait_queue_head_t response_wait;
- spinlock_t response_lock;
- /*
- * This mutex ensures responses are processed in sequential order and
- * that no two threads access and free the same response at the same
- * time.
- */
- struct mutex response_mutex_lock;
-};
-
-struct apr_data {
- struct apr_hdr hdr;
- __u8 payload[0];
-} __packed;
-
-struct apr_response_list {
- struct list_head list;
- struct voice_svc_cmd_response resp;
-};
-
-static struct voice_svc_device *voice_svc_dev;
-static struct class *voice_svc_class;
-static bool reg_dummy_sess;
-static void *dummy_q6_mvm;
-static void *dummy_q6_cvs;
-dev_t device_num;
-
-static int voice_svc_dummy_reg(void);
-static int32_t qdsp_dummy_apr_callback(struct apr_client_data *data,
- void *priv);
-
-static int32_t qdsp_apr_callback(struct apr_client_data *data, void *priv)
-{
- struct voice_svc_prvt *prtd;
- struct apr_response_list *response_list;
- unsigned long spin_flags;
-
- if ((data == NULL) || (priv == NULL)) {
- pr_err("%s: data or priv is NULL\n", __func__);
-
- return -EINVAL;
- }
-
- prtd = (struct voice_svc_prvt *)priv;
- if (prtd == NULL) {
- pr_err("%s: private data is NULL\n", __func__);
-
- return -EINVAL;
- }
-
- pr_debug("%s: data->opcode %x\n", __func__,
- data->opcode);
-
- if (data->opcode == RESET_EVENTS) {
- if (data->reset_proc == APR_DEST_QDSP6) {
- pr_debug("%s: Received ADSP reset event\n", __func__);
-
- if (prtd->apr_q6_mvm != NULL) {
- apr_reset(prtd->apr_q6_mvm);
- prtd->apr_q6_mvm = NULL;
- }
-
- if (prtd->apr_q6_cvs != NULL) {
- apr_reset(prtd->apr_q6_cvs);
- prtd->apr_q6_cvs = NULL;
- }
- } else if (data->reset_proc == APR_DEST_MODEM) {
- pr_debug("%s: Received Modem reset event\n", __func__);
- }
- /* Set the remaining member variables to default values
- * for RESET_EVENTS
- */
- data->payload_size = 0;
- data->payload = NULL;
- data->src_port = 0;
- data->dest_port = 0;
- data->token = 0;
- }
-
- spin_lock_irqsave(&prtd->response_lock, spin_flags);
-
- if (prtd->response_count < APR_MAX_RESPONSE) {
- response_list = kmalloc(sizeof(struct apr_response_list) +
- data->payload_size, GFP_ATOMIC);
- if (response_list == NULL) {
- spin_unlock_irqrestore(&prtd->response_lock,
- spin_flags);
- return -ENOMEM;
- }
-
- response_list->resp.src_port = data->src_port;
-
- /* Reverting the bit manipulation done in voice_svc_update_hdr
- * to the src_port which is returned to us as dest_port.
- */
- response_list->resp.dest_port = ((data->dest_port) >> 8);
- response_list->resp.token = data->token;
- response_list->resp.opcode = data->opcode;
- response_list->resp.payload_size = data->payload_size;
- if (data->payload != NULL && data->payload_size > 0) {
- memcpy(response_list->resp.payload, data->payload,
- data->payload_size);
- }
-
- list_add_tail(&response_list->list, &prtd->response_queue);
- prtd->response_count++;
- spin_unlock_irqrestore(&prtd->response_lock, spin_flags);
-
- wake_up(&prtd->response_wait);
- } else {
- spin_unlock_irqrestore(&prtd->response_lock, spin_flags);
- pr_err("%s: Response dropped since the queue is full\n",
- __func__);
- }
-
- return 0;
-}
-
-static int32_t qdsp_dummy_apr_callback(struct apr_client_data *data, void *priv)
-{
- /* Do Nothing */
- return 0;
-}
-
-static void voice_svc_update_hdr(struct voice_svc_cmd_request *apr_req_data,
- struct apr_data *aprdata)
-{
-
- aprdata->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD,
- APR_HDR_LEN(sizeof(struct apr_hdr)),
- APR_PKT_VER);
- /* Bit manipulation is done on src_port so that a unique ID is sent.
- * This manipulation can be used in the future where the same service
- * is tried to open multiple times with the same src_port. At that
- * time 0x0001 can be replaced with other values depending on the
- * count.
- */
- aprdata->hdr.src_port = ((apr_req_data->src_port) << 8 | 0x0001);
- aprdata->hdr.dest_port = apr_req_data->dest_port;
- aprdata->hdr.token = apr_req_data->token;
- aprdata->hdr.opcode = apr_req_data->opcode;
- aprdata->hdr.pkt_size = APR_PKT_SIZE(APR_HDR_SIZE,
- apr_req_data->payload_size);
- memcpy(aprdata->payload, apr_req_data->payload,
- apr_req_data->payload_size);
-}
-
-static int voice_svc_send_req(struct voice_svc_cmd_request *apr_request,
- struct voice_svc_prvt *prtd)
-{
- int ret = 0;
- void *apr_handle = NULL;
- struct apr_data *aprdata = NULL;
- uint32_t user_payload_size;
- uint32_t payload_size;
-
- pr_debug("%s\n", __func__);
-
- if (apr_request == NULL) {
- pr_err("%s: apr_request is NULL\n", __func__);
-
- ret = -EINVAL;
- goto done;
- }
-
- user_payload_size = apr_request->payload_size;
- payload_size = sizeof(struct apr_data) + user_payload_size;
-
- if (payload_size <= user_payload_size) {
- pr_err("%s: invalid payload size ( 0x%x ).\n",
- __func__, user_payload_size);
- ret = -EINVAL;
- goto done;
- } else {
- aprdata = kmalloc(payload_size, GFP_KERNEL);
- if (aprdata == NULL) {
- ret = -ENOMEM;
- goto done;
- }
- }
-
- voice_svc_update_hdr(apr_request, aprdata);
-
- if (!strcmp(apr_request->svc_name, VOICE_SVC_CVS_STR)) {
- apr_handle = prtd->apr_q6_cvs;
- } else if (!strcmp(apr_request->svc_name, VOICE_SVC_MVM_STR)) {
- apr_handle = prtd->apr_q6_mvm;
- } else {
- pr_err("%s: Invalid service %.*s\n", __func__,
- MAX_APR_SERVICE_NAME_LEN, apr_request->svc_name);
-
- ret = -EINVAL;
- goto done;
- }
-
- ret = apr_send_pkt(apr_handle, (uint32_t *)aprdata);
-
- if (ret < 0) {
- pr_err("%s: Fail in sending request %d\n",
- __func__, ret);
- ret = -EINVAL;
- } else {
- pr_debug("%s: apr packet sent successfully %d\n",
- __func__, ret);
- ret = 0;
- }
-
-done:
- kfree(aprdata);
- return ret;
-}
-static int voice_svc_reg(char *svc, uint32_t src_port,
- struct voice_svc_prvt *prtd, void **handle)
-{
- int ret = 0;
-
- pr_debug("%s\n", __func__);
-
- if (handle == NULL) {
- pr_err("%s: handle is NULL\n", __func__);
- ret = -EINVAL;
- goto done;
- }
-
- if (*handle != NULL) {
- pr_err("%s: svc handle not NULL\n", __func__);
- ret = -EINVAL;
- goto done;
- }
-
- if (src_port == (APR_MAX_PORTS - 1)) {
- pr_err("%s: SRC port reserved for dummy session\n", __func__);
- pr_err("%s: Unable to register %s\n", __func__, svc);
- ret = -EINVAL;
- goto done;
- }
-
- *handle = apr_register("ADSP",
- svc, qdsp_apr_callback,
- ((src_port) << 8 | 0x0001),
- prtd);
-
- if (*handle == NULL) {
- pr_err("%s: Unable to register %s\n",
- __func__, svc);
-
- ret = -EFAULT;
- goto done;
- }
- pr_debug("%s: Register %s successful\n",
- __func__, svc);
-done:
- return ret;
-}
-
-static int voice_svc_dereg(char *svc, void **handle)
-{
- int ret = 0;
-
- pr_debug("%s\n", __func__);
-
- if (handle == NULL) {
- pr_err("%s: handle is NULL\n", __func__);
- ret = -EINVAL;
- goto done;
- }
-
- if (*handle == NULL) {
- pr_err("%s: svc handle is NULL\n", __func__);
- ret = -EINVAL;
- goto done;
- }
-
- ret = apr_deregister(*handle);
- if (ret) {
- pr_err("%s: Unable to deregister service %s; error: %d\n",
- __func__, svc, ret);
-
- goto done;
- }
- *handle = NULL;
- pr_debug("%s: deregister %s successful\n", __func__, svc);
-
-done:
- return ret;
-}
-
-static int process_reg_cmd(struct voice_svc_register *apr_reg_svc,
- struct voice_svc_prvt *prtd)
-{
- int ret = 0;
- char *svc = NULL;
- void **handle = NULL;
-
- pr_debug("%s\n", __func__);
-
- if (!strcmp(apr_reg_svc->svc_name, VOICE_SVC_MVM_STR)) {
- svc = VOICE_SVC_MVM_STR;
- handle = &prtd->apr_q6_mvm;
- } else if (!strcmp(apr_reg_svc->svc_name, VOICE_SVC_CVS_STR)) {
- svc = VOICE_SVC_CVS_STR;
- handle = &prtd->apr_q6_cvs;
- } else {
- pr_err("%s: Invalid Service: %.*s\n", __func__,
- MAX_APR_SERVICE_NAME_LEN, apr_reg_svc->svc_name);
- ret = -EINVAL;
- goto done;
- }
-
- if (apr_reg_svc->reg_flag) {
- ret = voice_svc_reg(svc, apr_reg_svc->src_port, prtd,
- handle);
- } else if (!apr_reg_svc->reg_flag) {
- ret = voice_svc_dereg(svc, handle);
- }
-
-done:
- return ret;
-}
-
-static ssize_t voice_svc_write(struct file *file, const char __user *buf,
- size_t count, loff_t *ppos)
-{
- int ret = 0;
- struct voice_svc_prvt *prtd;
- struct voice_svc_write_msg *data = NULL;
- uint32_t cmd;
- struct voice_svc_register *register_data = NULL;
- struct voice_svc_cmd_request *request_data = NULL;
- uint32_t request_payload_size;
-
- pr_debug("%s\n", __func__);
-
- /*
- * Check if enough memory is allocated to parse the message type.
- * Will check there is enough to hold the payload later.
- */
- if (count >= sizeof(struct voice_svc_write_msg)) {
- data = kmalloc(count, GFP_KERNEL);
- } else {
- pr_debug("%s: invalid data size\n", __func__);
- ret = -EINVAL;
- goto done;
- }
-
- if (data == NULL) {
- pr_err("%s: data kmalloc failed.\n", __func__);
-
- ret = -ENOMEM;
- goto done;
- }
-
- ret = copy_from_user(data, buf, count);
- if (ret) {
- pr_err("%s: copy_from_user failed %d\n", __func__, ret);
-
- ret = -EPERM;
- goto done;
- }
-
- cmd = data->msg_type;
- prtd = (struct voice_svc_prvt *) file->private_data;
- if (prtd == NULL) {
- pr_err("%s: prtd is NULL\n", __func__);
-
- ret = -EINVAL;
- goto done;
- }
-
- switch (cmd) {
- case MSG_REGISTER:
- /*
- * Check that count reflects the expected size to ensure
- * sufficient memory was allocated. Since voice_svc_register
- * has a static size, this should be exact.
- */
- if (count == (sizeof(struct voice_svc_write_msg) +
- sizeof(struct voice_svc_register))) {
- register_data =
- (struct voice_svc_register *)data->payload;
- if (register_data == NULL) {
- pr_err("%s: register data is NULL", __func__);
- ret = -EINVAL;
- goto done;
- }
- ret = process_reg_cmd(register_data, prtd);
- if (!ret)
- ret = count;
- } else {
- pr_err("%s: invalid data payload size for register command\n",
- __func__);
- ret = -EINVAL;
- goto done;
- }
- break;
- case MSG_REQUEST:
- /*
- * Check that count reflects the expected size to ensure
- * sufficient memory was allocated. Since voice_svc_cmd_request
- * has a variable size, check the minimum value count must be to
- * parse the message request then check the minimum size to hold
- * the payload of the message request.
- */
- if (count >= (sizeof(struct voice_svc_write_msg) +
- sizeof(struct voice_svc_cmd_request))) {
- request_data =
- (struct voice_svc_cmd_request *)data->payload;
- if (request_data == NULL) {
- pr_err("%s: request data is NULL", __func__);
- ret = -EINVAL;
- goto done;
- }
-
- request_payload_size = request_data->payload_size;
-
- if (count >= (sizeof(struct voice_svc_write_msg) +
- sizeof(struct voice_svc_cmd_request) +
- request_payload_size)) {
- ret = voice_svc_send_req(request_data, prtd);
- if (!ret)
- ret = count;
- } else {
- pr_err("%s: invalid request payload size\n",
- __func__);
- ret = -EINVAL;
- goto done;
- }
- } else {
- pr_err("%s: invalid data payload size for request command\n",
- __func__);
- ret = -EINVAL;
- goto done;
- }
- break;
- default:
- pr_debug("%s: Invalid command: %u\n", __func__, cmd);
- ret = -EINVAL;
- }
-
-done:
- kfree(data);
- return ret;
-}
-
-static ssize_t voice_svc_read(struct file *file, char __user *arg,
- size_t count, loff_t *ppos)
-{
- int ret = 0;
- struct voice_svc_prvt *prtd;
- struct apr_response_list *resp;
- unsigned long spin_flags;
- int size;
-
- pr_debug("%s\n", __func__);
-
- prtd = (struct voice_svc_prvt *)file->private_data;
- if (prtd == NULL) {
- pr_err("%s: prtd is NULL\n", __func__);
-
- ret = -EINVAL;
- goto done;
- }
-
- mutex_lock(&prtd->response_mutex_lock);
- spin_lock_irqsave(&prtd->response_lock, spin_flags);
-
- if (list_empty(&prtd->response_queue)) {
- spin_unlock_irqrestore(&prtd->response_lock, spin_flags);
- pr_debug("%s: wait for a response\n", __func__);
-
- ret = wait_event_interruptible_timeout(prtd->response_wait,
- !list_empty(&prtd->response_queue),
- msecs_to_jiffies(TIMEOUT_MS));
- if (ret == 0) {
- pr_debug("%s: Read timeout\n", __func__);
-
- ret = -ETIMEDOUT;
- goto unlock;
- } else if (ret > 0 && !list_empty(&prtd->response_queue)) {
- pr_debug("%s: Interrupt received for response\n",
- __func__);
- } else if (ret < 0) {
- pr_debug("%s: Interrupted by SIGNAL %d\n",
- __func__, ret);
-
- goto unlock;
- }
-
- spin_lock_irqsave(&prtd->response_lock, spin_flags);
- }
-
- resp = list_first_entry(&prtd->response_queue,
- struct apr_response_list, list);
-
- spin_unlock_irqrestore(&prtd->response_lock, spin_flags);
-
- size = resp->resp.payload_size +
- sizeof(struct voice_svc_cmd_response);
-
- if (count < size) {
- pr_err("%s: Invalid payload size %zd, %d\n",
- __func__, count, size);
-
- ret = -ENOMEM;
- goto unlock;
- }
-
- if (!access_ok(VERIFY_WRITE, arg, size)) {
- pr_err("%s: Access denied to write\n",
- __func__);
-
- ret = -EPERM;
- goto unlock;
- }
-
- ret = copy_to_user(arg, &resp->resp,
- sizeof(struct voice_svc_cmd_response) +
- resp->resp.payload_size);
- if (ret) {
- pr_err("%s: copy_to_user failed %d\n", __func__, ret);
-
- ret = -EPERM;
- goto unlock;
- }
-
- spin_lock_irqsave(&prtd->response_lock, spin_flags);
-
- list_del(&resp->list);
- prtd->response_count--;
- kfree(resp);
-
- spin_unlock_irqrestore(&prtd->response_lock,
- spin_flags);
-
- ret = count;
-
-unlock:
- mutex_unlock(&prtd->response_mutex_lock);
-done:
- return ret;
-}
-
-static int voice_svc_dummy_reg(void)
-{
- uint32_t src_port = APR_MAX_PORTS - 1;
-
- pr_debug("%s\n", __func__);
- dummy_q6_mvm = apr_register("ADSP", "MVM",
- qdsp_dummy_apr_callback,
- src_port,
- NULL);
- if (dummy_q6_mvm == NULL) {
- pr_err("%s: Unable to register dummy MVM\n", __func__);
- goto err;
- }
-
- dummy_q6_cvs = apr_register("ADSP", "CVS",
- qdsp_dummy_apr_callback,
- src_port,
- NULL);
- if (dummy_q6_cvs == NULL) {
- pr_err("%s: Unable to register dummy CVS\n", __func__);
- goto err;
- }
- return 0;
-err:
- if (dummy_q6_mvm != NULL) {
- apr_deregister(dummy_q6_mvm);
- dummy_q6_mvm = NULL;
- }
- return -EINVAL;
-}
-
-static int voice_svc_open(struct inode *inode, struct file *file)
-{
- struct voice_svc_prvt *prtd = NULL;
-
- pr_debug("%s\n", __func__);
-
- prtd = kmalloc(sizeof(struct voice_svc_prvt), GFP_KERNEL);
-
- if (prtd == NULL)
- return -ENOMEM;
-
- memset(prtd, 0, sizeof(struct voice_svc_prvt));
- prtd->apr_q6_cvs = NULL;
- prtd->apr_q6_mvm = NULL;
- prtd->response_count = 0;
- INIT_LIST_HEAD(&prtd->response_queue);
- init_waitqueue_head(&prtd->response_wait);
- spin_lock_init(&prtd->response_lock);
- mutex_init(&prtd->response_mutex_lock);
- file->private_data = (void *)prtd;
-
- /* Current APR implementation doesn't support session based
- * multiple service registrations. The apr_deregister()
- * function sets the destination and client IDs to zero, if
- * deregister is called for a single service instance.
- * To avoid this, register for additional services.
- */
- if (!reg_dummy_sess) {
- voice_svc_dummy_reg();
- reg_dummy_sess = 1;
- }
- return 0;
-}
-
-static int voice_svc_release(struct inode *inode, struct file *file)
-{
- int ret = 0;
- struct apr_response_list *resp = NULL;
- unsigned long spin_flags;
- struct voice_svc_prvt *prtd = NULL;
- char *svc_name = NULL;
- void **handle = NULL;
-
- pr_debug("%s\n", __func__);
-
- prtd = (struct voice_svc_prvt *)file->private_data;
- if (prtd == NULL) {
- pr_err("%s: prtd is NULL\n", __func__);
-
- ret = -EINVAL;
- goto done;
- }
-
- if (prtd->apr_q6_cvs != NULL) {
- svc_name = VOICE_SVC_MVM_STR;
- handle = &prtd->apr_q6_cvs;
- ret = voice_svc_dereg(svc_name, handle);
- if (ret)
- pr_err("%s: Failed to dereg CVS %d\n", __func__, ret);
- }
-
- if (prtd->apr_q6_mvm != NULL) {
- svc_name = VOICE_SVC_MVM_STR;
- handle = &prtd->apr_q6_mvm;
- ret = voice_svc_dereg(svc_name, handle);
- if (ret)
- pr_err("%s: Failed to dereg MVM %d\n", __func__, ret);
- }
-
- mutex_lock(&prtd->response_mutex_lock);
- spin_lock_irqsave(&prtd->response_lock, spin_flags);
-
- while (!list_empty(&prtd->response_queue)) {
- pr_debug("%s: Remove item from response queue\n", __func__);
-
- resp = list_first_entry(&prtd->response_queue,
- struct apr_response_list, list);
- list_del(&resp->list);
- prtd->response_count--;
- kfree(resp);
- }
-
- spin_unlock_irqrestore(&prtd->response_lock, spin_flags);
- mutex_unlock(&prtd->response_mutex_lock);
-
- mutex_destroy(&prtd->response_mutex_lock);
-
- kfree(file->private_data);
- file->private_data = NULL;
-
-done:
- return ret;
-}
-
-static const struct file_operations voice_svc_fops = {
- .owner = THIS_MODULE,
- .open = voice_svc_open,
- .read = voice_svc_read,
- .write = voice_svc_write,
- .release = voice_svc_release,
-};
-
-
-static int voice_svc_probe(struct platform_device *pdev)
-{
- int ret = 0;
-
- pr_debug("%s\n", __func__);
-
- voice_svc_dev = devm_kzalloc(&pdev->dev,
- sizeof(struct voice_svc_device), GFP_KERNEL);
- if (!voice_svc_dev) {
- ret = -ENOMEM;
- goto done;
- }
-
- ret = alloc_chrdev_region(&device_num, 0, MINOR_NUMBER,
- VOICE_SVC_DRIVER_NAME);
- if (ret) {
- pr_err("%s: Failed to alloc chrdev\n", __func__);
- ret = -ENODEV;
- goto chrdev_err;
- }
-
- voice_svc_dev->major = MAJOR(device_num);
- voice_svc_class = class_create(THIS_MODULE, VOICE_SVC_DRIVER_NAME);
- if (IS_ERR(voice_svc_class)) {
- ret = PTR_ERR(voice_svc_class);
- pr_err("%s: Failed to create class; err = %d\n", __func__,
- ret);
- goto class_err;
- }
-
- voice_svc_dev->dev = device_create(voice_svc_class, NULL, device_num,
- NULL, VOICE_SVC_DRIVER_NAME);
- if (IS_ERR(voice_svc_dev->dev)) {
- ret = PTR_ERR(voice_svc_dev->dev);
- pr_err("%s: Failed to create device; err = %d\n", __func__,
- ret);
- goto dev_err;
- }
-
- voice_svc_dev->cdev = cdev_alloc();
- if (!voice_svc_dev->cdev) {
- pr_err("%s: Failed to alloc cdev\n", __func__);
- ret = -ENOMEM;
- goto cdev_alloc_err;
- }
-
- cdev_init(voice_svc_dev->cdev, &voice_svc_fops);
- ret = cdev_add(voice_svc_dev->cdev, device_num, MINOR_NUMBER);
- if (ret) {
- pr_err("%s: Failed to register chrdev; err = %d\n", __func__,
- ret);
- goto add_err;
- }
- pr_debug("%s: Device created\n", __func__);
- goto done;
-
-add_err:
- cdev_del(voice_svc_dev->cdev);
-cdev_alloc_err:
- device_destroy(voice_svc_class, device_num);
-dev_err:
- class_destroy(voice_svc_class);
-class_err:
- unregister_chrdev_region(0, MINOR_NUMBER);
-chrdev_err:
- kfree(voice_svc_dev);
-done:
- return ret;
-}
-
-static int voice_svc_remove(struct platform_device *pdev)
-{
- pr_debug("%s\n", __func__);
-
- cdev_del(voice_svc_dev->cdev);
- kfree(voice_svc_dev->cdev);
- device_destroy(voice_svc_class, device_num);
- class_destroy(voice_svc_class);
- unregister_chrdev_region(0, MINOR_NUMBER);
- kfree(voice_svc_dev);
-
- return 0;
-}
-
-static const struct of_device_id voice_svc_of_match[] = {
- {.compatible = "qcom,msm-voice-svc"},
- { }
-};
-MODULE_DEVICE_TABLE(of, voice_svc_of_match);
-
-static struct platform_driver voice_svc_driver = {
- .probe = voice_svc_probe,
- .remove = voice_svc_remove,
- .driver = {
- .name = "msm-voice-svc",
- .owner = THIS_MODULE,
- .of_match_table = voice_svc_of_match,
- },
-};
-
-static int __init voice_svc_init(void)
-{
- pr_debug("%s\n", __func__);
-
- return platform_driver_register(&voice_svc_driver);
-}
-
-static void __exit voice_svc_exit(void)
-{
- pr_debug("%s\n", __func__);
-
- platform_driver_unregister(&voice_svc_driver);
-}
-
-module_init(voice_svc_init);
-module_exit(voice_svc_exit);
-
-MODULE_DESCRIPTION("Soc QDSP6v2 Voice Service driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c
index e30c159..b9070bd 100644
--- a/drivers/soc/qcom/rpmh.c
+++ b/drivers/soc/qcom/rpmh.c
@@ -12,6 +12,7 @@
*/
#include <linux/atomic.h>
+#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/list.h>
@@ -70,6 +71,7 @@
struct rpmh_msg *msg_pool;
DECLARE_BITMAP(fast_req, RPMH_MAX_FAST_RES);
bool dirty;
+ bool in_solver_mode;
};
struct rpmh_client {
@@ -458,10 +460,21 @@
int count = 0;
int ret, i, j, k;
bool complete_set;
+ unsigned long flags;
+ struct rpmh_mbox *rpm;
if (rpmh_standalone)
return 0;
+ /* Do not allow setting wake votes when in solver mode */
+ rpm = rc->rpmh;
+ spin_lock_irqsave(&rpm->lock, flags);
+ if (rpm->in_solver_mode && state == RPMH_WAKE_ONLY_STATE) {
+ spin_unlock_irqrestore(&rpm->lock, flags);
+ return -EIO;
+ }
+ spin_unlock_irqrestore(&rpm->lock, flags);
+
while (n[count++])
;
count--;
@@ -526,6 +539,43 @@
EXPORT_SYMBOL(rpmh_write_passthru);
/**
+ * rpmh_mode_solver_set: Indicate that the RSC controller hardware has
+ * been configured to be in solver mode
+ *
+ * @rc: The RPMH handle
+ * @enable: Boolean value indicating if the controller is in solver mode.
+ *
+ * When solver mode is enabled, passthru API will not be able to send wake
+ * votes, just awake and active votes.
+ */
+int rpmh_mode_solver_set(struct rpmh_client *rc, bool enable)
+{
+ struct rpmh_mbox *rpm;
+ unsigned long flags;
+
+ if (IS_ERR_OR_NULL(rc))
+ return -EINVAL;
+
+ if (rpmh_standalone)
+ return 0;
+
+ rpm = rc->rpmh;
+ do {
+ spin_lock_irqsave(&rpm->lock, flags);
+ if (mbox_controller_is_idle(rc->chan)) {
+ rpm->in_solver_mode = enable;
+ spin_unlock_irqrestore(&rpm->lock, flags);
+ break;
+ }
+ spin_unlock_irqrestore(&rpm->lock, flags);
+ udelay(10);
+ } while (1);
+
+ return 0;
+}
+EXPORT_SYMBOL(rpmh_mode_solver_set);
+
+/**
* rpmh_write_control: Write async control commands to the controller
*
* @rc: The RPMh handle got from rpmh_get_dev_channel
diff --git a/drivers/soc/qcom/system_pm.c b/drivers/soc/qcom/system_pm.c
index 2855a15..d8c5a8f 100644
--- a/drivers/soc/qcom/system_pm.c
+++ b/drivers/soc/qcom/system_pm.c
@@ -56,9 +56,13 @@
* Set up the wake up value offset from the current time.
* Convert us to ns to allow div by 19.2 Mhz tick timer.
*/
- sleep_val *= NSEC_PER_USEC;
- do_div(sleep_val, NSEC_PER_SEC/ARCH_TIMER_HZ);
- sleep_val += arch_counter_get_cntvct();
+ if (sleep_val) {
+ sleep_val *= NSEC_PER_USEC;
+ do_div(sleep_val, NSEC_PER_SEC/ARCH_TIMER_HZ);
+ sleep_val += arch_counter_get_cntvct();
+ } else {
+ sleep_val = ~0ULL;
+ }
return setup_wakeup(sleep_val);
}
diff --git a/drivers/thermal/cpu_cooling.c b/drivers/thermal/cpu_cooling.c
index 37125c0..7da9211 100644
--- a/drivers/thermal/cpu_cooling.c
+++ b/drivers/thermal/cpu_cooling.c
@@ -909,13 +909,11 @@
struct cpufreq_cooling_device *cpufreq_dev;
char dev_name[THERMAL_NAME_LENGTH];
struct cpufreq_frequency_table *pos, *table;
- struct cpumask temp_mask;
unsigned int freq, i, num_cpus;
int ret;
struct thermal_cooling_device_ops *cooling_ops;
- cpumask_and(&temp_mask, clip_cpus, cpu_online_mask);
- policy = cpufreq_cpu_get(cpumask_first(&temp_mask));
+ policy = cpufreq_cpu_get(cpumask_first(clip_cpus));
if (!policy) {
pr_debug("%s: CPUFreq policy not found\n", __func__);
return ERR_PTR(-EPROBE_DEFER);
diff --git a/drivers/thermal/qcom/msm_lmh_dcvs.c b/drivers/thermal/qcom/msm_lmh_dcvs.c
index 74f5ce0..bfaf7c7 100644
--- a/drivers/thermal/qcom/msm_lmh_dcvs.c
+++ b/drivers/thermal/qcom/msm_lmh_dcvs.c
@@ -57,6 +57,7 @@
#define LIMITS_DOMAIN_MIN 0x444D494E
#define LIMITS_TEMP_DEFAULT 75000
+#define LIMITS_TEMP_HIGH_THRESH_MAX 120000
#define LIMITS_LOW_THRESHOLD_OFFSET 500
#define LIMITS_POLLING_DELAY_MS 10
#define LIMITS_CLUSTER_0_REQ 0x179C1B04
@@ -259,7 +260,7 @@
struct limits_dcvs_hw *hw = (struct limits_dcvs_hw *)data;
int ret = 0;
- if (high < LIMITS_LOW_THRESHOLD_OFFSET || low < 0) {
+ if (high >= LIMITS_TEMP_HIGH_THRESH_MAX || low < 0) {
pr_err("Value out of range low:%d high:%d\n",
low, high);
return -EINVAL;
diff --git a/drivers/thermal/qpnp-adc-tm.c b/drivers/thermal/qpnp-adc-tm.c
index 8d706cd..342160e 100644
--- a/drivers/thermal/qpnp-adc-tm.c
+++ b/drivers/thermal/qpnp-adc-tm.c
@@ -34,6 +34,7 @@
#include <linux/qpnp/qpnp-adc.h>
#include <linux/thermal.h>
#include <linux/platform_device.h>
+#include "thermal_core.h"
/* QPNP VADC TM register definition */
#define QPNP_REVISION3 0x2
@@ -41,126 +42,15 @@
#define QPNP_PERPH_TYPE2 0x2
#define QPNP_REVISION_EIGHT_CHANNEL_SUPPORT 2
#define QPNP_PERPH_SUBTYPE_TWO_CHANNEL_SUPPORT 0x22
-#define QPNP_STATUS1 0x8
-#define QPNP_STATUS1_OP_MODE 4
-#define QPNP_STATUS1_MEAS_INTERVAL_EN_STS BIT(2)
-#define QPNP_STATUS1_REQ_STS BIT(1)
-#define QPNP_STATUS1_EOC BIT(0)
-#define QPNP_STATUS2 0x9
-#define QPNP_STATUS2_CONV_SEQ_STATE 6
-#define QPNP_STATUS2_FIFO_NOT_EMPTY_FLAG BIT(1)
-#define QPNP_STATUS2_CONV_SEQ_TIMEOUT_STS BIT(0)
-#define QPNP_CONV_TIMEOUT_ERR 2
-
-#define QPNP_MODE_CTL 0x40
-#define QPNP_OP_MODE_SHIFT 3
-#define QPNP_VREF_XO_THM_FORCE BIT(2)
-#define QPNP_AMUX_TRIM_EN BIT(1)
-#define QPNP_ADC_TRIM_EN BIT(0)
#define QPNP_EN_CTL1 0x46
#define QPNP_ADC_TM_EN BIT(7)
#define QPNP_BTM_CONV_REQ 0x47
#define QPNP_ADC_CONV_REQ_EN BIT(7)
-#define QPNP_ADC_CH_SEL_CTL 0x48
-#define QPNP_ADC_DIG_PARAM 0x50
-#define QPNP_ADC_DIG_DEC_RATIO_SEL_SHIFT 3
-#define QPNP_HW_SETTLE_DELAY 0x51
+#define QPNP_OP_MODE_SHIFT 3
#define QPNP_CONV_REQ 0x52
#define QPNP_CONV_REQ_SET BIT(7)
-#define QPNP_CONV_SEQ_CTL 0x54
-#define QPNP_CONV_SEQ_HOLDOFF_SHIFT 4
-#define QPNP_CONV_SEQ_TRIG_CTL 0x55
-#define QPNP_ADC_TM_MEAS_INTERVAL_CTL 0x57
-#define QPNP_ADC_TM_MEAS_INTERVAL_TIME_SHIFT 0x3
-#define QPNP_ADC_TM_MEAS_INTERVAL_CTL2 0x58
-#define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_SHIFT 0x4
-#define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_MASK 0xf0
-#define QPNP_ADC_TM_MEAS_INTERVAL_CTL3_MASK 0xf
-#define QPNP_ADC_MEAS_INTERVAL_OP_CTL 0x59
-#define QPNP_ADC_MEAS_INTERVAL_OP BIT(7)
-
-#define QPNP_FAST_AVG_CTL 0x5a
-#define QPNP_FAST_AVG_EN 0x5b
-#define QPNP_FAST_AVG_ENABLED BIT(7)
-
-#define QPNP_M0_LOW_THR_LSB 0x5c
-#define QPNP_M0_LOW_THR_MSB 0x5d
-#define QPNP_M0_HIGH_THR_LSB 0x5e
-#define QPNP_M0_HIGH_THR_MSB 0x5f
-#define QPNP_M1_ADC_CH_SEL_CTL 0x68
-#define QPNP_M1_LOW_THR_LSB 0x69
-#define QPNP_M1_LOW_THR_MSB 0x6a
-#define QPNP_M1_HIGH_THR_LSB 0x6b
-#define QPNP_M1_HIGH_THR_MSB 0x6c
-#define QPNP_M2_ADC_CH_SEL_CTL 0x70
-#define QPNP_M2_LOW_THR_LSB 0x71
-#define QPNP_M2_LOW_THR_MSB 0x72
-#define QPNP_M2_HIGH_THR_LSB 0x73
-#define QPNP_M2_HIGH_THR_MSB 0x74
-#define QPNP_M3_ADC_CH_SEL_CTL 0x78
-#define QPNP_M3_LOW_THR_LSB 0x79
-#define QPNP_M3_LOW_THR_MSB 0x7a
-#define QPNP_M3_HIGH_THR_LSB 0x7b
-#define QPNP_M3_HIGH_THR_MSB 0x7c
-#define QPNP_M4_ADC_CH_SEL_CTL 0x80
-#define QPNP_M4_LOW_THR_LSB 0x81
-#define QPNP_M4_LOW_THR_MSB 0x82
-#define QPNP_M4_HIGH_THR_LSB 0x83
-#define QPNP_M4_HIGH_THR_MSB 0x84
-#define QPNP_M5_ADC_CH_SEL_CTL 0x88
-#define QPNP_M5_LOW_THR_LSB 0x89
-#define QPNP_M5_LOW_THR_MSB 0x8a
-#define QPNP_M5_HIGH_THR_LSB 0x8b
-#define QPNP_M5_HIGH_THR_MSB 0x8c
-#define QPNP_M6_ADC_CH_SEL_CTL 0x90
-#define QPNP_M6_LOW_THR_LSB 0x91
-#define QPNP_M6_LOW_THR_MSB 0x92
-#define QPNP_M6_HIGH_THR_LSB 0x93
-#define QPNP_M6_HIGH_THR_MSB 0x94
-#define QPNP_M7_ADC_CH_SEL_CTL 0x98
-#define QPNP_M7_LOW_THR_LSB 0x99
-#define QPNP_M7_LOW_THR_MSB 0x9a
-#define QPNP_M7_HIGH_THR_LSB 0x9b
-#define QPNP_M7_HIGH_THR_MSB 0x9c
-
-#define QPNP_ADC_TM_MULTI_MEAS_EN 0x41
-#define QPNP_ADC_TM_MULTI_MEAS_EN_M0 BIT(0)
-#define QPNP_ADC_TM_MULTI_MEAS_EN_M1 BIT(1)
-#define QPNP_ADC_TM_MULTI_MEAS_EN_M2 BIT(2)
-#define QPNP_ADC_TM_MULTI_MEAS_EN_M3 BIT(3)
-#define QPNP_ADC_TM_MULTI_MEAS_EN_M4 BIT(4)
-#define QPNP_ADC_TM_MULTI_MEAS_EN_M5 BIT(5)
-#define QPNP_ADC_TM_MULTI_MEAS_EN_M6 BIT(6)
-#define QPNP_ADC_TM_MULTI_MEAS_EN_M7 BIT(7)
-#define QPNP_ADC_TM_LOW_THR_INT_EN 0x42
-#define QPNP_ADC_TM_LOW_THR_INT_EN_M0 BIT(0)
-#define QPNP_ADC_TM_LOW_THR_INT_EN_M1 BIT(1)
-#define QPNP_ADC_TM_LOW_THR_INT_EN_M2 BIT(2)
-#define QPNP_ADC_TM_LOW_THR_INT_EN_M3 BIT(3)
-#define QPNP_ADC_TM_LOW_THR_INT_EN_M4 BIT(4)
-#define QPNP_ADC_TM_LOW_THR_INT_EN_M5 BIT(5)
-#define QPNP_ADC_TM_LOW_THR_INT_EN_M6 BIT(6)
-#define QPNP_ADC_TM_LOW_THR_INT_EN_M7 BIT(7)
-#define QPNP_ADC_TM_HIGH_THR_INT_EN 0x43
-#define QPNP_ADC_TM_HIGH_THR_INT_EN_M0 BIT(0)
-#define QPNP_ADC_TM_HIGH_THR_INT_EN_M1 BIT(1)
-#define QPNP_ADC_TM_HIGH_THR_INT_EN_M2 BIT(2)
-#define QPNP_ADC_TM_HIGH_THR_INT_EN_M3 BIT(3)
-#define QPNP_ADC_TM_HIGH_THR_INT_EN_M4 BIT(4)
-#define QPNP_ADC_TM_HIGH_THR_INT_EN_M5 BIT(5)
-#define QPNP_ADC_TM_HIGH_THR_INT_EN_M6 BIT(6)
-#define QPNP_ADC_TM_HIGH_THR_INT_EN_M7 BIT(7)
-
-#define QPNP_ADC_TM_M0_MEAS_INTERVAL_CTL 0x59
-#define QPNP_ADC_TM_M1_MEAS_INTERVAL_CTL 0x6d
-#define QPNP_ADC_TM_M2_MEAS_INTERVAL_CTL 0x75
-#define QPNP_ADC_TM_M3_MEAS_INTERVAL_CTL 0x7d
-#define QPNP_ADC_TM_M4_MEAS_INTERVAL_CTL 0x85
-#define QPNP_ADC_TM_M5_MEAS_INTERVAL_CTL 0x8d
-#define QPNP_ADC_TM_M6_MEAS_INTERVAL_CTL 0x95
-#define QPNP_ADC_TM_M7_MEAS_INTERVAL_CTL 0x9d
#define QPNP_ADC_TM_STATUS1 0x8
#define QPNP_ADC_TM_STATUS_LOW 0xa
#define QPNP_ADC_TM_STATUS_HIGH 0xb
@@ -172,22 +62,22 @@
#define QPNP_ADC_TM_THR_LSB_MASK(val) (val & 0xff)
#define QPNP_ADC_TM_THR_MSB_MASK(val) ((val & 0xff00) >> 8)
-#define QPNP_MIN_TIME 2000
-#define QPNP_MAX_TIME 2100
-#define QPNP_RETRY 1000
-
/* QPNP ADC TM HC start */
-#define QPNP_BTM_HC_STATUS1 0x08
-#define QPNP_BTM_HC_STATUS_LOW 0x0a
-#define QPNP_BTM_HC_STATUS_HIGH 0x0b
+#define QPNP_BTM_HC_STATUS1 0x08
+#define QPNP_BTM_HC_STATUS_LOW 0x0a
+#define QPNP_BTM_HC_STATUS_HIGH 0x0b
-#define QPNP_BTM_HC_ADC_DIG_PARAM 0x42
-#define QPNP_BTM_HC_FAST_AVG_CTL 0x43
-#define QPNP_BTM_EN_CTL1 0x46
-#define QPNP_BTM_CONV_REQ 0x47
+#define QPNP_BTM_HC_ADC_DIG_PARAM 0x42
+#define QPNP_BTM_HC_FAST_AVG_CTL 0x43
+#define QPNP_BTM_EN_CTL1 0x46
+#define QPNP_BTM_CONV_REQ 0x47
-#define QPNP_BTM_MEAS_INTERVAL_CTL 0x50
-#define QPNP_BTM_MEAS_INTERVAL_CTL2 0x51
+#define QPNP_BTM_MEAS_INTERVAL_CTL 0x50
+#define QPNP_BTM_MEAS_INTERVAL_CTL2 0x51
+#define QPNP_ADC_TM_MEAS_INTERVAL_TIME_SHIFT 0x3
+#define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_SHIFT 0x4
+#define QPNP_ADC_TM_MEAS_INTERVAL_CTL2_MASK 0xf0
+#define QPNP_ADC_TM_MEAS_INTERVAL_CTL3_MASK 0xf
#define QPNP_BTM_Mn_ADC_CH_SEL_CTL(n) ((n * 8) + 0x60)
#define QPNP_BTM_Mn_LOW_THR0(n) ((n * 8) + 0x61)
@@ -208,6 +98,7 @@
#define QPNP_BTM_Mn_DATA0(n) ((n * 2) + 0xa0)
#define QPNP_BTM_Mn_DATA1(n) ((n * 2) + 0xa1)
+#define QPNP_BTM_CHANNELS 8
/* QPNP ADC TM HC end */
@@ -277,69 +168,6 @@
LIST_HEAD(qpnp_adc_tm_device_list);
-struct qpnp_adc_tm_trip_reg_type {
- enum qpnp_adc_tm_channel_select btm_amux_chan;
- uint16_t low_thr_lsb_addr;
- uint16_t low_thr_msb_addr;
- uint16_t high_thr_lsb_addr;
- uint16_t high_thr_msb_addr;
- u8 multi_meas_en;
- u8 low_thr_int_chan_en;
- u8 high_thr_int_chan_en;
- u8 meas_interval_ctl;
-};
-
-static struct qpnp_adc_tm_trip_reg_type adc_tm_data[] = {
- [QPNP_ADC_TM_CHAN0] = {QPNP_ADC_TM_M0_ADC_CH_SEL_CTL,
- QPNP_M0_LOW_THR_LSB,
- QPNP_M0_LOW_THR_MSB, QPNP_M0_HIGH_THR_LSB,
- QPNP_M0_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M0,
- QPNP_ADC_TM_LOW_THR_INT_EN_M0, QPNP_ADC_TM_HIGH_THR_INT_EN_M0,
- QPNP_ADC_TM_M0_MEAS_INTERVAL_CTL},
- [QPNP_ADC_TM_CHAN1] = {QPNP_ADC_TM_M1_ADC_CH_SEL_CTL,
- QPNP_M1_LOW_THR_LSB,
- QPNP_M1_LOW_THR_MSB, QPNP_M1_HIGH_THR_LSB,
- QPNP_M1_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M1,
- QPNP_ADC_TM_LOW_THR_INT_EN_M1, QPNP_ADC_TM_HIGH_THR_INT_EN_M1,
- QPNP_ADC_TM_M1_MEAS_INTERVAL_CTL},
- [QPNP_ADC_TM_CHAN2] = {QPNP_ADC_TM_M2_ADC_CH_SEL_CTL,
- QPNP_M2_LOW_THR_LSB,
- QPNP_M2_LOW_THR_MSB, QPNP_M2_HIGH_THR_LSB,
- QPNP_M2_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M2,
- QPNP_ADC_TM_LOW_THR_INT_EN_M2, QPNP_ADC_TM_HIGH_THR_INT_EN_M2,
- QPNP_ADC_TM_M2_MEAS_INTERVAL_CTL},
- [QPNP_ADC_TM_CHAN3] = {QPNP_ADC_TM_M3_ADC_CH_SEL_CTL,
- QPNP_M3_LOW_THR_LSB,
- QPNP_M3_LOW_THR_MSB, QPNP_M3_HIGH_THR_LSB,
- QPNP_M3_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M3,
- QPNP_ADC_TM_LOW_THR_INT_EN_M3, QPNP_ADC_TM_HIGH_THR_INT_EN_M3,
- QPNP_ADC_TM_M3_MEAS_INTERVAL_CTL},
- [QPNP_ADC_TM_CHAN4] = {QPNP_ADC_TM_M4_ADC_CH_SEL_CTL,
- QPNP_M4_LOW_THR_LSB,
- QPNP_M4_LOW_THR_MSB, QPNP_M4_HIGH_THR_LSB,
- QPNP_M4_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M4,
- QPNP_ADC_TM_LOW_THR_INT_EN_M4, QPNP_ADC_TM_HIGH_THR_INT_EN_M4,
- QPNP_ADC_TM_M4_MEAS_INTERVAL_CTL},
- [QPNP_ADC_TM_CHAN5] = {QPNP_ADC_TM_M5_ADC_CH_SEL_CTL,
- QPNP_M5_LOW_THR_LSB,
- QPNP_M5_LOW_THR_MSB, QPNP_M5_HIGH_THR_LSB,
- QPNP_M5_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M5,
- QPNP_ADC_TM_LOW_THR_INT_EN_M5, QPNP_ADC_TM_HIGH_THR_INT_EN_M5,
- QPNP_ADC_TM_M5_MEAS_INTERVAL_CTL},
- [QPNP_ADC_TM_CHAN6] = {QPNP_ADC_TM_M6_ADC_CH_SEL_CTL,
- QPNP_M6_LOW_THR_LSB,
- QPNP_M6_LOW_THR_MSB, QPNP_M6_HIGH_THR_LSB,
- QPNP_M6_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M6,
- QPNP_ADC_TM_LOW_THR_INT_EN_M6, QPNP_ADC_TM_HIGH_THR_INT_EN_M6,
- QPNP_ADC_TM_M6_MEAS_INTERVAL_CTL},
- [QPNP_ADC_TM_CHAN7] = {QPNP_ADC_TM_M7_ADC_CH_SEL_CTL,
- QPNP_M7_LOW_THR_LSB,
- QPNP_M7_LOW_THR_MSB, QPNP_M7_HIGH_THR_LSB,
- QPNP_M7_HIGH_THR_MSB, QPNP_ADC_TM_MULTI_MEAS_EN_M7,
- QPNP_ADC_TM_LOW_THR_INT_EN_M7, QPNP_ADC_TM_HIGH_THR_INT_EN_M7,
- QPNP_ADC_TM_M7_MEAS_INTERVAL_CTL},
-};
-
static struct qpnp_adc_tm_reverse_scale_fn adc_tm_rscale_fn[] = {
[SCALE_R_VBATT] = {qpnp_adc_vbatt_rscaler},
[SCALE_RBATT_THERM] = {qpnp_adc_btm_scaler},
@@ -380,33 +208,6 @@
return rc;
}
-static int32_t qpnp_adc_tm_fast_avg_en(struct qpnp_adc_tm_chip *chip,
- uint32_t *fast_avg_sample)
-{
- int rc = 0, version = 0;
- u8 fast_avg_en = 0;
-
- version = qpnp_adc_get_revid_version(chip->dev);
- if (!((version == QPNP_REV_ID_8916_1_0) ||
- (version == QPNP_REV_ID_8916_1_1) ||
- (version == QPNP_REV_ID_8916_2_0))) {
- pr_debug("fast-avg-en not required for this version\n");
- return rc;
- }
-
- fast_avg_en = QPNP_FAST_AVG_ENABLED;
- rc = qpnp_adc_tm_write_reg(chip, QPNP_FAST_AVG_EN, fast_avg_en, 1);
- if (rc < 0) {
- pr_err("adc-tm fast-avg enable err\n");
- return rc;
- }
-
- if (*fast_avg_sample >= 3)
- *fast_avg_sample = 2;
-
- return rc;
-}
-
static int qpnp_adc_tm_check_vreg_vote(struct qpnp_adc_tm_chip *chip)
{
int rc = 0;
@@ -443,13 +244,11 @@
return rc;
}
- if (chip->adc_tm_hc) {
- data = QPNP_ADC_CONV_REQ_EN;
- rc = qpnp_adc_tm_write_reg(chip, QPNP_BTM_CONV_REQ, data, 1);
- if (rc < 0) {
- pr_err("adc-tm enable failed\n");
- return rc;
- }
+ data = QPNP_ADC_CONV_REQ_EN;
+ rc = qpnp_adc_tm_write_reg(chip, QPNP_BTM_CONV_REQ, data, 1);
+ if (rc < 0) {
+ pr_err("adc-tm enable failed\n");
+ return rc;
}
return rc;
@@ -460,12 +259,10 @@
u8 data = 0;
int rc = 0;
- if (chip->adc_tm_hc) {
- rc = qpnp_adc_tm_write_reg(chip, QPNP_BTM_CONV_REQ, data, 1);
- if (rc < 0) {
- pr_err("adc-tm enable failed\n");
- return rc;
- }
+ rc = qpnp_adc_tm_write_reg(chip, QPNP_BTM_CONV_REQ, data, 1);
+ if (rc < 0) {
+ pr_err("adc-tm enable failed\n");
+ return rc;
}
rc = qpnp_adc_tm_write_reg(chip, QPNP_EN_CTL1, data, 1);
@@ -538,132 +335,11 @@
static int32_t qpnp_adc_tm_enable_if_channel_meas(
struct qpnp_adc_tm_chip *chip)
{
- u8 adc_tm_meas_en = 0, status_low = 0, status_high = 0;
int rc = 0;
- if (chip->adc_tm_hc) {
- rc = qpnp_adc_tm_rc_check_channel_en(chip);
- if (rc) {
- pr_err("adc_tm channel check failed\n");
- return rc;
- }
- } else {
- /* Check if a measurement request is still required */
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
- &adc_tm_meas_en, 1);
- if (rc) {
- pr_err("read status high failed with %d\n", rc);
- return rc;
- }
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_LOW_THR_INT_EN,
- &status_low, 1);
- if (rc) {
- pr_err("read status low failed with %d\n", rc);
- return rc;
- }
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_HIGH_THR_INT_EN,
- &status_high, 1);
- if (rc) {
- pr_err("read status high failed with %d\n", rc);
- return rc;
- }
-
- /* Enable only if there are pending measurement requests */
- if ((adc_tm_meas_en && status_high) ||
- (adc_tm_meas_en && status_low)) {
- qpnp_adc_tm_enable(chip);
-
- /* Request conversion */
- rc = qpnp_adc_tm_write_reg(chip, QPNP_CONV_REQ,
- QPNP_CONV_REQ_SET, 1);
- if (rc < 0) {
- pr_err("adc-tm request conversion failed\n");
- return rc;
- }
- } else {
- /* disable the vote if applicable */
- if (chip->adc_vote_enable && chip->adc->hkadc_ldo &&
- chip->adc->hkadc_ldo_ok) {
- qpnp_adc_disable_voltage(chip->adc);
- chip->adc_vote_enable = false;
- }
- }
- }
-
- return rc;
-}
-
-static int32_t qpnp_adc_tm_mode_select(struct qpnp_adc_tm_chip *chip,
- u8 mode_ctl)
-{
- int rc;
-
- mode_ctl |= (QPNP_ADC_TRIM_EN | QPNP_AMUX_TRIM_EN);
-
- /* VADC_BTM current sets mode to recurring measurements */
- rc = qpnp_adc_tm_write_reg(chip, QPNP_MODE_CTL, mode_ctl, 1);
- if (rc < 0)
- pr_err("adc-tm write mode selection err\n");
-
- return rc;
-}
-
-static int32_t qpnp_adc_tm_req_sts_check(struct qpnp_adc_tm_chip *chip)
-{
- u8 status1 = 0, mode_ctl = 0;
- int rc, count = 0;
-
- /* Re-enable the peripheral */
- rc = qpnp_adc_tm_enable(chip);
+ rc = qpnp_adc_tm_rc_check_channel_en(chip);
if (rc) {
- pr_err("adc-tm re-enable peripheral failed\n");
- return rc;
- }
-
- /* The VADC_TM bank needs to be disabled for new conversion request */
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS1, &status1, 1);
- if (rc) {
- pr_err("adc-tm read status1 failed\n");
- return rc;
- }
-
- /* Disable the bank if a conversion is occurring */
- while (status1 & QPNP_STATUS1_REQ_STS) {
- if (count > QPNP_RETRY) {
- pr_err("retry error=%d with 0x%x\n", count, status1);
- break;
- }
- /*
- * Wait time is based on the optimum sampling rate
- * and adding enough time buffer to account for ADC conversions
- * occurring on different peripheral banks
- */
- usleep_range(QPNP_MIN_TIME, QPNP_MAX_TIME);
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS1,
- &status1, 1);
- if (rc < 0) {
- pr_err("adc-tm disable failed\n");
- return rc;
- }
- count++;
- }
-
- if (!chip->adc_tm_hc) {
- /* Change the mode back to recurring measurement mode */
- mode_ctl = ADC_OP_MEASUREMENT_INTERVAL << QPNP_OP_MODE_SHIFT;
- rc = qpnp_adc_tm_mode_select(chip, mode_ctl);
- if (rc < 0) {
- pr_err("adc-tm mode change to recurring failed\n");
- return rc;
- }
- }
-
- /* Disable the peripheral */
- rc = qpnp_adc_tm_disable(chip);
- if (rc < 0) {
- pr_err("adc-tm peripheral disable failed\n");
+ pr_err("adc_tm channel check failed\n");
return rc;
}
@@ -676,20 +352,11 @@
int rc = 0, i;
bool chan_found = false;
- if (!chip->adc_tm_hc) {
- for (i = 0; i < QPNP_ADC_TM_CHAN_NONE; i++) {
- if (adc_tm_data[i].btm_amux_chan == btm_chan) {
- *btm_chan_idx = i;
- chan_found = true;
- }
- }
- } else {
- for (i = 0; i < chip->max_channels_available; i++) {
- if (chip->sensor[i].btm_channel_num == btm_chan) {
- *btm_chan_idx = i;
- chan_found = true;
- break;
- }
+ for (i = 0; i < chip->max_channels_available; i++) {
+ if (chip->sensor[i].btm_channel_num == btm_chan) {
+ *btm_chan_idx = i;
+ chan_found = true;
+ break;
}
}
@@ -760,12 +427,7 @@
switch (chip->sensor[chan_idx].timer_select) {
case ADC_MEAS_TIMER_SELECT1:
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_ADC_TM_MEAS_INTERVAL_CTL,
- chip->sensor[chan_idx].meas_interval, 1);
- else
- rc = qpnp_adc_tm_write_reg(chip,
+ rc = qpnp_adc_tm_write_reg(chip,
QPNP_BTM_MEAS_INTERVAL_CTL,
chip->sensor[chan_idx].meas_interval, 1);
if (rc < 0) {
@@ -775,12 +437,7 @@
break;
case ADC_MEAS_TIMER_SELECT2:
/* Thermal channels uses timer2, default to 1 second */
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_read_reg(chip,
- QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
- &meas_interval_timer2, 1);
- else
- rc = qpnp_adc_tm_read_reg(chip,
+ rc = qpnp_adc_tm_read_reg(chip,
QPNP_BTM_MEAS_INTERVAL_CTL2,
&meas_interval_timer2, 1);
if (rc < 0) {
@@ -791,12 +448,7 @@
timer_interval_store <<= QPNP_ADC_TM_MEAS_INTERVAL_CTL2_SHIFT;
timer_interval_store &= QPNP_ADC_TM_MEAS_INTERVAL_CTL2_MASK;
meas_interval_timer2 |= timer_interval_store;
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
- meas_interval_timer2, 1);
- else
- rc = qpnp_adc_tm_write_reg(chip,
+ rc = qpnp_adc_tm_write_reg(chip,
QPNP_BTM_MEAS_INTERVAL_CTL2,
meas_interval_timer2, 1);
if (rc < 0) {
@@ -805,12 +457,7 @@
}
break;
case ADC_MEAS_TIMER_SELECT3:
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_read_reg(chip,
- QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
- &meas_interval_timer2, 1);
- else
- rc = qpnp_adc_tm_read_reg(chip,
+ rc = qpnp_adc_tm_read_reg(chip,
QPNP_BTM_MEAS_INTERVAL_CTL2,
&meas_interval_timer2, 1);
if (rc < 0) {
@@ -820,11 +467,6 @@
timer_interval_store = chip->sensor[chan_idx].meas_interval;
timer_interval_store &= QPNP_ADC_TM_MEAS_INTERVAL_CTL3_MASK;
meas_interval_timer2 |= timer_interval_store;
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_ADC_TM_MEAS_INTERVAL_CTL2,
- meas_interval_timer2, 1);
- else
rc = qpnp_adc_tm_write_reg(chip,
QPNP_BTM_MEAS_INTERVAL_CTL2,
meas_interval_timer2, 1);
@@ -844,14 +486,9 @@
pr_err("Invalid btm channel idx\n");
return rc;
}
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_write_reg(chip,
- adc_tm_data[btm_chan_idx].meas_interval_ctl,
- chip->sensor[chan_idx].timer_select, 1);
- else
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_BTM_Mn_MEAS_INTERVAL_CTL(btm_chan_idx),
- chip->sensor[chan_idx].timer_select, 1);
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_Mn_MEAS_INTERVAL_CTL(btm_chan_idx),
+ chip->sensor[chan_idx].timer_select, 1);
if (rc < 0) {
pr_err("TM channel timer configure failed\n");
return rc;
@@ -934,67 +571,6 @@
return rc;
}
-static int32_t qpnp_adc_tm_read_thr_value(struct qpnp_adc_tm_chip *chip,
- uint32_t btm_chan)
-{
- int rc = 0;
- u8 data_lsb = 0, data_msb = 0;
- uint32_t btm_chan_idx = 0;
- int32_t low_thr = 0, high_thr = 0;
-
- if (!chip->adc_tm_hc) {
- pr_err("Not applicable for VADC HC peripheral\n");
- return -EINVAL;
- }
-
- rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
- if (rc < 0) {
- pr_err("Invalid btm channel idx\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_read_reg(chip,
- adc_tm_data[btm_chan_idx].low_thr_lsb_addr,
- &data_lsb, 1);
- if (rc < 0) {
- pr_err("low threshold lsb setting failed\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_read_reg(chip,
- adc_tm_data[btm_chan_idx].low_thr_msb_addr,
- &data_msb, 1);
- if (rc < 0) {
- pr_err("low threshold msb setting failed\n");
- return rc;
- }
-
- low_thr = (data_msb << 8) | data_lsb;
-
- rc = qpnp_adc_tm_read_reg(chip,
- adc_tm_data[btm_chan_idx].high_thr_lsb_addr,
- &data_lsb, 1);
- if (rc < 0) {
- pr_err("high threshold lsb setting failed\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_read_reg(chip,
- adc_tm_data[btm_chan_idx].high_thr_msb_addr,
- &data_msb, 1);
- if (rc < 0) {
- pr_err("high threshold msb setting failed\n");
- return rc;
- }
-
- high_thr = (data_msb << 8) | data_lsb;
-
- pr_debug("configured thresholds high:0x%x and low:0x%x\n",
- high_thr, low_thr);
-
- return rc;
-}
-
static int32_t qpnp_adc_tm_thr_update(struct qpnp_adc_tm_chip *chip,
uint32_t btm_chan, int32_t high_thr, int32_t low_thr)
{
@@ -1007,69 +583,36 @@
return rc;
}
- if (!chip->adc_tm_hc) {
- rc = qpnp_adc_tm_write_reg(chip,
- adc_tm_data[btm_chan_idx].low_thr_lsb_addr,
- QPNP_ADC_TM_THR_LSB_MASK(low_thr), 1);
- if (rc < 0) {
- pr_err("low threshold lsb setting failed\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_write_reg(chip,
- adc_tm_data[btm_chan_idx].low_thr_msb_addr,
- QPNP_ADC_TM_THR_MSB_MASK(low_thr), 1);
- if (rc < 0) {
- pr_err("low threshold msb setting failed\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_write_reg(chip,
- adc_tm_data[btm_chan_idx].high_thr_lsb_addr,
- QPNP_ADC_TM_THR_LSB_MASK(high_thr), 1);
- if (rc < 0) {
- pr_err("high threshold lsb setting failed\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_write_reg(chip,
- adc_tm_data[btm_chan_idx].high_thr_msb_addr,
- QPNP_ADC_TM_THR_MSB_MASK(high_thr), 1);
- if (rc < 0)
- pr_err("high threshold msb setting failed\n");
- } else {
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_BTM_Mn_LOW_THR0(btm_chan_idx),
- QPNP_ADC_TM_THR_LSB_MASK(low_thr), 1);
- if (rc < 0) {
- pr_err("low threshold lsb setting failed\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_BTM_Mn_LOW_THR1(btm_chan_idx),
- QPNP_ADC_TM_THR_MSB_MASK(low_thr), 1);
- if (rc < 0) {
- pr_err("low threshold msb setting failed\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_BTM_Mn_HIGH_THR0(btm_chan_idx),
- QPNP_ADC_TM_THR_LSB_MASK(high_thr), 1);
- if (rc < 0) {
- pr_err("high threshold lsb setting failed\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_write_reg(chip,
- QPNP_BTM_Mn_HIGH_THR1(btm_chan_idx),
- QPNP_ADC_TM_THR_MSB_MASK(high_thr), 1);
- if (rc < 0)
- pr_err("high threshold msb setting failed\n");
-
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_Mn_LOW_THR0(btm_chan_idx),
+ QPNP_ADC_TM_THR_LSB_MASK(low_thr), 1);
+ if (rc < 0) {
+ pr_err("low threshold lsb setting failed\n");
+ return rc;
}
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_Mn_LOW_THR1(btm_chan_idx),
+ QPNP_ADC_TM_THR_MSB_MASK(low_thr), 1);
+ if (rc < 0) {
+ pr_err("low threshold msb setting failed\n");
+ return rc;
+ }
+
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_Mn_HIGH_THR0(btm_chan_idx),
+ QPNP_ADC_TM_THR_LSB_MASK(high_thr), 1);
+ if (rc < 0) {
+ pr_err("high threshold lsb setting failed\n");
+ return rc;
+ }
+
+ rc = qpnp_adc_tm_write_reg(chip,
+ QPNP_BTM_Mn_HIGH_THR1(btm_chan_idx),
+ QPNP_ADC_TM_THR_MSB_MASK(high_thr), 1);
+ if (rc < 0)
+ pr_err("high threshold msb setting failed\n");
+
pr_debug("client requested high:%d and low:%d\n",
high_thr, low_thr);
@@ -1206,14 +749,9 @@
pr_debug("low sensor mask:%x with state:%d\n",
sensor_mask, chan_prop->state_request);
/* Enable low threshold's interrupt */
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_LOW_THR_INT_EN,
- sensor_mask, true);
- else
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_BTM_Mn_EN(btm_chan_idx),
- QPNP_BTM_Mn_LOW_THR_INT_EN, true);
+ rc = qpnp_adc_tm_reg_update(chip,
+ QPNP_BTM_Mn_EN(btm_chan_idx),
+ QPNP_BTM_Mn_LOW_THR_INT_EN, true);
if (rc < 0) {
pr_err("low thr enable err:%d\n", btm_chan);
return rc;
@@ -1223,14 +761,9 @@
if (high_thr_set) {
/* Enable high threshold's interrupt */
pr_debug("high sensor mask:%x\n", sensor_mask);
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_HIGH_THR_INT_EN,
- sensor_mask, true);
- else
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_BTM_Mn_EN(btm_chan_idx),
- QPNP_BTM_Mn_HIGH_THR_INT_EN, true);
+ rc = qpnp_adc_tm_reg_update(chip,
+ QPNP_BTM_Mn_EN(btm_chan_idx),
+ QPNP_BTM_Mn_HIGH_THR_INT_EN, true);
if (rc < 0) {
pr_err("high thr enable err:%d\n", btm_chan);
return rc;
@@ -1239,11 +772,7 @@
}
/* Enable corresponding BTM channel measurement */
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_MULTI_MEAS_EN, sensor_mask, true);
- else
- rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_idx),
+ rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_idx),
QPNP_BTM_Mn_MEAS_EN, true);
if (rc < 0) {
pr_err("multi measurement en failed\n");
@@ -1358,135 +887,12 @@
return 0;
}
-static int32_t qpnp_adc_tm_configure(struct qpnp_adc_tm_chip *chip,
- struct qpnp_adc_amux_properties *chan_prop)
-{
- u8 decimation = 0, op_cntrl = 0, mode_ctl = 0;
- int rc = 0;
- uint32_t btm_chan = 0;
-
- /* Set measurement in single measurement mode */
- mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
- rc = qpnp_adc_tm_mode_select(chip, mode_ctl);
- if (rc < 0) {
- pr_err("adc-tm single mode select failed\n");
- return rc;
- }
-
- /* Disable bank */
- rc = qpnp_adc_tm_disable(chip);
- if (rc)
- return rc;
-
- /* Check if a conversion is in progress */
- rc = qpnp_adc_tm_req_sts_check(chip);
- if (rc < 0) {
- pr_err("adc-tm req_sts check failed\n");
- return rc;
- }
-
- /* Configure AMUX channel select for the corresponding BTM channel*/
- btm_chan = chan_prop->chan_prop->tm_channel_select;
- rc = qpnp_adc_tm_write_reg(chip, btm_chan, chan_prop->amux_channel, 1);
- if (rc < 0) {
- pr_err("adc-tm channel selection err\n");
- return rc;
- }
-
- /* Digital parameter setup */
- decimation |= chan_prop->decimation <<
- QPNP_ADC_DIG_DEC_RATIO_SEL_SHIFT;
- rc = qpnp_adc_tm_write_reg(chip, QPNP_ADC_DIG_PARAM, decimation, 1);
- if (rc < 0) {
- pr_err("adc-tm digital parameter setup err\n");
- return rc;
- }
-
- /* Hardware setting time */
- rc = qpnp_adc_tm_write_reg(chip, QPNP_HW_SETTLE_DELAY,
- chan_prop->hw_settle_time, 1);
- if (rc < 0) {
- pr_err("adc-tm hw settling time setup err\n");
- return rc;
- }
-
- /* Fast averaging setup/enable */
- rc = qpnp_adc_tm_fast_avg_en(chip, &chan_prop->fast_avg_setup);
- if (rc < 0) {
- pr_err("adc-tm fast-avg enable err\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_write_reg(chip, QPNP_FAST_AVG_CTL,
- chan_prop->fast_avg_setup, 1);
- if (rc < 0) {
- pr_err("adc-tm fast-avg setup err\n");
- return rc;
- }
-
- /* Measurement interval setup */
- rc = qpnp_adc_tm_timer_interval_select(chip, btm_chan,
- chan_prop->chan_prop);
- if (rc < 0) {
- pr_err("adc-tm timer select failed\n");
- return rc;
- }
-
- /* Channel configuration setup */
- rc = qpnp_adc_tm_channel_configure(chip, btm_chan,
- chan_prop->chan_prop, chan_prop->amux_channel);
- if (rc < 0) {
- pr_err("adc-tm channel configure failed\n");
- return rc;
- }
-
- /* Recurring interval measurement enable */
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_MEAS_INTERVAL_OP_CTL,
- &op_cntrl, 1);
- op_cntrl |= QPNP_ADC_MEAS_INTERVAL_OP;
- rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_MEAS_INTERVAL_OP_CTL,
- op_cntrl, true);
- if (rc < 0) {
- pr_err("adc-tm meas interval op configure failed\n");
- return rc;
- }
-
- /* Enable bank */
- rc = qpnp_adc_tm_enable(chip);
- if (rc)
- return rc;
-
- /* Request conversion */
- rc = qpnp_adc_tm_write_reg(chip, QPNP_CONV_REQ, QPNP_CONV_REQ_SET, 1);
- if (rc < 0) {
- pr_err("adc-tm request conversion failed\n");
- return rc;
- }
-
- return 0;
-}
-
-static int qpnp_adc_tm_get_mode(struct thermal_zone_device *thermal,
- enum thermal_device_mode *mode)
-{
- struct qpnp_adc_tm_sensor *adc_tm = thermal->devdata;
-
- if ((IS_ERR(adc_tm)) || qpnp_adc_tm_check_revision(
- adc_tm->chip, adc_tm->btm_channel_num))
- return -EINVAL;
-
- *mode = adc_tm->mode;
-
- return 0;
-}
-
-static int qpnp_adc_tm_set_mode(struct thermal_zone_device *thermal,
+static int qpnp_adc_tm_set_mode(struct qpnp_adc_tm_sensor *adc_tm,
enum thermal_device_mode mode)
{
- struct qpnp_adc_tm_sensor *adc_tm = thermal->devdata;
struct qpnp_adc_tm_chip *chip = adc_tm->chip;
int rc = 0, channel;
- u8 sensor_mask = 0, mode_ctl = 0;
+ u8 sensor_mask = 0;
uint32_t btm_chan_idx = 0, btm_chan = 0;
if (qpnp_adc_tm_is_valid(chip)) {
@@ -1525,32 +931,14 @@
chip->adc->amux_prop->calib_type =
chip->adc->adc_channels[channel].calib_type;
- if (!chip->adc_tm_hc) {
- rc = qpnp_adc_tm_configure(chip, chip->adc->amux_prop);
- if (rc) {
- pr_err("adc-tm configure failed with %d\n", rc);
- goto fail;
- }
- } else {
- rc = qpnp_adc_tm_hc_configure(chip,
- chip->adc->amux_prop);
- if (rc) {
- pr_err("hc configure failed with %d\n", rc);
- goto fail;
- }
+ rc = qpnp_adc_tm_hc_configure(chip, chip->adc->amux_prop);
+ if (rc) {
+ pr_err("hc configure failed with %d\n", rc);
+ goto fail;
}
} else if (mode == THERMAL_DEVICE_DISABLED) {
sensor_mask = 1 << adc_tm->sensor_num;
- if (!chip->adc_tm_hc) {
- mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
- rc = qpnp_adc_tm_mode_select(chip, mode_ctl);
- if (rc < 0) {
- pr_err("adc-tm single mode select failed\n");
- goto fail;
- }
- }
-
/* Disable bank */
rc = qpnp_adc_tm_disable(chip);
if (rc < 0) {
@@ -1558,28 +946,12 @@
goto fail;
}
- if (!chip->adc_tm_hc) {
- /* Check if a conversion is in progress */
- rc = qpnp_adc_tm_req_sts_check(chip);
- if (rc < 0) {
- pr_err("adc-tm req_sts check failed\n");
- goto fail;
- }
-
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_MULTI_MEAS_EN, sensor_mask, false);
- if (rc < 0) {
- pr_err("multi measurement update failed\n");
- goto fail;
- }
- } else {
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_BTM_Mn_EN(btm_chan_idx),
- QPNP_BTM_Mn_MEAS_EN, false);
- if (rc < 0) {
- pr_err("multi measurement disable failed\n");
- goto fail;
- }
+ rc = qpnp_adc_tm_reg_update(chip,
+ QPNP_BTM_Mn_EN(btm_chan_idx),
+ QPNP_BTM_Mn_MEAS_EN, false);
+ if (rc < 0) {
+ pr_err("multi measurement disable failed\n");
+ goto fail;
}
rc = qpnp_adc_tm_enable_if_channel_meas(chip);
@@ -1597,11 +969,13 @@
return 0;
}
-static int qpnp_adc_tm_get_trip_type(struct thermal_zone_device *thermal,
- int trip, enum thermal_trip_type *type)
+static int qpnp_adc_tm_activate_trip_type(struct qpnp_adc_tm_sensor *adc_tm,
+ int trip, enum thermal_trip_activation_mode mode)
{
- struct qpnp_adc_tm_sensor *adc_tm = thermal->devdata;
struct qpnp_adc_tm_chip *chip = adc_tm->chip;
+ int rc = 0, sensor_mask = 0;
+ bool state = false;
+ uint32_t btm_chan_idx = 0, btm_chan = 0;
if (qpnp_adc_tm_is_valid(chip))
return -ENODEV;
@@ -1609,110 +983,48 @@
if (qpnp_adc_tm_check_revision(chip, adc_tm->btm_channel_num))
return -EINVAL;
- switch (trip) {
- case ADC_TM_TRIP_HIGH_WARM:
- *type = THERMAL_TRIP_CONFIGURABLE_HI;
- break;
- case ADC_TM_TRIP_LOW_COOL:
- *type = THERMAL_TRIP_CONFIGURABLE_LOW;
- break;
- default:
- return -EINVAL;
- }
+ if (mode == THERMAL_TRIP_ACTIVATION_ENABLED)
+ state = true;
- return 0;
-}
+ sensor_mask = 1 << adc_tm->sensor_num;
-static int qpnp_adc_tm_get_trip_temp(struct thermal_zone_device *thermal,
- int trip, int *temp)
-{
- struct qpnp_adc_tm_sensor *adc_tm_sensor = thermal->devdata;
- struct qpnp_adc_tm_chip *chip = adc_tm_sensor->chip;
- int64_t result = 0;
- u8 trip_cool_thr0, trip_cool_thr1, trip_warm_thr0, trip_warm_thr1;
- unsigned int reg, rc = 0;
- uint16_t reg_low_thr_lsb, reg_low_thr_msb;
- uint16_t reg_high_thr_lsb, reg_high_thr_msb;
- uint32_t btm_chan_idx = 0, btm_chan = 0;
+ pr_debug("Sensor number:%x with state:%d\n",
+ adc_tm->sensor_num, state);
- if (qpnp_adc_tm_is_valid(chip))
- return -ENODEV;
-
- if (qpnp_adc_tm_check_revision(chip, adc_tm_sensor->btm_channel_num))
- return -EINVAL;
-
- btm_chan = adc_tm_sensor->btm_channel_num;
+ btm_chan = adc_tm->btm_channel_num;
rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
if (rc < 0) {
pr_err("Invalid btm channel idx\n");
return rc;
}
- if (!chip->adc_tm_hc) {
- reg_low_thr_lsb = adc_tm_data[btm_chan_idx].low_thr_lsb_addr;
- reg_low_thr_msb = adc_tm_data[btm_chan_idx].low_thr_msb_addr;
- reg_high_thr_lsb = adc_tm_data[btm_chan_idx].high_thr_lsb_addr;
- reg_high_thr_msb = adc_tm_data[btm_chan_idx].high_thr_msb_addr;
- } else {
- reg_low_thr_lsb = QPNP_BTM_Mn_LOW_THR0(btm_chan_idx);
- reg_low_thr_msb = QPNP_BTM_Mn_LOW_THR1(btm_chan_idx);
- reg_high_thr_lsb = QPNP_BTM_Mn_HIGH_THR0(btm_chan_idx);
- reg_high_thr_msb = QPNP_BTM_Mn_HIGH_THR1(btm_chan_idx);
- }
-
switch (trip) {
case ADC_TM_TRIP_HIGH_WARM:
- rc = qpnp_adc_tm_read_reg(chip, reg_low_thr_lsb,
- &trip_warm_thr0, 1);
- if (rc) {
- pr_err("adc-tm low_thr_lsb err\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_read_reg(chip, reg_low_thr_msb,
- &trip_warm_thr1, 1);
- if (rc) {
- pr_err("adc-tm low_thr_msb err\n");
- return rc;
- }
- reg = (trip_warm_thr1 << 8) | trip_warm_thr0;
+ /* low_thr (lower voltage) for higher temp */
+ rc = qpnp_adc_tm_reg_update(chip,
+ QPNP_BTM_Mn_EN(btm_chan_idx),
+ QPNP_BTM_Mn_LOW_THR_INT_EN, state);
+ if (rc)
+ pr_err("channel:%x failed\n", btm_chan);
break;
case ADC_TM_TRIP_LOW_COOL:
- rc = qpnp_adc_tm_read_reg(chip, reg_high_thr_lsb,
- &trip_cool_thr0, 1);
- if (rc) {
- pr_err("adc-tm_tm high_thr_lsb err\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_read_reg(chip, reg_high_thr_msb,
- &trip_cool_thr1, 1);
- if (rc) {
- pr_err("adc-tm_tm high_thr_lsb err\n");
- return rc;
- }
- reg = (trip_cool_thr1 << 8) | trip_cool_thr0;
+ /* high_thr (higher voltage) for cooler temp */
+ rc = qpnp_adc_tm_reg_update(chip,
+ QPNP_BTM_Mn_EN(btm_chan_idx),
+ QPNP_BTM_Mn_HIGH_THR_INT_EN, state);
+ if (rc)
+ pr_err("channel:%x failed\n", btm_chan);
break;
default:
return -EINVAL;
}
- rc = qpnp_adc_tm_scale_voltage_therm_pu2(chip->vadc_dev,
- chip->adc->adc_prop, reg, &result);
- if (rc < 0) {
- pr_err("Failed to lookup the therm thresholds\n");
- return rc;
- }
-
- *temp = result;
-
- return 0;
+ return rc;
}
-static int qpnp_adc_tm_set_trip_temp(struct thermal_zone_device *thermal,
- int trip, int temp)
+static int qpnp_adc_tm_set_trip_temp(void *data, int low_temp, int high_temp)
{
- struct qpnp_adc_tm_sensor *adc_tm = thermal->devdata;
+ struct qpnp_adc_tm_sensor *adc_tm = data;
struct qpnp_adc_tm_chip *chip = adc_tm->chip;
struct qpnp_adc_tm_config tm_config;
u8 trip_cool_thr0, trip_cool_thr1, trip_warm_thr0, trip_warm_thr1;
@@ -1729,19 +1041,18 @@
tm_config.channel = adc_tm->vadc_channel_num;
tm_config.high_thr_temp = tm_config.low_thr_temp = 0;
- switch (trip) {
- case ADC_TM_TRIP_HIGH_WARM:
- tm_config.high_thr_temp = temp;
- break;
- case ADC_TM_TRIP_LOW_COOL:
- tm_config.low_thr_temp = temp;
- break;
- default:
+ if (high_temp != INT_MAX)
+ tm_config.high_thr_temp = high_temp;
+ if (low_temp != INT_MIN)
+ tm_config.low_thr_temp = low_temp;
+
+ if ((high_temp == INT_MAX) && (low_temp == INT_MIN)) {
+ pr_err("No trips to set\n");
return -EINVAL;
}
- pr_debug("requested a high - %d and low - %d with trip - %d\n",
- tm_config.high_thr_temp, tm_config.low_thr_temp, trip);
+ pr_debug("requested a high - %d and low - %d\n",
+ tm_config.high_thr_temp, tm_config.low_thr_temp);
rc = qpnp_adc_tm_scale_therm_voltage_pu2(chip->vadc_dev,
chip->adc->adc_prop, &tm_config);
if (rc < 0) {
@@ -1764,20 +1075,12 @@
return rc;
}
- if (!chip->adc_tm_hc) {
- reg_low_thr_lsb = adc_tm_data[btm_chan_idx].low_thr_lsb_addr;
- reg_low_thr_msb = adc_tm_data[btm_chan_idx].low_thr_msb_addr;
- reg_high_thr_lsb = adc_tm_data[btm_chan_idx].high_thr_lsb_addr;
- reg_high_thr_msb = adc_tm_data[btm_chan_idx].high_thr_msb_addr;
- } else {
- reg_low_thr_lsb = QPNP_BTM_Mn_LOW_THR0(btm_chan_idx);
- reg_low_thr_msb = QPNP_BTM_Mn_LOW_THR1(btm_chan_idx);
- reg_high_thr_lsb = QPNP_BTM_Mn_HIGH_THR0(btm_chan_idx);
- reg_high_thr_msb = QPNP_BTM_Mn_HIGH_THR1(btm_chan_idx);
- }
+ reg_low_thr_lsb = QPNP_BTM_Mn_LOW_THR0(btm_chan_idx);
+ reg_low_thr_msb = QPNP_BTM_Mn_LOW_THR1(btm_chan_idx);
+ reg_high_thr_lsb = QPNP_BTM_Mn_HIGH_THR0(btm_chan_idx);
+ reg_high_thr_msb = QPNP_BTM_Mn_HIGH_THR1(btm_chan_idx);
- switch (trip) {
- case ADC_TM_TRIP_HIGH_WARM:
+ if (high_temp != INT_MAX) {
rc = qpnp_adc_tm_write_reg(chip, reg_low_thr_lsb,
trip_cool_thr0, 1);
if (rc) {
@@ -1791,9 +1094,26 @@
pr_err("adc-tm_tm read threshold err\n");
return rc;
}
- adc_tm->low_thr = tm_config.high_thr_voltage;
- break;
- case ADC_TM_TRIP_LOW_COOL:
+ adc_tm->low_thr = tm_config.high_thr_voltage;
+
+ rc = qpnp_adc_tm_activate_trip_type(adc_tm,
+ ADC_TM_TRIP_HIGH_WARM,
+ THERMAL_TRIP_ACTIVATION_ENABLED);
+ if (rc) {
+ pr_err("adc-tm warm activation failed\n");
+ return rc;
+ }
+ } else {
+ rc = qpnp_adc_tm_activate_trip_type(adc_tm,
+ ADC_TM_TRIP_HIGH_WARM,
+ THERMAL_TRIP_ACTIVATION_DISABLED);
+ if (rc) {
+ pr_err("adc-tm warm deactivation failed\n");
+ return rc;
+ }
+ }
+
+ if (low_temp != INT_MIN) {
rc = qpnp_adc_tm_write_reg(chip, reg_high_thr_lsb,
trip_warm_thr0, 1);
if (rc) {
@@ -1807,10 +1127,37 @@
pr_err("adc-tm_tm read threshold err\n");
return rc;
}
- adc_tm->high_thr = tm_config.low_thr_voltage;
- break;
- default:
- return -EINVAL;
+ adc_tm->high_thr = tm_config.low_thr_voltage;
+
+ rc = qpnp_adc_tm_activate_trip_type(adc_tm,
+ ADC_TM_TRIP_LOW_COOL,
+ THERMAL_TRIP_ACTIVATION_ENABLED);
+ if (rc) {
+ pr_err("adc-tm cool activation failed\n");
+ return rc;
+ }
+ } else {
+ rc = qpnp_adc_tm_activate_trip_type(adc_tm,
+ ADC_TM_TRIP_LOW_COOL,
+ THERMAL_TRIP_ACTIVATION_DISABLED);
+ if (rc) {
+ pr_err("adc-tm cool deactivation failed\n");
+ return rc;
+ }
+ }
+
+ if ((high_temp != INT_MAX) || (low_temp != INT_MIN)) {
+ rc = qpnp_adc_tm_set_mode(adc_tm, THERMAL_DEVICE_ENABLED);
+ if (rc) {
+ pr_err("sensor enabled failed\n");
+ return rc;
+ }
+ } else {
+ rc = qpnp_adc_tm_set_mode(adc_tm, THERMAL_DEVICE_DISABLED);
+ if (rc) {
+ pr_err("sensor disable failed\n");
+ return rc;
+ }
}
return 0;
@@ -1878,9 +1225,8 @@
struct qpnp_adc_tm_chip *chip = adc_tm->chip;
if (adc_tm->thermal_node) {
- sysfs_notify(&adc_tm->tz_dev->device.kobj,
- NULL, "type");
pr_debug("notifying uspace client\n");
+ of_thermal_handle_trip(adc_tm->tz_dev);
} else {
if (adc_tm->scale_type == SCALE_RBATT_THERM)
notify_battery_therm(adc_tm);
@@ -1891,222 +1237,23 @@
atomic_dec(&chip->wq_cnt);
}
-static int qpnp_adc_tm_activate_trip_type(struct thermal_zone_device *thermal,
- int trip, enum thermal_trip_activation_mode mode)
-{
- struct qpnp_adc_tm_sensor *adc_tm = thermal->devdata;
- struct qpnp_adc_tm_chip *chip = adc_tm->chip;
- int rc = 0, sensor_mask = 0;
- u8 thr_int_en = 0;
- bool state = false;
- uint32_t btm_chan_idx = 0, btm_chan = 0;
-
- if (qpnp_adc_tm_is_valid(chip))
- return -ENODEV;
-
- if (qpnp_adc_tm_check_revision(chip, adc_tm->btm_channel_num))
- return -EINVAL;
-
- if (mode == THERMAL_TRIP_ACTIVATION_ENABLED)
- state = true;
-
- sensor_mask = 1 << adc_tm->sensor_num;
-
- pr_debug("Sensor number:%x with state:%d\n",
- adc_tm->sensor_num, state);
-
- btm_chan = adc_tm->btm_channel_num;
- rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan, &btm_chan_idx);
- if (rc < 0) {
- pr_err("Invalid btm channel idx\n");
- return rc;
- }
-
- switch (trip) {
- case ADC_TM_TRIP_HIGH_WARM:
- /* low_thr (lower voltage) for higher temp */
- thr_int_en = adc_tm_data[btm_chan_idx].low_thr_int_chan_en;
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_LOW_THR_INT_EN,
- sensor_mask, state);
- else
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_BTM_Mn_EN(btm_chan_idx),
- QPNP_BTM_Mn_LOW_THR_INT_EN, state);
- if (rc)
- pr_err("channel:%x failed\n", btm_chan);
- break;
- case ADC_TM_TRIP_LOW_COOL:
- /* high_thr (higher voltage) for cooler temp */
- thr_int_en = adc_tm_data[btm_chan_idx].high_thr_int_chan_en;
- if (!chip->adc_tm_hc)
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_HIGH_THR_INT_EN,
- sensor_mask, state);
- else
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_BTM_Mn_EN(btm_chan_idx),
- QPNP_BTM_Mn_HIGH_THR_INT_EN, state);
- if (rc)
- pr_err("channel:%x failed\n", btm_chan);
- break;
- default:
- return -EINVAL;
- }
-
- return rc;
-}
-
-static int qpnp_adc_tm_recalib_request_check(struct qpnp_adc_tm_chip *chip,
- int sensor_num, u8 status_high, u8 *notify_check)
-{
- int rc = 0;
- u8 sensor_mask = 0, mode_ctl = 0;
- int32_t old_thr = 0, new_thr = 0;
- uint32_t channel, btm_chan_num, scale_type;
- struct qpnp_vadc_result result;
- struct qpnp_adc_thr_client_info *client_info = NULL;
- struct list_head *thr_list;
- bool status = false;
-
- if (!chip->adc_tm_recalib_check) {
- *notify_check = 1;
- return rc;
- }
-
- list_for_each(thr_list, &chip->sensor[sensor_num].thr_list) {
- client_info = list_entry(thr_list,
- struct qpnp_adc_thr_client_info, list);
- channel = client_info->btm_param->channel;
- btm_chan_num = chip->sensor[sensor_num].btm_channel_num;
- sensor_mask = 1 << sensor_num;
-
- rc = qpnp_vadc_read(chip->vadc_dev, channel, &result);
- if (rc < 0) {
- pr_err("failure to read vadc channel=%d\n",
- client_info->btm_param->channel);
- goto fail;
- }
- new_thr = result.physical;
-
- if (status_high)
- old_thr = client_info->btm_param->high_thr;
- else
- old_thr = client_info->btm_param->low_thr;
-
- if (new_thr > old_thr)
- status = (status_high) ? true : false;
- else
- status = (status_high) ? false : true;
-
- pr_debug(
- "recalib:sen=%d, new_thr=%d, new_thr_adc_code=0x%x, old_thr=%d status=%d valid_status=%d\n",
- sensor_num, new_thr, result.adc_code,
- old_thr, status_high, status);
-
- rc = qpnp_adc_tm_read_thr_value(chip, btm_chan_num);
- if (rc < 0) {
- pr_err("adc-tm thresholds read failed\n");
- goto fail;
- }
-
- if (status) {
- *notify_check = 1;
- pr_debug("Client can be notify\n");
- return rc;
- }
-
- pr_debug("Client can not be notify, restart measurement\n");
- /* Set measurement in single measurement mode */
- mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
- rc = qpnp_adc_tm_mode_select(chip, mode_ctl);
- if (rc < 0) {
- pr_err("adc-tm single mode select failed\n");
- goto fail;
- }
-
- /* Disable bank */
- rc = qpnp_adc_tm_disable(chip);
- if (rc < 0) {
- pr_err("adc-tm disable failed\n");
- goto fail;
- }
-
- /* Check if a conversion is in progress */
- rc = qpnp_adc_tm_req_sts_check(chip);
- if (rc < 0) {
- pr_err("adc-tm req_sts check failed\n");
- goto fail;
- }
-
- rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_LOW_THR_INT_EN,
- sensor_mask, false);
- if (rc < 0) {
- pr_err("low threshold int write failed\n");
- goto fail;
- }
-
- rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_HIGH_THR_INT_EN,
- sensor_mask, false);
- if (rc < 0) {
- pr_err("high threshold int enable failed\n");
- goto fail;
- }
-
- rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
- sensor_mask, false);
- if (rc < 0) {
- pr_err("multi measurement en failed\n");
- goto fail;
- }
-
- /* restart measurement */
- scale_type = chip->sensor[sensor_num].scale_type;
- chip->adc->amux_prop->amux_channel = channel;
- chip->adc->amux_prop->decimation =
- chip->adc->adc_channels[sensor_num].adc_decimation;
- chip->adc->amux_prop->hw_settle_time =
- chip->adc->adc_channels[sensor_num].hw_settle_time;
- chip->adc->amux_prop->fast_avg_setup =
- chip->adc->adc_channels[sensor_num].fast_avg_setup;
- chip->adc->amux_prop->mode_sel =
- ADC_OP_MEASUREMENT_INTERVAL << QPNP_OP_MODE_SHIFT;
- adc_tm_rscale_fn[scale_type].chan(chip->vadc_dev,
- client_info->btm_param,
- &chip->adc->amux_prop->chan_prop->low_thr,
- &chip->adc->amux_prop->chan_prop->high_thr);
- qpnp_adc_tm_add_to_list(chip, sensor_num,
- client_info->btm_param,
- chip->adc->amux_prop->chan_prop);
- chip->adc->amux_prop->chan_prop->tm_channel_select =
- chip->sensor[sensor_num].btm_channel_num;
- chip->adc->amux_prop->chan_prop->state_request =
- client_info->btm_param->state_request;
-
- rc = qpnp_adc_tm_configure(chip, chip->adc->amux_prop);
- if (rc) {
- pr_err("adc-tm configure failed with %d\n", rc);
- goto fail;
- }
- *notify_check = 0;
- pr_debug("BTM channel reconfigured for measuremnt\n");
- }
-fail:
- return rc;
-}
-
static int qpnp_adc_tm_disable_rearm_high_thresholds(
struct qpnp_adc_tm_chip *chip, int sensor_num)
{
struct qpnp_adc_thr_client_info *client_info = NULL;
struct list_head *thr_list;
- uint32_t btm_chan_num = 0;
- u8 sensor_mask = 0, notify_check = 0;
+ uint32_t btm_chan_num = 0, btm_chan_idx = 0;
+ u8 sensor_mask = 0;
int rc = 0;
btm_chan_num = chip->sensor[sensor_num].btm_channel_num;
+ rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan_num, &btm_chan_idx);
+ if (rc < 0) {
+ pr_err("Invalid btm channel idx\n");
+ return rc;
+ }
+
pr_debug("high:sen:%d, hs:0x%x, ls:0x%x, meas_en:0x%x\n",
sensor_num, chip->th_info.adc_tm_high_enable,
chip->th_info.adc_tm_low_enable,
@@ -2118,11 +1265,11 @@
*/
sensor_mask = 1 << sensor_num;
pr_debug("non thermal node - mask:%x\n", sensor_mask);
- rc = qpnp_adc_tm_recalib_request_check(chip,
- sensor_num, true, ¬ify_check);
- if (rc < 0 || !notify_check) {
- pr_debug("Calib recheck re-armed rc=%d\n", rc);
- chip->th_info.adc_tm_high_enable = 0;
+ rc = qpnp_adc_tm_reg_update(chip,
+ QPNP_BTM_Mn_EN(btm_chan_idx),
+ QPNP_BTM_Mn_HIGH_THR_INT_EN, false);
+ if (rc < 0) {
+ pr_err("high threshold int update failed\n");
return rc;
}
} else {
@@ -2134,7 +1281,7 @@
sensor_mask = 1 << sensor_num;
pr_debug("thermal node with mask:%x\n", sensor_mask);
rc = qpnp_adc_tm_activate_trip_type(
- chip->sensor[sensor_num].tz_dev,
+ &chip->sensor[sensor_num],
ADC_TM_TRIP_LOW_COOL,
THERMAL_TRIP_ACTIVATION_DISABLED);
if (rc < 0) {
@@ -2159,22 +1306,12 @@
}
qpnp_adc_tm_manage_thresholds(chip, sensor_num, btm_chan_num);
- if (!chip->adc_tm_hc) {
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_MULTI_MEAS_EN,
- sensor_mask, false);
- if (rc < 0) {
- pr_err("multi meas disable failed\n");
- return rc;
- }
- } else {
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_BTM_Mn_EN(sensor_num),
- QPNP_BTM_Mn_MEAS_EN, false);
- if (rc < 0) {
- pr_err("multi meas disable failed\n");
- return rc;
- }
+ rc = qpnp_adc_tm_reg_update(chip,
+ QPNP_BTM_Mn_EN(sensor_num),
+ QPNP_BTM_Mn_MEAS_EN, false);
+ if (rc < 0) {
+ pr_err("multi meas disable failed\n");
+ return rc;
}
rc = qpnp_adc_tm_enable_if_channel_meas(chip);
@@ -2194,11 +1331,17 @@
{
struct qpnp_adc_thr_client_info *client_info = NULL;
struct list_head *thr_list;
- uint32_t btm_chan_num = 0;
- u8 sensor_mask = 0, notify_check = 0;
+ uint32_t btm_chan_num = 0, btm_chan_idx = 0;
+ u8 sensor_mask = 0;
int rc = 0;
btm_chan_num = chip->sensor[sensor_num].btm_channel_num;
+ rc = qpnp_adc_tm_get_btm_idx(chip, btm_chan_num, &btm_chan_idx);
+ if (rc < 0) {
+ pr_err("Invalid btm channel idx\n");
+ return rc;
+ }
+
pr_debug("low:sen:%d, hs:0x%x, ls:0x%x, meas_en:0x%x\n",
sensor_num, chip->th_info.adc_tm_high_enable,
chip->th_info.adc_tm_low_enable,
@@ -2208,20 +1351,13 @@
* For non thermal registered clients such as usb_id,
* vbatt, pmic_therm
*/
- pr_debug("non thermal node - mask:%x\n", sensor_mask);
- rc = qpnp_adc_tm_recalib_request_check(chip,
- sensor_num, false, ¬ify_check);
- if (rc < 0 || !notify_check) {
- pr_debug("Calib recheck re-armed rc=%d\n", rc);
- chip->th_info.adc_tm_low_enable = 0;
- return rc;
- }
sensor_mask = 1 << sensor_num;
+ pr_debug("non thermal node - mask:%x\n", sensor_mask);
rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_LOW_THR_INT_EN,
- sensor_mask, false);
+ QPNP_BTM_Mn_EN(btm_chan_idx),
+ QPNP_BTM_Mn_LOW_THR_INT_EN, false);
if (rc < 0) {
- pr_err("low threshold int read failed\n");
+ pr_err("low threshold int update failed\n");
return rc;
}
} else {
@@ -2233,7 +1369,7 @@
sensor_mask = 1 << sensor_num;
pr_debug("thermal node with mask:%x\n", sensor_mask);
rc = qpnp_adc_tm_activate_trip_type(
- chip->sensor[sensor_num].tz_dev,
+ &chip->sensor[sensor_num],
ADC_TM_TRIP_HIGH_WARM,
THERMAL_TRIP_ACTIVATION_DISABLED);
if (rc < 0) {
@@ -2258,22 +1394,12 @@
}
qpnp_adc_tm_manage_thresholds(chip, sensor_num, btm_chan_num);
- if (!chip->adc_tm_hc) {
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_MULTI_MEAS_EN,
- sensor_mask, false);
- if (rc < 0) {
- pr_err("multi meas disable failed\n");
- return rc;
- }
- } else {
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_BTM_Mn_EN(sensor_num),
- QPNP_BTM_Mn_MEAS_EN, false);
- if (rc < 0) {
- pr_err("multi meas disable failed\n");
- return rc;
- }
+ rc = qpnp_adc_tm_reg_update(chip,
+ QPNP_BTM_Mn_EN(sensor_num),
+ QPNP_BTM_Mn_MEAS_EN, false);
+ if (rc < 0) {
+ pr_err("multi meas disable failed\n");
+ return rc;
}
rc = qpnp_adc_tm_enable_if_channel_meas(chip);
@@ -2299,14 +1425,6 @@
mutex_lock(&chip->adc->adc_lock);
- if (!chip->adc_tm_hc) {
- rc = qpnp_adc_tm_req_sts_check(chip);
- if (rc) {
- pr_err("adc-tm-tm req sts check failed with %d\n", rc);
- goto fail;
- }
- }
-
while (sensor_num < chip->max_channels_available) {
if (chip->sensor[sensor_num].high_thr_triggered) {
rc = qpnp_adc_tm_disable_rearm_high_thresholds(
@@ -2364,93 +1482,6 @@
pr_err("adc-tm high thr work failed\n");
}
-static irqreturn_t qpnp_adc_tm_high_thr_isr(int irq, void *data)
-{
- struct qpnp_adc_tm_chip *chip = data;
- u8 mode_ctl = 0, status1 = 0, sensor_mask = 0;
- int rc = 0, sensor_notify_num = 0, i = 0, sensor_num = 0;
-
- mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
- /* Set measurement in single measurement mode */
- qpnp_adc_tm_mode_select(chip, mode_ctl);
-
- qpnp_adc_tm_disable(chip);
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS1, &status1, 1);
- if (rc) {
- pr_err("adc-tm read status1 failed\n");
- return IRQ_HANDLED;
- }
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS_HIGH,
- &chip->th_info.status_high, 1);
- if (rc) {
- pr_err("adc-tm-tm read status high failed with %d\n", rc);
- return IRQ_HANDLED;
- }
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_HIGH_THR_INT_EN,
- &chip->th_info.adc_tm_high_thr_set, 1);
- if (rc) {
- pr_err("adc-tm-tm read high thr failed with %d\n", rc);
- return IRQ_HANDLED;
- }
-
- /*
- * Check which interrupt threshold is lower and measure against the
- * enabled channel.
- */
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
- &chip->th_info.qpnp_adc_tm_meas_en, 1);
- if (rc) {
- pr_err("adc-tm-tm read status high failed with %d\n", rc);
- return IRQ_HANDLED;
- }
-
- chip->th_info.adc_tm_high_enable = chip->th_info.qpnp_adc_tm_meas_en &
- chip->th_info.status_high;
- chip->th_info.adc_tm_high_enable &= chip->th_info.adc_tm_high_thr_set;
-
- sensor_notify_num = chip->th_info.adc_tm_high_enable;
- while (i < chip->max_channels_available) {
- if ((sensor_notify_num & 0x1) == 1)
- sensor_num = i;
- sensor_notify_num >>= 1;
- i++;
- }
-
- if (!chip->sensor[sensor_num].thermal_node) {
- sensor_mask = 1 << sensor_num;
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_HIGH_THR_INT_EN,
- sensor_mask, false);
- if (rc < 0) {
- pr_err("high threshold int read failed\n");
- return IRQ_HANDLED;
- }
- } else {
- /*
- * Uses the thermal sysfs registered device to disable
- * the corresponding high voltage threshold which
- * is triggered by low temp
- */
- pr_debug("thermal node with mask:%x\n", sensor_mask);
- rc = qpnp_adc_tm_activate_trip_type(
- chip->sensor[sensor_num].tz_dev,
- ADC_TM_TRIP_LOW_COOL,
- THERMAL_TRIP_ACTIVATION_DISABLED);
- if (rc < 0) {
- pr_err("notify error:%d\n", sensor_num);
- return IRQ_HANDLED;
- }
- }
-
- atomic_inc(&chip->wq_cnt);
- queue_work(chip->high_thr_wq, &chip->trigger_high_thr_work);
-
- return IRQ_HANDLED;
-}
-
static void qpnp_adc_tm_low_thr_work(struct work_struct *work)
{
struct qpnp_adc_tm_chip *chip = container_of(work,
@@ -2471,88 +1502,6 @@
pr_err("adc-tm low thr work failed\n");
}
-static irqreturn_t qpnp_adc_tm_low_thr_isr(int irq, void *data)
-{
- struct qpnp_adc_tm_chip *chip = data;
- u8 mode_ctl = 0, status1 = 0, sensor_mask = 0;
- int rc = 0, sensor_notify_num = 0, i = 0, sensor_num = 0;
-
- mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
- /* Set measurement in single measurement mode */
- qpnp_adc_tm_mode_select(chip, mode_ctl);
-
- qpnp_adc_tm_disable(chip);
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS1, &status1, 1);
- if (rc) {
- pr_err("adc-tm read status1 failed\n");
- return IRQ_HANDLED;
- }
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS_LOW,
- &chip->th_info.status_low, 1);
- if (rc) {
- pr_err("adc-tm-tm read status low failed with %d\n", rc);
- return IRQ_HANDLED;
- }
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_LOW_THR_INT_EN,
- &chip->th_info.adc_tm_low_thr_set, 1);
- if (rc) {
- pr_err("adc-tm-tm read low thr failed with %d\n", rc);
- return IRQ_HANDLED;
- }
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
- &chip->th_info.qpnp_adc_tm_meas_en, 1);
- if (rc) {
- pr_err("adc-tm-tm read status high failed with %d\n", rc);
- return IRQ_HANDLED;
- }
-
- chip->th_info.adc_tm_low_enable = chip->th_info.qpnp_adc_tm_meas_en &
- chip->th_info.status_low;
- chip->th_info.adc_tm_low_enable &= chip->th_info.adc_tm_low_thr_set;
-
- sensor_notify_num = chip->th_info.adc_tm_low_enable;
- while (i < chip->max_channels_available) {
- if ((sensor_notify_num & 0x1) == 1)
- sensor_num = i;
- sensor_notify_num >>= 1;
- i++;
- }
-
- if (!chip->sensor[sensor_num].thermal_node) {
- sensor_mask = 1 << sensor_num;
- rc = qpnp_adc_tm_reg_update(chip,
- QPNP_ADC_TM_LOW_THR_INT_EN,
- sensor_mask, false);
- if (rc < 0) {
- pr_err("low threshold int read failed\n");
- return IRQ_HANDLED;
- }
- } else {
- /* Uses the thermal sysfs registered device to disable
- * the corresponding low voltage threshold which
- * is triggered by high temp
- */
- pr_debug("thermal node with mask:%x\n", sensor_mask);
- rc = qpnp_adc_tm_activate_trip_type(
- chip->sensor[sensor_num].tz_dev,
- ADC_TM_TRIP_HIGH_WARM,
- THERMAL_TRIP_ACTIVATION_DISABLED);
- if (rc < 0) {
- pr_err("notify error:%d\n", sensor_num);
- return IRQ_HANDLED;
- }
- }
-
- atomic_inc(&chip->wq_cnt);
- queue_work(chip->low_thr_wq, &chip->trigger_low_thr_work);
-
- return IRQ_HANDLED;
-}
-
static int qpnp_adc_tm_rc_check_sensor_trip(struct qpnp_adc_tm_chip *chip,
u8 status_low, u8 status_high, int i,
int *sensor_low_notify_num, int *sensor_high_notify_num)
@@ -2587,7 +1536,7 @@
*/
pr_debug("thermal node with mask:%x\n", sensor_mask);
rc = qpnp_adc_tm_activate_trip_type(
- chip->sensor[i].tz_dev,
+ &chip->sensor[i],
ADC_TM_TRIP_HIGH_WARM,
THERMAL_TRIP_ACTIVATION_DISABLED);
if (rc < 0) {
@@ -2618,7 +1567,7 @@
*/
pr_debug("thermal node with mask:%x\n", i);
rc = qpnp_adc_tm_activate_trip_type(
- chip->sensor[i].tz_dev,
+ &chip->sensor[i],
ADC_TM_TRIP_LOW_COOL,
THERMAL_TRIP_ACTIVATION_DISABLED);
if (rc < 0) {
@@ -2688,10 +1637,9 @@
return IRQ_HANDLED;
}
-static int qpnp_adc_read_temp(struct thermal_zone_device *thermal,
- int *temp)
+static int qpnp_adc_read_temp(void *data, int *temp)
{
- struct qpnp_adc_tm_sensor *adc_tm_sensor = thermal->devdata;
+ struct qpnp_adc_tm_sensor *adc_tm_sensor = data;
struct qpnp_adc_tm_chip *chip = adc_tm_sensor->chip;
struct qpnp_vadc_result result;
int rc = 0;
@@ -2706,14 +1654,9 @@
return rc;
}
-static struct thermal_zone_device_ops qpnp_adc_tm_thermal_ops = {
+static struct thermal_zone_of_device_ops qpnp_adc_tm_thermal_ops = {
.get_temp = qpnp_adc_read_temp,
- .get_mode = qpnp_adc_tm_get_mode,
- .set_mode = qpnp_adc_tm_set_mode,
- .get_trip_type = qpnp_adc_tm_get_trip_type,
- .activate_trip_type = qpnp_adc_tm_activate_trip_type,
- .get_trip_temp = qpnp_adc_tm_get_trip_temp,
- .set_trip_temp = qpnp_adc_tm_set_trip_temp,
+ .set_trips = qpnp_adc_tm_set_trip_temp,
};
int32_t qpnp_adc_tm_channel_measure(struct qpnp_adc_tm_chip *chip,
@@ -2807,18 +1750,11 @@
param->state_request;
chip->adc->amux_prop->calib_type =
chip->adc->adc_channels[dt_index].calib_type;
- if (!chip->adc_tm_hc) {
- rc = qpnp_adc_tm_configure(chip, chip->adc->amux_prop);
- if (rc) {
- pr_err("adc-tm configure failed with %d\n", rc);
- goto fail_unlock;
- }
- } else {
- rc = qpnp_adc_tm_hc_configure(chip, chip->adc->amux_prop);
- if (rc) {
- pr_err("adc-tm hc configure failed with %d\n", rc);
- goto fail_unlock;
- }
+
+ rc = qpnp_adc_tm_hc_configure(chip, chip->adc->amux_prop);
+ if (rc) {
+ pr_err("adc-tm hc configure failed with %d\n", rc);
+ goto fail_unlock;
}
chip->sensor[dt_index].scale_type = scale_type;
@@ -2834,7 +1770,6 @@
struct qpnp_adc_tm_btm_param *param)
{
uint32_t channel, dt_index = 0, btm_chan_num;
- u8 sensor_mask = 0, mode_ctl = 0;
int rc = 0;
if (qpnp_adc_tm_is_valid(chip))
@@ -2842,16 +1777,6 @@
mutex_lock(&chip->adc->adc_lock);
- if (!chip->adc_tm_hc) {
- /* Set measurement in single measurement mode */
- mode_ctl = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
- rc = qpnp_adc_tm_mode_select(chip, mode_ctl);
- if (rc < 0) {
- pr_err("adc-tm single mode select failed\n");
- goto fail;
- }
- }
-
/* Disable bank */
rc = qpnp_adc_tm_disable(chip);
if (rc < 0) {
@@ -2859,15 +1784,6 @@
goto fail;
}
- if (!chip->adc_tm_hc) {
- /* Check if a conversion is in progress */
- rc = qpnp_adc_tm_req_sts_check(chip);
- if (rc < 0) {
- pr_err("adc-tm req_sts check failed\n");
- goto fail;
- }
- }
-
channel = param->channel;
while ((chip->adc->adc_channels[dt_index].channel_num
!= channel) && (dt_index < chip->max_channels_available))
@@ -2881,50 +1797,25 @@
btm_chan_num = chip->sensor[dt_index].btm_channel_num;
- if (!chip->adc_tm_hc) {
- sensor_mask = 1 << chip->sensor[dt_index].sensor_num;
+ rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_num),
+ QPNP_BTM_Mn_HIGH_THR_INT_EN, false);
+ if (rc < 0) {
+ pr_err("high thr disable err:%d\n", btm_chan_num);
+ return rc;
+ }
- rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_LOW_THR_INT_EN,
- sensor_mask, false);
- if (rc < 0) {
- pr_err("low threshold int write failed\n");
- goto fail;
- }
+ rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_num),
+ QPNP_BTM_Mn_LOW_THR_INT_EN, false);
+ if (rc < 0) {
+ pr_err("low thr disable err:%d\n", btm_chan_num);
+ return rc;
+ }
- rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_HIGH_THR_INT_EN,
- sensor_mask, false);
- if (rc < 0) {
- pr_err("high threshold int enable failed\n");
- goto fail;
- }
-
- rc = qpnp_adc_tm_reg_update(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
- sensor_mask, false);
- if (rc < 0) {
- pr_err("multi measurement en failed\n");
- goto fail;
- }
- } else {
- rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_num),
- QPNP_BTM_Mn_HIGH_THR_INT_EN, false);
- if (rc < 0) {
- pr_err("high thr disable err:%d\n", btm_chan_num);
- return rc;
- }
-
- rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_num),
- QPNP_BTM_Mn_LOW_THR_INT_EN, false);
- if (rc < 0) {
- pr_err("low thr disable err:%d\n", btm_chan_num);
- return rc;
- }
-
- rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_num),
- QPNP_BTM_Mn_MEAS_EN, false);
- if (rc < 0) {
- pr_err("multi measurement disable failed\n");
- return rc;
- }
+ rc = qpnp_adc_tm_reg_update(chip, QPNP_BTM_Mn_EN(btm_chan_num),
+ QPNP_BTM_Mn_MEAS_EN, false);
+ if (rc < 0) {
+ pr_err("multi measurement disable failed\n");
+ return rc;
}
rc = qpnp_adc_tm_enable_if_channel_meas(chip);
@@ -2938,22 +1829,6 @@
}
EXPORT_SYMBOL(qpnp_adc_tm_disable_chan_meas);
-int32_t qpnp_adc_tm_usbid_configure(struct qpnp_adc_tm_chip *chip,
- struct qpnp_adc_tm_btm_param *param)
-{
- param->channel = LR_MUX10_PU2_AMUX_USB_ID_LV;
- return qpnp_adc_tm_channel_measure(chip, param);
-}
-EXPORT_SYMBOL(qpnp_adc_tm_usbid_configure);
-
-int32_t qpnp_adc_tm_usbid_end(struct qpnp_adc_tm_chip *chip)
-{
- struct qpnp_adc_tm_btm_param param;
-
- return qpnp_adc_tm_disable_chan_meas(chip, ¶m);
-}
-EXPORT_SYMBOL(qpnp_adc_tm_usbid_end);
-
struct qpnp_adc_tm_chip *qpnp_get_adc_tm(struct device *dev, const char *name)
{
struct qpnp_adc_tm_chip *chip;
@@ -2974,35 +1849,6 @@
}
EXPORT_SYMBOL(qpnp_get_adc_tm);
-static int qpnp_adc_tm_initial_setup(struct qpnp_adc_tm_chip *chip)
-{
- u8 thr_init = 0;
- int rc = 0;
-
- rc = qpnp_adc_tm_write_reg(chip, QPNP_ADC_TM_HIGH_THR_INT_EN,
- thr_init, 1);
- if (rc < 0) {
- pr_err("high thr init failed\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_write_reg(chip, QPNP_ADC_TM_LOW_THR_INT_EN,
- thr_init, 1);
- if (rc < 0) {
- pr_err("low thr init failed\n");
- return rc;
- }
-
- rc = qpnp_adc_tm_write_reg(chip, QPNP_ADC_TM_MULTI_MEAS_EN,
- thr_init, 1);
- if (rc < 0) {
- pr_err("multi meas en failed\n");
- return rc;
- }
-
- return rc;
-}
-
static const struct of_device_id qpnp_adc_tm_match_table[] = {
{ .compatible = "qcom,qpnp-adc-tm" },
{ .compatible = "qcom,qpnp-adc-tm-hc" },
@@ -3055,10 +1901,8 @@
goto fail;
}
- if (of_device_is_compatible(node, "qcom,qpnp-adc-tm-hc")) {
- chip->adc_tm_hc = true;
- chip->adc->adc_hc = true;
- }
+ chip->adc_tm_hc = true;
+ chip->adc->adc_hc = true;
rc = qpnp_adc_get_devicetree_data(pdev, chip->adc);
if (rc) {
@@ -3067,25 +1911,6 @@
}
mutex_init(&chip->adc->adc_lock);
- /* Register the ADC peripheral interrupt */
- if (!chip->adc_tm_hc) {
- chip->adc->adc_high_thr_irq = platform_get_irq_byname(pdev,
- "high-thr-en-set");
- if (chip->adc->adc_high_thr_irq < 0) {
- pr_err("Invalid irq\n");
- rc = -ENXIO;
- goto fail;
- }
-
- chip->adc->adc_low_thr_irq = platform_get_irq_byname(pdev,
- "low-thr-en-set");
- if (chip->adc->adc_low_thr_irq < 0) {
- pr_err("Invalid irq\n");
- rc = -ENXIO;
- goto fail;
- }
- }
-
chip->vadc_dev = qpnp_get_vadc(&pdev->dev, "adc_tm");
if (IS_ERR(chip->vadc_dev)) {
rc = PTR_ERR(chip->vadc_dev);
@@ -3155,10 +1980,11 @@
chip->sensor[sen_idx].high_thr =
QPNP_ADC_TM_M0_HIGH_THR;
chip->sensor[sen_idx].tz_dev =
- thermal_zone_device_register(name,
- ADC_TM_TRIP_NUM, ADC_TM_WRITABLE_TRIPS_MASK,
+ devm_thermal_zone_of_sensor_register(
+ chip->dev,
+ chip->sensor[sen_idx].vadc_channel_num,
&chip->sensor[sen_idx],
- &qpnp_adc_tm_thermal_ops, NULL, 0, 0);
+ &qpnp_adc_tm_thermal_ops);
if (IS_ERR(chip->sensor[sen_idx].tz_dev))
pr_err("thermal device register failed.\n");
}
@@ -3173,18 +1999,21 @@
sen_idx++;
}
chip->max_channels_available = count_adc_channel_list;
+
chip->high_thr_wq = alloc_workqueue("qpnp_adc_tm_high_thr_wq",
WQ_HIGHPRI, 0);
if (!chip->high_thr_wq) {
pr_err("Requesting high thr priority wq failed\n");
goto fail;
}
+
chip->low_thr_wq = alloc_workqueue("qpnp_adc_tm_low_thr_wq",
WQ_HIGHPRI, 0);
if (!chip->low_thr_wq) {
pr_err("Requesting low thr priority wq failed\n");
goto fail;
}
+
chip->thr_wq = alloc_workqueue("qpnp_adc_tm_thr_wq",
WQ_HIGHPRI, 0);
if (!chip->thr_wq) {
@@ -3196,39 +2025,13 @@
INIT_WORK(&chip->trigger_low_thr_work, qpnp_adc_tm_low_thr_work);
atomic_set(&chip->wq_cnt, 0);
- if (!chip->adc_tm_hc) {
- rc = qpnp_adc_tm_initial_setup(chip);
- if (rc)
- goto fail;
-
- rc = devm_request_irq(&pdev->dev, chip->adc->adc_high_thr_irq,
- qpnp_adc_tm_high_thr_isr,
- IRQF_TRIGGER_RISING, "qpnp_adc_tm_high_interrupt", chip);
- if (rc) {
- dev_err(&pdev->dev, "failed to request adc irq\n");
- goto fail;
- } else {
- enable_irq_wake(chip->adc->adc_high_thr_irq);
- }
-
- rc = devm_request_irq(&pdev->dev, chip->adc->adc_low_thr_irq,
- qpnp_adc_tm_low_thr_isr,
- IRQF_TRIGGER_RISING, "qpnp_adc_tm_low_interrupt", chip);
- if (rc) {
- dev_err(&pdev->dev, "failed to request adc irq\n");
- goto fail;
- } else {
- enable_irq_wake(chip->adc->adc_low_thr_irq);
- }
- } else {
- rc = devm_request_irq(&pdev->dev, chip->adc->adc_irq_eoc,
- qpnp_adc_tm_rc_thr_isr,
- IRQF_TRIGGER_RISING, "qpnp_adc_tm_interrupt", chip);
- if (rc)
- dev_err(&pdev->dev, "failed to request adc irq\n");
- else
- enable_irq_wake(chip->adc->adc_irq_eoc);
- }
+ rc = devm_request_irq(&pdev->dev, chip->adc->adc_irq_eoc,
+ qpnp_adc_tm_rc_thr_isr,
+ IRQF_TRIGGER_RISING, "qpnp_adc_tm_interrupt", chip);
+ if (rc)
+ dev_err(&pdev->dev, "failed to request adc irq\n");
+ else
+ enable_irq_wake(chip->adc->adc_irq_eoc);
chip->adc_vote_enable = false;
dev_set_drvdata(&pdev->dev, chip);
@@ -3258,17 +2061,11 @@
{
struct qpnp_adc_tm_chip *chip = dev_get_drvdata(&pdev->dev);
struct device_node *node = pdev->dev.of_node, *child;
- bool thermal_node = false;
int i = 0;
for_each_child_of_node(node, child) {
- thermal_node = of_property_read_bool(child,
- "qcom,thermal-node");
- if (thermal_node) {
- thermal_zone_device_unregister(chip->sensor[i].tz_dev);
- if (chip->sensor[i].req_wq)
- destroy_workqueue(chip->sensor[i].req_wq);
- }
+ if (chip->sensor[i].req_wq)
+ destroy_workqueue(chip->sensor[i].req_wq);
i++;
}
@@ -3286,40 +2083,20 @@
static void qpnp_adc_tm_shutdown(struct platform_device *pdev)
{
struct qpnp_adc_tm_chip *chip = dev_get_drvdata(&pdev->dev);
- int rc = 0;
- u8 reg_val = 0, status1 = 0, en_ctl1 = 0;
-
- /* Set measurement in single measurement mode */
- reg_val = ADC_OP_NORMAL_MODE << QPNP_OP_MODE_SHIFT;
- rc = qpnp_adc_tm_mode_select(chip, reg_val);
- if (rc < 0)
- pr_err("adc-tm single mode select failed\n");
+ int rc = 0, i = 0;
/* Disable bank */
rc = qpnp_adc_tm_disable(chip);
if (rc < 0)
pr_err("adc-tm disable failed\n");
- /* Check if a conversion is in progress */
- rc = qpnp_adc_tm_req_sts_check(chip);
- if (rc < 0)
- pr_err("adc-tm req_sts check failed\n");
-
- /* Disable multimeasurement */
- reg_val = 0;
- rc = qpnp_adc_tm_write_reg(chip, QPNP_ADC_TM_MULTI_MEAS_EN, reg_val, 1);
- if (rc < 0)
- pr_err("adc-tm multi-measurement mode disable failed\n");
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_ADC_TM_STATUS1, &status1, 1);
- if (rc < 0)
- pr_err("adc-tm status1 read failed\n");
-
- rc = qpnp_adc_tm_read_reg(chip, QPNP_EN_CTL1, &en_ctl1, 1);
- if (rc < 0)
- pr_err("adc-tm en_ctl1 read failed\n");
-
- pr_debug("adc-tm status1=0%x, en_ctl1=0x%x\n", status1, en_ctl1);
+ for (i = 0; i < QPNP_BTM_CHANNELS; i++) {
+ rc = qpnp_adc_tm_reg_update(chip,
+ QPNP_BTM_Mn_EN(i),
+ QPNP_BTM_Mn_MEAS_EN, false);
+ if (rc < 0)
+ pr_err("multi measurement disable failed\n");
+ }
}
static int qpnp_adc_tm_suspend_noirq(struct device *dev)
diff --git a/drivers/thermal/qpnp-temp-alarm.c b/drivers/thermal/qpnp-temp-alarm.c
index e86a297..09c95e5 100644
--- a/drivers/thermal/qpnp-temp-alarm.c
+++ b/drivers/thermal/qpnp-temp-alarm.c
@@ -28,6 +28,8 @@
#include <linux/thermal.h>
#include <linux/qpnp/qpnp-adc.h>
+#include "thermal_core.h"
+
#define QPNP_TM_DRIVER_NAME "qcom,qpnp-temp-alarm"
enum qpnp_tm_registers {
@@ -97,7 +99,6 @@
unsigned int subtype;
enum qpnp_tm_adc_type adc_type;
int temperature;
- enum thermal_device_mode mode;
unsigned int thresh;
unsigned int clock_rate;
unsigned int stage;
@@ -105,18 +106,12 @@
int irq;
enum qpnp_vadc_channels adc_channel;
u16 base_addr;
- bool allow_software_override;
struct qpnp_vadc_chip *vadc_dev;
};
/* Delay between TEMP_STAT IRQ going high and status value changing in ms. */
#define STATUS_REGISTER_DELAY_MS 40
-enum pmic_thermal_override_mode {
- SOFTWARE_OVERRIDE_DISABLED = 0,
- SOFTWARE_OVERRIDE_ENABLED,
-};
-
/* This array maps from GEN2 alarm state to GEN1 alarm stage */
const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3};
@@ -156,28 +151,6 @@
return rc;
}
-
-static inline int qpnp_tm_shutdown_override(struct qpnp_tm_chip *chip,
- enum pmic_thermal_override_mode mode)
-{
- int rc = 0;
- u8 reg;
-
- if (chip->allow_software_override) {
- reg = chip->thresh & SHUTDOWN_CTRL1_THRESHOLD_MASK;
- reg |= (chip->clock_rate << SHUTDOWN_CTRL1_CLK_RATE_SHIFT)
- & SHUTDOWN_CTRL1_CLK_RATE_MASK;
-
- if (mode == SOFTWARE_OVERRIDE_ENABLED)
- reg |= SHUTDOWN_CTRL1_OVERRIDE_STAGE2
- | SHUTDOWN_CTRL1_OVERRIDE_STAGE3;
-
- rc = qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®, 1);
- }
-
- return rc;
-}
-
static int qpnp_tm_update_temp(struct qpnp_tm_chip *chip)
{
struct qpnp_vadc_result adc_result;
@@ -274,10 +247,9 @@
return 0;
}
-static int qpnp_tz_get_temp_no_adc(struct thermal_zone_device *thermal,
- int *temperature)
+static int qpnp_tz_get_temp_no_adc(void *data, int *temperature)
{
- struct qpnp_tm_chip *chip = thermal->devdata;
+ struct qpnp_tm_chip *chip = (struct qpnp_tm_chip *)data;
int rc;
if (!temperature)
@@ -292,10 +264,9 @@
return 0;
}
-static int qpnp_tz_get_temp_qpnp_adc(struct thermal_zone_device *thermal,
- int *temperature)
+static int qpnp_tz_get_temp_qpnp_adc(void *data, int *temperature)
{
- struct qpnp_tm_chip *chip = thermal->devdata;
+ struct qpnp_tm_chip *chip = (struct qpnp_tm_chip *)data;
int rc;
if (!temperature)
@@ -314,121 +285,12 @@
return 0;
}
-static int qpnp_tz_get_mode(struct thermal_zone_device *thermal,
- enum thermal_device_mode *mode)
-{
- struct qpnp_tm_chip *chip = thermal->devdata;
-
- if (!mode)
- return -EINVAL;
-
- *mode = chip->mode;
-
- return 0;
-}
-
-static int qpnp_tz_set_mode(struct thermal_zone_device *thermal,
- enum thermal_device_mode mode)
-{
- struct qpnp_tm_chip *chip = thermal->devdata;
- int rc = 0;
-
- if (mode != chip->mode) {
- if (mode == THERMAL_DEVICE_ENABLED)
- rc = qpnp_tm_shutdown_override(chip,
- SOFTWARE_OVERRIDE_ENABLED);
- else
- rc = qpnp_tm_shutdown_override(chip,
- SOFTWARE_OVERRIDE_DISABLED);
-
- chip->mode = mode;
- }
-
- return rc;
-}
-
-static int qpnp_tz_get_trip_type(struct thermal_zone_device *thermal,
- int trip, enum thermal_trip_type *type)
-{
- if (trip < 0 || !type)
- return -EINVAL;
-
- switch (trip) {
- case TRIP_STAGE3:
- *type = THERMAL_TRIP_CRITICAL;
- break;
- case TRIP_STAGE2:
- *type = THERMAL_TRIP_HOT;
- break;
- case TRIP_STAGE1:
- *type = THERMAL_TRIP_HOT;
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int qpnp_tz_get_trip_temp(struct thermal_zone_device *thermal,
- int trip, int *temperature)
-{
- struct qpnp_tm_chip *chip = thermal->devdata;
- int thresh_temperature;
-
- if (trip < 0 || !temperature)
- return -EINVAL;
-
- thresh_temperature = chip->thresh * TEMP_THRESH_STEP + TEMP_THRESH_MIN;
-
- switch (trip) {
- case TRIP_STAGE3:
- thresh_temperature += 2 * TEMP_STAGE_STEP;
- break;
- case TRIP_STAGE2:
- thresh_temperature += TEMP_STAGE_STEP;
- break;
- case TRIP_STAGE1:
- break;
- default:
- return -EINVAL;
- }
-
- *temperature = thresh_temperature;
-
- return 0;
-}
-
-static int qpnp_tz_get_crit_temp(struct thermal_zone_device *thermal,
- int *temperature)
-{
- struct qpnp_tm_chip *chip = thermal->devdata;
-
- if (!temperature)
- return -EINVAL;
-
- *temperature = chip->thresh * TEMP_THRESH_STEP + TEMP_THRESH_MIN +
- 2 * TEMP_STAGE_STEP;
-
- return 0;
-}
-
-static struct thermal_zone_device_ops qpnp_thermal_zone_ops_no_adc = {
+static struct thermal_zone_of_device_ops qpnp_thermal_zone_ops_no_adc = {
.get_temp = qpnp_tz_get_temp_no_adc,
- .get_mode = qpnp_tz_get_mode,
- .set_mode = qpnp_tz_set_mode,
- .get_trip_type = qpnp_tz_get_trip_type,
- .get_trip_temp = qpnp_tz_get_trip_temp,
- .get_crit_temp = qpnp_tz_get_crit_temp,
};
-static struct thermal_zone_device_ops qpnp_thermal_zone_ops_qpnp_adc = {
+static struct thermal_zone_of_device_ops qpnp_thermal_zone_ops_qpnp_adc = {
.get_temp = qpnp_tz_get_temp_qpnp_adc,
- .get_mode = qpnp_tz_get_mode,
- .set_mode = qpnp_tz_set_mode,
- .get_trip_type = qpnp_tz_get_trip_type,
- .get_trip_temp = qpnp_tz_get_trip_temp,
- .get_crit_temp = qpnp_tz_get_crit_temp,
};
static void qpnp_tm_work(struct work_struct *work)
@@ -474,11 +336,7 @@
chip->tm_name, stage_new, chip->stage,
chip->thresh, chip->temperature);
- thermal_zone_device_update(chip->tz_dev,
- THERMAL_EVENT_UNSPECIFIED);
-
- /* Notify user space */
- sysfs_notify(&chip->tz_dev->device.kobj, NULL, "type");
+ of_thermal_handle_trip(chip->tz_dev);
}
bail:
@@ -539,7 +397,7 @@
struct device_node *node;
unsigned int base;
struct qpnp_tm_chip *chip;
- struct thermal_zone_device_ops *tz_ops;
+ struct thermal_zone_of_device_ops *tz_ops;
char *tm_name;
u32 default_temperature;
int rc = 0;
@@ -640,9 +498,6 @@
else
tz_ops = &qpnp_thermal_zone_ops_no_adc;
- chip->allow_software_override
- = of_property_read_bool(node, "qcom,allow-override");
-
default_temperature = DEFAULT_NO_ADC_TEMP;
rc = of_property_read_u32(node, "qcom,default-temp",
&default_temperature);
@@ -686,18 +541,8 @@
}
}
- /* Start in HW control; switch to SW control when user changes mode. */
- chip->mode = THERMAL_DEVICE_DISABLED;
- rc = qpnp_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_DISABLED);
- if (rc) {
- dev_err(&pdev->dev,
- "%s: qpnp_tm_shutdown_override() failed, rc=%d\n",
- __func__, rc);
- goto err_cancel_work;
- }
-
- chip->tz_dev = thermal_zone_device_register(tm_name, TRIP_NUM, 0, chip,
- tz_ops, NULL, 0, 0);
+ chip->tz_dev = thermal_zone_of_sensor_register(&pdev->dev, 0, chip,
+ tz_ops);
if (chip->tz_dev == NULL) {
dev_err(&pdev->dev,
"%s: thermal_zone_device_register() failed.\n",
@@ -717,7 +562,7 @@
return 0;
err_free_tz:
- thermal_zone_device_unregister(chip->tz_dev);
+ thermal_zone_of_sensor_unregister(&pdev->dev, chip->tz_dev);
err_cancel_work:
cancel_delayed_work_sync(&chip->irq_work);
kfree(chip->tm_name);
@@ -731,10 +576,9 @@
{
struct qpnp_tm_chip *chip = dev_get_drvdata(&pdev->dev);
+ thermal_zone_of_sensor_unregister(&pdev->dev, chip->tz_dev);
dev_set_drvdata(&pdev->dev, NULL);
- thermal_zone_device_unregister(chip->tz_dev);
kfree(chip->tm_name);
- qpnp_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_DISABLED);
free_irq(chip->irq, chip);
cancel_delayed_work_sync(&chip->irq_work);
kfree(chip);
@@ -742,38 +586,6 @@
return 0;
}
-#ifdef CONFIG_PM
-static int qpnp_tm_suspend(struct device *dev)
-{
- struct qpnp_tm_chip *chip = dev_get_drvdata(dev);
-
- /* Clear override bits in suspend to allow hardware control */
- qpnp_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_DISABLED);
-
- return 0;
-}
-
-static int qpnp_tm_resume(struct device *dev)
-{
- struct qpnp_tm_chip *chip = dev_get_drvdata(dev);
-
- /* Override hardware actions so software can control */
- if (chip->mode == THERMAL_DEVICE_ENABLED)
- qpnp_tm_shutdown_override(chip, SOFTWARE_OVERRIDE_ENABLED);
-
- return 0;
-}
-
-static const struct dev_pm_ops qpnp_tm_pm_ops = {
- .suspend = qpnp_tm_suspend,
- .resume = qpnp_tm_resume,
-};
-
-#define QPNP_TM_PM_OPS (&qpnp_tm_pm_ops)
-#else
-#define QPNP_TM_PM_OPS NULL
-#endif
-
static const struct of_device_id qpnp_tm_match_table[] = {
{ .compatible = QPNP_TM_DRIVER_NAME, },
{}
@@ -789,7 +601,6 @@
.name = QPNP_TM_DRIVER_NAME,
.of_match_table = qpnp_tm_match_table,
.owner = THIS_MODULE,
- .pm = QPNP_TM_PM_OPS,
},
.probe = qpnp_tm_probe,
.remove = qpnp_tm_remove,
diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 6e3e636..22d32d2 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -5621,17 +5621,15 @@
static void serial8250_io_resume(struct pci_dev *dev)
{
struct serial_private *priv = pci_get_drvdata(dev);
- const struct pciserial_board *board;
+ struct serial_private *new;
if (!priv)
return;
- board = priv->board;
- kfree(priv);
- priv = pciserial_init_ports(dev, board);
-
- if (!IS_ERR(priv)) {
- pci_set_drvdata(dev, priv);
+ new = pciserial_init_ports(dev, priv->board);
+ if (!IS_ERR(new)) {
+ pci_set_drvdata(dev, new);
+ kfree(priv);
}
}
diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c
index df9be34..6a3f2ac 100644
--- a/drivers/tty/serial/msm_geni_serial.c
+++ b/drivers/tty/serial/msm_geni_serial.c
@@ -17,6 +17,7 @@
#include <linux/delay.h>
#include <linux/console.h>
#include <linux/io.h>
+#include <linux/ipc_logging.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -41,7 +42,7 @@
#define SE_UART_RX_STALE_CNT (0x294)
#define SE_UART_TX_PARITY_CFG (0x2A4)
#define SE_UART_RX_PARITY_CFG (0x2A8)
-#define SE_UART_MANUAL_RFT (0x2AC)
+#define SE_UART_MANUAL_RFR (0x2AC)
/* SE_UART_LOOPBACK_CFG */
#define NO_LOOPBACK (0)
@@ -84,6 +85,11 @@
#define PAR_SPACE (0x10)
#define PAR_MARK (0x11)
+/* SE_UART_MANUAL_RFR register fields */
+#define UART_MANUAL_RFR_EN (BIT(31))
+#define UART_RFR_NOT_READY (BIT(1))
+#define UART_RFR_READY (BIT(0))
+
/* UART M_CMD OP codes */
#define UART_START_TX (0x1)
#define UART_START_BREAK (0x4)
@@ -94,13 +100,26 @@
#define UART_OVERSAMPLING (32)
#define STALE_TIMEOUT (16)
+#define DEFAULT_BITS_PER_CHAR (10)
#define GENI_UART_NR_PORTS (15)
+#define GENI_UART_CONS_PORTS (1)
#define DEF_FIFO_DEPTH_WORDS (16)
+#define DEF_TX_WM (2)
#define DEF_FIFO_WIDTH_BITS (32)
#define UART_CORE2X_VOTE (10000)
#define DEFAULT_SE_CLK (19200000)
#define DEFAULT_BUS_WIDTH (4)
+#define WAKEBYTE_TIMEOUT_MSEC (2000)
+#define IPC_LOG_PWR_PAGES (2)
+#define IPC_LOG_MISC_PAGES (2)
+#define IPC_LOG_TX_RX_PAGES (3)
+#define DATA_BYTES_PER_LINE (32)
+
+#define IPC_LOG_MSG(ctx, x...) do { \
+ if (ctx) \
+ ipc_log_string(ctx, x); \
+} while (0)
struct msm_geni_serial_port {
struct uart_port uport;
@@ -121,6 +140,14 @@
unsigned int rx_last);
struct se_geni_rsc serial_rsc;
int loopback;
+ int wakeup_irq;
+ unsigned char wakeup_byte;
+ struct wakeup_source geni_wake;
+ void *ipc_log_tx;
+ void *ipc_log_rx;
+ void *ipc_log_pwr;
+ void *ipc_log_misc;
+ unsigned int cur_baud;
};
static const struct uart_ops msm_geni_serial_pops;
@@ -134,12 +161,16 @@
unsigned int rx_fifo_wc,
unsigned int rx_last_byte_valid,
unsigned int rx_last);
+static unsigned int msm_geni_serial_tx_empty(struct uart_port *port);
+static int msm_geni_serial_power_on(struct uart_port *uport);
+static void msm_geni_serial_power_off(struct uart_port *uport);
static atomic_t uart_line_id = ATOMIC_INIT(0);
#define GET_DEV_PORT(uport) \
container_of(uport, struct msm_geni_serial_port, uport)
+static struct msm_geni_serial_port msm_geni_console_port;
static struct msm_geni_serial_port msm_geni_serial_ports[GENI_UART_NR_PORTS];
static void msm_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
@@ -174,22 +205,172 @@
static DEVICE_ATTR(loopback, 0644, msm_geni_serial_loopback_show,
msm_geni_serial_loopback_store);
-static void msm_geni_serial_set_mctrl(struct uart_port *port,
+static void dump_ipc(void *ipc_ctx, char *prefix, char *string,
+ u64 addr, int size)
+
+{
+ char buf[DATA_BYTES_PER_LINE * 2];
+ int len = 0;
+
+ if (!ipc_ctx)
+ return;
+ len = min(size, DATA_BYTES_PER_LINE);
+ hex_dump_to_buffer(string, len, DATA_BYTES_PER_LINE, 1, buf,
+ sizeof(buf), false);
+ ipc_log_string(ipc_ctx, "%s[0x%.10x:%d] : %s", prefix,
+ (unsigned int)addr, size, buf);
+}
+
+static void check_tx_active(struct uart_port *uport)
+{
+ u32 geni_status = geni_read_reg_nolog(uport->membase,
+ SE_GENI_STATUS);
+
+ while ((geni_status & M_GENI_CMD_ACTIVE)) {
+ cpu_relax();
+ geni_status = geni_read_reg_nolog(uport->membase,
+ SE_GENI_STATUS);
+ }
+}
+
+static int vote_clock_on(struct uart_port *uport)
+{
+ int ret = 0;
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
+
+ if (!pm_runtime_enabled(uport->dev)) {
+ dev_err(uport->dev, "RPM not available.Can't enable clocks\n");
+ ret = -EPERM;
+ return ret;
+ }
+ ret = msm_geni_serial_power_on(uport);
+ if (ret) {
+ dev_err(uport->dev, "Failed to vote clock on\n");
+ return ret;
+ }
+ __pm_relax(&port->geni_wake);
+ IPC_LOG_MSG(port->ipc_log_pwr, "%s\n", __func__);
+ return 0;
+}
+
+static int vote_clock_off(struct uart_port *uport)
+{
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
+ int ret = 0;
+
+ if (!pm_runtime_enabled(uport->dev)) {
+ dev_err(uport->dev, "RPM not available.Can't enable clocks\n");
+ ret = -EPERM;
+ return ret;
+ }
+ /* Block till any on going Tx goes out.*/
+ check_tx_active(uport);
+ msm_geni_serial_power_off(uport);
+ IPC_LOG_MSG(port->ipc_log_pwr, "%s\n", __func__);
+ return 0;
+};
+
+static int msm_geni_serial_ioctl(struct uart_port *uport, unsigned int cmd,
+ unsigned long arg)
+{
+ int ret = -ENOIOCTLCMD;
+
+ switch (cmd) {
+ case TIOCPMGET: {
+ ret = vote_clock_on(uport);
+ break;
+ }
+ case TIOCPMPUT: {
+ ret = vote_clock_off(uport);
+ break;
+ }
+ case TIOCPMACT: {
+ ret = !pm_runtime_status_suspended(uport->dev);
+ break;
+ }
+ default:
+ break;
+ }
+ return ret;
+}
+
+static void msm_geni_serial_break_ctl(struct uart_port *uport, int ctl)
+{
+ if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
+ dev_err(uport->dev, "%s Device suspended,vote clocks on.\n",
+ __func__);
+ return;
+ }
+
+ if (ctl) {
+ check_tx_active(uport);
+ geni_setup_m_cmd(uport->membase, UART_START_BREAK, 0);
+ } else {
+ geni_setup_m_cmd(uport->membase, UART_STOP_BREAK, 0);
+ }
+ /* Ensure break start/stop command is setup before returning.*/
+ mb();
+}
+
+static unsigned int msm_geni_serial_get_mctrl(struct uart_port *uport)
+{
+ u32 geni_ios = 0;
+ unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
+
+ if (pm_runtime_status_suspended(uport->dev))
+ return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
+
+ geni_ios = geni_read_reg_nolog(uport->membase, SE_GENI_IOS);
+ if (!(geni_ios & IO2_DATA_IN))
+ mctrl |= TIOCM_CTS;
+
+ return mctrl;
+}
+
+static void msm_geni_cons_set_mctrl(struct uart_port *uport,
unsigned int mctrl)
{
}
+static void msm_geni_serial_set_mctrl(struct uart_port *uport,
+ unsigned int mctrl)
+{
+ u32 uart_manual_rfr = 0;
+
+ if (pm_runtime_status_suspended(uport->dev)) {
+ dev_info(uport->dev, "%sDevice suspended,vote clocks on\n",
+ __func__);
+ return;
+ }
+ if (!(mctrl & TIOCM_RTS))
+ uart_manual_rfr |= (UART_MANUAL_RFR_EN | UART_RFR_NOT_READY);
+ geni_write_reg_nolog(uart_manual_rfr, uport->membase,
+ SE_UART_MANUAL_RFR);
+ /* Write to flow control must complete before return to client*/
+ mb();
+}
+
static const char *msm_geni_serial_get_type(struct uart_port *uport)
{
return "MSM";
}
-static struct msm_geni_serial_port *get_port_from_line(int line)
+static struct msm_geni_serial_port *get_port_from_line(int line,
+ bool is_console)
{
- if ((line < 0) || (line >= GENI_UART_NR_PORTS))
- return ERR_PTR(-ENXIO);
+ struct msm_geni_serial_port *port = NULL;
- return &msm_geni_serial_ports[line];
+ if (is_console) {
+ if ((line < 0) || (line >= GENI_UART_CONS_PORTS))
+ port = ERR_PTR(-ENXIO);
+ port = &msm_geni_console_port;
+ } else {
+ if ((line < 0) || (line >= GENI_UART_NR_PORTS))
+ return ERR_PTR(-ENXIO);
+ port = &msm_geni_serial_ports[line];
+ }
+
+ return port;
}
static int msm_geni_serial_power_on(struct uart_port *uport)
@@ -198,16 +379,16 @@
ret = pm_runtime_get_sync(uport->dev);
if (ret < 0) {
- dev_err(uport->dev, "%s: Failed (%d)", __func__, ret);
pm_runtime_put_noidle(uport->dev);
+ pm_runtime_set_suspended(uport->dev);
+ return ret;
}
- return ret;
+ return 0;
}
static void msm_geni_serial_power_off(struct uart_port *uport)
{
- pm_runtime_mark_last_busy(uport->dev);
- pm_runtime_put_autosuspend(uport->dev);
+ pm_runtime_put_sync(uport->dev);
}
static int msm_geni_serial_poll_bit(struct uart_port *uport,
@@ -216,9 +397,26 @@
int iter = 0;
unsigned int reg;
bool met = false;
+ struct msm_geni_serial_port *port = NULL;
bool cond = false;
+ unsigned int baud = 115200;
+ unsigned int fifo_bits = DEF_FIFO_DEPTH_WORDS * DEF_FIFO_WIDTH_BITS;
+ unsigned long total_iter = 0;
- while (iter < 1000) {
+
+ if (uport->private_data) {
+ port = GET_DEV_PORT(uport);
+ baud = (port->cur_baud ? port->cur_baud : 115200);
+ fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
+ }
+ /*
+ * Total polling iterations based on FIFO worth of bytes to be
+ * sent at current baud .Add a little fluff to the wait.
+ */
+ total_iter = ((fifo_bits * USEC_PER_SEC) / baud);
+ total_iter += 50;
+
+ while (iter < total_iter) {
reg = geni_read_reg_nolog(uport->membase, offset);
cond = reg & bit_field;
if (cond == set) {
@@ -232,7 +430,7 @@
}
static void msm_geni_serial_setup_tx(struct uart_port *uport,
- unsigned int xmit_size)
+ unsigned int xmit_size)
{
u32 m_cmd = 0;
@@ -290,23 +488,21 @@
unsigned int s_irq_status;
if (!(msm_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
- M_SEC_IRQ_EN, true))) {
- dev_err(uport->dev, "%s: Failed waiting for SE\n", __func__);
+ M_SEC_IRQ_EN, true)))
return -ENXIO;
- }
m_irq_status = geni_read_reg_nolog(uport->membase,
SE_GENI_M_IRQ_STATUS);
s_irq_status = geni_read_reg_nolog(uport->membase,
SE_GENI_S_IRQ_STATUS);
- geni_write_reg_nolog(m_irq_status, uport->membase, SE_GENI_M_IRQ_CLEAR);
- geni_write_reg_nolog(s_irq_status, uport->membase, SE_GENI_S_IRQ_CLEAR);
+ geni_write_reg_nolog(m_irq_status, uport->membase,
+ SE_GENI_M_IRQ_CLEAR);
+ geni_write_reg_nolog(s_irq_status, uport->membase,
+ SE_GENI_S_IRQ_CLEAR);
if (!(msm_geni_serial_poll_bit(uport, SE_GENI_RX_FIFO_STATUS,
- RX_FIFO_WC_MSK, true))) {
- dev_err(uport->dev, "%s: Failed waiting for Rx\n", __func__);
+ RX_FIFO_WC_MSK, true)))
return -ENXIO;
- }
/*
* Read the Rx FIFO only after clearing the interrupt registers and
@@ -324,7 +520,6 @@
int b = (int) c;
struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
- se_config_packing(uport->membase, 8, 1, false);
geni_write_reg_nolog(port->tx_wm, uport->membase,
SE_GENI_TX_WATERMARK_REG);
msm_geni_serial_setup_tx(uport, 1);
@@ -358,10 +553,11 @@
__msm_geni_serial_console_write(struct uart_port *uport, const char *s,
unsigned int count)
{
- struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
int new_line = 0;
int i;
int bytes_to_send = count;
+ int fifo_depth = DEF_FIFO_DEPTH_WORDS;
+ int tx_wm = DEF_TX_WM;
for (i = 0; i < count; i++) {
if (s[i] == '\n')
@@ -369,14 +565,13 @@
}
bytes_to_send += new_line;
- se_config_packing(uport->membase, 8, 1, false);
- geni_write_reg_nolog(port->tx_wm, uport->membase,
+ geni_write_reg_nolog(tx_wm, uport->membase,
SE_GENI_TX_WATERMARK_REG);
msm_geni_serial_setup_tx(uport, bytes_to_send);
i = 0;
while (i < count) {
u32 chars_to_write = 0;
- u32 avail_fifo_bytes = (port->tx_fifo_depth - port->tx_wm);
+ u32 avail_fifo_bytes = (fifo_depth - tx_wm);
/*
* If the WM bit never set, then the Tx state machine is not
* in a valid state, so break, cancel/abort any existing
@@ -409,11 +604,9 @@
WARN_ON(co->index < 0 || co->index >= GENI_UART_NR_PORTS);
- port = get_port_from_line(co->index);
- if (IS_ERR_OR_NULL(port)) {
- pr_err("%s:Invalid line %d\n", __func__, co->index);
+ port = get_port_from_line(co->index, true);
+ if (IS_ERR_OR_NULL(port))
return;
- }
uport = &port->uport;
spin_lock(&uport->lock);
@@ -432,7 +625,6 @@
struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);
tport = &uport->state->port;
-
for (i = 0; i < rx_fifo_wc; i++) {
int bytes = 4;
@@ -471,23 +663,35 @@
static void msm_geni_serial_start_tx(struct uart_port *uport)
{
unsigned int geni_m_irq_en;
- struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
+ struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);
+
+ if (!msm_geni_serial_tx_empty(uport))
+ return;
+
+ if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
+ dev_err(uport->dev, "%s.Device is suspended.\n", __func__);
+ return;
+ }
geni_m_irq_en = geni_read_reg_nolog(uport->membase, SE_GENI_M_IRQ_EN);
geni_m_irq_en |= M_TX_FIFO_WATERMARK_EN;
- se_config_packing(uport->membase, 8, 4, false);
- geni_write_reg_nolog(port->tx_wm, uport->membase,
+ geni_write_reg_nolog(msm_port->tx_wm, uport->membase,
SE_GENI_TX_WATERMARK_REG);
geni_write_reg_nolog(geni_m_irq_en, uport->membase, SE_GENI_M_IRQ_EN);
/* Geni command setup/irq enables should complete before returning.*/
mb();
+ IPC_LOG_MSG(msm_port->ipc_log_misc, "%s\n", __func__);
}
static void msm_geni_serial_stop_tx(struct uart_port *uport)
{
unsigned int geni_m_irq_en;
unsigned int geni_status;
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
+
+ if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev))
+ return;
geni_m_irq_en = geni_read_reg_nolog(uport->membase, SE_GENI_M_IRQ_EN);
geni_m_irq_en &= ~(M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN);
@@ -510,21 +714,34 @@
SE_GENI_M_IRQ_CLEAR);
}
geni_write_reg_nolog(M_CMD_CANCEL_EN, uport, SE_GENI_M_IRQ_CLEAR);
+ IPC_LOG_MSG(port->ipc_log_misc, "%s\n", __func__);
}
static void msm_geni_serial_start_rx(struct uart_port *uport)
{
unsigned int geni_s_irq_en;
unsigned int geni_m_irq_en;
+ unsigned long cfg0, cfg1;
+ unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
+ unsigned int geni_status;
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
- msm_geni_serial_abort_rx(uport);
+ if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev))
+ return;
+
+ geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS);
+ if (geni_status & S_GENI_CMD_ACTIVE)
+ msm_geni_serial_abort_rx(uport);
geni_s_irq_en = geni_read_reg_nolog(uport->membase,
SE_GENI_S_IRQ_EN);
geni_m_irq_en = geni_read_reg_nolog(uport->membase,
SE_GENI_M_IRQ_EN);
geni_s_irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
geni_m_irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
-
+ se_get_packing_config(8, 4, false, &cfg0, &cfg1);
+ geni_write_reg_nolog(cfg0, uport->membase, SE_GENI_RX_PACKING_CFG0);
+ geni_write_reg_nolog(cfg1, uport->membase, SE_GENI_RX_PACKING_CFG1);
+ geni_write_reg_nolog(rxstale, uport->membase, SE_UART_RX_STALE_CNT);
geni_setup_s_cmd(uport->membase, UART_START_READ, 0);
geni_write_reg_nolog(geni_s_irq_en, uport->membase, SE_GENI_S_IRQ_EN);
geni_write_reg_nolog(geni_m_irq_en, uport->membase, SE_GENI_M_IRQ_EN);
@@ -533,6 +750,7 @@
* go through.
*/
mb();
+ IPC_LOG_MSG(port->ipc_log_misc, "%s\n", __func__);
}
static void msm_geni_serial_stop_rx(struct uart_port *uport)
@@ -541,6 +759,9 @@
unsigned int geni_m_irq_en;
unsigned int geni_status;
+ if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev))
+ return;
+
geni_s_irq_en = geni_read_reg_nolog(uport->membase,
SE_GENI_S_IRQ_EN);
geni_m_irq_en = geni_read_reg_nolog(uport->membase,
@@ -586,6 +807,8 @@
}
uport->icount.rx += ret;
tty_flip_buffer_push(tport);
+ dump_ipc(msm_port->ipc_log_rx, "Rx", (char *)msm_port->rx_fifo, 0,
+ rx_bytes);
return ret;
}
@@ -597,7 +820,7 @@
unsigned int rx_last_byte_valid = 0;
unsigned int rx_last = 0;
struct tty_port *tport;
- struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
tport = &uport->state->port;
rx_fifo_status = geni_read_reg_nolog(uport->membase,
@@ -607,7 +830,7 @@
RX_LAST_BYTE_VALID_SHFT);
rx_last = rx_fifo_status & RX_LAST;
if (rx_fifo_wc)
- msm_port->handle_rx(uport, rx_fifo_wc, rx_last_byte_valid,
+ port->handle_rx(uport, rx_fifo_wc, rx_last_byte_valid,
rx_last);
return ret;
}
@@ -622,7 +845,8 @@
int i = 0;
unsigned int tx_fifo_status;
unsigned int xmit_size;
- unsigned int fifo_width_bytes = msm_port->tx_fifo_width >> 3;
+ unsigned int fifo_width_bytes =
+ (uart_console(uport) ? 1 : (msm_port->tx_fifo_width >> 3));
tx_fifo_status = geni_read_reg_nolog(uport->membase,
SE_GENI_TX_FIFO_STATUS);
@@ -645,6 +869,8 @@
msm_geni_serial_setup_tx(uport, xmit_size);
bytes_remaining = xmit_size;
+ dump_ipc(msm_port->ipc_log_tx, "Tx", (char *)&xmit->buf[xmit->tail], 0,
+ xmit_size);
while (i < xmit_size) {
unsigned int tx_bytes;
unsigned int buf = 0;
@@ -664,6 +890,8 @@
wmb();
}
msm_geni_serial_poll_cancel_tx(uport);
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(uport);
exit_handle_tx:
return ret;
}
@@ -676,12 +904,18 @@
unsigned long flags;
spin_lock_irqsave(&uport->lock, flags);
+ if (uart_console(uport) && uport->suspended)
+ goto exit_geni_serial_isr;
+ if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev))
+ goto exit_geni_serial_isr;
m_irq_status = geni_read_reg_nolog(uport->membase,
- SE_GENI_M_IRQ_STATUS);
+ SE_GENI_M_IRQ_STATUS);
s_irq_status = geni_read_reg_nolog(uport->membase,
- SE_GENI_S_IRQ_STATUS);
- geni_write_reg_nolog(m_irq_status, uport->membase, SE_GENI_M_IRQ_CLEAR);
- geni_write_reg_nolog(s_irq_status, uport->membase, SE_GENI_S_IRQ_CLEAR);
+ SE_GENI_S_IRQ_STATUS);
+ geni_write_reg_nolog(m_irq_status, uport->membase,
+ SE_GENI_M_IRQ_CLEAR);
+ geni_write_reg_nolog(s_irq_status, uport->membase,
+ SE_GENI_S_IRQ_CLEAR);
if ((m_irq_status & M_ILLEGAL_CMD_EN)) {
WARN_ON(1);
@@ -701,6 +935,28 @@
return IRQ_HANDLED;
}
+static irqreturn_t msm_geni_wakeup_isr(int isr, void *dev)
+{
+ struct uart_port *uport = dev;
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
+ struct tty_struct *tty;
+ unsigned long flags;
+
+ spin_lock_irqsave(&uport->lock, flags);
+ if (port->wakeup_byte) {
+ tty = uport->state->port.tty;
+ tty_insert_flip_char(tty->port, port->wakeup_byte, TTY_NORMAL);
+ IPC_LOG_MSG(port->ipc_log_rx, "%s: Inject 0x%x\n",
+ __func__, port->wakeup_byte);
+ tty_flip_buffer_push(tty->port);
+ }
+ __pm_wakeup_event(&port->geni_wake, WAKEBYTE_TIMEOUT_MSEC);
+ IPC_LOG_MSG(port->ipc_log_misc, "%s:Holding Wake Lock for %d ms\n",
+ __func__, WAKEBYTE_TIMEOUT_MSEC);
+ spin_unlock_irqrestore(&uport->lock, flags);
+ return IRQ_HANDLED;
+}
+
static int get_tx_fifo_size(struct msm_geni_serial_port *port)
{
struct uart_port *uport;
@@ -719,7 +975,7 @@
port->tx_fifo_width = get_tx_fifo_width(uport->membase);
if (!port->tx_fifo_width) {
dev_err(uport->dev, "%s:Invalid TX FIFO width read\n",
- __func__);
+ __func__);
return -ENXIO;
}
@@ -755,33 +1011,89 @@
msm_geni_serial_stop_rx(uport);
disable_irq(uport->irq);
free_irq(uport->irq, msm_port);
- if (uart_console(uport))
+ if (uart_console(uport)) {
se_geni_resources_off(&msm_port->serial_rsc);
- else
+ } else {
+ if (msm_port->wakeup_irq > 0) {
+ disable_irq(msm_port->wakeup_irq);
+ free_irq(msm_port->wakeup_irq, msm_port);
+ }
+ __pm_relax(&msm_port->geni_wake);
msm_geni_serial_power_off(uport);
+ }
+ IPC_LOG_MSG(msm_port->ipc_log_misc, "%s\n", __func__);
}
static int msm_geni_serial_port_setup(struct uart_port *uport)
{
int ret = 0;
struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);
+ unsigned long cfg0, cfg1;
- /* For now only assume FIFO mode. */
- msm_port->xfer_mode = FIFO_MODE;
+
set_rfr_wm(msm_port);
- ret = geni_se_init(uport->membase, msm_port->xfer_mode,
+ if (!uart_console(uport)) {
+ /* For now only assume FIFO mode. */
+ msm_port->xfer_mode = FIFO_MODE;
+ ret = geni_se_init(uport->membase, msm_port->xfer_mode,
msm_port->rx_wm, msm_port->rx_rfr);
- if (ret) {
- dev_err(uport->dev, "%s: Fail\n", __func__);
- goto exit_portsetup;
+ if (ret) {
+ dev_err(uport->dev, "%s: Fail\n", __func__);
+ goto exit_portsetup;
+ }
+ se_get_packing_config(8, 4, false, &cfg0, &cfg1);
+ geni_write_reg_nolog(cfg0, uport->membase,
+ SE_GENI_TX_PACKING_CFG0);
+ geni_write_reg_nolog(cfg1, uport->membase,
+ SE_GENI_TX_PACKING_CFG1);
}
-
msm_port->port_setup = true;
/*
* Ensure Port setup related IO completes before returning to
* framework.
*/
mb();
+ if (!uart_console(uport)) {
+ char name[30];
+
+ memset(name, 0, sizeof(name));
+ if (!msm_port->ipc_log_rx) {
+ scnprintf(name, sizeof(name), "%s%s",
+ dev_name(uport->dev), "_rx");
+ msm_port->ipc_log_rx = ipc_log_context_create(
+ IPC_LOG_TX_RX_PAGES, name, 0);
+ if (!msm_port->ipc_log_rx)
+ dev_info(uport->dev, "Err in Rx IPC Log\n");
+ }
+ memset(name, 0, sizeof(name));
+ if (!msm_port->ipc_log_tx) {
+ scnprintf(name, sizeof(name), "%s%s",
+ dev_name(uport->dev), "_tx");
+ msm_port->ipc_log_tx = ipc_log_context_create(
+ IPC_LOG_TX_RX_PAGES, name, 0);
+ if (!msm_port->ipc_log_tx)
+ dev_info(uport->dev, "Err in Tx IPC Log\n");
+ }
+ memset(name, 0, sizeof(name));
+ if (!msm_port->ipc_log_pwr) {
+ scnprintf(name, sizeof(name), "%s%s",
+ dev_name(uport->dev), "_pwr");
+ msm_port->ipc_log_pwr = ipc_log_context_create(
+ IPC_LOG_PWR_PAGES, name, 0);
+ if (!msm_port->ipc_log_pwr)
+ dev_info(uport->dev, "Err in Pwr IPC Log\n");
+ }
+ memset(name, 0, sizeof(name));
+ if (!msm_port->ipc_log_misc) {
+ scnprintf(name, sizeof(name), "%s%s",
+ dev_name(uport->dev), "_misc");
+ msm_port->ipc_log_misc = ipc_log_context_create(
+ IPC_LOG_MISC_PAGES, name, 0);
+ if (!msm_port->ipc_log_misc)
+ dev_info(uport->dev, "Err in Misc IPC Log\n");
+ }
+
+ }
exit_portsetup:
return ret;
}
@@ -802,12 +1114,36 @@
goto exit_startup;
}
+ if (msm_port->wakeup_irq > 0) {
+ ret = request_threaded_irq(msm_port->wakeup_irq, NULL,
+ msm_geni_wakeup_isr,
+ IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+ "hs_uart_wakeup", uport);
+ if (unlikely(ret)) {
+ dev_err(uport->dev, "%s:Failed to get WakeIRQ ret%d\n",
+ __func__, ret);
+ goto exit_startup;
+ }
+ disable_irq(msm_port->wakeup_irq);
+ }
+
if (likely(!uart_console(uport))) {
ret = msm_geni_serial_power_on(&msm_port->uport);
if (ret)
goto exit_startup;
}
+ if (unlikely(get_se_proto(uport->membase) != UART)) {
+ dev_err(uport->dev, "%s: Invalid FW %d loaded.\n",
+ __func__, get_se_proto(uport->membase));
+ if (unlikely(get_se_proto(uport->membase) != UART)) {
+ ret = -ENXIO;
+ disable_irq(uport->irq);
+ free_irq(uport->irq, msm_port);
+ goto exit_startup;
+ }
+ }
+
if (!msm_port->port_setup) {
if (msm_geni_serial_port_setup(uport))
goto exit_startup;
@@ -820,14 +1156,15 @@
* before returning to the framework.
*/
mb();
+ IPC_LOG_MSG(msm_port->ipc_log_misc, "%s\n", __func__);
exit_startup:
return ret;
}
-static int get_dfs_index(unsigned long clk_freq, unsigned long *ser_clk)
+static int get_clk_cfg(unsigned long clk_freq, unsigned long *ser_clk)
{
- unsigned long root_freq[] = {19200000, 7372800, 64000000,
- 96000000, 100000000, 102400000, 128000000};
+ unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
+ 32000000, 48000000, 64000000, 80000000, 96000000, 100000000};
int i;
int match = -1;
@@ -842,13 +1179,15 @@
}
if (match != -1)
*ser_clk = root_freq[match];
+ else
+ pr_err("clk_freq %ld\n", clk_freq);
return match;
}
static void geni_serial_write_term_regs(struct uart_port *uport, u32 loopback,
u32 tx_trans_cfg, u32 tx_parity_cfg, u32 rx_trans_cfg,
u32 rx_parity_cfg, u32 bits_per_char, u32 stop_bit_len,
- u32 rxstale, u32 s_clk_cfg)
+ u32 s_clk_cfg)
{
geni_write_reg_nolog(loopback, uport->membase, SE_UART_LOOPBACK_CFG);
geni_write_reg_nolog(tx_trans_cfg, uport->membase,
@@ -865,7 +1204,6 @@
SE_UART_RX_WORD_LEN);
geni_write_reg_nolog(stop_bit_len, uport->membase,
SE_UART_TX_STOP_BIT_LEN);
- geni_write_reg_nolog(rxstale, uport->membase, SE_UART_RX_STALE_CNT);
geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_M_CLK_CFG);
geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_S_CLK_CFG);
}
@@ -877,8 +1215,8 @@
int clk_div = 0;
*desired_clk_rate = baud * UART_OVERSAMPLING;
- dfs_index = get_dfs_index(*desired_clk_rate, &ser_clk);
- if (dfs_index < 1) {
+ dfs_index = get_clk_cfg(*desired_clk_rate, &ser_clk);
+ if (dfs_index < 0) {
pr_err("%s: Can't find matching DFS entry for baud %d\n",
__func__, baud);
clk_div = -EINVAL;
@@ -901,7 +1239,6 @@
unsigned int rx_trans_cfg;
unsigned int rx_parity_cfg;
unsigned int stop_bit_len;
- unsigned int rxstale;
unsigned int clk_div;
unsigned long ser_clk_cfg = 0;
struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
@@ -909,6 +1246,7 @@
/* baud rate */
baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
+ port->cur_baud = baud;
clk_div = get_clk_div_rate(baud, &clk_rate);
if (clk_div <= 0)
goto exit_set_termios;
@@ -966,8 +1304,6 @@
break;
}
- /* stale timer, set this to 16 characters. */
- rxstale = bits_per_char * STALE_TIMEOUT;
/* stop bits */
if (termios->c_cflag & CSTOPB)
@@ -984,19 +1320,26 @@
geni_serial_write_term_regs(uport, port->loopback, tx_trans_cfg,
tx_parity_cfg, rx_trans_cfg, rx_parity_cfg, bits_per_char,
- stop_bit_len, rxstale, ser_clk_cfg);
+ stop_bit_len, ser_clk_cfg);
+ IPC_LOG_MSG(port->ipc_log_misc, "%s: baud %d\n", __func__, baud);
+ IPC_LOG_MSG(port->ipc_log_misc, "Tx: trans_cfg%d parity %d\n",
+ tx_trans_cfg, tx_parity_cfg);
+ IPC_LOG_MSG(port->ipc_log_misc, "Rx: trans_cfg%d parity %d",
+ rx_trans_cfg, rx_parity_cfg);
+ IPC_LOG_MSG(port->ipc_log_misc, "BitsChar%d stop bit%d\n",
+ bits_per_char, stop_bit_len);
exit_set_termios:
return;
}
-static unsigned int msm_geni_serial_tx_empty(struct uart_port *port)
+static unsigned int msm_geni_serial_tx_empty(struct uart_port *uport)
{
unsigned int tx_fifo_status;
unsigned int is_tx_empty = 1;
- tx_fifo_status = geni_read_reg_nolog(port->membase,
- SE_GENI_TX_FIFO_STATUS);
+ tx_fifo_status = geni_read_reg_nolog(uport->membase,
+ SE_GENI_TX_FIFO_STATUS);
if (tx_fifo_status)
is_tx_empty = 0;
@@ -1013,11 +1356,12 @@
int parity = 'n';
int flow = 'n';
int ret = 0;
+ unsigned long cfg0, cfg1;
if (unlikely(co->index >= GENI_UART_NR_PORTS || co->index < 0))
return -ENXIO;
- dev_port = get_port_from_line(co->index);
+ dev_port = get_port_from_line(co->index, true);
if (IS_ERR_OR_NULL(dev_port)) {
ret = PTR_ERR(dev_port);
pr_err("Invalid line %d(%d)\n", co->index, ret);
@@ -1045,6 +1389,9 @@
* it else we could end up in data loss scenarios.
*/
msm_geni_serial_poll_cancel_tx(uport);
+ se_get_packing_config(8, 1, false, &cfg0, &cfg1);
+ geni_write_reg_nolog(cfg0, uport->membase, SE_GENI_TX_PACKING_CFG0);
+ geni_write_reg_nolog(cfg1, uport->membase, SE_GENI_TX_PACKING_CFG1);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
@@ -1066,7 +1413,6 @@
{
struct uart_port *uport = &dev->port;
int ret = 0;
- struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);
u32 tx_trans_cfg = 0;
u32 tx_parity_cfg = 0;
u32 rx_trans_cfg = 0;
@@ -1078,6 +1424,7 @@
u32 baud = 115200;
u32 clk_div;
unsigned long clk_rate;
+ unsigned long cfg0, cfg1;
if (!uport->membase) {
ret = -ENOMEM;
@@ -1089,13 +1436,8 @@
goto exit_geni_serial_earlyconsetup;
}
- msm_port->xfer_mode = FIFO_MODE;
- set_rfr_wm(msm_port);
- msm_port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
- msm_port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
- msm_port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
- geni_se_init(uport->membase, msm_port->xfer_mode, msm_port->rx_wm,
- msm_port->rx_rfr);
+ geni_se_init(uport->membase, FIFO_MODE, (DEF_FIFO_DEPTH_WORDS >> 1),
+ (DEF_FIFO_DEPTH_WORDS - 2));
/*
* Ignore Flow control.
* Disable Tx Parity.
@@ -1126,9 +1468,24 @@
* it else we could end up in data loss scenarios.
*/
msm_geni_serial_poll_cancel_tx(uport);
- geni_serial_write_term_regs(uport, 0, tx_trans_cfg,
- tx_parity_cfg, rx_trans_cfg, rx_parity_cfg, bits_per_char,
- stop_bit, rx_stale, s_clk_cfg);
+ se_get_packing_config(8, 1, false, &cfg0, &cfg1);
+ geni_write_reg_nolog(cfg0, uport->membase, SE_GENI_TX_PACKING_CFG0);
+ geni_write_reg_nolog(cfg1, uport->membase, SE_GENI_TX_PACKING_CFG1);
+ geni_write_reg_nolog(tx_trans_cfg, uport->membase,
+ SE_UART_TX_TRANS_CFG);
+ geni_write_reg_nolog(tx_parity_cfg, uport->membase,
+ SE_UART_TX_PARITY_CFG);
+ geni_write_reg_nolog(rx_trans_cfg, uport->membase,
+ SE_UART_RX_TRANS_CFG);
+ geni_write_reg_nolog(rx_parity_cfg, uport->membase,
+ SE_UART_RX_PARITY_CFG);
+ geni_write_reg_nolog(bits_per_char, uport->membase,
+ SE_UART_TX_WORD_LEN);
+ geni_write_reg_nolog(bits_per_char, uport->membase,
+ SE_UART_RX_WORD_LEN);
+ geni_write_reg_nolog(stop_bit, uport->membase, SE_UART_TX_STOP_BIT_LEN);
+ geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_M_CLK_CFG);
+ geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_S_CLK_CFG);
dev->con->write = msm_geni_serial_early_console_write;
dev->con->setup = NULL;
@@ -1189,6 +1546,23 @@
dev_err(uport->dev, "Failed to create dbg dir\n");
}
+static const struct uart_ops msm_geni_console_pops = {
+ .tx_empty = msm_geni_serial_tx_empty,
+ .stop_tx = msm_geni_serial_stop_tx,
+ .start_tx = msm_geni_serial_start_tx,
+ .stop_rx = msm_geni_serial_stop_rx,
+ .set_termios = msm_geni_serial_set_termios,
+ .startup = msm_geni_serial_startup,
+ .config_port = msm_geni_serial_config_port,
+ .shutdown = msm_geni_serial_shutdown,
+ .type = msm_geni_serial_get_type,
+ .set_mctrl = msm_geni_cons_set_mctrl,
+#ifdef CONFIG_CONSOLE_POLL
+ .poll_get_char = msm_geni_serial_get_char,
+ .poll_put_char = msm_geni_serial_poll_put_char,
+#endif
+};
+
static const struct uart_ops msm_geni_serial_pops = {
.tx_empty = msm_geni_serial_tx_empty,
.stop_tx = msm_geni_serial_stop_tx,
@@ -1200,10 +1574,10 @@
.shutdown = msm_geni_serial_shutdown,
.type = msm_geni_serial_get_type,
.set_mctrl = msm_geni_serial_set_mctrl,
-#ifdef CONFIG_CONSOLE_POLL
- .poll_get_char = msm_geni_serial_get_char,
- .poll_put_char = msm_geni_serial_poll_put_char,
-#endif
+ .get_mctrl = msm_geni_serial_get_mctrl,
+ .break_ctl = msm_geni_serial_break_ctl,
+ .flush_buffer = NULL,
+ .ioctl = msm_geni_serial_ioctl,
};
static const struct of_device_id msm_geni_device_tbl[] = {
@@ -1225,17 +1599,7 @@
struct resource *res;
struct uart_driver *drv;
const struct of_device_id *id;
-
- if (pdev->dev.of_node)
- line = of_alias_get_id(pdev->dev.of_node, "serial");
- else
- line = pdev->id;
-
- if (line < 0)
- line = atomic_inc_return(&uart_line_id) - 1;
-
- if ((line < 0) || (line >= GENI_UART_NR_PORTS))
- return -ENXIO;
+ bool is_console = false;
id = of_match_device(msm_geni_device_tbl, &pdev->dev);
if (id) {
@@ -1246,7 +1610,22 @@
return -ENODEV;
}
- dev_port = get_port_from_line(line);
+ if (pdev->dev.of_node) {
+ if (drv->cons)
+ line = of_alias_get_id(pdev->dev.of_node, "serial");
+ else
+ line = of_alias_get_id(pdev->dev.of_node, "hsuart");
+ } else {
+ line = pdev->id;
+ }
+
+ if (line < 0)
+ line = atomic_inc_return(&uart_line_id) - 1;
+
+ if ((line < 0) || (line >= GENI_UART_NR_PORTS))
+ return -ENXIO;
+ is_console = (drv->cons ? true : false);
+ dev_port = get_port_from_line(line, is_console);
if (IS_ERR_OR_NULL(dev_port)) {
ret = PTR_ERR(dev_port);
dev_err(&pdev->dev, "Invalid line %d(%d)\n",
@@ -1279,9 +1658,13 @@
dev_port->serial_rsc.ab = UART_CORE2X_VOTE;
dev_port->serial_rsc.ib = DEFAULT_SE_CLK * DEFAULT_BUS_WIDTH;
} else {
- dev_info(&pdev->dev, "No bus master specified");
+ dev_info(&pdev->dev, "No bus master specified\n");
}
+ if (of_property_read_u8(pdev->dev.of_node, "qcom,wakeup-byte",
+ &dev_port->wakeup_byte))
+ dev_info(&pdev->dev, "No Wakeup byte specified\n");
+
dev_port->serial_rsc.se_clk = devm_clk_get(&pdev->dev, "se-clk");
if (IS_ERR(dev_port->serial_rsc.se_clk)) {
ret = PTR_ERR(dev_port->serial_rsc.se_clk);
@@ -1342,6 +1725,7 @@
goto exit_geni_serial_probe;
}
+ wakeup_source_init(&dev_port->geni_wake, dev_name(&pdev->dev));
dev_port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
dev_port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
dev_port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
@@ -1355,9 +1739,14 @@
goto exit_geni_serial_probe;
}
+ /* Optional to use the Rx pin as wakeup irq */
+ dev_port->wakeup_irq = platform_get_irq(pdev, 1);
+ if ((dev_port->wakeup_irq < 0 && !is_console))
+ dev_info(&pdev->dev, "No wakeup IRQ configured\n");
+
uport->private_data = (void *)drv;
platform_set_drvdata(pdev, dev_port);
- if (drv->cons) {
+ if (is_console) {
dev_port->handle_rx = handle_rx_console;
dev_port->rx_fifo = devm_kzalloc(uport->dev, sizeof(u32),
GFP_KERNEL);
@@ -1366,13 +1755,11 @@
dev_port->rx_fifo = devm_kzalloc(uport->dev,
sizeof(dev_port->rx_fifo_depth * sizeof(u32)),
GFP_KERNEL);
- pm_runtime_set_autosuspend_delay(&pdev->dev, MSEC_PER_SEC);
- pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(&pdev->dev);
}
dev_info(&pdev->dev, "Serial port%d added.FifoSize %d is_console%d\n",
- line, uport->fifosize, (drv->cons ? 1 : 0));
+ line, uport->fifosize, is_console);
device_create_file(uport->dev, &dev_attr_loopback);
msm_geni_serial_debug_init(uport);
dev_port->port_setup = false;
@@ -1388,6 +1775,7 @@
struct uart_driver *drv =
(struct uart_driver *)port->uport.private_data;
+ wakeup_source_trash(&port->geni_wake);
uart_remove_one_port(drv, &port->uport);
msm_bus_scale_unregister(port->serial_rsc.bus_bw);
return 0;
@@ -1399,16 +1787,38 @@
{
struct platform_device *pdev = to_platform_device(dev);
struct msm_geni_serial_port *port = platform_get_drvdata(pdev);
+ int ret = 0;
- return se_geni_resources_off(&port->serial_rsc);
+ ret = se_geni_resources_off(&port->serial_rsc);
+ if (ret) {
+ dev_err(dev, "%s: Error ret %d\n", __func__, ret);
+ goto exit_runtime_suspend;
+ }
+ if (port->wakeup_irq > 0)
+ enable_irq(port->wakeup_irq);
+ IPC_LOG_MSG(port->ipc_log_pwr, "%s: Current usage count %d\n", __func__,
+ atomic_read(&dev->power.usage_count));
+exit_runtime_suspend:
+ return ret;
}
static int msm_geni_serial_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct msm_geni_serial_port *port = platform_get_drvdata(pdev);
+ int ret = 0;
- return se_geni_resources_on(&port->serial_rsc);
+ if (port->wakeup_irq > 0)
+ disable_irq(port->wakeup_irq);
+ ret = se_geni_resources_on(&port->serial_rsc);
+ if (ret) {
+ dev_err(dev, "%s: Error ret %d\n", __func__, ret);
+ goto exit_runtime_resume;
+ }
+ IPC_LOG_MSG(port->ipc_log_pwr, "%s: Current usage count %d\n", __func__,
+ atomic_read(&dev->power.usage_count));
+exit_runtime_resume:
+ return ret;
}
static int msm_geni_serial_sys_suspend_noirq(struct device *dev)
@@ -1435,9 +1845,11 @@
struct msm_geni_serial_port *port = platform_get_drvdata(pdev);
struct uart_port *uport = &port->uport;
- if (uart_console(uport))
+ if (uart_console(uport)) {
+ se_geni_resources_on(&port->serial_rsc);
uart_resume_port((struct uart_driver *)uport->private_data,
uport);
+ }
return 0;
}
#else
@@ -1504,6 +1916,13 @@
msm_geni_serial_ports[i].uport.line = i;
}
+ for (i = 0; i < GENI_UART_CONS_PORTS; i++) {
+ msm_geni_console_port.uport.iotype = UPIO_MEM;
+ msm_geni_console_port.uport.ops = &msm_geni_console_pops;
+ msm_geni_console_port.uport.flags = UPF_BOOT_AUTOCONF;
+ msm_geni_console_port.uport.line = i;
+ }
+
ret = console_register(&msm_geni_console_driver);
if (ret)
return ret;
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 0dfe271..62574bf 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -301,9 +301,6 @@
*/
if (dwc->ep0_bounced && dep->number <= 1) {
dwc->ep0_bounced = false;
-
- usb_gadget_unmap_request_by_dev(dwc->sysdev,
- &req->request, req->direction);
unmap_after_complete = true;
} else {
usb_gadget_unmap_request(&dwc->gadget,
@@ -1454,9 +1451,6 @@
unsigned transfer_in_flight;
unsigned started;
- if (dep->flags & DWC3_EP_STALL)
- return 0;
-
if (dep->number > 1)
trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
else
@@ -1481,8 +1475,6 @@
else
dep->flags |= DWC3_EP_STALL;
} else {
- if (!(dep->flags & DWC3_EP_STALL))
- return 0;
ret = dwc3_send_clear_stall_ep_cmd(dep);
if (ret)
diff --git a/drivers/usb/gadget/function/f_audio_source.c b/drivers/usb/gadget/function/f_audio_source.c
index a2a9185..51ab794 100644
--- a/drivers/usb/gadget/function/f_audio_source.c
+++ b/drivers/usb/gadget/function/f_audio_source.c
@@ -17,6 +17,7 @@
#include <linux/device.h>
#include <linux/usb/audio.h>
#include <linux/wait.h>
+#include <linux/pm_qos.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm.h>
@@ -268,6 +269,8 @@
/* number of frames sent since start_time */
s64 frames_sent;
struct audio_source_config *config;
+ /* for creating and issuing QoS requests */
+ struct pm_qos_request pm_qos;
};
static inline struct audio_dev *func_to_audio(struct usb_function *f)
@@ -740,6 +743,10 @@
runtime->hw.channels_max = 2;
audio->substream = substream;
+
+ /* Add the QoS request and set the latency to 0 */
+ pm_qos_add_request(&audio->pm_qos, PM_QOS_CPU_DMA_LATENCY, 0);
+
return 0;
}
@@ -749,6 +756,10 @@
unsigned long flags;
spin_lock_irqsave(&audio->lock, flags);
+
+ /* Remove the QoS request */
+ pm_qos_remove_request(&audio->pm_qos);
+
audio->substream = NULL;
spin_unlock_irqrestore(&audio->lock, flags);
diff --git a/drivers/usb/gadget/function/f_mtp.c b/drivers/usb/gadget/function/f_mtp.c
index aaa0fc2..af1bca6 100644
--- a/drivers/usb/gadget/function/f_mtp.c
+++ b/drivers/usb/gadget/function/f_mtp.c
@@ -47,6 +47,7 @@
#define MTP_BULK_BUFFER_SIZE 16384
#define INTR_BUFFER_SIZE 28
#define MAX_INST_NAME_LEN 40
+#define MTP_MAX_FILE_SIZE 0xFFFFFFFFL
/* String IDs */
#define INTERFACE_STRING_INDEX 0
@@ -837,7 +838,12 @@
if (hdr_size) {
/* prepend MTP data header */
header = (struct mtp_data_header *)req->buf;
- header->length = __cpu_to_le32(count);
+ /*
+ * set file size with header according to
+ * MTP Specification v1.0
+ */
+ header->length = (count > MTP_MAX_FILE_SIZE) ?
+ MTP_MAX_FILE_SIZE : __cpu_to_le32(count);
header->type = __cpu_to_le16(2); /* data packet */
header->command = __cpu_to_le16(dev->xfer_command);
header->transaction_id =
diff --git a/fs/ceph/addr.c b/fs/ceph/addr.c
index 1e643c7..18dc18f 100644
--- a/fs/ceph/addr.c
+++ b/fs/ceph/addr.c
@@ -315,7 +315,32 @@
struct page **pages;
pgoff_t next_index;
int nr_pages = 0;
- int ret;
+ int got = 0;
+ int ret = 0;
+
+ if (!current->journal_info) {
+ /* caller of readpages does not hold buffer and read caps
+ * (fadvise, madvise and readahead cases) */
+ int want = CEPH_CAP_FILE_CACHE;
+ ret = ceph_try_get_caps(ci, CEPH_CAP_FILE_RD, want, &got);
+ if (ret < 0) {
+ dout("start_read %p, error getting cap\n", inode);
+ } else if (!(got & want)) {
+ dout("start_read %p, no cache cap\n", inode);
+ ret = 0;
+ }
+ if (ret <= 0) {
+ if (got)
+ ceph_put_cap_refs(ci, got);
+ while (!list_empty(page_list)) {
+ page = list_entry(page_list->prev,
+ struct page, lru);
+ list_del(&page->lru);
+ put_page(page);
+ }
+ return ret;
+ }
+ }
off = (u64) page_offset(page);
@@ -338,15 +363,18 @@
CEPH_OSD_FLAG_READ, NULL,
ci->i_truncate_seq, ci->i_truncate_size,
false);
- if (IS_ERR(req))
- return PTR_ERR(req);
+ if (IS_ERR(req)) {
+ ret = PTR_ERR(req);
+ goto out;
+ }
/* build page vector */
nr_pages = calc_pages_for(0, len);
pages = kmalloc(sizeof(*pages) * nr_pages, GFP_KERNEL);
- ret = -ENOMEM;
- if (!pages)
- goto out;
+ if (!pages) {
+ ret = -ENOMEM;
+ goto out_put;
+ }
for (i = 0; i < nr_pages; ++i) {
page = list_entry(page_list->prev, struct page, lru);
BUG_ON(PageLocked(page));
@@ -379,6 +407,12 @@
if (ret < 0)
goto out_pages;
ceph_osdc_put_request(req);
+
+ /* After adding locked pages to page cache, the inode holds cache cap.
+ * So we can drop our cap refs. */
+ if (got)
+ ceph_put_cap_refs(ci, got);
+
return nr_pages;
out_pages:
@@ -387,8 +421,11 @@
unlock_page(pages[i]);
}
ceph_put_page_vector(pages, nr_pages, false);
-out:
+out_put:
ceph_osdc_put_request(req);
+out:
+ if (got)
+ ceph_put_cap_refs(ci, got);
return ret;
}
@@ -425,7 +462,6 @@
rc = start_read(inode, page_list, max);
if (rc < 0)
goto out;
- BUG_ON(rc == 0);
}
out:
ceph_fscache_readpages_cancel(inode, page_list);
@@ -1372,9 +1408,11 @@
inode, off, (size_t)PAGE_SIZE, ceph_cap_string(got));
if ((got & (CEPH_CAP_FILE_CACHE | CEPH_CAP_FILE_LAZYIO)) ||
- ci->i_inline_version == CEPH_INLINE_NONE)
+ ci->i_inline_version == CEPH_INLINE_NONE) {
+ current->journal_info = vma->vm_file;
ret = filemap_fault(vma, vmf);
- else
+ current->journal_info = NULL;
+ } else
ret = -EAGAIN;
dout("filemap_fault %p %llu~%zd dropping cap refs on %s ret %d\n",
diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c
index f3f2110..03951f9 100644
--- a/fs/ceph/caps.c
+++ b/fs/ceph/caps.c
@@ -2479,6 +2479,27 @@
ceph_check_caps(ci, CHECK_CAPS_AUTHONLY, NULL);
}
+int ceph_try_get_caps(struct ceph_inode_info *ci, int need, int want, int *got)
+{
+ int ret, err = 0;
+
+ BUG_ON(need & ~CEPH_CAP_FILE_RD);
+ BUG_ON(want & ~(CEPH_CAP_FILE_CACHE|CEPH_CAP_FILE_LAZYIO));
+ ret = ceph_pool_perm_check(ci, need);
+ if (ret < 0)
+ return ret;
+
+ ret = try_get_cap_refs(ci, need, want, 0, true, got, &err);
+ if (ret) {
+ if (err == -EAGAIN) {
+ ret = 0;
+ } else if (err < 0) {
+ ret = err;
+ }
+ }
+ return ret;
+}
+
/*
* Wait for caps, and take cap references. If we can't get a WR cap
* due to a small max_size, make sure we check_max_size (and possibly
diff --git a/fs/ceph/file.c b/fs/ceph/file.c
index f995e35..ca3f630 100644
--- a/fs/ceph/file.c
+++ b/fs/ceph/file.c
@@ -1249,8 +1249,9 @@
dout("aio_read %p %llx.%llx %llu~%u got cap refs on %s\n",
inode, ceph_vinop(inode), iocb->ki_pos, (unsigned)len,
ceph_cap_string(got));
-
+ current->journal_info = filp;
ret = generic_file_read_iter(iocb, to);
+ current->journal_info = NULL;
}
dout("aio_read %p %llx.%llx dropping cap refs on %s = %d\n",
inode, ceph_vinop(inode), ceph_cap_string(got), (int)ret);
diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c
index 12f2252..953275b 100644
--- a/fs/ceph/inode.c
+++ b/fs/ceph/inode.c
@@ -2080,11 +2080,6 @@
if (inode_dirty_flags)
__mark_inode_dirty(inode, inode_dirty_flags);
- if (ia_valid & ATTR_MODE) {
- err = posix_acl_chmod(inode, attr->ia_mode);
- if (err)
- goto out_put;
- }
if (mask) {
req->r_inode = inode;
@@ -2098,13 +2093,11 @@
ceph_cap_string(dirtied), mask);
ceph_mdsc_put_request(req);
- if (mask & CEPH_SETATTR_SIZE)
+ ceph_free_cap_flush(prealloc_cf);
+
+ if (err >= 0 && (mask & CEPH_SETATTR_SIZE))
__ceph_do_pending_vmtruncate(inode);
- ceph_free_cap_flush(prealloc_cf);
- return err;
-out_put:
- ceph_mdsc_put_request(req);
- ceph_free_cap_flush(prealloc_cf);
+
return err;
}
@@ -2123,7 +2116,12 @@
if (err != 0)
return err;
- return __ceph_setattr(inode, attr);
+ err = __ceph_setattr(inode, attr);
+
+ if (err >= 0 && (attr->ia_valid & ATTR_MODE))
+ err = posix_acl_chmod(inode, attr->ia_mode);
+
+ return err;
}
/*
diff --git a/fs/ceph/super.h b/fs/ceph/super.h
index 3e3fa916..622d5dd 100644
--- a/fs/ceph/super.h
+++ b/fs/ceph/super.h
@@ -905,6 +905,8 @@
extern int ceph_get_caps(struct ceph_inode_info *ci, int need, int want,
loff_t endoff, int *got, struct page **pinned_page);
+extern int ceph_try_get_caps(struct ceph_inode_info *ci,
+ int need, int want, int *got);
/* for counting open files by mode */
extern void __ceph_get_fmode(struct ceph_inode_info *ci, int mode);
diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h
index 94661cf..b3830f7 100644
--- a/fs/cifs/cifsglob.h
+++ b/fs/cifs/cifsglob.h
@@ -241,6 +241,7 @@
/* verify the message */
int (*check_message)(char *, unsigned int, struct TCP_Server_Info *);
bool (*is_oplock_break)(char *, struct TCP_Server_Info *);
+ int (*handle_cancelled_mid)(char *, struct TCP_Server_Info *);
void (*downgrade_oplock)(struct TCP_Server_Info *,
struct cifsInodeInfo *, bool);
/* process transaction2 response */
@@ -1314,12 +1315,19 @@
void *callback_data; /* general purpose pointer for callback */
void *resp_buf; /* pointer to received SMB header */
int mid_state; /* wish this were enum but can not pass to wait_event */
+ unsigned int mid_flags;
__le16 command; /* smb command code */
bool large_buf:1; /* if valid response, is pointer to large buf */
bool multiRsp:1; /* multiple trans2 responses for one request */
bool multiEnd:1; /* both received */
};
+struct close_cancelled_open {
+ struct cifs_fid fid;
+ struct cifs_tcon *tcon;
+ struct work_struct work;
+};
+
/* Make code in transport.c a little cleaner by moving
update of optional stats into function below */
#ifdef CONFIG_CIFS_STATS2
@@ -1451,6 +1459,9 @@
#define MID_RESPONSE_MALFORMED 0x10
#define MID_SHUTDOWN 0x20
+/* Flags */
+#define MID_WAIT_CANCELLED 1 /* Cancelled while waiting for response */
+
/* Types of response buffer returned from SendReceive2 */
#define CIFS_NO_BUFFER 0 /* Response buffer not returned */
#define CIFS_SMALL_BUFFER 1
diff --git a/fs/cifs/cifssmb.c b/fs/cifs/cifssmb.c
index e3fed92..586fdac 100644
--- a/fs/cifs/cifssmb.c
+++ b/fs/cifs/cifssmb.c
@@ -1423,6 +1423,8 @@
length = discard_remaining_data(server);
dequeue_mid(mid, rdata->result);
+ mid->resp_buf = server->smallbuf;
+ server->smallbuf = NULL;
return length;
}
@@ -1534,6 +1536,8 @@
return cifs_readv_discard(server, mid);
dequeue_mid(mid, false);
+ mid->resp_buf = server->smallbuf;
+ server->smallbuf = NULL;
return length;
}
diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index 893be07..b8015de 100644
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -882,10 +882,19 @@
server->lstrp = jiffies;
if (mid_entry != NULL) {
+ if ((mid_entry->mid_flags & MID_WAIT_CANCELLED) &&
+ mid_entry->mid_state == MID_RESPONSE_RECEIVED &&
+ server->ops->handle_cancelled_mid)
+ server->ops->handle_cancelled_mid(
+ mid_entry->resp_buf,
+ server);
+
if (!mid_entry->multiRsp || mid_entry->multiEnd)
mid_entry->callback(mid_entry);
- } else if (!server->ops->is_oplock_break ||
- !server->ops->is_oplock_break(buf, server)) {
+ } else if (server->ops->is_oplock_break &&
+ server->ops->is_oplock_break(buf, server)) {
+ cifs_dbg(FYI, "Received oplock break\n");
+ } else {
cifs_dbg(VFS, "No task to wake, unknown frame received! NumMids %d\n",
atomic_read(&midCount));
cifs_dump_mem("Received Data is: ", buf,
diff --git a/fs/cifs/smb2misc.c b/fs/cifs/smb2misc.c
index 3d38348..9730780 100644
--- a/fs/cifs/smb2misc.c
+++ b/fs/cifs/smb2misc.c
@@ -654,3 +654,47 @@
cifs_dbg(FYI, "Can not process oplock break for non-existent connection\n");
return false;
}
+
+void
+smb2_cancelled_close_fid(struct work_struct *work)
+{
+ struct close_cancelled_open *cancelled = container_of(work,
+ struct close_cancelled_open, work);
+
+ cifs_dbg(VFS, "Close unmatched open\n");
+
+ SMB2_close(0, cancelled->tcon, cancelled->fid.persistent_fid,
+ cancelled->fid.volatile_fid);
+ cifs_put_tcon(cancelled->tcon);
+ kfree(cancelled);
+}
+
+int
+smb2_handle_cancelled_mid(char *buffer, struct TCP_Server_Info *server)
+{
+ struct smb2_hdr *hdr = (struct smb2_hdr *)buffer;
+ struct smb2_create_rsp *rsp = (struct smb2_create_rsp *)buffer;
+ struct cifs_tcon *tcon;
+ struct close_cancelled_open *cancelled;
+
+ if (hdr->Command != SMB2_CREATE || hdr->Status != STATUS_SUCCESS)
+ return 0;
+
+ cancelled = kzalloc(sizeof(*cancelled), GFP_KERNEL);
+ if (!cancelled)
+ return -ENOMEM;
+
+ tcon = smb2_find_smb_tcon(server, hdr->SessionId, hdr->TreeId);
+ if (!tcon) {
+ kfree(cancelled);
+ return -ENOENT;
+ }
+
+ cancelled->fid.persistent_fid = rsp->PersistentFileId;
+ cancelled->fid.volatile_fid = rsp->VolatileFileId;
+ cancelled->tcon = tcon;
+ INIT_WORK(&cancelled->work, smb2_cancelled_close_fid);
+ queue_work(cifsiod_wq, &cancelled->work);
+
+ return 0;
+}
diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c
index 5d456eb..007abf7 100644
--- a/fs/cifs/smb2ops.c
+++ b/fs/cifs/smb2ops.c
@@ -1565,6 +1565,7 @@
.clear_stats = smb2_clear_stats,
.print_stats = smb2_print_stats,
.is_oplock_break = smb2_is_valid_oplock_break,
+ .handle_cancelled_mid = smb2_handle_cancelled_mid,
.downgrade_oplock = smb2_downgrade_oplock,
.need_neg = smb2_need_neg,
.negotiate = smb2_negotiate,
@@ -1645,6 +1646,7 @@
.clear_stats = smb2_clear_stats,
.print_stats = smb2_print_stats,
.is_oplock_break = smb2_is_valid_oplock_break,
+ .handle_cancelled_mid = smb2_handle_cancelled_mid,
.downgrade_oplock = smb2_downgrade_oplock,
.need_neg = smb2_need_neg,
.negotiate = smb2_negotiate,
@@ -1727,6 +1729,7 @@
.print_stats = smb2_print_stats,
.dump_share_caps = smb2_dump_share_caps,
.is_oplock_break = smb2_is_valid_oplock_break,
+ .handle_cancelled_mid = smb2_handle_cancelled_mid,
.downgrade_oplock = smb2_downgrade_oplock,
.need_neg = smb2_need_neg,
.negotiate = smb2_negotiate,
@@ -1815,6 +1818,7 @@
.print_stats = smb2_print_stats,
.dump_share_caps = smb2_dump_share_caps,
.is_oplock_break = smb2_is_valid_oplock_break,
+ .handle_cancelled_mid = smb2_handle_cancelled_mid,
.downgrade_oplock = smb2_downgrade_oplock,
.need_neg = smb2_need_neg,
.negotiate = smb2_negotiate,
diff --git a/fs/cifs/smb2proto.h b/fs/cifs/smb2proto.h
index f2d511a..04ef6e9 100644
--- a/fs/cifs/smb2proto.h
+++ b/fs/cifs/smb2proto.h
@@ -48,6 +48,10 @@
struct smb_rqst *rqst);
extern struct mid_q_entry *smb2_setup_async_request(
struct TCP_Server_Info *server, struct smb_rqst *rqst);
+extern struct cifs_ses *smb2_find_smb_ses(struct TCP_Server_Info *server,
+ __u64 ses_id);
+extern struct cifs_tcon *smb2_find_smb_tcon(struct TCP_Server_Info *server,
+ __u64 ses_id, __u32 tid);
extern int smb2_calc_signature(struct smb_rqst *rqst,
struct TCP_Server_Info *server);
extern int smb3_calc_signature(struct smb_rqst *rqst,
@@ -158,6 +162,9 @@
extern int SMB2_oplock_break(const unsigned int xid, struct cifs_tcon *tcon,
const u64 persistent_fid, const u64 volatile_fid,
const __u8 oplock_level);
+extern int smb2_handle_cancelled_mid(char *buffer,
+ struct TCP_Server_Info *server);
+void smb2_cancelled_close_fid(struct work_struct *work);
extern int SMB2_QFS_info(const unsigned int xid, struct cifs_tcon *tcon,
u64 persistent_file_id, u64 volatile_file_id,
struct kstatfs *FSData);
diff --git a/fs/cifs/smb2transport.c b/fs/cifs/smb2transport.c
index bc9a7b6..390b0d0 100644
--- a/fs/cifs/smb2transport.c
+++ b/fs/cifs/smb2transport.c
@@ -115,22 +115,68 @@
}
static struct cifs_ses *
-smb2_find_smb_ses(struct smb2_hdr *smb2hdr, struct TCP_Server_Info *server)
+smb2_find_smb_ses_unlocked(struct TCP_Server_Info *server, __u64 ses_id)
{
struct cifs_ses *ses;
- spin_lock(&cifs_tcp_ses_lock);
list_for_each_entry(ses, &server->smb_ses_list, smb_ses_list) {
- if (ses->Suid != smb2hdr->SessionId)
+ if (ses->Suid != ses_id)
continue;
- spin_unlock(&cifs_tcp_ses_lock);
return ses;
}
- spin_unlock(&cifs_tcp_ses_lock);
return NULL;
}
+struct cifs_ses *
+smb2_find_smb_ses(struct TCP_Server_Info *server, __u64 ses_id)
+{
+ struct cifs_ses *ses;
+
+ spin_lock(&cifs_tcp_ses_lock);
+ ses = smb2_find_smb_ses_unlocked(server, ses_id);
+ spin_unlock(&cifs_tcp_ses_lock);
+
+ return ses;
+}
+
+static struct cifs_tcon *
+smb2_find_smb_sess_tcon_unlocked(struct cifs_ses *ses, __u32 tid)
+{
+ struct cifs_tcon *tcon;
+
+ list_for_each_entry(tcon, &ses->tcon_list, tcon_list) {
+ if (tcon->tid != tid)
+ continue;
+ ++tcon->tc_count;
+ return tcon;
+ }
+
+ return NULL;
+}
+
+/*
+ * Obtain tcon corresponding to the tid in the given
+ * cifs_ses
+ */
+
+struct cifs_tcon *
+smb2_find_smb_tcon(struct TCP_Server_Info *server, __u64 ses_id, __u32 tid)
+{
+ struct cifs_ses *ses;
+ struct cifs_tcon *tcon;
+
+ spin_lock(&cifs_tcp_ses_lock);
+ ses = smb2_find_smb_ses_unlocked(server, ses_id);
+ if (!ses) {
+ spin_unlock(&cifs_tcp_ses_lock);
+ return NULL;
+ }
+ tcon = smb2_find_smb_sess_tcon_unlocked(ses, tid);
+ spin_unlock(&cifs_tcp_ses_lock);
+
+ return tcon;
+}
int
smb2_calc_signature(struct smb_rqst *rqst, struct TCP_Server_Info *server)
@@ -142,7 +188,7 @@
struct smb2_hdr *smb2_pdu = (struct smb2_hdr *)iov[0].iov_base;
struct cifs_ses *ses;
- ses = smb2_find_smb_ses(smb2_pdu, server);
+ ses = smb2_find_smb_ses(server, smb2_pdu->SessionId);
if (!ses) {
cifs_dbg(VFS, "%s: Could not find session\n", __func__);
return 0;
@@ -359,7 +405,7 @@
struct smb2_hdr *smb2_pdu = (struct smb2_hdr *)iov[0].iov_base;
struct cifs_ses *ses;
- ses = smb2_find_smb_ses(smb2_pdu, server);
+ ses = smb2_find_smb_ses(server, smb2_pdu->SessionId);
if (!ses) {
cifs_dbg(VFS, "%s: Could not find session\n", __func__);
return 0;
diff --git a/fs/cifs/transport.c b/fs/cifs/transport.c
index 206a597..cc26d41 100644
--- a/fs/cifs/transport.c
+++ b/fs/cifs/transport.c
@@ -727,9 +727,11 @@
rc = wait_for_response(ses->server, midQ);
if (rc != 0) {
+ cifs_dbg(FYI, "Cancelling wait for mid %llu\n", midQ->mid);
send_cancel(ses->server, buf, midQ);
spin_lock(&GlobalMid_Lock);
if (midQ->mid_state == MID_REQUEST_SUBMITTED) {
+ midQ->mid_flags |= MID_WAIT_CANCELLED;
midQ->callback = DeleteMidQEntry;
spin_unlock(&GlobalMid_Lock);
cifs_small_buf_release(buf);
diff --git a/fs/nfsd/nfs3xdr.c b/fs/nfsd/nfs3xdr.c
index dba2ff8..4523346 100644
--- a/fs/nfsd/nfs3xdr.c
+++ b/fs/nfsd/nfs3xdr.c
@@ -358,6 +358,8 @@
{
unsigned int len, v, hdr, dlen;
u32 max_blocksize = svc_max_payload(rqstp);
+ struct kvec *head = rqstp->rq_arg.head;
+ struct kvec *tail = rqstp->rq_arg.tail;
p = decode_fh(p, &args->fh);
if (!p)
@@ -367,6 +369,8 @@
args->count = ntohl(*p++);
args->stable = ntohl(*p++);
len = args->len = ntohl(*p++);
+ if ((void *)p > head->iov_base + head->iov_len)
+ return 0;
/*
* The count must equal the amount of data passed.
*/
@@ -377,9 +381,8 @@
* Check to make sure that we got the right number of
* bytes.
*/
- hdr = (void*)p - rqstp->rq_arg.head[0].iov_base;
- dlen = rqstp->rq_arg.head[0].iov_len + rqstp->rq_arg.page_len
- + rqstp->rq_arg.tail[0].iov_len - hdr;
+ hdr = (void*)p - head->iov_base;
+ dlen = head->iov_len + rqstp->rq_arg.page_len + tail->iov_len - hdr;
/*
* Round the length of the data which was specified up to
* the next multiple of XDR units and then compare that
@@ -396,7 +399,7 @@
len = args->len = max_blocksize;
}
rqstp->rq_vec[0].iov_base = (void*)p;
- rqstp->rq_vec[0].iov_len = rqstp->rq_arg.head[0].iov_len - hdr;
+ rqstp->rq_vec[0].iov_len = head->iov_len - hdr;
v = 0;
while (len > rqstp->rq_vec[v].iov_len) {
len -= rqstp->rq_vec[v].iov_len;
@@ -471,6 +474,8 @@
/* first copy and check from the first page */
old = (char*)p;
vec = &rqstp->rq_arg.head[0];
+ if ((void *)old > vec->iov_base + vec->iov_len)
+ return 0;
avail = vec->iov_len - (old - (char*)vec->iov_base);
while (len && avail && *old) {
*new++ = *old++;
diff --git a/fs/nfsd/nfssvc.c b/fs/nfsd/nfssvc.c
index a2b65fc..1645b97 100644
--- a/fs/nfsd/nfssvc.c
+++ b/fs/nfsd/nfssvc.c
@@ -733,6 +733,37 @@
return nfserr;
}
+/*
+ * A write procedure can have a large argument, and a read procedure can
+ * have a large reply, but no NFSv2 or NFSv3 procedure has argument and
+ * reply that can both be larger than a page. The xdr code has taken
+ * advantage of this assumption to be a sloppy about bounds checking in
+ * some cases. Pending a rewrite of the NFSv2/v3 xdr code to fix that
+ * problem, we enforce these assumptions here:
+ */
+static bool nfs_request_too_big(struct svc_rqst *rqstp,
+ struct svc_procedure *proc)
+{
+ /*
+ * The ACL code has more careful bounds-checking and is not
+ * susceptible to this problem:
+ */
+ if (rqstp->rq_prog != NFS_PROGRAM)
+ return false;
+ /*
+ * Ditto NFSv4 (which can in theory have argument and reply both
+ * more than a page):
+ */
+ if (rqstp->rq_vers >= 4)
+ return false;
+ /* The reply will be small, we're OK: */
+ if (proc->pc_xdrressize > 0 &&
+ proc->pc_xdrressize < XDR_QUADLEN(PAGE_SIZE))
+ return false;
+
+ return rqstp->rq_arg.len > PAGE_SIZE;
+}
+
int
nfsd_dispatch(struct svc_rqst *rqstp, __be32 *statp)
{
@@ -745,6 +776,11 @@
rqstp->rq_vers, rqstp->rq_proc);
proc = rqstp->rq_procinfo;
+ if (nfs_request_too_big(rqstp, proc)) {
+ dprintk("nfsd: NFSv%d argument too large\n", rqstp->rq_vers);
+ *statp = rpc_garbage_args;
+ return 1;
+ }
/*
* Give the xdr decoder a chance to change this if it wants
* (necessary in the NFSv4.0 compound case)
diff --git a/fs/nfsd/nfsxdr.c b/fs/nfsd/nfsxdr.c
index 41b468a..de07ff6 100644
--- a/fs/nfsd/nfsxdr.c
+++ b/fs/nfsd/nfsxdr.c
@@ -280,6 +280,7 @@
struct nfsd_writeargs *args)
{
unsigned int len, hdr, dlen;
+ struct kvec *head = rqstp->rq_arg.head;
int v;
p = decode_fh(p, &args->fh);
@@ -300,9 +301,10 @@
* Check to make sure that we got the right number of
* bytes.
*/
- hdr = (void*)p - rqstp->rq_arg.head[0].iov_base;
- dlen = rqstp->rq_arg.head[0].iov_len + rqstp->rq_arg.page_len
- - hdr;
+ hdr = (void*)p - head->iov_base;
+ if (hdr > head->iov_len)
+ return 0;
+ dlen = head->iov_len + rqstp->rq_arg.page_len - hdr;
/*
* Round the length of the data which was specified up to
@@ -316,7 +318,7 @@
return 0;
rqstp->rq_vec[0].iov_base = (void*)p;
- rqstp->rq_vec[0].iov_len = rqstp->rq_arg.head[0].iov_len - hdr;
+ rqstp->rq_vec[0].iov_len = head->iov_len - hdr;
v = 0;
while (len > rqstp->rq_vec[v].iov_len) {
len -= rqstp->rq_vec[v].iov_len;
diff --git a/fs/timerfd.c b/fs/timerfd.c
index b938fa7..7ec77f8 100644
--- a/fs/timerfd.c
+++ b/fs/timerfd.c
@@ -40,6 +40,7 @@
short unsigned settime_flags; /* to show in fdinfo */
struct rcu_head rcu;
struct list_head clist;
+ spinlock_t cancel_lock;
bool might_cancel;
};
@@ -113,7 +114,7 @@
rcu_read_unlock();
}
-static void timerfd_remove_cancel(struct timerfd_ctx *ctx)
+static void __timerfd_remove_cancel(struct timerfd_ctx *ctx)
{
if (ctx->might_cancel) {
ctx->might_cancel = false;
@@ -123,6 +124,13 @@
}
}
+static void timerfd_remove_cancel(struct timerfd_ctx *ctx)
+{
+ spin_lock(&ctx->cancel_lock);
+ __timerfd_remove_cancel(ctx);
+ spin_unlock(&ctx->cancel_lock);
+}
+
static bool timerfd_canceled(struct timerfd_ctx *ctx)
{
if (!ctx->might_cancel || ctx->moffs.tv64 != KTIME_MAX)
@@ -133,6 +141,7 @@
static void timerfd_setup_cancel(struct timerfd_ctx *ctx, int flags)
{
+ spin_lock(&ctx->cancel_lock);
if ((ctx->clockid == CLOCK_REALTIME ||
ctx->clockid == CLOCK_REALTIME_ALARM ||
ctx->clockid == CLOCK_POWEROFF_ALARM) &&
@@ -143,9 +152,10 @@
list_add_rcu(&ctx->clist, &cancel_list);
spin_unlock(&cancel_lock);
}
- } else if (ctx->might_cancel) {
- timerfd_remove_cancel(ctx);
+ } else {
+ __timerfd_remove_cancel(ctx);
}
+ spin_unlock(&ctx->cancel_lock);
}
static ktime_t timerfd_get_remaining(struct timerfd_ctx *ctx)
@@ -403,6 +413,7 @@
return -ENOMEM;
init_waitqueue_head(&ctx->wqh);
+ spin_lock_init(&ctx->cancel_lock);
ctx->clockid = clockid;
if (isalarm(ctx)) {
diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
index 24dd11e..91ea077 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
@@ -55,7 +55,6 @@
#define DISP_CC_PLL0 38
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 39
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 40
-#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 41
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_GCC_CLOCKS_BCR 1
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
index a31fa20..f3c3d1d 100644
--- a/include/dt-bindings/clock/qcom,rpmh.h
+++ b/include/dt-bindings/clock/qcom,rpmh.h
@@ -27,7 +27,5 @@
#define RPMH_RF_CLK2_A 9
#define RPMH_RF_CLK3 10
#define RPMH_RF_CLK3_A 11
-#define RPMH_QDSS_CLK 12
-#define RPMH_QDSS_A_CLK 13
#endif
diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h
index bda14ef..744ea4f 100644
--- a/include/linux/blk_types.h
+++ b/include/linux/blk_types.h
@@ -125,6 +125,7 @@
* BVEC_POOL_IDX()
*/
#define BIO_RESET_BITS 10
+#define BIO_INLINECRYPT 15
/*
* We support 6 different bvec pools, the last one is magic in that it
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index ec7047c..0538291 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -41,13 +41,6 @@
extern struct bus_type coresight_bustype;
-enum coresight_clk_rate {
- CORESIGHT_CLK_RATE_OFF,
- CORESIGHT_CLK_RATE_TRACE = 1000,
- CORESIGHT_CLK_RATE_HSTRACE = 2000,
- CORESIGHT_CLK_RATE_FIXED = 3000,
-};
-
enum coresight_dev_type {
CORESIGHT_DEV_TYPE_NONE,
CORESIGHT_DEV_TYPE_SINK,
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 1f6892c..e3d181e 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -436,6 +436,7 @@
void iommu_fwspec_free(struct device *dev);
int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids);
int iommu_fwspec_get_id(struct device *dev, u32 *id);
+int iommu_is_available(struct device *dev);
#else /* CONFIG_IOMMU_API */
@@ -711,6 +712,10 @@
return -ENODEV;
}
+static inline int iommu_is_available(struct device *dev)
+{
+ return -ENODEV;
+}
#endif /* CONFIG_IOMMU_API */
#endif /* __LINUX_IOMMU_H */
diff --git a/include/linux/msm_pcie.h b/include/linux/msm_pcie.h
index 8316aaa..b9527d3 100644
--- a/include/linux/msm_pcie.h
+++ b/include/linux/msm_pcie.h
@@ -157,18 +157,6 @@
int msm_pcie_debug_info(struct pci_dev *dev, u32 option, u32 base,
u32 offset, u32 mask, u32 value);
-/*
- * msm_pcie_configure_sid - calculates the SID for a PCIe endpoint.
- * @dev: device structure
- * @sid: the calculated SID
- * @domain: the domain number of the Root Complex
- *
- * This function calculates the SID for a PCIe endpoint device.
- *
- * Return: 0 on success, negative value on error
- */
-int msm_pcie_configure_sid(struct device *dev, u32 *sid,
- int *domain);
#else /* !CONFIG_PCI_MSM */
static inline int msm_pcie_pm_control(enum msm_pcie_pm_opt pm_opt, u32 busnr,
void *user, void *data, u32 options)
@@ -206,12 +194,6 @@
{
return -ENODEV;
}
-
-static inline int msm_pcie_configure_sid(struct device *dev, u32 *sid,
- int *domain)
-{
- return -ENODEV;
-}
#endif /* CONFIG_PCI_MSM */
#endif /* __MSM_PCIE_H */
diff --git a/include/linux/phy.h b/include/linux/phy.h
index e25f183..bd22670 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -806,6 +806,7 @@
void phy_mac_interrupt(struct phy_device *phydev, int new_link);
void phy_start_machine(struct phy_device *phydev);
void phy_stop_machine(struct phy_device *phydev);
+void phy_trigger_machine(struct phy_device *phydev, bool sync);
int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd);
int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd);
int phy_ethtool_ksettings_get(struct phy_device *phydev,
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index cb4387d..12b3d51e8 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -86,6 +86,7 @@
#define SE_GENI_TX_WATERMARK_REG (0x80C)
#define SE_GENI_RX_WATERMARK_REG (0x810)
#define SE_GENI_RX_RFR_WATERMARK_REG (0x814)
+#define SE_GENI_IOS (0x908)
#define SE_GENI_M_GP_LENGTH (0x910)
#define SE_GENI_S_GP_LENGTH (0x914)
#define SE_GSI_EVENT_EN (0xE18)
@@ -228,6 +229,10 @@
#define GENI_M_EVENT_EN (BIT(2))
#define GENI_S_EVENT_EN (BIT(3))
+/* SE_GENI_IOS fields */
+#define IO2_DATA_IN (BIT(1))
+#define RX_DATA_IN (BIT(0))
+
/* SE_IRQ_EN fields */
#define DMA_RX_IRQ_EN (BIT(0))
#define DMA_TX_IRQ_EN (BIT(1))
@@ -275,7 +280,7 @@
static inline void geni_write_reg(unsigned int value, void __iomem *base,
int offset)
{
- return writel_relaxed(value, (base + offset));
+ writel_relaxed(value, (base + offset));
}
static inline int get_se_proto(void __iomem *base)
@@ -479,11 +484,11 @@
return rx_fifo_depth;
}
-static inline void se_config_packing(void __iomem *base, int bpw,
- int pack_words, bool msb_to_lsb)
+static inline void se_get_packing_config(int bpw, int pack_words,
+ bool msb_to_lsb, unsigned long *cfg0,
+ unsigned long *cfg1)
{
u32 cfg[4] = {0};
- unsigned long cfg0, cfg1;
int len = ((bpw < 8) ? (bpw - 1) : 7);
int idx = ((msb_to_lsb == 1) ? len : 0);
int iter = (bpw * pack_words) >> 3;
@@ -495,8 +500,16 @@
if (i == iter - 1)
cfg[i] |= 1;
}
- cfg0 = cfg[0] | (cfg[1] << 10);
- cfg1 = cfg[2] | (cfg[3] << 10);
+ *cfg0 = cfg[0] | (cfg[1] << 10);
+ *cfg1 = cfg[2] | (cfg[3] << 10);
+}
+
+static inline void se_config_packing(void __iomem *base, int bpw,
+ int pack_words, bool msb_to_lsb)
+{
+ unsigned long cfg0, cfg1;
+
+ se_get_packing_config(bpw, pack_words, msb_to_lsb, &cfg0, &cfg1);
geni_write_reg(cfg0, base, SE_GENI_TX_PACKING_CFG0);
geni_write_reg(cfg1, base, SE_GENI_TX_PACKING_CFG1);
geni_write_reg(cfg0, base, SE_GENI_RX_PACKING_CFG0);
diff --git a/include/linux/qpnp/qpnp-adc.h b/include/linux/qpnp/qpnp-adc.h
index 1c13cd2..0e4586f 100644
--- a/include/linux/qpnp/qpnp-adc.h
+++ b/include/linux/qpnp/qpnp-adc.h
@@ -2216,25 +2216,6 @@
#if defined(CONFIG_THERMAL_QPNP_ADC_TM) \
|| defined(CONFIG_THERMAL_QPNP_ADC_TM_MODULE)
/**
- * qpnp_adc_tm_usbid_configure() - Configures Channel 0 of VADC_BTM to
- * monitor USB_ID channel using 100k internal pull-up.
- * USB driver passes the high/low voltage threshold along
- * with the notification callback once the set thresholds
- * are crossed.
- * @param: Structure pointer of qpnp_adc_tm_usbid_param type.
- * Clients pass the low/high voltage along with the threshold
- * notification callback.
- */
-int32_t qpnp_adc_tm_usbid_configure(struct qpnp_adc_tm_chip *chip,
- struct qpnp_adc_tm_btm_param *param);
-/**
- * qpnp_adc_tm_usbid_end() - Disables the monitoring of channel 0 thats
- * assigned for monitoring USB_ID. Disables the low/high
- * threshold activation for channel 0 as well.
- * @param: none.
- */
-int32_t qpnp_adc_tm_usbid_end(struct qpnp_adc_tm_chip *chip);
-/**
* qpnp_adc_tm_channel_measure() - Configures kernel clients a channel to
* monitor the corresponding ADC channel for threshold detection.
* Driver passes the high/low voltage threshold along
diff --git a/include/linux/sde_rsc.h b/include/linux/sde_rsc.h
index 60cc768..f3fa9e6 100644
--- a/include/linux/sde_rsc.h
+++ b/include/linux/sde_rsc.h
@@ -79,6 +79,7 @@
* @current_state: current client state
* @crtc_id: crtc_id associated with this rsc client.
* @rsc_index: rsc index of a client - only index "0" valid.
+ * @id: Index of client. It will be assigned during client_create call
* @list: list to attach client master list
*/
struct sde_rsc_client {
@@ -86,6 +87,7 @@
short current_state;
int crtc_id;
u32 rsc_index;
+ u32 id;
struct list_head list;
};
diff --git a/include/media/msm_vidc.h b/include/media/msm_vidc.h
index 262fa64..0583431 100644
--- a/include/media/msm_vidc.h
+++ b/include/media/msm_vidc.h
@@ -103,6 +103,7 @@
int msm_vidc_g_fmt(void *instance, struct v4l2_format *f);
int msm_vidc_s_ctrl(void *instance, struct v4l2_control *a);
int msm_vidc_s_ext_ctrl(void *instance, struct v4l2_ext_controls *a);
+int msm_vidc_g_ext_ctrl(void *instance, struct v4l2_ext_controls *a);
int msm_vidc_g_ctrl(void *instance, struct v4l2_control *a);
int msm_vidc_reqbufs(void *instance, struct v4l2_requestbuffers *b);
int msm_vidc_release_buffer(void *instance, int buffer_type,
diff --git a/include/soc/qcom/rpmh.h b/include/soc/qcom/rpmh.h
index 34434fd..75e6ccd 100644
--- a/include/soc/qcom/rpmh.h
+++ b/include/soc/qcom/rpmh.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -34,6 +34,8 @@
int rpmh_write_passthru(struct rpmh_client *rc, enum rpmh_state state,
struct tcs_cmd *cmd, int *n);
+int rpmh_mode_solver_set(struct rpmh_client *rc, bool enable);
+
int rpmh_write_control(struct rpmh_client *rc, struct tcs_cmd *cmd, int n);
int rpmh_invalidate(struct rpmh_client *rc);
@@ -70,6 +72,9 @@
enum rpmh_state state, struct tcs_cmd *cmd, int *n)
{ return -ENODEV; }
+static inline int rpmh_mode_solver_set(struct rpmh_client *rc, bool enable)
+{ return -ENODEV; }
+
static inline int rpmh_write_control(struct rpmh_client *rc,
struct tcs_cmd *cmd, int n)
{ return -ENODEV; }
diff --git a/include/sound/voice_svc.h b/include/sound/voice_svc.h
deleted file mode 100644
index 035053f..0000000
--- a/include/sound/voice_svc.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __VOICE_SVC_H__
-#define __VOICE_SVC_H__
-
-#include <linux/types.h>
-#include <linux/ioctl.h>
-
-#define VOICE_SVC_DRIVER_NAME "voice_svc"
-
-#define VOICE_SVC_MVM_STR "MVM"
-#define VOICE_SVC_CVS_STR "CVS"
-#define MAX_APR_SERVICE_NAME_LEN 64
-
-#define MSG_REGISTER 0x1
-#define MSG_REQUEST 0x2
-#define MSG_RESPONSE 0x3
-
-struct voice_svc_write_msg {
- __u32 msg_type;
- __u8 payload[0];
-};
-
-struct voice_svc_register {
- char svc_name[MAX_APR_SERVICE_NAME_LEN];
- __u32 src_port;
- __u8 reg_flag;
-};
-
-struct voice_svc_cmd_response {
- __u32 src_port;
- __u32 dest_port;
- __u32 token;
- __u32 opcode;
- __u32 payload_size;
- __u8 payload[0];
-};
-
-struct voice_svc_cmd_request {
- char svc_name[MAX_APR_SERVICE_NAME_LEN];
- __u32 src_port;
- __u32 dest_port;
- __u32 token;
- __u32 opcode;
- __u32 payload_size;
- __u8 payload[0];
-};
-
-#endif
diff --git a/include/trace/events/clk.h b/include/trace/events/clk.h
index 7586072..ad19e73 100644
--- a/include/trace/events/clk.h
+++ b/include/trace/events/clk.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2015, 2017, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -192,6 +192,42 @@
TP_ARGS(core, phase)
);
+DECLARE_EVENT_CLASS(clk_state_dump,
+
+ TP_PROTO(const char *name, unsigned int prepare_count,
+ unsigned int enable_count, unsigned long rate, unsigned int vdd_level),
+
+ TP_ARGS(name, prepare_count, enable_count, rate, vdd_level),
+
+ TP_STRUCT__entry(
+ __string(name, name)
+ __field(unsigned int, prepare_count)
+ __field(unsigned int, enable_count)
+ __field(unsigned long, rate)
+ __field(unsigned int, vdd_level)
+ ),
+
+ TP_fast_assign(
+ __assign_str(name, name);
+ __entry->prepare_count = prepare_count;
+ __entry->enable_count = enable_count;
+ __entry->rate = rate;
+ __entry->vdd_level = vdd_level;
+ ),
+
+ TP_printk("%s\tprepare:enable cnt [%u:%u]\trate: vdd_level [%lu:%u]",
+ __get_str(name), __entry->prepare_count, __entry->enable_count,
+ __entry->rate, __entry->vdd_level)
+);
+
+DEFINE_EVENT(clk_state_dump, clk_state,
+
+ TP_PROTO(const char *name, unsigned int prepare_count,
+ unsigned int enable_count, unsigned long rate, unsigned int vdd_level),
+
+ TP_ARGS(name, prepare_count, enable_count, rate, vdd_level)
+);
+
#endif /* _TRACE_CLK_H */
/* This part must be outside protection */
diff --git a/include/uapi/asm-generic/ioctls.h b/include/uapi/asm-generic/ioctls.h
index 143dacb..deb98c7 100644
--- a/include/uapi/asm-generic/ioctls.h
+++ b/include/uapi/asm-generic/ioctls.h
@@ -77,6 +77,9 @@
#define TIOCGPKT _IOR('T', 0x38, int) /* Get packet mode state */
#define TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */
#define TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */
+#define TIOCPMGET 0x5441 /* PM get */
+#define TIOCPMPUT 0x5442 /* PM put */
+#define TIOCPMACT 0x5443 /* PM is active */
#define FIONCLEX 0x5450
#define FIOCLEX 0x5451
diff --git a/include/uapi/drm/sde_drm.h b/include/uapi/drm/sde_drm.h
index 74034c6..44b42a6 100644
--- a/include/uapi/drm/sde_drm.h
+++ b/include/uapi/drm/sde_drm.h
@@ -356,4 +356,14 @@
struct drm_clip_rect roi[SDE_MAX_ROI_V1];
};
+/**
+ * Define extended power modes supported by the SDE connectors.
+ */
+#define SDE_MODE_DPMS_ON 0
+#define SDE_MODE_DPMS_LP1 1
+#define SDE_MODE_DPMS_LP2 2
+#define SDE_MODE_DPMS_STANDBY 3
+#define SDE_MODE_DPMS_SUSPEND 4
+#define SDE_MODE_DPMS_OFF 5
+
#endif /* _SDE_DRM_H_ */
diff --git a/include/uapi/linux/ipv6_route.h b/include/uapi/linux/ipv6_route.h
index f6598d1..316e838 100644
--- a/include/uapi/linux/ipv6_route.h
+++ b/include/uapi/linux/ipv6_route.h
@@ -34,7 +34,7 @@
#define RTF_PREF(pref) ((pref) << 27)
#define RTF_PREF_MASK 0x18000000
-#define RTF_PCPU 0x40000000
+#define RTF_PCPU 0x40000000 /* read-only: can not be set by user */
#define RTF_LOCAL 0x80000000
diff --git a/include/uapi/linux/msm_kgsl.h b/include/uapi/linux/msm_kgsl.h
index c190446..f05155b 100644
--- a/include/uapi/linux/msm_kgsl.h
+++ b/include/uapi/linux/msm_kgsl.h
@@ -67,6 +67,8 @@
#define KGSL_CONTEXT_TYPE_RS 4
#define KGSL_CONTEXT_TYPE_UNKNOWN 0x1E
+#define KGSL_CONTEXT_INVALIDATE_ON_FAULT 0x10000000
+
#define KGSL_CONTEXT_INVALID 0xffffffff
/*
diff --git a/include/uapi/media/Kbuild b/include/uapi/media/Kbuild
index 5f375c4..478f7fe 100644
--- a/include/uapi/media/Kbuild
+++ b/include/uapi/media/Kbuild
@@ -1,3 +1,4 @@
+header-y += cam_cpas.h
header-y += cam_defs.h
header-y += cam_isp.h
header-y += cam_isp_vfe.h
diff --git a/include/uapi/media/cam_cpas.h b/include/uapi/media/cam_cpas.h
new file mode 100644
index 0000000..300bd87
--- /dev/null
+++ b/include/uapi/media/cam_cpas.h
@@ -0,0 +1,23 @@
+#ifndef __UAPI_CAM_CPAS_H__
+#define __UAPI_CAM_CPAS_H__
+
+#include "cam_defs.h"
+
+#define CAM_FAMILY_CAMERA_SS 1
+#define CAM_FAMILY_CPAS_SS 2
+
+/**
+ * struct cam_cpas_query_cap - CPAS query device capability payload
+ *
+ * @camera_family : Camera family type
+ * @reserved : Reserved field for alignment
+ * @camera_version : Camera version
+ *
+ */
+struct cam_cpas_query_cap {
+ uint32_t camera_family;
+ uint32_t reserved;
+ struct cam_hw_version camera_version;
+};
+
+#endif /* __UAPI_CAM_CPAS_H__ */
diff --git a/include/uapi/sound/Kbuild b/include/uapi/sound/Kbuild
index b0350f0..27e9ef8 100644
--- a/include/uapi/sound/Kbuild
+++ b/include/uapi/sound/Kbuild
@@ -18,7 +18,6 @@
header-y += audio_slimslave.h
header-y += voice_params.h
header-y += audio_effects.h
-header-y += voice_svc.h
header-y += devdep_params.h
header-y += msmcal-hwdep.h
header-y += wcd-dsp-glink.h
diff --git a/init/Kconfig b/init/Kconfig
index 007186d..2c382dc1 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -795,19 +795,6 @@
endchoice
-config RCU_EXPEDITE_BOOT
- bool
- default n
- help
- This option enables expedited grace periods at boot time,
- as if rcu_expedite_gp() had been invoked early in boot.
- The corresponding rcu_unexpedite_gp() is invoked from
- rcu_end_inkernel_boot(), which is intended to be invoked
- at the end of the kernel-only boot sequence, just before
- init is exec'ed.
-
- Accept the default if unsure.
-
endmenu # "RCU Subsystem"
config BUILD_BIN2C
diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index 85d1c94..7c9f94c 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -1829,14 +1829,15 @@
for (i = 0; i < MAX_BPF_REG; i++)
if (regs[i].type == PTR_TO_PACKET && regs[i].id == dst_reg->id)
- regs[i].range = dst_reg->off;
+ /* keep the maximum range already checked */
+ regs[i].range = max(regs[i].range, dst_reg->off);
for (i = 0; i < MAX_BPF_STACK; i += BPF_REG_SIZE) {
if (state->stack_slot_type[i] != STACK_SPILL)
continue;
reg = &state->spilled_regs[i / BPF_REG_SIZE];
if (reg->type == PTR_TO_PACKET && reg->id == dst_reg->id)
- reg->range = dst_reg->off;
+ reg->range = max(reg->range, dst_reg->off);
}
}
diff --git a/kernel/configs/android-base.config b/kernel/configs/android-base.config
index 30e0107..3c32c74 100644
--- a/kernel/configs/android-base.config
+++ b/kernel/configs/android-base.config
@@ -29,7 +29,6 @@
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_INET6_AH=y
-CONFIG_INET6_DIAG_DESTROY=y
CONFIG_INET6_ESP=y
CONFIG_INET6_IPCOMP=y
CONFIG_INET=y
@@ -72,7 +71,6 @@
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_NETFILTER=y
-CONFIG_NETFILTER_TPROXY=y
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
@@ -173,5 +171,4 @@
CONFIG_USB_CONFIGFS_F_PTP=y
CONFIG_USB_CONFIGFS_UEVENT=y
CONFIG_USB_GADGET=y
-CONFIG_USB_OTG_WAKELOCK=y
CONFIG_XFRM_USER=y
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 1d203e1..21a8764 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -1488,14 +1488,12 @@
/* (Un)Install the callbacks for further cpu hotplug operations */
struct cpuhp_step *sp;
- mutex_lock(&cpuhp_state_mutex);
sp = cpuhp_get_step(state);
sp->startup.single = startup;
sp->teardown.single = teardown;
sp->name = name;
sp->multi_instance = multi_instance;
INIT_HLIST_HEAD(&sp->list);
- mutex_unlock(&cpuhp_state_mutex);
}
static void *cpuhp_get_teardown_cb(enum cpuhp_state state)
@@ -1565,16 +1563,13 @@
{
enum cpuhp_state i;
- mutex_lock(&cpuhp_state_mutex);
for (i = CPUHP_AP_ONLINE_DYN; i <= CPUHP_AP_ONLINE_DYN_END; i++) {
if (cpuhp_ap_states[i].name)
continue;
cpuhp_ap_states[i].name = "Reserved";
- mutex_unlock(&cpuhp_state_mutex);
return i;
}
- mutex_unlock(&cpuhp_state_mutex);
WARN(1, "No more dynamic states available for CPU hotplug\n");
return -ENOSPC;
}
@@ -1591,6 +1586,7 @@
return -EINVAL;
get_online_cpus();
+ mutex_lock(&cpuhp_state_mutex);
if (!invoke || !sp->startup.multi)
goto add_node;
@@ -1615,11 +1611,10 @@
}
add_node:
ret = 0;
- mutex_lock(&cpuhp_state_mutex);
hlist_add_head(node, &sp->list);
- mutex_unlock(&cpuhp_state_mutex);
err:
+ mutex_unlock(&cpuhp_state_mutex);
put_online_cpus();
return ret;
}
@@ -1648,6 +1643,7 @@
return -EINVAL;
get_online_cpus();
+ mutex_lock(&cpuhp_state_mutex);
/* currently assignments for the ONLINE state are possible */
if (state == CPUHP_AP_ONLINE_DYN) {
@@ -1683,6 +1679,8 @@
}
}
out:
+ mutex_unlock(&cpuhp_state_mutex);
+
put_online_cpus();
if (!ret && dyn_state)
return state;
@@ -1702,6 +1700,8 @@
return -EINVAL;
get_online_cpus();
+ mutex_lock(&cpuhp_state_mutex);
+
if (!invoke || !cpuhp_get_teardown_cb(state))
goto remove;
/*
@@ -1718,7 +1718,6 @@
}
remove:
- mutex_lock(&cpuhp_state_mutex);
hlist_del(node);
mutex_unlock(&cpuhp_state_mutex);
put_online_cpus();
@@ -1743,6 +1742,7 @@
BUG_ON(cpuhp_cb_check(state));
get_online_cpus();
+ mutex_lock(&cpuhp_state_mutex);
if (sp->multi_instance) {
WARN(!hlist_empty(&sp->list),
@@ -1768,6 +1768,7 @@
}
remove:
cpuhp_store_callbacks(state, NULL, NULL, NULL, false);
+ mutex_unlock(&cpuhp_state_mutex);
put_online_cpus();
}
EXPORT_SYMBOL(__cpuhp_remove_state);
diff --git a/kernel/rcu/update.c b/kernel/rcu/update.c
index 4f6db7e..9e03db9 100644
--- a/kernel/rcu/update.c
+++ b/kernel/rcu/update.c
@@ -132,8 +132,7 @@
}
EXPORT_SYMBOL_GPL(rcu_gp_is_normal);
-static atomic_t rcu_expedited_nesting =
- ATOMIC_INIT(IS_ENABLED(CONFIG_RCU_EXPEDITE_BOOT) ? 1 : 0);
+static atomic_t rcu_expedited_nesting = ATOMIC_INIT(1);
/*
* Should normal grace-period primitives be expedited? Intended for
@@ -182,8 +181,7 @@
*/
void rcu_end_inkernel_boot(void)
{
- if (IS_ENABLED(CONFIG_RCU_EXPEDITE_BOOT))
- rcu_unexpedite_gp();
+ rcu_unexpedite_gp();
if (rcu_normal_after_boot)
WRITE_ONCE(rcu_normal, 1);
}
diff --git a/net/9p/client.c b/net/9p/client.c
index 3fc94a4..cf129fe 100644
--- a/net/9p/client.c
+++ b/net/9p/client.c
@@ -2101,6 +2101,10 @@
trace_9p_protocol_dump(clnt, req->rc);
goto free_and_error;
}
+ if (rsize < count) {
+ pr_err("bogus RREADDIR count (%d > %d)\n", count, rsize);
+ count = rsize;
+ }
p9_debug(P9_DEBUG_9P, "<<< RREADDIR count %d\n", count);
diff --git a/net/core/neighbour.c b/net/core/neighbour.c
index 9901e5b..f45f619 100644
--- a/net/core/neighbour.c
+++ b/net/core/neighbour.c
@@ -859,7 +859,8 @@
if (skb)
skb = skb_clone(skb, GFP_ATOMIC);
write_unlock(&neigh->lock);
- neigh->ops->solicit(neigh, skb);
+ if (neigh->ops->solicit)
+ neigh->ops->solicit(neigh, skb);
atomic_inc(&neigh->probes);
kfree_skb(skb);
}
diff --git a/net/core/netpoll.c b/net/core/netpoll.c
index 53599bd..457f882 100644
--- a/net/core/netpoll.c
+++ b/net/core/netpoll.c
@@ -105,15 +105,21 @@
while ((skb = skb_dequeue(&npinfo->txq))) {
struct net_device *dev = skb->dev;
struct netdev_queue *txq;
+ unsigned int q_index;
if (!netif_device_present(dev) || !netif_running(dev)) {
kfree_skb(skb);
continue;
}
- txq = skb_get_tx_queue(dev, skb);
-
local_irq_save(flags);
+ /* check if skb->queue_mapping is still valid */
+ q_index = skb_get_queue_mapping(skb);
+ if (unlikely(q_index >= dev->real_num_tx_queues)) {
+ q_index = q_index % dev->real_num_tx_queues;
+ skb_set_queue_mapping(skb, q_index);
+ }
+ txq = netdev_get_tx_queue(dev, q_index);
HARD_TX_LOCK(dev, txq, smp_processor_id());
if (netif_xmit_frozen_or_stopped(txq) ||
netpoll_start_xmit(skb, dev, txq) != NETDEV_TX_OK) {
diff --git a/net/core/skbuff.c b/net/core/skbuff.c
index 8de6707..ba1146c 100644
--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
@@ -3082,22 +3082,32 @@
if (sg && csum && (mss != GSO_BY_FRAGS)) {
if (!(features & NETIF_F_GSO_PARTIAL)) {
struct sk_buff *iter;
+ unsigned int frag_len;
if (!list_skb ||
!net_gso_ok(features, skb_shinfo(head_skb)->gso_type))
goto normal;
- /* Split the buffer at the frag_list pointer.
- * This is based on the assumption that all
- * buffers in the chain excluding the last
- * containing the same amount of data.
+ /* If we get here then all the required
+ * GSO features except frag_list are supported.
+ * Try to split the SKB to multiple GSO SKBs
+ * with no frag_list.
+ * Currently we can do that only when the buffers don't
+ * have a linear part and all the buffers except
+ * the last are of the same length.
*/
+ frag_len = list_skb->len;
skb_walk_frags(head_skb, iter) {
+ if (frag_len != iter->len && iter->next)
+ goto normal;
if (skb_headlen(iter))
goto normal;
len -= iter->len;
}
+
+ if (len != frag_len)
+ goto normal;
}
/* GSO partial only requires that we trim off any excess that
@@ -3785,6 +3795,7 @@
serr->ee.ee_errno = ENOMSG;
serr->ee.ee_origin = SO_EE_ORIGIN_TIMESTAMPING;
serr->ee.ee_info = tstype;
+ serr->header.h4.iif = skb->dev ? skb->dev->ifindex : 0;
if (sk->sk_tsflags & SOF_TIMESTAMPING_OPT_ID) {
serr->ee.ee_data = skb_shinfo(skb)->tskey;
if (sk->sk_protocol == IPPROTO_TCP &&
diff --git a/net/ipv4/ip_sockglue.c b/net/ipv4/ip_sockglue.c
index 9826695..4d37bdc 100644
--- a/net/ipv4/ip_sockglue.c
+++ b/net/ipv4/ip_sockglue.c
@@ -474,16 +474,15 @@
return false;
/* Support IP_PKTINFO on tstamp packets if requested, to correlate
- * timestamp with egress dev. Not possible for packets without dev
+ * timestamp with egress dev. Not possible for packets without iif
* or without payload (SOF_TIMESTAMPING_OPT_TSONLY).
*/
- if ((!(sk->sk_tsflags & SOF_TIMESTAMPING_OPT_CMSG)) ||
- (!skb->dev))
+ info = PKTINFO_SKB_CB(skb);
+ if (!(sk->sk_tsflags & SOF_TIMESTAMPING_OPT_CMSG) ||
+ !info->ipi_ifindex)
return false;
- info = PKTINFO_SKB_CB(skb);
info->ipi_spec_dst.s_addr = ip_hdr(skb)->saddr;
- info->ipi_ifindex = skb->dev->ifindex;
return true;
}
diff --git a/net/ipv4/ping.c b/net/ipv4/ping.c
index 06879e6..93bfadf 100644
--- a/net/ipv4/ping.c
+++ b/net/ipv4/ping.c
@@ -156,17 +156,18 @@
void ping_unhash(struct sock *sk)
{
struct inet_sock *isk = inet_sk(sk);
+
pr_debug("ping_unhash(isk=%p,isk->num=%u)\n", isk, isk->inet_num);
+ write_lock_bh(&ping_table.lock);
if (sk_hashed(sk)) {
- write_lock_bh(&ping_table.lock);
hlist_nulls_del(&sk->sk_nulls_node);
sk_nulls_node_init(&sk->sk_nulls_node);
sock_put(sk);
isk->inet_num = 0;
isk->inet_sport = 0;
sock_prot_inuse_add(sock_net(sk), sk->sk_prot, -1);
- write_unlock_bh(&ping_table.lock);
}
+ write_unlock_bh(&ping_table.lock);
}
EXPORT_SYMBOL_GPL(ping_unhash);
diff --git a/net/ipv4/route.c b/net/ipv4/route.c
index e6acef5..70c40ba2 100644
--- a/net/ipv4/route.c
+++ b/net/ipv4/route.c
@@ -2581,7 +2581,7 @@
skb_reset_network_header(skb);
/* Bugfix: need to give ip_route_input enough of an IP header to not gag. */
- ip_hdr(skb)->protocol = IPPROTO_ICMP;
+ ip_hdr(skb)->protocol = IPPROTO_UDP;
skb_reserve(skb, MAX_HEADER + sizeof(struct iphdr));
src = tb[RTA_SRC] ? nla_get_in_addr(tb[RTA_SRC]) : 0;
diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
index 6a90a0e..eb142ca 100644
--- a/net/ipv4/tcp.c
+++ b/net/ipv4/tcp.c
@@ -2297,6 +2297,7 @@
tcp_init_send_head(sk);
memset(&tp->rx_opt, 0, sizeof(tp->rx_opt));
__sk_dst_reset(sk);
+ tcp_saved_syn_free(tp);
WARN_ON(inet->inet_num && !icsk->icsk_bind_hash);
diff --git a/net/ipv4/tcp_cong.c b/net/ipv4/tcp_cong.c
index f9038d6b..baea5df 100644
--- a/net/ipv4/tcp_cong.c
+++ b/net/ipv4/tcp_cong.c
@@ -167,12 +167,8 @@
}
out:
rcu_read_unlock();
+ memset(icsk->icsk_ca_priv, 0, sizeof(icsk->icsk_ca_priv));
- /* Clear out private data before diag gets it and
- * the ca has not been initialized.
- */
- if (ca->get_info)
- memset(icsk->icsk_ca_priv, 0, sizeof(icsk->icsk_ca_priv));
if (ca->flags & TCP_CONG_NEEDS_ECN)
INET_ECN_xmit(sk);
else
@@ -199,11 +195,10 @@
tcp_cleanup_congestion_control(sk);
icsk->icsk_ca_ops = ca;
icsk->icsk_ca_setsockopt = 1;
+ memset(icsk->icsk_ca_priv, 0, sizeof(icsk->icsk_ca_priv));
- if (sk->sk_state != TCP_CLOSE) {
- memset(icsk->icsk_ca_priv, 0, sizeof(icsk->icsk_ca_priv));
+ if (sk->sk_state != TCP_CLOSE)
tcp_init_congestion_control(sk);
- }
}
/* Manage refcounts on socket close. */
diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c
index 7588fa9..553138d 100644
--- a/net/ipv6/addrconf.c
+++ b/net/ipv6/addrconf.c
@@ -3293,14 +3293,24 @@
static int fixup_permanent_addr(struct inet6_dev *idev,
struct inet6_ifaddr *ifp)
{
- if (!ifp->rt) {
- struct rt6_info *rt;
+ /* rt6i_ref == 0 means the host route was removed from the
+ * FIB, for example, if 'lo' device is taken down. In that
+ * case regenerate the host route.
+ */
+ if (!ifp->rt || !atomic_read(&ifp->rt->rt6i_ref)) {
+ struct rt6_info *rt, *prev;
rt = addrconf_dst_alloc(idev, &ifp->addr, false);
if (unlikely(IS_ERR(rt)))
return PTR_ERR(rt);
+ /* ifp->rt can be accessed outside of rtnl */
+ spin_lock(&ifp->lock);
+ prev = ifp->rt;
ifp->rt = rt;
+ spin_unlock(&ifp->lock);
+
+ ip6_rt_put(prev);
}
if (!(ifp->flags & IFA_F_NOPREFIXROUTE)) {
@@ -3642,14 +3652,19 @@
INIT_LIST_HEAD(&del_list);
list_for_each_entry_safe(ifa, tmp, &idev->addr_list, if_list) {
struct rt6_info *rt = NULL;
+ bool keep;
addrconf_del_dad_work(ifa);
+ keep = keep_addr && (ifa->flags & IFA_F_PERMANENT) &&
+ !addr_is_local(&ifa->addr);
+ if (!keep)
+ list_move(&ifa->if_list, &del_list);
+
write_unlock_bh(&idev->lock);
spin_lock_bh(&ifa->lock);
- if (keep_addr && (ifa->flags & IFA_F_PERMANENT) &&
- !addr_is_local(&ifa->addr)) {
+ if (keep) {
/* set state to skip the notifier below */
state = INET6_IFADDR_STATE_DEAD;
ifa->state = 0;
@@ -3661,8 +3676,6 @@
} else {
state = ifa->state;
ifa->state = INET6_IFADDR_STATE_DEAD;
-
- list_move(&ifa->if_list, &del_list);
}
spin_unlock_bh(&ifa->lock);
diff --git a/net/ipv6/datagram.c b/net/ipv6/datagram.c
index 1529833..a381772 100644
--- a/net/ipv6/datagram.c
+++ b/net/ipv6/datagram.c
@@ -401,9 +401,6 @@
* At one point, excluding local errors was a quick test to identify icmp/icmp6
* errors. This is no longer true, but the test remained, so the v6 stack,
* unlike v4, also honors cmsg requests on all wifi and timestamp errors.
- *
- * Timestamp code paths do not initialize the fields expected by cmsg:
- * the PKTINFO fields in skb->cb[]. Fill those in here.
*/
static bool ip6_datagram_support_cmsg(struct sk_buff *skb,
struct sock_exterr_skb *serr)
@@ -415,14 +412,9 @@
if (serr->ee.ee_origin == SO_EE_ORIGIN_LOCAL)
return false;
- if (!skb->dev)
+ if (!IP6CB(skb)->iif)
return false;
- if (skb->protocol == htons(ETH_P_IPV6))
- IP6CB(skb)->iif = skb->dev->ifindex;
- else
- PKTINFO_SKB_CB(skb)->ipi_ifindex = skb->dev->ifindex;
-
return true;
}
diff --git a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c
index 885b411..97e89a2 100644
--- a/net/ipv6/ip6_tunnel.c
+++ b/net/ipv6/ip6_tunnel.c
@@ -1037,7 +1037,7 @@
struct ip6_tnl *t = netdev_priv(dev);
struct net *net = t->net;
struct net_device_stats *stats = &t->dev->stats;
- struct ipv6hdr *ipv6h = ipv6_hdr(skb);
+ struct ipv6hdr *ipv6h;
struct ipv6_tel_txoption opt;
struct dst_entry *dst = NULL, *ndst = NULL;
struct net_device *tdev;
@@ -1057,26 +1057,28 @@
/* NBMA tunnel */
if (ipv6_addr_any(&t->parms.raddr)) {
- struct in6_addr *addr6;
- struct neighbour *neigh;
- int addr_type;
+ if (skb->protocol == htons(ETH_P_IPV6)) {
+ struct in6_addr *addr6;
+ struct neighbour *neigh;
+ int addr_type;
- if (!skb_dst(skb))
- goto tx_err_link_failure;
+ if (!skb_dst(skb))
+ goto tx_err_link_failure;
- neigh = dst_neigh_lookup(skb_dst(skb),
- &ipv6_hdr(skb)->daddr);
- if (!neigh)
- goto tx_err_link_failure;
+ neigh = dst_neigh_lookup(skb_dst(skb),
+ &ipv6_hdr(skb)->daddr);
+ if (!neigh)
+ goto tx_err_link_failure;
- addr6 = (struct in6_addr *)&neigh->primary_key;
- addr_type = ipv6_addr_type(addr6);
+ addr6 = (struct in6_addr *)&neigh->primary_key;
+ addr_type = ipv6_addr_type(addr6);
- if (addr_type == IPV6_ADDR_ANY)
- addr6 = &ipv6_hdr(skb)->daddr;
+ if (addr_type == IPV6_ADDR_ANY)
+ addr6 = &ipv6_hdr(skb)->daddr;
- memcpy(&fl6->daddr, addr6, sizeof(fl6->daddr));
- neigh_release(neigh);
+ memcpy(&fl6->daddr, addr6, sizeof(fl6->daddr));
+ neigh_release(neigh);
+ }
} else if (!(t->parms.flags &
(IP6_TNL_F_USE_ORIG_TCLASS | IP6_TNL_F_USE_ORIG_FWMARK))) {
/* enable the cache only only if the routing decision does
diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c
index 7f4265b..117405d 100644
--- a/net/ipv6/ip6mr.c
+++ b/net/ipv6/ip6mr.c
@@ -774,7 +774,8 @@
* Delete a VIF entry
*/
-static int mif6_delete(struct mr6_table *mrt, int vifi, struct list_head *head)
+static int mif6_delete(struct mr6_table *mrt, int vifi, int notify,
+ struct list_head *head)
{
struct mif_device *v;
struct net_device *dev;
@@ -820,7 +821,7 @@
dev->ifindex, &in6_dev->cnf);
}
- if (v->flags & MIFF_REGISTER)
+ if ((v->flags & MIFF_REGISTER) && !notify)
unregister_netdevice_queue(dev, head);
dev_put(dev);
@@ -1331,7 +1332,6 @@
struct mr6_table *mrt;
struct mif_device *v;
int ct;
- LIST_HEAD(list);
if (event != NETDEV_UNREGISTER)
return NOTIFY_DONE;
@@ -1340,10 +1340,9 @@
v = &mrt->vif6_table[0];
for (ct = 0; ct < mrt->maxvif; ct++, v++) {
if (v->dev == dev)
- mif6_delete(mrt, ct, &list);
+ mif6_delete(mrt, ct, 1, NULL);
}
}
- unregister_netdevice_many(&list);
return NOTIFY_DONE;
}
@@ -1552,7 +1551,7 @@
for (i = 0; i < mrt->maxvif; i++) {
if (!all && (mrt->vif6_table[i].flags & VIFF_STATIC))
continue;
- mif6_delete(mrt, i, &list);
+ mif6_delete(mrt, i, 0, &list);
}
unregister_netdevice_many(&list);
@@ -1706,7 +1705,7 @@
if (copy_from_user(&mifi, optval, sizeof(mifi_t)))
return -EFAULT;
rtnl_lock();
- ret = mif6_delete(mrt, mifi, NULL);
+ ret = mif6_delete(mrt, mifi, 0, NULL);
rtnl_unlock();
return ret;
diff --git a/net/ipv6/raw.c b/net/ipv6/raw.c
index 5665375..1a34da0 100644
--- a/net/ipv6/raw.c
+++ b/net/ipv6/raw.c
@@ -1172,8 +1172,7 @@
spin_lock_bh(&sk->sk_receive_queue.lock);
skb = skb_peek(&sk->sk_receive_queue);
if (skb)
- amount = skb_tail_pointer(skb) -
- skb_transport_header(skb);
+ amount = skb->len;
spin_unlock_bh(&sk->sk_receive_queue.lock);
return put_user(amount, (int __user *)arg);
}
diff --git a/net/ipv6/route.c b/net/ipv6/route.c
index 73527d8..7d17670 100644
--- a/net/ipv6/route.c
+++ b/net/ipv6/route.c
@@ -1825,6 +1825,10 @@
int addr_type;
int err = -EINVAL;
+ /* RTF_PCPU is an internal flag; can not be set by userspace */
+ if (cfg->fc_flags & RTF_PCPU)
+ goto out;
+
if (cfg->fc_dst_len > 128 || cfg->fc_src_len > 128)
goto out;
#ifndef CONFIG_IPV6_SUBTREES
diff --git a/net/kcm/kcmsock.c b/net/kcm/kcmsock.c
index a646f34..fecad10 100644
--- a/net/kcm/kcmsock.c
+++ b/net/kcm/kcmsock.c
@@ -1685,7 +1685,7 @@
struct kcm_attach info;
if (copy_from_user(&info, (void __user *)arg, sizeof(info)))
- err = -EFAULT;
+ return -EFAULT;
err = kcm_attach_ioctl(sock, &info);
@@ -1695,7 +1695,7 @@
struct kcm_unattach info;
if (copy_from_user(&info, (void __user *)arg, sizeof(info)))
- err = -EFAULT;
+ return -EFAULT;
err = kcm_unattach_ioctl(sock, &info);
@@ -1706,7 +1706,7 @@
struct socket *newsock = NULL;
if (copy_from_user(&info, (void __user *)arg, sizeof(info)))
- err = -EFAULT;
+ return -EFAULT;
err = kcm_clone(sock, &info, &newsock);
diff --git a/net/l2tp/l2tp_core.c b/net/l2tp/l2tp_core.c
index a2ed3bd..e702cb95 100644
--- a/net/l2tp/l2tp_core.c
+++ b/net/l2tp/l2tp_core.c
@@ -278,7 +278,8 @@
}
EXPORT_SYMBOL_GPL(l2tp_session_find);
-struct l2tp_session *l2tp_session_find_nth(struct l2tp_tunnel *tunnel, int nth)
+struct l2tp_session *l2tp_session_get_nth(struct l2tp_tunnel *tunnel, int nth,
+ bool do_ref)
{
int hash;
struct l2tp_session *session;
@@ -288,6 +289,9 @@
for (hash = 0; hash < L2TP_HASH_SIZE; hash++) {
hlist_for_each_entry(session, &tunnel->session_hlist[hash], hlist) {
if (++count > nth) {
+ l2tp_session_inc_refcount(session);
+ if (do_ref && session->ref)
+ session->ref(session);
read_unlock_bh(&tunnel->hlist_lock);
return session;
}
@@ -298,7 +302,7 @@
return NULL;
}
-EXPORT_SYMBOL_GPL(l2tp_session_find_nth);
+EXPORT_SYMBOL_GPL(l2tp_session_get_nth);
/* Lookup a session by interface name.
* This is very inefficient but is only used by management interfaces.
diff --git a/net/l2tp/l2tp_core.h b/net/l2tp/l2tp_core.h
index 181e755c..e7233ba 100644
--- a/net/l2tp/l2tp_core.h
+++ b/net/l2tp/l2tp_core.h
@@ -243,7 +243,8 @@
struct l2tp_session *l2tp_session_find(struct net *net,
struct l2tp_tunnel *tunnel,
u32 session_id);
-struct l2tp_session *l2tp_session_find_nth(struct l2tp_tunnel *tunnel, int nth);
+struct l2tp_session *l2tp_session_get_nth(struct l2tp_tunnel *tunnel, int nth,
+ bool do_ref);
struct l2tp_session *l2tp_session_find_by_ifname(struct net *net, char *ifname);
struct l2tp_tunnel *l2tp_tunnel_find(struct net *net, u32 tunnel_id);
struct l2tp_tunnel *l2tp_tunnel_find_nth(struct net *net, int nth);
diff --git a/net/l2tp/l2tp_debugfs.c b/net/l2tp/l2tp_debugfs.c
index 2d6760a..d100aed 100644
--- a/net/l2tp/l2tp_debugfs.c
+++ b/net/l2tp/l2tp_debugfs.c
@@ -53,7 +53,7 @@
static void l2tp_dfs_next_session(struct l2tp_dfs_seq_data *pd)
{
- pd->session = l2tp_session_find_nth(pd->tunnel, pd->session_idx);
+ pd->session = l2tp_session_get_nth(pd->tunnel, pd->session_idx, true);
pd->session_idx++;
if (pd->session == NULL) {
@@ -238,10 +238,14 @@
}
/* Show the tunnel or session context */
- if (pd->session == NULL)
+ if (!pd->session) {
l2tp_dfs_seq_tunnel_show(m, pd->tunnel);
- else
+ } else {
l2tp_dfs_seq_session_show(m, pd->session);
+ if (pd->session->deref)
+ pd->session->deref(pd->session);
+ l2tp_session_dec_refcount(pd->session);
+ }
out:
return 0;
diff --git a/net/l2tp/l2tp_ip.c b/net/l2tp/l2tp_ip.c
index ff750bb..2066953 100644
--- a/net/l2tp/l2tp_ip.c
+++ b/net/l2tp/l2tp_ip.c
@@ -178,9 +178,10 @@
tunnel_id = ntohl(*(__be32 *) &skb->data[4]);
tunnel = l2tp_tunnel_find(net, tunnel_id);
- if (tunnel != NULL)
+ if (tunnel) {
sk = tunnel->sock;
- else {
+ sock_hold(sk);
+ } else {
struct iphdr *iph = (struct iphdr *) skb_network_header(skb);
read_lock_bh(&l2tp_ip_lock);
diff --git a/net/l2tp/l2tp_ip6.c b/net/l2tp/l2tp_ip6.c
index 7095786..26cf4dc 100644
--- a/net/l2tp/l2tp_ip6.c
+++ b/net/l2tp/l2tp_ip6.c
@@ -191,9 +191,10 @@
tunnel_id = ntohl(*(__be32 *) &skb->data[4]);
tunnel = l2tp_tunnel_find(net, tunnel_id);
- if (tunnel != NULL)
+ if (tunnel) {
sk = tunnel->sock;
- else {
+ sock_hold(sk);
+ } else {
struct ipv6hdr *iph = ipv6_hdr(skb);
read_lock_bh(&l2tp_ip6_lock);
diff --git a/net/l2tp/l2tp_netlink.c b/net/l2tp/l2tp_netlink.c
index bf31177..9f66272 100644
--- a/net/l2tp/l2tp_netlink.c
+++ b/net/l2tp/l2tp_netlink.c
@@ -844,7 +844,7 @@
goto out;
}
- session = l2tp_session_find_nth(tunnel, si);
+ session = l2tp_session_get_nth(tunnel, si, false);
if (session == NULL) {
ti++;
tunnel = NULL;
@@ -854,8 +854,11 @@
if (l2tp_nl_session_send(skb, NETLINK_CB(cb->skb).portid,
cb->nlh->nlmsg_seq, NLM_F_MULTI,
- session, L2TP_CMD_SESSION_GET) < 0)
+ session, L2TP_CMD_SESSION_GET) < 0) {
+ l2tp_session_dec_refcount(session);
break;
+ }
+ l2tp_session_dec_refcount(session);
si++;
}
diff --git a/net/l2tp/l2tp_ppp.c b/net/l2tp/l2tp_ppp.c
index 41d47bf..1387f54 100644
--- a/net/l2tp/l2tp_ppp.c
+++ b/net/l2tp/l2tp_ppp.c
@@ -450,6 +450,10 @@
static void pppol2tp_session_destruct(struct sock *sk)
{
struct l2tp_session *session = sk->sk_user_data;
+
+ skb_queue_purge(&sk->sk_receive_queue);
+ skb_queue_purge(&sk->sk_write_queue);
+
if (session) {
sk->sk_user_data = NULL;
BUG_ON(session->magic != L2TP_SESSION_MAGIC);
@@ -488,9 +492,6 @@
l2tp_session_queue_purge(session);
sock_put(sk);
}
- skb_queue_purge(&sk->sk_receive_queue);
- skb_queue_purge(&sk->sk_write_queue);
-
release_sock(sk);
/* This will delete the session context via
@@ -1554,7 +1555,7 @@
static void pppol2tp_next_session(struct net *net, struct pppol2tp_seq_data *pd)
{
- pd->session = l2tp_session_find_nth(pd->tunnel, pd->session_idx);
+ pd->session = l2tp_session_get_nth(pd->tunnel, pd->session_idx, true);
pd->session_idx++;
if (pd->session == NULL) {
@@ -1681,10 +1682,14 @@
/* Show the tunnel or session context.
*/
- if (pd->session == NULL)
+ if (!pd->session) {
pppol2tp_seq_tunnel_show(m, pd->tunnel);
- else
+ } else {
pppol2tp_seq_session_show(m, pd->session);
+ if (pd->session->deref)
+ pd->session->deref(pd->session);
+ l2tp_session_dec_refcount(pd->session);
+ }
out:
return 0;
@@ -1843,4 +1848,4 @@
MODULE_LICENSE("GPL");
MODULE_VERSION(PPPOL2TP_DRV_VERSION);
MODULE_ALIAS_NET_PF_PROTO(PF_PPPOX, PX_PROTO_OL2TP);
-MODULE_ALIAS_L2TP_PWTYPE(11);
+MODULE_ALIAS_L2TP_PWTYPE(7);
diff --git a/net/netfilter/xt_qtaguid.c b/net/netfilter/xt_qtaguid.c
index 0f5628a..3c7ae04 100644
--- a/net/netfilter/xt_qtaguid.c
+++ b/net/netfilter/xt_qtaguid.c
@@ -969,9 +969,8 @@
for (ifa = in_dev->ifa_list; ifa; ifa = ifa->ifa_next) {
IF_DEBUG("qtaguid: iface_stat: create(%s): "
"ifa=%p ifa_label=%s\n",
- ifname, ifa,
- ifa->ifa_label ? ifa->ifa_label : "(null)");
- if (ifa->ifa_label && !strcmp(ifname, ifa->ifa_label))
+ ifname, ifa, ifa->ifa_label);
+ if (!strcmp(ifname, ifa->ifa_label))
break;
}
}
@@ -1209,10 +1208,6 @@
pr_err_ratelimited("qtaguid[%d]: %s(): no par->in/out?!!\n",
par->hooknum, __func__);
BUG();
- } else if (unlikely(!el_dev->name)) {
- pr_err_ratelimited("qtaguid[%d]: %s(): no dev->name?!!\n",
- par->hooknum, __func__);
- BUG();
} else {
proto = ipx_proto(skb, par);
MT_DEBUG("qtaguid[%d]: dev name=%s type=%d fam=%d proto=%d\n",
@@ -1637,8 +1632,6 @@
if (unlikely(!el_dev)) {
pr_info("qtaguid[%d]: no par->in/out?!!\n", par->hooknum);
- } else if (unlikely(!el_dev->name)) {
- pr_info("qtaguid[%d]: no dev->name?!!\n", par->hooknum);
} else {
int proto = ipx_proto(skb, par);
MT_DEBUG("qtaguid[%d]: dev name=%s type=%d fam=%d proto=%d\n",
diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
index 8ab0974..cb76ff3 100644
--- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c
@@ -3702,6 +3702,8 @@
return -EBUSY;
if (copy_from_user(&val, optval, sizeof(val)))
return -EFAULT;
+ if (val > INT_MAX)
+ return -EINVAL;
po->tp_reserve = val;
return 0;
}
@@ -4247,6 +4249,8 @@
rb->frames_per_block = req->tp_block_size / req->tp_frame_size;
if (unlikely(rb->frames_per_block == 0))
goto out;
+ if (unlikely(req->tp_block_size > UINT_MAX / req->tp_block_nr))
+ goto out;
if (unlikely((rb->frames_per_block * req->tp_block_nr) !=
req->tp_frame_nr))
goto out;
diff --git a/net/sctp/socket.c b/net/sctp/socket.c
index 6734420..14346dc 100644
--- a/net/sctp/socket.c
+++ b/net/sctp/socket.c
@@ -6861,6 +6861,9 @@
if (sock->state != SS_UNCONNECTED)
goto out;
+ if (!sctp_sstate(sk, LISTENING) && !sctp_sstate(sk, CLOSED))
+ goto out;
+
/* If backlog is zero, disable listening. */
if (!backlog) {
if (sctp_sstate(sk, CLOSED))
diff --git a/net/wireless/db.txt b/net/wireless/db.txt
index 449e4a3..c3f8005 100644
--- a/net/wireless/db.txt
+++ b/net/wireless/db.txt
@@ -58,6 +58,8 @@
(5490 - 5590 @ 80), (36)
(5650 - 5730 @ 80), (36)
(5735 - 5835 @ 80), (36)
+ # 60 gHz band channels 1-3
+ (57240 - 63720 @ 2160), (40), NO-OUTDOOR
country AS: DFS-FCC
(2402 - 2472 @ 40), (30)
@@ -91,6 +93,9 @@
(5650 - 5730 @ 80), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-4
+ (57240 - 65880 @ 2160), (43), NO-OUTDOOR
+
country AW: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
@@ -107,8 +112,6 @@
(5170 - 5250 @ 80), (23), AUTO-BW
(5250 - 5330 @ 80), (23), DFS, AUTO-BW
(5490 - 5710 @ 160), (30), DFS
- # 60 gHz band channels 1-4, ref: Etsi En 302 567
- (57240 - 65880 @ 2160), (40), NO-OUTDOOR
country BB: DFS-FCC
(2402 - 2482 @ 40), (20)
@@ -135,7 +138,7 @@
(5900 - 5920 @ 10), (30)
(5910 - 5930 @ 10), (30)
# 60 gHz band channels 1-4, ref: Etsi En 302 567
- (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+ (57240 - 65880 @ 2160), (40)
country BF: DFS-FCC
(2402 - 2482 @ 40), (20)
@@ -190,6 +193,9 @@
(5250 - 5330 @ 80), (30), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-3, FCC
+ (57240 - 63720 @ 2160), (40)
+
country BR: DFS-FCC
(2402 - 2482 @ 40), (30)
(5170 - 5250 @ 80), (24), AUTO-BW
@@ -197,6 +203,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-3
+ (57240 - 63720 @ 2160), (40)
+
country BS: DFS-FCC
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (24), AUTO-BW
@@ -230,6 +239,9 @@
(5650 - 5730 @ 80), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-3
+ (57240 - 63720 @ 2160), (40)
+
country CF: DFS-FCC
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 40), (24)
@@ -252,6 +264,9 @@
(5900 - 5920 @ 10), (30)
(5910 - 5930 @ 10), (30)
+ # 60 gHz band channels 1-4, ref: Etsi En 302 567
+ (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+
country CI: DFS-FCC
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (24), AUTO-BW
@@ -264,16 +279,16 @@
(5170 - 5330 @ 160), (20)
(5735 - 5835 @ 80), (20)
+ # 60 gHz band channels 1-3
+ (57240 - 63720 @ 2160), (50), NO-OUTDOOR
+
country CN: DFS-FCC
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
(5250 - 5330 @ 80), (23), DFS, AUTO-BW
(5735 - 5835 @ 80), (33)
- # 60 gHz band channels 1,4: 28dBm, channels 2,3: 44dBm
- # ref: http://www.miit.gov.cn/n11293472/n11505629/n11506593/n11960250/n11960606/n11960700/n12330791.files/n12330790.pdf
- (57240 - 59400 @ 2160), (28)
+ # 60 gHz band channels 2,3: 44dBm
(59400 - 63720 @ 2160), (44)
- (63720 - 65880 @ 2160), (28)
country CO: DFS-FCC
(2402 - 2482 @ 40), (20)
@@ -289,6 +304,9 @@
(5490 - 5730 @ 20), (24), DFS
(5735 - 5835 @ 20), (30)
+ # 60 gHz band channels 1-3
+ (57240 - 63720 @ 2160), (30)
+
country CX: DFS-FCC
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (24), AUTO-BW
@@ -397,6 +415,9 @@
(5490 - 5730 @ 20), (24), DFS
(5735 - 5835 @ 20), (30)
+ # 60 gHz band channels 1-3, FCC
+ (57240 - 63720 @ 2160), (40)
+
country EE: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
@@ -511,8 +532,6 @@
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (18), AUTO-BW
(5250 - 5330 @ 80), (18), DFS, AUTO-BW
- # 60 gHz band channels 1-4, ref: Etsi En 302 567
- (57240 - 65880 @ 2160), (40), NO-OUTDOOR
country GF: DFS-ETSI
(2402 - 2482 @ 40), (20)
@@ -569,6 +588,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-3, FCC
+ (57240 - 63720 @ 2160), (40)
+
country GY:
(2402 - 2482 @ 40), (30)
(5735 - 5835 @ 80), (30)
@@ -580,12 +602,18 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-4, ref: FCC/EU
+ (57240 - 65880 @ 2160), (40)
+
country HN:
(2402 - 2482 @ 40), (20)
(5170 - 5330 @ 160), (24)
(5490 - 5730 @ 160), (24)
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-3, FCC
+ (57240 - 63720 @ 2160), (40)
+
country HR: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
@@ -637,7 +665,6 @@
(5170 - 5250 @ 80), (23), AUTO-BW
(5250 - 5330 @ 80), (23), DFS, AUTO-BW
(5490 - 5710 @ 160), (30), DFS
- # 60 gHz band channels 1-4, ref: Etsi En 302 567
# 5.9ghz band
# reference: http://www.etsi.org/deliver/etsi_en/302500_302599/302571/01.02.00_20/en_302571v010200a.pdf
(5850 - 5870 @ 10), (30)
@@ -647,7 +674,7 @@
(5890 - 5910 @ 10), (30)
(5900 - 5920 @ 10), (30)
(5910 - 5930 @ 10), (30)
- # 60 gHz band channels 1-4, ref: Etsi En 302 567
+ # 60 gHz band channels 1-4, ref: Etsi En 302 567
(57240 - 65880 @ 2160), (40), NO-OUTDOOR
country IL: DFS-ETSI
@@ -655,6 +682,9 @@
(5170 - 5250 @ 80), (23), AUTO-BW
(5250 - 5330 @ 80), (23), DFS, AUTO-BW
+ # 60 gHz band channels 1-4, base on Etsi En 302 567
+ (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+
country IN:
(2402 - 2482 @ 40), (20)
(5170 - 5330 @ 160), (23)
@@ -705,20 +735,25 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-3, FCC
+ (57240 - 63720 @ 2160), (40)
+
country JO:
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23)
(5735 - 5835 @ 80), (23)
+ # 60 gHz band channels 1-4, ref: Etsi En 302 567
+ (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+
country JP: DFS-JP
(2402 - 2482 @ 40), (20)
(2474 - 2494 @ 20), (20), NO-OFDM
(5170 - 5250 @ 80), (20), AUTO-BW, NO-OUTDOOR
(5250 - 5330 @ 80), (20), DFS, AUTO-BW, NO-OUTDOOR
(5490 - 5710 @ 160), (20), DFS
- # 60 GHz band channels 2-4 at 10mW,
- # ref: http://www.arib.or.jp/english/html/overview/doc/1-STD-T74v1_1.pdf
- (59000 - 66000 @ 2160), (10 mW)
+ # 60 gHz band channels 1-4
+ (57240 - 65880 @ 2160), (40)
country KE: DFS-ETSI
(2402 - 2482 @ 40), (20)
@@ -747,7 +782,7 @@
(5735 - 5835 @ 80), (30)
# 60 GHz band channels 1-4,
# ref: http://www.law.go.kr/%ED%96%89%EC%A0%95%EA%B7%9C%EC%B9%99/%EB%AC%B4%EC%84%A0%EC%84%A4%EB%B9%84%EA%B7%9C%EC%B9%99
- (57000 - 66000 @ 2160), (43)
+ (57240 - 65880 @ 2160), (43)
country KP: DFS-ETSI
(2402 - 2482 @ 40), (20)
@@ -800,6 +835,9 @@
(5900 - 5920 @ 10), (30)
(5910 - 5930 @ 10), (30)
+ # 60 gHz band channels 1-4, ref: Etsi En 302 567
+ (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+
country LK: DFS-FCC
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 20), (24)
@@ -861,6 +899,7 @@
(5890 - 5910 @ 10), (30)
(5900 - 5920 @ 10), (30)
(5910 - 5930 @ 10), (30)
+
# 60 gHz band channels 1-4, ref: Etsi En 302 567
(57240 - 65880 @ 2160), (40), NO-OUTDOOR
@@ -869,6 +908,9 @@
(5170 - 5250 @ 80), (23), AUTO-BW
(5250 - 5330 @ 80), (23), DFS, AUTO-BW
+ # 60 gHz band channels 1-4, ref: Etsi En 302 567
+ (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+
country MC: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
@@ -905,8 +947,6 @@
(5170 - 5250 @ 80), (23), AUTO-BW
(5250 - 5330 @ 80), (23), DFS, AUTO-BW
(5490 - 5710 @ 160), (30), DFS
- # 60 gHz band channels 1-4, ref: Etsi En 302 567
- (57240 - 65880 @ 2160), (40), NO-OUTDOOR
country MN: DFS-FCC
(2402 - 2482 @ 40), (20)
@@ -984,6 +1024,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-3, FCC
+ (57240 - 63720 @ 2160), (40)
+
country MY: DFS-FCC
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (24), AUTO-BW
@@ -991,6 +1034,9 @@
(5490 - 5650 @ 160), (24), DFS
(5735 - 5815 @ 80), (24)
+ # 60 gHz band channels 1-3
+ (57240 - 63720 @ 2160), (40)
+
country NA: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
@@ -1010,6 +1056,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-3, FCC
+ (57240 - 63720 @ 2160), (40)
+
country NL: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
@@ -1056,6 +1105,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-4, ref: Etsi En 302 567
+ (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+
country OM: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
@@ -1095,6 +1147,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-4, ref: Etsi En 302 567
+ (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+
country PK:
(2402 - 2482 @ 40), (30)
(5735 - 5835 @ 80), (30)
@@ -1167,6 +1222,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-3, FCC
+ (57240 - 63720 @ 2160), (40)
+
country QA:
(2402 - 2482 @ 40), (20)
(5735 - 5835 @ 80), (30)
@@ -1210,6 +1268,9 @@
(5490 - 5730 @ 160), (30)
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-4
+ (57240 - 65880 @ 2160), (40)
+
country RW: DFS-FCC
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (24), AUTO-BW
@@ -1247,6 +1308,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-4, ref: Etsi En 302 567
+ (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+
country SI: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
@@ -1328,6 +1392,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-4
+ (57240 - 65880 @ 2160), (40)
+
country TN: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
@@ -1338,8 +1405,6 @@
(5170 - 5250 @ 80), (23), AUTO-BW
(5250 - 5330 @ 80), (23), DFS, AUTO-BW
(5490 - 5710 @ 160), (30), DFS
- # 60 gHz band channels 1-4, ref: Etsi En 302 567
- (57240 - 65880 @ 2160), (40), NO-OUTDOOR
country TT:
(2402 - 2482 @ 40), (20)
@@ -1347,6 +1412,9 @@
(5490 - 5730 @ 160), (36)
(5735 - 5835 @ 80), (36)
+ # 60 gHz band channels 1-3, FCC
+ (57240 - 63720 @ 2160), (40)
+
country TW: DFS-FCC
(2402 - 2472 @ 40), (30)
(5170 - 5250 @ 80), (24), AUTO-BW
@@ -1354,6 +1422,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-3, FCC
+ (57240 - 63720 @ 2160), (40)
+
country TZ:
(2402 - 2482 @ 40), (20)
(5735 - 5835 @ 80), (30)
@@ -1372,7 +1443,7 @@
(5490 - 5670 @ 160), (20), DFS
(5735 - 5835 @ 80), (20)
# 60 gHz band channels 1-4, ref: Etsi En 302 567
- (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+ (57240 - 65880 @ 2160), (20)
country UG: DFS-FCC
(2402 - 2482 @ 40), (20)
@@ -1401,8 +1472,8 @@
(5910 - 5930 @ 10), (30)
# 60g band
# reference: http://cfr.regstoday.com/47cfr15.aspx#47_CFR_15p255
- # channels 1,2,3, EIRP=40dBm(43dBm peak)
- (57240 - 63720 @ 2160), (40)
+ # channels 1,2,3,4,5,6 EIRP=40dBm(43dBm peak)
+ (57240 - 70200 @ 2160), (40)
country UY: DFS-FCC
(2402 - 2482 @ 40), (20)
@@ -1410,6 +1481,9 @@
(5250 - 5330 @ 80), (23), DFS, AUTO-BW
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-4
+ (57240 - 65880 @ 2160), (40)
+
country UZ: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
@@ -1441,6 +1515,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-4
+ (57240 - 65880 @ 2160), (40)
+
country VU: DFS-FCC
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (24), AUTO-BW
@@ -1466,7 +1543,6 @@
(5170 - 5250 @ 80), (20), NO-IR, AUTO-BW, NO-OUTDOOR
(5250 - 5330 @ 80), (20), DFS, AUTO-BW, NO-OUTDOOR
(5490 - 5710 @ 160), (20), DFS
- (59000 - 66000 @ 2160), (10 mW)
country YE:
(2402 - 2482 @ 40), (20)
@@ -1484,6 +1560,9 @@
(5490 - 5730 @ 160), (24), DFS
(5735 - 5835 @ 80), (30)
+ # 60 gHz band channels 1-4
+ (57240 - 65880 @ 2160), (40), NO-OUTDOOR
+
country ZW: DFS-ETSI
(2402 - 2482 @ 40), (20)
(5170 - 5250 @ 80), (23), AUTO-BW
diff --git a/net/wireless/scan.c b/net/wireless/scan.c
index e318878..35ad69f 100644
--- a/net/wireless/scan.c
+++ b/net/wireless/scan.c
@@ -70,7 +70,7 @@
MODULE_PARM_DESC(bss_entries_limit,
"limit to number of scan BSS entries (per wiphy, default 1000)");
-#define IEEE80211_SCAN_RESULT_EXPIRE (7 * HZ)
+#define IEEE80211_SCAN_RESULT_EXPIRE (30 * HZ)
static void bss_free(struct cfg80211_internal_bss *bss)
{
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index f93db0e..a0d45ef 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2438,15 +2438,6 @@
$herecurr);
}
$shorttext = AFTER_SHORTTEXT;
- } elsif (length($line) > (SHORTTEXT_LIMIT +
- $shorttext_exspc)
- && $line !~ /^:([0-7]{6}\s){2}
- ([[:xdigit:]]+\.*
- \s){2}\w+\s\w+/xms) {
- WARN("LONG_COMMIT_TEXT",
- "commit text line over " .
- SHORTTEXT_LIMIT .
- " characters\n" . $herecurr);
} elsif ($line=~/^\s*change-id:/i ||
$line=~/^\s*signed-off-by:/i ||
$line=~/^\s*crs-fixed:/i ||
diff --git a/sound/core/seq/seq_lock.c b/sound/core/seq/seq_lock.c
index 3b693e9..12ba833 100644
--- a/sound/core/seq/seq_lock.c
+++ b/sound/core/seq/seq_lock.c
@@ -28,19 +28,16 @@
/* wait until all locks are released */
void snd_use_lock_sync_helper(snd_use_lock_t *lockp, const char *file, int line)
{
- int max_count = 5 * HZ;
+ int warn_count = 5 * HZ;
if (atomic_read(lockp) < 0) {
pr_warn("ALSA: seq_lock: lock trouble [counter = %d] in %s:%d\n", atomic_read(lockp), file, line);
return;
}
while (atomic_read(lockp) > 0) {
- if (max_count == 0) {
- pr_warn("ALSA: seq_lock: timeout [%d left] in %s:%d\n", atomic_read(lockp), file, line);
- break;
- }
+ if (warn_count-- == 0)
+ pr_warn("ALSA: seq_lock: waiting [%d left] in %s:%d\n", atomic_read(lockp), file, line);
schedule_timeout_uninterruptible(1);
- max_count--;
}
}
diff --git a/sound/firewire/lib.h b/sound/firewire/lib.h
index f676931..c3768cd 100644
--- a/sound/firewire/lib.h
+++ b/sound/firewire/lib.h
@@ -45,7 +45,7 @@
struct snd_rawmidi_substream *substream;
snd_fw_async_midi_port_fill fill;
- unsigned int consume_bytes;
+ int consume_bytes;
};
int snd_fw_async_midi_port_init(struct snd_fw_async_midi_port *port,
diff --git a/sound/firewire/oxfw/oxfw.c b/sound/firewire/oxfw/oxfw.c
index e629b88..474b06d 100644
--- a/sound/firewire/oxfw/oxfw.c
+++ b/sound/firewire/oxfw/oxfw.c
@@ -226,11 +226,11 @@
if (err < 0)
goto error;
- err = detect_quirks(oxfw);
+ err = snd_oxfw_stream_discover(oxfw);
if (err < 0)
goto error;
- err = snd_oxfw_stream_discover(oxfw);
+ err = detect_quirks(oxfw);
if (err < 0)
goto error;
diff --git a/sound/soc/intel/boards/bytcr_rt5640.c b/sound/soc/intel/boards/bytcr_rt5640.c
index 4c8ff29..d5873ee 100644
--- a/sound/soc/intel/boards/bytcr_rt5640.c
+++ b/sound/soc/intel/boards/bytcr_rt5640.c
@@ -621,7 +621,7 @@
.codec_dai_name = "snd-soc-dummy-dai",
.codec_name = "snd-soc-dummy",
.platform_name = "sst-mfld-platform",
- .ignore_suspend = 1,
+ .nonatomic = true,
.dynamic = 1,
.dpcm_playback = 1,
.dpcm_capture = 1,
@@ -634,7 +634,6 @@
.codec_dai_name = "snd-soc-dummy-dai",
.codec_name = "snd-soc-dummy",
.platform_name = "sst-mfld-platform",
- .ignore_suspend = 1,
.nonatomic = true,
.dynamic = 1,
.dpcm_playback = 1,
@@ -661,6 +660,7 @@
| SND_SOC_DAIFMT_CBS_CFS,
.be_hw_params_fixup = byt_rt5640_codec_fixup,
.ignore_suspend = 1,
+ .nonatomic = true,
.dpcm_playback = 1,
.dpcm_capture = 1,
.init = byt_rt5640_init,
diff --git a/sound/soc/intel/boards/bytcr_rt5651.c b/sound/soc/intel/boards/bytcr_rt5651.c
index 35f591e..eabff3a 100644
--- a/sound/soc/intel/boards/bytcr_rt5651.c
+++ b/sound/soc/intel/boards/bytcr_rt5651.c
@@ -235,7 +235,6 @@
.codec_dai_name = "snd-soc-dummy-dai",
.codec_name = "snd-soc-dummy",
.platform_name = "sst-mfld-platform",
- .ignore_suspend = 1,
.nonatomic = true,
.dynamic = 1,
.dpcm_playback = 1,
@@ -249,7 +248,6 @@
.codec_dai_name = "snd-soc-dummy-dai",
.codec_name = "snd-soc-dummy",
.platform_name = "sst-mfld-platform",
- .ignore_suspend = 1,
.nonatomic = true,
.dynamic = 1,
.dpcm_playback = 1,
diff --git a/sound/soc/msm/sdm845.c b/sound/soc/msm/sdm845.c
index 0f41387..304bf47 100644
--- a/sound/soc/msm/sdm845.c
+++ b/sound/soc/msm/sdm845.c
@@ -155,6 +155,21 @@
u32 index;
};
+enum pinctrl_pin_state {
+ STATE_DISABLE = 0, /* All pins are in sleep state */
+ STATE_MI2S_ACTIVE, /* IS2 = active, TDM = sleep */
+ STATE_TDM_ACTIVE, /* IS2 = sleep, TDM = active */
+};
+
+struct msm_pinctrl_info {
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *mi2s_disable;
+ struct pinctrl_state *tdm_disable;
+ struct pinctrl_state *mi2s_active;
+ struct pinctrl_state *tdm_active;
+ enum pinctrl_pin_state curr_state;
+};
+
struct msm_asoc_mach_data {
u32 mclk_freq;
int us_euro_gpio; /* used by gpio driver API */
@@ -162,6 +177,7 @@
struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
struct snd_info_entry *codec_root;
+ struct msm_pinctrl_info pinctrl_info;
};
struct msm_asoc_wcd93xx_codec {
@@ -170,6 +186,9 @@
void (*mbhc_hs_detect_exit)(struct snd_soc_codec *codec);
};
+static const char *const pin_states[] = {"sleep", "i2s-active",
+ "tdm-active"};
+
enum {
TDM_0 = 0,
TDM_1,
@@ -3803,6 +3822,275 @@
return ret;
}
+static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
+ enum pinctrl_pin_state new_state)
+{
+ int ret = 0;
+ int curr_state = 0;
+
+ if (pinctrl_info == NULL) {
+ pr_err("%s: pinctrl_info is NULL\n", __func__);
+ ret = -EINVAL;
+ goto err;
+ }
+ curr_state = pinctrl_info->curr_state;
+ pinctrl_info->curr_state = new_state;
+ pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
+ pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
+
+ if (curr_state == pinctrl_info->curr_state) {
+ pr_debug("%s: Already in same state\n", __func__);
+ goto err;
+ }
+
+ if (curr_state != STATE_DISABLE &&
+ pinctrl_info->curr_state != STATE_DISABLE) {
+ pr_debug("%s: state already active cannot switch\n", __func__);
+ ret = -EIO;
+ goto err;
+ }
+
+ switch (pinctrl_info->curr_state) {
+ case STATE_MI2S_ACTIVE:
+ ret = pinctrl_select_state(pinctrl_info->pinctrl,
+ pinctrl_info->mi2s_active);
+ if (ret) {
+ pr_err("%s: MI2S state select failed with %d\n",
+ __func__, ret);
+ ret = -EIO;
+ goto err;
+ }
+ break;
+ case STATE_TDM_ACTIVE:
+ ret = pinctrl_select_state(pinctrl_info->pinctrl,
+ pinctrl_info->tdm_active);
+ if (ret) {
+ pr_err("%s: TDM state select failed with %d\n",
+ __func__, ret);
+ ret = -EIO;
+ goto err;
+ }
+ break;
+ case STATE_DISABLE:
+ if (curr_state == STATE_MI2S_ACTIVE) {
+ ret = pinctrl_select_state(pinctrl_info->pinctrl,
+ pinctrl_info->mi2s_disable);
+ } else {
+ ret = pinctrl_select_state(pinctrl_info->pinctrl,
+ pinctrl_info->tdm_disable);
+ }
+ if (ret) {
+ pr_err("%s: state disable failed with %d\n",
+ __func__, ret);
+ ret = -EIO;
+ goto err;
+ }
+ break;
+ default:
+ pr_err("%s: TLMM pin state is invalid\n", __func__);
+ return -EINVAL;
+ }
+
+err:
+ return ret;
+}
+
+static void msm_release_pinctrl(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
+ struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
+ struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
+
+ if (pinctrl_info->pinctrl) {
+ devm_pinctrl_put(pinctrl_info->pinctrl);
+ pinctrl_info->pinctrl = NULL;
+ }
+}
+
+static int msm_get_pinctrl(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
+ struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
+ struct msm_pinctrl_info *pinctrl_info = NULL;
+ struct pinctrl *pinctrl;
+ int ret;
+
+ pinctrl_info = &pdata->pinctrl_info;
+
+ if (pinctrl_info == NULL) {
+ pr_err("%s: pinctrl_info is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR_OR_NULL(pinctrl)) {
+ pr_err("%s: Unable to get pinctrl handle\n", __func__);
+ return -EINVAL;
+ }
+ pinctrl_info->pinctrl = pinctrl;
+
+ /* get all the states handles from Device Tree */
+ pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
+ "quat-mi2s-sleep");
+ if (IS_ERR(pinctrl_info->mi2s_disable)) {
+ pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
+ goto err;
+ }
+ pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
+ "quat-mi2s-active");
+ if (IS_ERR(pinctrl_info->mi2s_active)) {
+ pr_err("%s: could not get mi2s_active pinstate\n", __func__);
+ goto err;
+ }
+ pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
+ "quat-tdm-sleep");
+ if (IS_ERR(pinctrl_info->tdm_disable)) {
+ pr_err("%s: could not get tdm_disable pinstate\n", __func__);
+ goto err;
+ }
+ pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
+ "quat-tdm-active");
+ if (IS_ERR(pinctrl_info->tdm_active)) {
+ pr_err("%s: could not get tdm_active pinstate\n",
+ __func__);
+ goto err;
+ }
+ /* Reset the TLMM pins to a default state */
+ ret = pinctrl_select_state(pinctrl_info->pinctrl,
+ pinctrl_info->mi2s_disable);
+ if (ret != 0) {
+ pr_err("%s: Disable TLMM pins failed with %d\n",
+ __func__, ret);
+ ret = -EIO;
+ goto err;
+ }
+ pinctrl_info->curr_state = STATE_DISABLE;
+
+ return 0;
+
+err:
+ devm_pinctrl_put(pinctrl);
+ pinctrl_info->pinctrl = NULL;
+ return -EINVAL;
+}
+
+static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ struct snd_interval *rate = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_RATE);
+ struct snd_interval *channels = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_CHANNELS);
+
+ if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
+ channels->min = channels->max =
+ tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
+ param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
+ tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
+ rate->min = rate->max =
+ tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
+ } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
+ channels->min = channels->max =
+ tdm_rx_cfg[TDM_SEC][TDM_0].channels;
+ param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
+ tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
+ rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
+ } else {
+ pr_err("%s: dai id 0x%x not supported\n",
+ __func__, cpu_dai->id);
+ return -EINVAL;
+ }
+
+ pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
+ __func__, cpu_dai->id, channels->max, rate->max,
+ params_format(params));
+
+ return 0;
+}
+
+static int sdm845_tdm_snd_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ int ret = 0;
+ int channels, slot_width, slots;
+ unsigned int slot_mask;
+ unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
+
+ pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
+
+ slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
+ /*2 slot config - bits 0 and 1 set for the first two slots */
+ slot_mask = 0x0000FFFF >> (16-slots);
+ slot_width = 32;
+ channels = slots;
+
+ pr_debug("%s: slot_width %d slots %d\n", __func__, slot_width, slots);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ pr_debug("%s: slot_width %d\n", __func__, slot_width);
+ ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
+ slots, slot_width);
+ if (ret < 0) {
+ pr_err("%s: failed to set tdm slot, err:%d\n",
+ __func__, ret);
+ goto end;
+ }
+
+ ret = snd_soc_dai_set_channel_map(cpu_dai,
+ 0, NULL, channels, slot_offset);
+ if (ret < 0) {
+ pr_err("%s: failed to set channel map, err:%d\n",
+ __func__, ret);
+ goto end;
+ }
+ } else {
+ pr_err("%s: invalid use case, err:%d\n",
+ __func__, ret);
+ }
+
+end:
+ return ret;
+}
+
+static int sdm845_tdm_snd_startup(struct snd_pcm_substream *substream)
+{
+ int ret = 0;
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *card = rtd->card;
+ struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
+ struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
+
+ ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
+ if (ret)
+ pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
+ __func__, ret);
+
+ return ret;
+}
+
+static void sdm845_tdm_snd_shutdown(struct snd_pcm_substream *substream)
+{
+ int ret = 0;
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_card *card = rtd->card;
+ struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
+ struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
+
+ ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
+ if (ret)
+ pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
+ __func__, ret);
+
+}
+
+static struct snd_soc_ops sdm845_tdm_be_ops = {
+ .hw_params = sdm845_tdm_snd_hw_params,
+ .startup = sdm845_tdm_snd_startup,
+ .shutdown = sdm845_tdm_snd_shutdown
+};
+
static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
{
int ret = 0;
@@ -3810,6 +4098,9 @@
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
int index = cpu_dai->id;
unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
+ struct snd_soc_card *card = rtd->card;
+ struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
+ struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
dev_dbg(rtd->card->dev,
"%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
@@ -3823,6 +4114,14 @@
__func__, cpu_dai->id);
goto err;
}
+ if (index == QUAT_MI2S) {
+ ret = msm_set_pinctrl(pinctrl_info, STATE_MI2S_ACTIVE);
+ if (ret) {
+ pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
+ __func__, ret);
+ goto err;
+ }
+ }
/*
* Muxtex protection in case the same MI2S
* interface using for both TX and RX so
@@ -3875,6 +4174,9 @@
int ret;
struct snd_soc_pcm_runtime *rtd = substream->private_data;
int index = rtd->cpu_dai->id;
+ struct snd_soc_card *card = rtd->card;
+ struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
+ struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
pr_debug("%s(): substream = %s stream = %d\n", __func__,
substream->name, substream->stream);
@@ -3893,6 +4195,13 @@
}
}
mutex_unlock(&mi2s_intf_conf[index].lock);
+
+ if (index == QUAT_MI2S) {
+ ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
+ if (ret)
+ pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
+ __func__, ret);
+ }
}
static struct snd_soc_ops msm_mi2s_be_ops = {
@@ -4930,8 +5239,8 @@
.no_pcm = 1,
.dpcm_playback = 1,
.id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
- .be_hw_params_fixup = msm_be_hw_params_fixup,
- .ops = &msm_tdm_be_ops,
+ .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
+ .ops = &sdm845_tdm_be_ops,
.ignore_suspend = 1,
},
{
@@ -6297,6 +6606,17 @@
dev_dbg(&pdev->dev, "msm_prepare_us_euro failed (%d)\n",
ret);
+ /* Parse pinctrl info from devicetree */
+ ret = msm_get_pinctrl(pdev);
+ if (!ret) {
+ pr_debug("%s: pinctrl parsing successful\n", __func__);
+ } else {
+ dev_dbg(&pdev->dev,
+ "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
+ __func__, ret);
+ ret = 0;
+ }
+
msm_i2s_auxpcm_init(pdev);
is_initial_boot = true;
@@ -6308,6 +6628,7 @@
return 0;
err:
+ msm_release_pinctrl(pdev);
devm_kfree(&pdev->dev, pdata);
return ret;
}
@@ -6324,6 +6645,7 @@
}
msm_i2s_auxpcm_deinit();
+ msm_release_pinctrl(pdev);
snd_soc_unregister_card(card);
return 0;
}