blob: 4d2f54db1ef4d9b8708d458074656b499471056c [file] [log] [blame]
/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/cdev.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/fs.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <soc/qcom/memory_dump.h>
#include <soc/qcom/scm.h>
#define TIMEOUT_US (100)
#define BM(lsb, msb) ((BIT(msb) - BIT(lsb)) + BIT(msb))
#define BMVAL(val, lsb, msb) ((val & BM(lsb, msb)) >> lsb)
#define BVAL(val, n) ((val & BIT(n)) >> n)
#define dcc_writel(drvdata, val, off) \
__raw_writel((val), drvdata->base + off)
#define dcc_readl(drvdata, off) \
__raw_readl(drvdata->base + off)
#define dcc_sram_writel(drvdata, val, off) \
__raw_writel((val), drvdata->ram_base + off)
#define dcc_sram_readl(drvdata, off) \
__raw_readl(drvdata->ram_base + off)
#define HLOS_LIST_START 1
/* DCC registers */
#define DCC_HW_VERSION (0x00)
#define DCC_HW_INFO (0x04)
#define DCC_EXEC_CTRL (0x08)
#define DCC_STATUS (0x0C)
#define DCC_CFG (0x10)
#define DCC_FDA_CURR (0x14)
#define DCC_LLA_CURR (0x18)
#define DCC_LL_LOCK(m) (0x1C + 0x80 * (m + HLOS_LIST_START))
#define DCC_LL_CFG(m) (0x20 + 0x80 * (m + HLOS_LIST_START))
#define DCC_LL_BASE(m) (0x24 + 0x80 * (m + HLOS_LIST_START))
#define DCC_FD_BASE(m) (0x28 + 0x80 * (m + HLOS_LIST_START))
#define DCC_LL_TIMEOUT(m) (0x2c + 0x80 * (m + HLOS_LIST_START))
#define DCC_LL_INT_ENABLE(m) (0x30 + 0x80 * (m + HLOS_LIST_START))
#define DCC_LL_INT_STATUS(m) (0x34 + 0x80 * (m + HLOS_LIST_START))
#define DCC_FDA_CAPTURED(m) (0x38 + 0x80 * (m + HLOS_LIST_START))
#define DCC_LLA_CAPTURED(m) (0x3C + 0x80 * (m + HLOS_LIST_START))
#define DCC_LL_CRC_CAPTURED(m) (0x40 + 0x80 * (m + HLOS_LIST_START))
#define DCC_LL_SW_TRIGGER(m) (0x44 + 0x80 * (m + HLOS_LIST_START))
#define DCC_LL_BUS_ACCESS_STATUS(m) (0x48 + 0x80 * (m + HLOS_LIST_START))
#define DCC_REG_DUMP_MAGIC_V2 (0x42445953)
#define DCC_REG_DUMP_VER (1)
#define MAX_DCC_OFFSET (0xFF * 4)
#define MAX_DCC_LEN 0x7F
#define MAX_LOOP_CNT 0xFF
#define DCC_ADDR_DESCRIPTOR 0x00
#define DCC_LOOP_DESCRIPTOR (BIT(30))
#define DCC_RD_MOD_WR_DESCRIPTOR (BIT(31))
#define DCC_LINK_DESCRIPTOR (BIT(31) | BIT(30))
#define DCC_MAX_LINK_LIST 5
#define DCC_INVALID_LINK_LIST 0xFF
enum dcc_func_type {
DCC_FUNC_TYPE_CAPTURE,
DCC_FUNC_TYPE_CRC,
};
static const char * const str_dcc_func_type[] = {
[DCC_FUNC_TYPE_CAPTURE] = "cap",
[DCC_FUNC_TYPE_CRC] = "crc",
};
enum dcc_data_sink {
DCC_DATA_SINK_SRAM,
DCC_DATA_SINK_ATB
};
static const char * const str_dcc_data_sink[] = {
[DCC_DATA_SINK_SRAM] = "sram",
[DCC_DATA_SINK_ATB] = "atb",
};
struct rpm_trig_req {
uint32_t enable;
uint32_t reserved;
};
struct dcc_config_entry {
uint32_t base;
uint32_t offset;
uint32_t len;
uint32_t index;
uint32_t loop_cnt;
uint32_t rd_mod_wr;
uint32_t mask;
bool rd_wr_entry;
struct list_head list;
};
struct dcc_drvdata {
void __iomem *base;
uint32_t reg_size;
struct device *dev;
struct mutex mutex;
void __iomem *ram_base;
uint32_t ram_size;
uint32_t ram_offset;
enum dcc_data_sink data_sink;
enum dcc_func_type func_type[DCC_MAX_LINK_LIST];
uint32_t ram_cfg;
uint32_t ram_start;
bool enable[DCC_MAX_LINK_LIST];
bool configured[DCC_MAX_LINK_LIST];
bool interrupt_disable;
char *sram_node;
struct cdev sram_dev;
struct class *sram_class;
struct list_head cfg_head[DCC_MAX_LINK_LIST];
uint32_t nr_config[DCC_MAX_LINK_LIST];
void *reg_buf;
struct msm_dump_data reg_data;
bool save_reg;
void *sram_buf;
struct msm_dump_data sram_data;
uint8_t curr_list;
};
static bool dcc_ready(struct dcc_drvdata *drvdata)
{
uint32_t val;
/* poll until DCC ready */
if (!readl_poll_timeout((drvdata->base + DCC_STATUS), val,
(BMVAL(val, 0, 1) == 0), 1, TIMEOUT_US))
return true;
return false;
}
static int dcc_read_status(struct dcc_drvdata *drvdata)
{
int curr_list;
uint32_t bus_status;
for (curr_list = 0; curr_list < DCC_MAX_LINK_LIST; curr_list++) {
if (!drvdata->enable[curr_list])
continue;
bus_status = dcc_readl(drvdata,
DCC_LL_BUS_ACCESS_STATUS(curr_list));
if (bus_status) {
dev_err(drvdata->dev,
"Read access error for list %d err: 0x%x",
curr_list, bus_status);
dcc_writel(drvdata, 0x3,
DCC_LL_BUS_ACCESS_STATUS(curr_list));
return -ENODATA;
}
}
return 0;
}
static int dcc_sw_trigger(struct dcc_drvdata *drvdata)
{
int ret = 0;
int curr_list;
mutex_lock(&drvdata->mutex);
if (!dcc_ready(drvdata)) {
dev_err(drvdata->dev, "DCC is not ready!\n");
ret = -EBUSY;
goto err;
}
for (curr_list = 0; curr_list < DCC_MAX_LINK_LIST; curr_list++) {
if (!drvdata->enable[curr_list])
continue;
dcc_writel(drvdata, 1, DCC_LL_SW_TRIGGER(curr_list));
}
if (!dcc_ready(drvdata)) {
dev_err(drvdata->dev,
"DCC is busy after receiving sw tigger.\n");
ret = -EBUSY;
goto err;
}
ret = dcc_read_status(drvdata);
err:
mutex_unlock(&drvdata->mutex);
return ret;
}
static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list)
{
int ret = 0;
uint32_t sram_offset = drvdata->ram_cfg * 4;
uint32_t prev_addr, addr;
uint32_t prev_off = 0, off;
uint32_t loop_off = 0;
uint32_t link;
uint32_t pos, total_len = 0, loop_len = 0;
uint32_t loop, loop_cnt;
bool loop_start = false;
struct dcc_config_entry *entry;
prev_addr = 0;
addr = 0;
link = 0;
list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) {
if (entry->rd_wr_entry) {
if (link) {
/* write new offset = 1 to continue
* processing the list
*/
link |= ((0x1 << 8) & BM(8, 14));
dcc_sram_writel(drvdata, link, sram_offset);
sram_offset += 4;
/* Reset link and prev_off */
addr = 0x00;
link = 0;
prev_off = 0;
prev_addr = addr;
}
addr = DCC_RD_MOD_WR_DESCRIPTOR;
dcc_sram_writel(drvdata, addr, sram_offset);
sram_offset += 4;
dcc_sram_writel(drvdata, entry->mask, sram_offset);
sram_offset += 4;
dcc_sram_writel(drvdata, entry->rd_mod_wr, sram_offset);
sram_offset += 4;
continue;
}
if (entry->loop_cnt) {
/* Check if we need to write link of prev entry */
if (link) {
dcc_sram_writel(drvdata, link, sram_offset);
sram_offset += 4;
}
if (loop_start) {
loop = (sram_offset - loop_off) / 4;
loop |= (loop_cnt << 13) & BM(13, 27);
loop |= DCC_LOOP_DESCRIPTOR;
total_len += (total_len - loop_len) * loop_cnt;
dcc_sram_writel(drvdata, loop, sram_offset);
sram_offset += 4;
loop_start = false;
loop_len = 0;
loop_off = 0;
} else {
loop_start = true;
loop_cnt = entry->loop_cnt - 1;
loop_len = total_len;
loop_off = sram_offset;
}
/* Reset link and prev_off */
addr = 0x00;
link = 0;
prev_off = 0;
prev_addr = addr;
continue;
}
/* Address type */
addr = (entry->base >> 4) & BM(0, 27);
addr |= DCC_ADDR_DESCRIPTOR;
off = entry->offset/4;
total_len += entry->len * 4;
if (!prev_addr || prev_addr != addr || prev_off > off) {
/* Check if we need to write link of prev entry */
if (link) {
dcc_sram_writel(drvdata, link, sram_offset);
sram_offset += 4;
}
dev_err(drvdata->dev,
"DCC: sram address.%d\n", sram_offset);
/* Write address */
dcc_sram_writel(drvdata, addr, sram_offset);
sram_offset += 4;
/* Reset link and prev_off */
link = 0;
prev_off = 0;
}
if ((off - prev_off) > 0xFF || entry->len > MAX_DCC_LEN) {
dev_err(drvdata->dev,
"DCC: Progamming error! Base: 0x%x, offset 0x%x.\n",
entry->base, entry->offset);
ret = -EINVAL;
goto err;
}
if (link) {
/*
* link already has one offset-length so new
* offset-length needs to be placed at bits [29:15]
*/
pos = 15;
/* Clear bits [31:16] */
link &= BM(0, 14);
} else {
/*
* link is empty, so new offset-length needs to be
* placed at bits [15:0]
*/
pos = 0;
link = 1 << 15;
}
/* write new offset-length pair to correct position */
link |= (((off-prev_off) & BM(0, 7)) |
((entry->len << 8) & BM(8, 14))) << pos;
link |= DCC_LINK_DESCRIPTOR;
if (pos) {
dcc_sram_writel(drvdata, link, sram_offset);
sram_offset += 4;
link = 0;
}
prev_off = off;
prev_addr = addr;
}
if (link) {
dcc_sram_writel(drvdata, link, sram_offset);
sram_offset += 4;
}
if (loop_start) {
dev_err(drvdata->dev,
"DCC: Progamming error! Loop unterminated.\n");
ret = -EINVAL;
goto err;
}
/* Handling special case of list ending with a rd_mod_wr */
if (addr == DCC_RD_MOD_WR_DESCRIPTOR) {
addr = (0xC105E) & BM(0, 27);
addr |= DCC_ADDR_DESCRIPTOR;
dcc_sram_writel(drvdata, addr, sram_offset);
sram_offset += 4;
}
/* Setting zero to indicate end of the list */
link = DCC_LINK_DESCRIPTOR;
dcc_sram_writel(drvdata, link, sram_offset);
sram_offset += 4;
/* Update ram_cfg and check if the data will overstep */
if (drvdata->data_sink == DCC_DATA_SINK_SRAM &&
drvdata->func_type[curr_list] == DCC_FUNC_TYPE_CAPTURE) {
drvdata->ram_cfg = (sram_offset + total_len) / 4;
if (sram_offset + total_len > drvdata->ram_size) {
sram_offset += total_len;
goto overstep;
}
} else {
drvdata->ram_cfg = sram_offset / 4;
if (sram_offset > drvdata->ram_size)
goto overstep;
}
drvdata->ram_start = sram_offset/4;
return 0;
overstep:
ret = -EINVAL;
memset_io(drvdata->ram_base, 0, drvdata->ram_size);
dev_err(drvdata->dev, "DCC SRAM oversteps, 0x%x (0x%x)\n",
sram_offset, drvdata->ram_size);
err:
return ret;
}
static void __dcc_reg_dump(struct dcc_drvdata *drvdata)
{
uint32_t *reg_buf;
uint8_t i = 0;
uint8_t j;
if (!drvdata->reg_buf)
return;
drvdata->reg_data.version = DCC_REG_DUMP_VER;
reg_buf = drvdata->reg_buf;
reg_buf[i++] = dcc_readl(drvdata, DCC_HW_VERSION);
reg_buf[i++] = dcc_readl(drvdata, DCC_HW_INFO);
reg_buf[i++] = dcc_readl(drvdata, DCC_EXEC_CTRL);
reg_buf[i++] = dcc_readl(drvdata, DCC_STATUS);
reg_buf[i++] = dcc_readl(drvdata, DCC_CFG);
reg_buf[i++] = dcc_readl(drvdata, DCC_FDA_CURR);
reg_buf[i++] = dcc_readl(drvdata, DCC_LLA_CURR);
for (j = 0; j < DCC_MAX_LINK_LIST; j++)
reg_buf[i++] = dcc_readl(drvdata, DCC_LL_LOCK(j));
for (j = 0; j < DCC_MAX_LINK_LIST; j++)
reg_buf[i++] = dcc_readl(drvdata, DCC_LL_CFG(j));
for (j = 0; j < DCC_MAX_LINK_LIST; j++)
reg_buf[i++] = dcc_readl(drvdata, DCC_LL_BASE(j));
for (j = 0; j < DCC_MAX_LINK_LIST; j++)
reg_buf[i++] = dcc_readl(drvdata, DCC_FD_BASE(j));
drvdata->reg_data.magic = DCC_REG_DUMP_MAGIC_V2;
}
static void __dcc_first_crc(struct dcc_drvdata *drvdata)
{
int i;
/*
* Need to send 2 triggers to DCC. First trigger sets CRC error status
* bit. So need second trigger to reset this bit.
*/
for (i = 0; i < 2; i++) {
if (!dcc_ready(drvdata))
dev_err(drvdata->dev, "DCC is not ready!\n");
dcc_writel(drvdata, 1,
DCC_LL_SW_TRIGGER(drvdata->curr_list));
}
/* Clear CRC error interrupt */
dcc_writel(drvdata, BIT(1),
DCC_LL_INT_STATUS(drvdata->curr_list));
}
static int dcc_valid_list(struct dcc_drvdata *drvdata, int curr_list)
{
uint32_t lock_reg;
if (list_empty(&drvdata->cfg_head[curr_list]))
return -EINVAL;
if (drvdata->enable[curr_list]) {
dev_err(drvdata->dev, "DCC is already enabled!\n");
return -EINVAL;
}
lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(curr_list));
if (lock_reg & 0x1) {
dev_err(drvdata->dev, "DCC is already enabled!\n");
return -EINVAL;
}
dev_err(drvdata->dev, "DCC list passed %d\n", curr_list);
return 0;
}
static int dcc_enable(struct dcc_drvdata *drvdata)
{
int ret = 0;
int list;
uint32_t ram_cfg_base;
mutex_lock(&drvdata->mutex);
memset_io(drvdata->ram_base, 0, drvdata->ram_size);
for (list = 0; list < DCC_MAX_LINK_LIST; list++) {
if (dcc_valid_list(drvdata, list))
continue;
/* 1. Take ownership of the list */
dcc_writel(drvdata, BIT(0), DCC_LL_LOCK(list));
/* 2. Program linked-list in the SRAM */
ram_cfg_base = drvdata->ram_cfg;
ret = __dcc_ll_cfg(drvdata, list);
if (ret) {
dev_info(drvdata->dev, "DCC ram programming failed\n");
goto err;
}
/* 3. If in capture mode program DCC_RAM_CFG reg */
if (drvdata->func_type[list] == DCC_FUNC_TYPE_CAPTURE) {
dcc_writel(drvdata, ram_cfg_base +
drvdata->ram_offset/4, DCC_LL_BASE(list));
dcc_writel(drvdata, drvdata->ram_start +
drvdata->ram_offset/4, DCC_FD_BASE(list));
dcc_writel(drvdata, 0, DCC_LL_TIMEOUT(list));
}
/* 4. Configure data sink and function type */
dcc_writel(drvdata, ((drvdata->data_sink << 4) |
(drvdata->func_type[list])), DCC_LL_CFG(list));
/* 5. Clears interrupt status register */
dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list));
dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)),
DCC_LL_INT_STATUS(list));
dev_info(drvdata->dev, "All values written to enable");
/* Make sure all config is written in sram */
mb();
drvdata->enable[list] = 1;
if (drvdata->func_type[list] == DCC_FUNC_TYPE_CRC) {
__dcc_first_crc(drvdata);
/* Enable CRC error interrupt */
if (!drvdata->interrupt_disable)
dcc_writel(drvdata, BIT(1),
DCC_LL_INT_ENABLE(list));
}
}
/* Save DCC registers */
if (drvdata->save_reg)
__dcc_reg_dump(drvdata);
err:
mutex_unlock(&drvdata->mutex);
return ret;
}
static void dcc_disable(struct dcc_drvdata *drvdata)
{
int curr_list;
mutex_lock(&drvdata->mutex);
if (!dcc_ready(drvdata))
dev_err(drvdata->dev, "DCC is not ready! Disabling DCC...\n");
for (curr_list = 0; curr_list < DCC_MAX_LINK_LIST; curr_list++) {
if (!drvdata->enable[curr_list])
continue;
dcc_writel(drvdata, 0, DCC_LL_LOCK(curr_list));
drvdata->enable[curr_list] = 0;
}
drvdata->ram_cfg = 0;
drvdata->ram_start = 0;
/* Save DCC registers */
if (drvdata->save_reg)
__dcc_reg_dump(drvdata);
mutex_unlock(&drvdata->mutex);
}
static ssize_t dcc_curr_list(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
unsigned long val;
uint32_t lock_reg;
if (kstrtoul(buf, 16, &val))
return -EINVAL;
if (val >= DCC_MAX_LINK_LIST)
return -EINVAL;
mutex_lock(&drvdata->mutex);
lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(val));
if (lock_reg & 0x1) {
dev_err(drvdata->dev, "DCC linked list is already configured!\n");
mutex_unlock(&drvdata->mutex);
return -EINVAL;
}
drvdata->curr_list = val;
mutex_unlock(&drvdata->mutex);
return size;
}
static DEVICE_ATTR(curr_list, 0200,
NULL, dcc_curr_list);
static ssize_t dcc_show_func_type(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
ssize_t len = 0;
unsigned int i;
for (i = 0; i < DCC_MAX_LINK_LIST; i++)
len += scnprintf(buf + len, PAGE_SIZE - len, "%u :%s\n",
i, str_dcc_func_type[drvdata->func_type[i]]);
return len;
}
static ssize_t dcc_store_func_type(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
char str[10] = "";
int ret;
if (strlen(buf) >= 10)
return -EINVAL;
if (sscanf(buf, "%s", str) != 1)
return -EINVAL;
if (drvdata->curr_list >= DCC_MAX_LINK_LIST) {
dev_err(dev,
"Select link list to program using curr_list\n");
return -EINVAL;
}
mutex_lock(&drvdata->mutex);
if (drvdata->enable[drvdata->curr_list]) {
ret = -EBUSY;
goto out;
}
if (!strcmp(str, str_dcc_func_type[DCC_FUNC_TYPE_CAPTURE]))
drvdata->func_type[drvdata->curr_list] =
DCC_FUNC_TYPE_CAPTURE;
else if (!strcmp(str, str_dcc_func_type[DCC_FUNC_TYPE_CRC]))
drvdata->func_type[drvdata->curr_list] =
DCC_FUNC_TYPE_CRC;
else {
ret = -EINVAL;
goto out;
}
ret = size;
out:
mutex_unlock(&drvdata->mutex);
return ret;
}
static DEVICE_ATTR(func_type, 0644,
dcc_show_func_type, dcc_store_func_type);
static ssize_t dcc_show_data_sink(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
return scnprintf(buf, PAGE_SIZE, "%s\n",
str_dcc_data_sink[drvdata->data_sink]);
}
static ssize_t dcc_store_data_sink(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
char str[10] = "";
int ret;
if (strlen(buf) >= 10)
return -EINVAL;
if (sscanf(buf, "%s", str) != 1)
return -EINVAL;
mutex_lock(&drvdata->mutex);
if (drvdata->enable[drvdata->curr_list]) {
ret = -EBUSY;
goto out;
}
if (!strcmp(str, str_dcc_data_sink[DCC_DATA_SINK_SRAM]))
drvdata->data_sink = DCC_DATA_SINK_SRAM;
else if (!strcmp(str, str_dcc_data_sink[DCC_DATA_SINK_ATB]))
drvdata->data_sink = DCC_DATA_SINK_ATB;
else {
ret = -EINVAL;
goto out;
}
ret = size;
out:
mutex_unlock(&drvdata->mutex);
return ret;
}
static DEVICE_ATTR(data_sink, 0644,
dcc_show_data_sink, dcc_store_data_sink);
static ssize_t dcc_store_trigger(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
int ret = 0;
unsigned long val;
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
if (kstrtoul(buf, 16, &val))
return -EINVAL;
if (val != 1)
return -EINVAL;
ret = dcc_sw_trigger(drvdata);
if (!ret)
ret = size;
return ret;
}
static DEVICE_ATTR(trigger, 0200, NULL, dcc_store_trigger);
static ssize_t dcc_show_enable(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
return scnprintf(buf, PAGE_SIZE, "%u\n",
(unsigned int)drvdata->enable[drvdata->curr_list]);
}
static ssize_t dcc_store_enable(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
int ret = 0;
unsigned long val;
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
if (kstrtoul(buf, 16, &val))
return -EINVAL;
if (val)
ret = dcc_enable(drvdata);
else
dcc_disable(drvdata);
if (!ret)
ret = size;
return ret;
}
static DEVICE_ATTR(enable, 0644, dcc_show_enable,
dcc_store_enable);
static ssize_t dcc_show_config(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
struct dcc_config_entry *entry;
char local_buf[64];
int len = 0, count = 0;
buf[0] = '\0';
mutex_lock(&drvdata->mutex);
list_for_each_entry(entry,
&drvdata->cfg_head[drvdata->curr_list], list) {
if (entry->rd_wr_entry)
len = snprintf(local_buf, 64,
"Index: 0x%x, mask: 0x%x, val: 0x%x\n",
entry->index, entry->mask,
entry->rd_mod_wr);
else if (entry->loop_cnt)
len = snprintf(local_buf, 64, "Index: 0x%x, Loop: %d\n",
entry->index, entry->loop_cnt);
else
len = snprintf(local_buf, 64,
"Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x\n",
entry->index, entry->base,
entry->offset, entry->len);
if ((count + len) > PAGE_SIZE) {
dev_err(dev, "DCC: Couldn't write complete config!\n");
break;
}
strlcat(buf, local_buf, PAGE_SIZE);
count += len;
}
mutex_unlock(&drvdata->mutex);
return count;
}
static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr,
unsigned int len)
{
int ret;
struct dcc_config_entry *entry, *pentry;
unsigned int base, offset;
mutex_lock(&drvdata->mutex);
if (!len) {
dev_err(drvdata->dev, "DCC: Invalid length!\n");
ret = -EINVAL;
goto err;
}
base = addr & BM(4, 31);
if (!list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
pentry = list_last_entry(&drvdata->cfg_head[drvdata->curr_list],
struct dcc_config_entry, list);
if (addr >= (pentry->base + pentry->offset) &&
addr <= (pentry->base + pentry->offset + MAX_DCC_OFFSET)) {
/* Re-use base address from last entry */
base = pentry->base;
/*
* Check if new address is contiguous to last entry's
* addresses. If yes then we can re-use last entry and
* just need to update its length.
*/
if ((pentry->len * 4 + pentry->base + pentry->offset)
== addr) {
len += pentry->len;
/*
* Check if last entry can hold additional new
* length. If yes then we don't need to create
* a new entry else we need to add a new entry
* with same base but updated offset.
*/
if (len > MAX_DCC_LEN)
pentry->len = MAX_DCC_LEN;
else
pentry->len = len;
/*
* Update start addr and len for remaining
* addresses, which will be part of new
* entry.
*/
addr = pentry->base + pentry->offset +
pentry->len * 4;
len -= pentry->len;
}
}
}
offset = addr - base;
while (len) {
entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
if (!entry) {
ret = -ENOMEM;
goto err;
}
entry->base = base;
entry->offset = offset;
entry->len = min_t(uint32_t, len, MAX_DCC_LEN);
entry->index = drvdata->nr_config[drvdata->curr_list]++;
INIT_LIST_HEAD(&entry->list);
list_add_tail(&entry->list,
&drvdata->cfg_head[drvdata->curr_list]);
len -= entry->len;
offset += MAX_DCC_LEN * 4;
}
mutex_unlock(&drvdata->mutex);
return 0;
err:
mutex_unlock(&drvdata->mutex);
return ret;
}
static ssize_t dcc_store_config(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
int ret, len;
unsigned int base;
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
int nval;
nval = sscanf(buf, "%x %i", &base, &len);
if (nval <= 0 || nval > 2)
return -EINVAL;
if (nval == 1)
len = 1;
if (drvdata->curr_list >= DCC_MAX_LINK_LIST) {
dev_err(dev, "Select link list to program using curr_list\n");
return -EINVAL;
}
ret = dcc_config_add(drvdata, base, len);
if (ret)
return ret;
return size;
}
static DEVICE_ATTR(config, 0644, dcc_show_config,
dcc_store_config);
static void dcc_config_reset(struct dcc_drvdata *drvdata)
{
struct dcc_config_entry *entry, *temp;
int curr_list;
mutex_lock(&drvdata->mutex);
for (curr_list = 0; curr_list < DCC_MAX_LINK_LIST; curr_list++) {
list_for_each_entry_safe(entry, temp,
&drvdata->cfg_head[curr_list], list) {
list_del(&entry->list);
devm_kfree(drvdata->dev, entry);
drvdata->nr_config[curr_list]--;
}
}
drvdata->ram_start = 0;
drvdata->ram_cfg = 0;
mutex_unlock(&drvdata->mutex);
}
static ssize_t dcc_store_config_reset(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
unsigned long val;
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
if (kstrtoul(buf, 16, &val))
return -EINVAL;
if (val)
dcc_config_reset(drvdata);
return size;
}
static DEVICE_ATTR(config_reset, 0200, NULL, dcc_store_config_reset);
static ssize_t dcc_show_crc_error(struct device *dev,
struct device_attribute *attr, char *buf)
{
int ret;
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
mutex_lock(&drvdata->mutex);
if (!drvdata->enable[drvdata->curr_list]) {
ret = -EINVAL;
goto err;
}
ret = scnprintf(buf, PAGE_SIZE, "%u\n",
(unsigned int)BVAL(dcc_readl(
drvdata, DCC_LL_INT_STATUS(drvdata->curr_list)), 1));
err:
mutex_unlock(&drvdata->mutex);
return ret;
}
static DEVICE_ATTR(crc_error, 0444, dcc_show_crc_error, NULL);
static ssize_t dcc_show_ready(struct device *dev,
struct device_attribute *attr, char *buf)
{
int ret;
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
mutex_lock(&drvdata->mutex);
if (!drvdata->enable[drvdata->curr_list]) {
ret = -EINVAL;
goto err;
}
ret = scnprintf(buf, PAGE_SIZE, "%u\n",
(unsigned int)BVAL(dcc_readl(drvdata, DCC_STATUS), 1));
err:
mutex_unlock(&drvdata->mutex);
return ret;
}
static DEVICE_ATTR(ready, 0444, dcc_show_ready, NULL);
static ssize_t dcc_show_interrupt_disable(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
return scnprintf(buf, PAGE_SIZE, "%u\n",
(unsigned int)drvdata->interrupt_disable);
}
static ssize_t dcc_store_interrupt_disable(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
unsigned long val;
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
if (kstrtoul(buf, 16, &val))
return -EINVAL;
mutex_lock(&drvdata->mutex);
drvdata->interrupt_disable = (val ? 1:0);
mutex_unlock(&drvdata->mutex);
return size;
}
static DEVICE_ATTR(interrupt_disable, 0644,
dcc_show_interrupt_disable, dcc_store_interrupt_disable);
static ssize_t dcc_store_loop(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
int ret = size;
unsigned long loop_cnt;
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
struct dcc_config_entry *entry;
mutex_lock(&drvdata->mutex);
if (kstrtoul(buf, 16, &loop_cnt))
ret = -EINVAL;
entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
if (!entry) {
ret = -ENOMEM;
goto err;
}
entry->loop_cnt = min_t(uint32_t, loop_cnt, MAX_LOOP_CNT);
entry->index = drvdata->nr_config[drvdata->curr_list]++;
INIT_LIST_HEAD(&entry->list);
list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
err:
mutex_unlock(&drvdata->mutex);
return ret;
}
static DEVICE_ATTR(loop, 0200, NULL, dcc_store_loop);
static ssize_t dcc_rd_mod_wr(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
int ret = size;
int nval;
unsigned int mask, val;
struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
struct dcc_config_entry *entry;
mutex_lock(&drvdata->mutex);
nval = sscanf(buf, "%x %x", &mask, &val);
if (nval <= 1 || nval > 2) {
ret = -EINVAL;
goto err;
}
if (list_empty(&drvdata->cfg_head[drvdata->curr_list])) {
dev_err(drvdata->dev, "DCC: No read address programmed!\n");
ret = -EPERM;
goto err;
}
entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL);
if (!entry) {
ret = -ENOMEM;
goto err;
}
entry->rd_wr_entry = true;
entry->mask = mask;
entry->rd_mod_wr = val;
entry->index = drvdata->nr_config[drvdata->curr_list]++;
INIT_LIST_HEAD(&entry->list);
list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]);
err:
mutex_unlock(&drvdata->mutex);
return ret;
}
static DEVICE_ATTR(rd_mod_wr, 0200, NULL, dcc_rd_mod_wr);
static const struct device_attribute *dcc_attrs[] = {
&dev_attr_func_type,
&dev_attr_data_sink,
&dev_attr_trigger,
&dev_attr_enable,
&dev_attr_config,
&dev_attr_config_reset,
&dev_attr_ready,
&dev_attr_crc_error,
&dev_attr_interrupt_disable,
&dev_attr_loop,
&dev_attr_rd_mod_wr,
&dev_attr_curr_list,
NULL,
};
static int dcc_create_files(struct device *dev,
const struct device_attribute **attrs)
{
int ret = 0, i;
for (i = 0; attrs[i] != NULL; i++) {
ret = device_create_file(dev, attrs[i]);
if (ret) {
dev_err(dev, "DCC: Couldn't create sysfs attribute: %s!\n",
attrs[i]->attr.name);
break;
}
}
return ret;
}
static int dcc_sram_open(struct inode *inode, struct file *file)
{
struct dcc_drvdata *drvdata = container_of(inode->i_cdev,
struct dcc_drvdata,
sram_dev);
file->private_data = drvdata;
return 0;
}
static ssize_t dcc_sram_read(struct file *file, char __user *data,
size_t len, loff_t *ppos)
{
unsigned char *buf;
struct dcc_drvdata *drvdata = file->private_data;
/* EOF check */
if (drvdata->ram_size <= *ppos)
return 0;
if ((*ppos + len) > drvdata->ram_size)
len = (drvdata->ram_size - *ppos);
buf = kzalloc(len, GFP_KERNEL);
if (!buf)
return -ENOMEM;
memcpy_fromio(buf, (drvdata->ram_base + *ppos), len);
if (copy_to_user(data, buf, len)) {
dev_err(drvdata->dev,
"DCC: Couldn't copy all data to user!\n");
kfree(buf);
return -EFAULT;
}
*ppos += len;
kfree(buf);
return len;
}
static const struct file_operations dcc_sram_fops = {
.owner = THIS_MODULE,
.open = dcc_sram_open,
.read = dcc_sram_read,
.llseek = no_llseek,
};
static int dcc_sram_dev_register(struct dcc_drvdata *drvdata)
{
int ret;
struct device *device;
dev_t dev;
ret = alloc_chrdev_region(&dev, 0, 1, drvdata->sram_node);
if (ret)
goto err_alloc;
cdev_init(&drvdata->sram_dev, &dcc_sram_fops);
drvdata->sram_dev.owner = THIS_MODULE;
ret = cdev_add(&drvdata->sram_dev, dev, 1);
if (ret)
goto err_cdev_add;
drvdata->sram_class = class_create(THIS_MODULE,
drvdata->sram_node);
if (IS_ERR(drvdata->sram_class)) {
ret = PTR_ERR(drvdata->sram_class);
goto err_class_create;
}
device = device_create(drvdata->sram_class, NULL,
drvdata->sram_dev.dev, drvdata,
drvdata->sram_node);
if (IS_ERR(device)) {
ret = PTR_ERR(device);
goto err_dev_create;
}
return 0;
err_dev_create:
class_destroy(drvdata->sram_class);
err_class_create:
cdev_del(&drvdata->sram_dev);
err_cdev_add:
unregister_chrdev_region(drvdata->sram_dev.dev, 1);
err_alloc:
return ret;
}
static void dcc_sram_dev_deregister(struct dcc_drvdata *drvdata)
{
device_destroy(drvdata->sram_class, drvdata->sram_dev.dev);
class_destroy(drvdata->sram_class);
cdev_del(&drvdata->sram_dev);
unregister_chrdev_region(drvdata->sram_dev.dev, 1);
}
static int dcc_sram_dev_init(struct dcc_drvdata *drvdata)
{
int ret = 0;
size_t node_size;
char *node_name = "dcc_sram";
struct device *dev = drvdata->dev;
node_size = strlen(node_name) + 1;
drvdata->sram_node = devm_kzalloc(dev, node_size, GFP_KERNEL);
if (!drvdata->sram_node)
return -ENOMEM;
strlcpy(drvdata->sram_node, node_name, node_size);
ret = dcc_sram_dev_register(drvdata);
if (ret)
dev_err(drvdata->dev, "DCC: sram node not registered.\n");
return ret;
}
static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata)
{
dcc_sram_dev_deregister(drvdata);
}
static void dcc_allocate_dump_mem(struct dcc_drvdata *drvdata)
{
int ret;
struct device *dev = drvdata->dev;
struct msm_dump_entry reg_dump_entry, sram_dump_entry;
/* Allocate memory for dcc reg dump */
drvdata->reg_buf = devm_kzalloc(dev, drvdata->reg_size, GFP_KERNEL);
if (drvdata->reg_buf) {
drvdata->reg_data.addr = virt_to_phys(drvdata->reg_buf);
drvdata->reg_data.len = drvdata->reg_size;
reg_dump_entry.id = MSM_DUMP_DATA_DCC_REG;
reg_dump_entry.addr = virt_to_phys(&drvdata->reg_data);
ret = msm_dump_data_register(MSM_DUMP_TABLE_APPS,
&reg_dump_entry);
if (ret) {
dev_err(dev, "DCC REG dump setup failed\n");
devm_kfree(dev, drvdata->reg_buf);
}
} else {
dev_err(dev, "DCC REG dump allocation failed\n");
}
/* Allocate memory for dcc sram dump */
drvdata->sram_buf = devm_kzalloc(dev, drvdata->ram_size, GFP_KERNEL);
if (drvdata->sram_buf) {
drvdata->sram_data.addr = virt_to_phys(drvdata->sram_buf);
drvdata->sram_data.len = drvdata->ram_size;
sram_dump_entry.id = MSM_DUMP_DATA_DCC_SRAM;
sram_dump_entry.addr = virt_to_phys(&drvdata->sram_data);
ret = msm_dump_data_register(MSM_DUMP_TABLE_APPS,
&sram_dump_entry);
if (ret) {
dev_err(dev, "DCC SRAM dump setup failed\n");
devm_kfree(dev, drvdata->sram_buf);
}
} else {
dev_err(dev, "DCC SRAM dump allocation failed\n");
}
}
static int dcc_probe(struct platform_device *pdev)
{
int ret, i;
struct device *dev = &pdev->dev;
struct dcc_drvdata *drvdata;
struct resource *res;
const char *data_sink;
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
drvdata->dev = &pdev->dev;
platform_set_drvdata(pdev, drvdata);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dcc-base");
if (!res)
return -EINVAL;
drvdata->reg_size = resource_size(res);
drvdata->base = devm_ioremap(dev, res->start, resource_size(res));
if (!drvdata->base)
return -ENOMEM;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"dcc-ram-base");
if (!res)
return -EINVAL;
drvdata->ram_size = resource_size(res);
drvdata->ram_base = devm_ioremap(dev, res->start, resource_size(res));
if (!drvdata->ram_base)
return -ENOMEM;
ret = of_property_read_u32(pdev->dev.of_node, "dcc-ram-offset",
&drvdata->ram_offset);
if (ret)
return -EINVAL;
drvdata->save_reg = of_property_read_bool(pdev->dev.of_node,
"qcom,save-reg");
mutex_init(&drvdata->mutex);
for (i = 0; i < DCC_MAX_LINK_LIST; i++) {
INIT_LIST_HEAD(&drvdata->cfg_head[i]);
drvdata->nr_config[i] = 0;
}
memset_io(drvdata->ram_base, 0, drvdata->ram_size);
drvdata->data_sink = DCC_DATA_SINK_SRAM;
ret = of_property_read_string(pdev->dev.of_node, "qcom,data-sink",
&data_sink);
if (!ret) {
for (i = 0; i < ARRAY_SIZE(str_dcc_data_sink); i++)
if (!strcmp(data_sink, str_dcc_data_sink[i])) {
drvdata->data_sink = i;
break;
}
if (i == ARRAY_SIZE(str_dcc_data_sink)) {
dev_err(dev, "Unknown sink type for DCC! Using '%s' as data sink\n",
str_dcc_data_sink[drvdata->data_sink]);
}
}
drvdata->curr_list = DCC_INVALID_LINK_LIST;
ret = dcc_sram_dev_init(drvdata);
if (ret)
goto err;
ret = dcc_create_files(dev, dcc_attrs);
if (ret)
goto err;
dcc_allocate_dump_mem(drvdata);
return 0;
err:
return ret;
}
static int dcc_remove(struct platform_device *pdev)
{
struct dcc_drvdata *drvdata = platform_get_drvdata(pdev);
dcc_sram_dev_exit(drvdata);
dcc_config_reset(drvdata);
return 0;
}
static const struct of_device_id msm_dcc_match[] = {
{ .compatible = "qcom,dcc_v2"},
{}
};
static struct platform_driver dcc_driver = {
.probe = dcc_probe,
.remove = dcc_remove,
.driver = {
.name = "msm-dcc",
.owner = THIS_MODULE,
.of_match_table = msm_dcc_match,
},
};
static int __init dcc_init(void)
{
return platform_driver_register(&dcc_driver);
}
module_init(dcc_init);
static void __exit dcc_exit(void)
{
platform_driver_unregister(&dcc_driver);
}
module_exit(dcc_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MSM data capture and compare engine");