| /* |
| * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 an |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| &soc { |
| tmc_etr: tmc@826000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b961>; |
| |
| reg = <0x826000 0x1000>, |
| <0x884000 0x15000>; |
| reg-names = "tmc-base", "bam-base"; |
| |
| interrupts = <0 166 0>; |
| interrupt-names = "byte-cntr-irq"; |
| |
| arm,buffer-size = <0x100000>; |
| arm,sg-enable; |
| |
| coresight-name = "coresight-tmc-etr"; |
| coresight-ctis = <&cti0 &cti8>; |
| coresight-csr = <&csr>; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| port { |
| tmc_etr_in_replicator: endpoint { |
| slave-mode; |
| remote-endpoint = <&replicator_out_tmc_etr>; |
| }; |
| }; |
| }; |
| |
| tmc_etf: tmc@825000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b961>; |
| |
| reg = <0x825000 0x1000>; |
| reg-names = "tmc-base"; |
| |
| coresight-name = "coresight-tmc-etf"; |
| |
| arm,default-sink; |
| coresight-ctis = <&cti0 &cti8>; |
| coresight-csr = <&csr>; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| tmc_etf_out_replicator:endpoint { |
| remote-endpoint = |
| <&replicator_in_tmc_etf>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <0>; |
| tmc_etf_in_funnel_in0: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_in0_out_tmc_etf>; |
| }; |
| }; |
| }; |
| }; |
| |
| replicator: replicator@824000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b909>; |
| |
| reg = <0x824000 0x1000>; |
| reg-names = "replicator-base"; |
| |
| coresight-name = "coresight-replicator"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| replicator_out_tmc_etr: endpoint { |
| remote-endpoint = |
| <&tmc_etr_in_replicator>; |
| }; |
| }; |
| port@1 { |
| reg = <0>; |
| replicator_in_tmc_etf: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&tmc_etf_out_replicator>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel_in0: funnel@821000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b908>; |
| |
| reg = <0x821000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-in0"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| port@0 { |
| funnel_in0_out_tmc_etf: endpoint { |
| remote-endpoint = |
| <&tmc_etf_in_funnel_in0>; |
| }; |
| }; |
| port@1 { |
| reg = <7>; |
| funnel_in0_in_stm: endpoint { |
| slave-mode; |
| remote-endpoint = <&stm_out_funnel_in0>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <3>; |
| funnel_in0_in_funnel_center: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_center_out_funnel_in0>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <4>; |
| funnel_in0_in_funnel_right: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_right_out_funnel_in0>; |
| }; |
| }; |
| |
| port@4 { |
| |
| reg = <0>; |
| funnel_in0_in_rpm_etm0: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&rpm_etm0_out_funnel_center>; |
| }; |
| }; |
| |
| port@5 { |
| reg = <1>; |
| funnel_in0_in_modem_etm0: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&modem_etm0_out_funnel_right>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel_center: funnel@869000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b908>; |
| |
| reg = <0x869000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-center"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| funnel_center_out_funnel_in0: endpoint { |
| remote-endpoint = |
| <&funnel_in0_in_funnel_center>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| funnel_center_in_dbgui: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&dbgui_out_funnel_center>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel_right: funnel@868000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b908>; |
| |
| reg = <0x868000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-right"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| funnel_right_out_funnel_in0: endpoint { |
| remote-endpoint = |
| <&funnel_in0_in_funnel_right>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| funnel_right_in_funnel_apss: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_apss_out_funnel_right>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <0>; |
| funnel_right_in_wcn_etm0: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&wcn_etm0_out_funnel_mm>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel_apss: funnel@855000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b908>; |
| |
| reg = <0x855000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-apss"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| funnel_apss_out_funnel_right: endpoint { |
| remote-endpoint = |
| <&funnel_right_in_funnel_apss>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <4>; |
| funnel_apss0_in_etm0: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&etm0_out_funnel_apss0>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <5>; |
| funnel_apss0_in_etm1: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&etm1_out_funnel_apss0>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <6>; |
| funnel_apss0_in_etm2: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&etm2_out_funnel_apss0>; |
| }; |
| }; |
| |
| port@4 { |
| reg = <7>; |
| funnel_apss0_in_etm3: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&etm3_out_funnel_apss0>; |
| }; |
| }; |
| |
| }; |
| |
| }; |
| |
| tpiu: tpiu@820000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b912>; |
| coresight-name = "coresight-tpiu"; |
| |
| reg = <0x820000 0x1000>, |
| <0x1100000 0xb0000>; |
| reg-names = "tpiu-base", "nidnt-base"; |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| etm0: etm@84c000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b955>; |
| |
| reg = <0x84c000 0x1000>; |
| cpu = <&CPU0>; |
| coresight-name = "coresight-etm0"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| port { |
| etm0_out_funnel_apss0: endpoint { |
| remote-endpoint = <&funnel_apss0_in_etm0>; |
| }; |
| }; |
| }; |
| |
| etm1: etm@84d000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b955>; |
| |
| reg = <0x84d000 0x1000>; |
| cpu = <&CPU1>; |
| coresight-name = "coresight-etm1"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| port { |
| etm1_out_funnel_apss0: endpoint { |
| remote-endpoint = <&funnel_apss0_in_etm1>; |
| }; |
| }; |
| }; |
| |
| etm2: etm@84e000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b955>; |
| |
| reg = <0x84e000 0x1000>; |
| cpu = <&CPU2>; |
| coresight-name = "coresight-etm2"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| port { |
| etm2_out_funnel_apss0: endpoint { |
| remote-endpoint = <&funnel_apss0_in_etm2>; |
| }; |
| }; |
| }; |
| |
| etm3: etm@84f000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b955>; |
| |
| reg = <0x84f000 0x1000>; |
| coresight-name = "coresight-etm3"; |
| cpu = <&CPU3>; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| port { |
| etm3_out_funnel_apss0: endpoint { |
| remote-endpoint = <&funnel_apss0_in_etm3>; |
| }; |
| }; |
| }; |
| |
| stm: stm@802000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b962>; |
| |
| reg = <0x802000 0x1000>, |
| <0x9280000 0x180000>; |
| reg-names = "stm-base", "stm-stimulus-base"; |
| |
| coresight-name = "coresight-stm"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| port { |
| stm_out_funnel_in0: endpoint { |
| remote-endpoint = <&funnel_in0_in_stm>; |
| }; |
| }; |
| }; |
| |
| cti0: cti@810000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x810000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti0"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti1: cti@811000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x811000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti1"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti2: cti@812000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x812000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti2"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti3: cti@813000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x813000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti3"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti4: cti@814000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x814000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti4"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti5: cti@815000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x815000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti5"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti6: cti@816000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x816000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti6"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti7: cti@817000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x817000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti7"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti8: cti@818000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x818000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti8"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti_cpu0: cti@851000{ |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x851000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti-cpu0"; |
| cpu = <&CPU0>; |
| qcom,cti-save; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti_cpu1: cti@852000{ |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x852000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti-cpu1"; |
| cpu = <&CPU1>; |
| qcom,cti-save; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti_cpu2: cti@853000{ |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x853000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti-cpu2"; |
| cpu = <&CPU2>; |
| qcom,cti-save; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti_cpu3: cti@854000{ |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x854000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti-cpu3"; |
| cpu = <&CPU3>; |
| qcom,cti-save; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| cti_modem_cpu0: cti@838000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x838000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti-modem-cpu0"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| /* Venus CTI */ |
| cti_video_cpu0: cti@830000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x830000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti-video-cpu0"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| /* Pronto CTI */ |
| cti_wcn_cpu0: cti@835000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b966>; |
| |
| reg = <0x835000 0x1000>; |
| reg-names = "cti-base"; |
| coresight-name = "coresight-cti-wcn-cpu0"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| wcn_etm0 { |
| compatible = "qcom,coresight-remote-etm"; |
| coresight-name = "coresight-wcn-etm0"; |
| qcom,inst-id = <3>; |
| |
| port { |
| wcn_etm0_out_funnel_mm: endpoint { |
| remote-endpoint = <&funnel_right_in_wcn_etm0>; |
| }; |
| }; |
| }; |
| |
| /* MSS_SCL */ |
| modem_etm0 { |
| compatible = "qcom,coresight-remote-etm"; |
| coresight-name = "coresight-modem-etm0"; |
| qcom,inst-id = <11>; |
| |
| port { |
| modem_etm0_out_funnel_right: endpoint { |
| remote-endpoint = <&funnel_in0_in_modem_etm0>; |
| }; |
| }; |
| }; |
| |
| rpm_etm0 { |
| compatible = "qcom,coresight-remote-etm"; |
| coresight-name = "coresight-rpm-etm0"; |
| qcom,inst-id = <4>; |
| |
| port { |
| rpm_etm0_out_funnel_center: endpoint { |
| remote-endpoint = <&funnel_in0_in_rpm_etm0>; |
| }; |
| }; |
| }; |
| |
| csr: csr@801000 { |
| compatible = "qcom,coresight-csr"; |
| reg = <0x801000 0x1000>; |
| reg-names = "csr-base"; |
| |
| coresight-name = "coresight-csr"; |
| |
| qcom,usb-bam-support; |
| qcom,hwctrl-set-support; |
| qcom,set-byte-cntr-support; |
| qcom,blk-size = <1>; |
| }; |
| |
| dbgui: dbgui@86d000 { |
| compatible = "qcom,coresight-dbgui"; |
| reg = <0x86d000 0x1000>; |
| reg-names = "dbgui-base"; |
| coresight-name = "coresight-dbgui"; |
| |
| qcom,dbgui-addr-offset = <0x30>; |
| qcom,dbgui-data-offset = <0x130>; |
| qcom,dbgui-size = <64>; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| |
| port { |
| dbgui_out_funnel_center: endpoint { |
| remote-endpoint = <&funnel_center_in_dbgui>; |
| }; |
| }; |
| }; |
| |
| hwevent: hwevent@86c000 { |
| compatible = "qcom,coresight-hwevent"; |
| |
| reg = <0x86c000 0x108>, |
| <0x86cfb0 0x4>, |
| <0x78c5010 0x4>, |
| <0x7885010 0x4>; |
| |
| reg-names = "center-wrapper-mux", "center-wrapper-lockaccess", |
| "right-wrapper-mux", "right-wrapper-lockaccess"; |
| |
| coresight-csr = <&csr>; |
| coresight-name = "coresight-hwevent"; |
| |
| clocks = <&clock_rpm clk_qdss_clk>, |
| <&clock_rpm clk_qdss_a_clk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| }; |