| /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include "skeleton64.dtsi" |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,camcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,gpucc-sdm845.h> |
| #include <dt-bindings/clock/qcom,videocc-sdm845.h> |
| #include <dt-bindings/clock/qcom,cpucc-sdm845.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/soc/qcom,tcs-mbox.h> |
| #include <dt-bindings/regulator/qcom,rpmh-regulator.h> |
| #include <dt-bindings/clock/qcom,aop-qmp.h> |
| |
| / { |
| model = "Qualcomm Technologies, Inc. SDM670"; |
| compatible = "qcom,sdm670"; |
| qcom,msm-id = <336 0x0>; |
| interrupt-parent = <&pdc>; |
| |
| aliases { |
| ufshc1 = &ufshc_mem; /* Embedded UFS slot */ |
| sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ |
| sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ |
| serial0 = &qupv3_se12_2uart; |
| spi0 = &qupv3_se8_spi; |
| i2c0 = &qupv3_se10_i2c; |
| i2c1 = &qupv3_se3_i2c; |
| hsuart0 = &qupv3_se6_4uart; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_0>; |
| L2_0: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| L3_0: l3-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x100000>; |
| cache-level = <3>; |
| }; |
| }; |
| L1_I_0: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_0: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_TLB_0: l1-tlb { |
| qcom,dump-size = <0x3000>; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_100>; |
| L2_100: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_100: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_100: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_TLB_100: l1-tlb { |
| qcom,dump-size = <0x3000>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_200>; |
| L2_200: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_200: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_200: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_TLB_200: l1-tlb { |
| qcom,dump-size = <0x3000>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_300>; |
| L2_300: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_300: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_300: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_TLB_300: l1-tlb { |
| qcom,dump-size = <0x3000>; |
| }; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_400>; |
| L2_400: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_400: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_400: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_TLB_400: l1-tlb { |
| qcom,dump-size = <0x3000>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| efficiency = <1024>; |
| cache-size = <0x8000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_500>; |
| L2_500: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_500: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_D_500: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| L1_TLB_500: l1-tlb { |
| qcom,dump-size = <0x3000>; |
| }; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x600>; |
| enable-method = "psci"; |
| efficiency = <1740>; |
| cache-size = <0x10000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_600>; |
| L2_600: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x40000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_600: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x12000>; |
| }; |
| L1_D_600: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x12000>; |
| }; |
| L1_TLB_600: l1-tlb { |
| qcom,dump-size = <0x3c000>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x700>; |
| enable-method = "psci"; |
| efficiency = <1740>; |
| cache-size = <0x10000>; |
| cpu-release-addr = <0x0 0x90000000>; |
| next-level-cache = <&L2_700>; |
| L2_700: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x40000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| L1_I_700: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x12000>; |
| }; |
| L1_D_700: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x12000>; |
| }; |
| L1_TLB_700: l1-tlb { |
| qcom,dump-size = <0x3c000>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| |
| core4 { |
| cpu = <&CPU4>; |
| }; |
| |
| core5 { |
| cpu = <&CPU5>; |
| }; |
| }; |
| cluster1 { |
| core0 { |
| cpu = <&CPU6>; |
| }; |
| |
| core1 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| soc: soc { }; |
| |
| vendor: vendor { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| }; |
| |
| firmware: firmware { |
| android { |
| compatible = "android,firmware"; |
| |
| fstab { |
| compatible = "android,fstab"; |
| vendor { |
| compatible = "android,vendor"; |
| dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; |
| type = "ext4"; |
| mnt_flags = "ro,barrier=1,discard"; |
| fsmgr_flags = "wait,slotselect"; |
| }; |
| }; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| removed_regions: removed_regions@85700000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x85700000 0 0x3800000>; |
| }; |
| |
| pil_camera_mem: camera_region@8ab00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x8ab00000 0 0x500000>; |
| }; |
| |
| pil_modem_mem: modem_region@8b000000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x8b000000 0 0x7e00000>; |
| }; |
| |
| pil_video_mem: pil_video_region@92e00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x92e00000 0 0x500000>; |
| }; |
| |
| pil_cdsp_mem: cdsp_regions@93300000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x93300000 0 0x800000>; |
| }; |
| |
| pil_mba_mem: pil_mba_region@0x93b00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x93b00000 0 0x200000>; |
| }; |
| |
| pil_adsp_mem: pil_adsp_region@93d00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x93d00000 0 0x1e00000>; |
| }; |
| |
| pil_ipa_fw_mem: pil_ipa_fw_region@95b00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x95b00000 0 0x10000>; |
| }; |
| |
| pil_ipa_gsi_mem: pil_ipa_gsi_region@95b10000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x95b10000 0 0x5000>; |
| }; |
| |
| pil_gpu_mem: pil_gpu_region@95b15000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0 0x95b15000 0 0x1000>; |
| }; |
| |
| adsp_mem: adsp_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0xc00000>; |
| }; |
| |
| qseecom_mem: qseecom_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0x1400000>; |
| }; |
| |
| sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0x800000>; |
| }; |
| |
| secure_display_memory: secure_display_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0x5c00000>; |
| }; |
| |
| /* global autoconfigured region for contiguous allocations */ |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0x2000000>; |
| linux,cma-default; |
| }; |
| }; |
| }; |
| |
| #include "sdm670-ion.dtsi" |
| |
| #include "sdm670-smp2p.dtsi" |
| |
| #include "sdm670-qupv3.dtsi" |
| |
| #include "sdm670-coresight.dtsi" |
| &soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x20000>; |
| reg = <0x17a00000 0x10000>, /* GICD */ |
| <0x17a60000 0x100000>; /* GICR * 8 */ |
| interrupts = <1 9 4>; |
| interrupt-parent = <&intc>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 1 0xf08>, |
| <1 2 0xf08>, |
| <1 3 0xf08>, |
| <1 0 0xf08>; |
| clock-frequency = <19200000>; |
| }; |
| |
| qcom,sps { |
| compatible = "qcom,msm_sps_4k"; |
| qcom,pipe-attr-ee; |
| }; |
| |
| thermal_zones: thermal-zones { |
| aoss0-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-governor = "user_space"; |
| thermal-sensors = <&tsens0 0>; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| cpu0-silver-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-governor = "user_space"; |
| thermal-sensors = <&tsens0 1>; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| cpu1-silver-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-governor = "user_space"; |
| thermal-sensors = <&tsens0 2>; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| cpu2-silver-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-governor = "user_space"; |
| thermal-sensors = <&tsens0 3>; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| cpu3-silver-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens0 4>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| cpu4-silver-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens0 5>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| cpu5-silver-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens0 6>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| kryo-l3-0-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens0 7>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| kryo-l3-1-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens0 8>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| cpu0-gold-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens0 9>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| cpu1-gold-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens0 10>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| gpu0-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens0 11>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| gpu1-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-governor = "user_space"; |
| thermal-sensors = <&tsens0 12>; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| aoss1-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens1 0>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| mdm-dsp-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens1 1>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| ddr-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens1 2>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| wlan-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens1 3>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| compute-hvx-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens1 4>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| camera-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens1 5>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| mmss-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens1 6>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| |
| mdm-core-usr { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tsens1 7>; |
| thermal-governor = "user_space"; |
| trips { |
| active-config0 { |
| temperature = <125000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| }; |
| }; |
| }; |
| |
| tsens0: tsens@c222000 { |
| compatible = "qcom,tsens24xx"; |
| reg = <0xc222000 0x4>, |
| <0xc263000 0x1ff>; |
| reg-names = "tsens_srot_physical", |
| "tsens_tm_physical"; |
| interrupts = <0 506 0>, <0 508 0>; |
| interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| tsens1: tsens@c223000 { |
| compatible = "qcom,tsens24xx"; |
| reg = <0xc223000 0x4>, |
| <0xc265000 0x1ff>; |
| reg-names = "tsens_srot_physical", |
| "tsens_tm_physical"; |
| interrupts = <0 507 0>, <0 509 0>; |
| interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| timer@0x17c90000{ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x17c90000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@0x17ca0000 { |
| frame-number = <0>; |
| interrupts = <0 7 0x4>, |
| <0 6 0x4>; |
| reg = <0x17ca0000 0x1000>, |
| <0x17cb0000 0x1000>; |
| }; |
| |
| frame@17cc0000 { |
| frame-number = <1>; |
| interrupts = <0 8 0x4>; |
| reg = <0x17cc0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17cd0000 { |
| frame-number = <2>; |
| interrupts = <0 9 0x4>; |
| reg = <0x17cd0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17ce0000 { |
| frame-number = <3>; |
| interrupts = <0 10 0x4>; |
| reg = <0x17ce0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17cf0000 { |
| frame-number = <4>; |
| interrupts = <0 11 0x4>; |
| reg = <0x17cf0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17d00000 { |
| frame-number = <5>; |
| interrupts = <0 12 0x4>; |
| reg = <0x17d00000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17d10000 { |
| frame-number = <6>; |
| interrupts = <0 13 0x4>; |
| reg = <0x17d10000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| restart@10ac000 { |
| compatible = "qcom,pshold"; |
| reg = <0xC264000 0x4>, |
| <0x1fd3000 0x4>; |
| reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| }; |
| |
| aop-msg-client { |
| compatible = "qcom,debugfs-qmp-client"; |
| mboxes = <&qmp_aop 0>; |
| mbox-names = "aop"; |
| }; |
| |
| clock_rpmh: qcom,rpmhclk { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "rpmh_clocks"; |
| #clock-cells = <1>; |
| }; |
| |
| clock_gcc: qcom,gcc@100000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "gcc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_videocc: qcom,videocc@ab00000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "videocc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_camcc: qcom,camcc@ad00000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "camcc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_dispcc: qcom,dispcc@af00000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "dispcc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_gpucc: qcom,gpucc@5090000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "gpucc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_gfx: qcom,gfxcc@5090000 { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "gfxcc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_cpucc: qcom,cpucc { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "cpucc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_aop: qcom,aopclk { |
| compatible = "qcom,aop-qmp-clk-v2"; |
| #clock-cells = <1>; |
| mboxes = <&qmp_aop 0>; |
| mbox-names = "qdss_clk"; |
| }; |
| |
| slim_aud: slim@62dc0000 { |
| cell-index = <1>; |
| compatible = "qcom,slim-ngd"; |
| reg = <0x62dc0000 0x2c000>, |
| <0x62d84000 0x2a000>; |
| reg-names = "slimbus_physical", "slimbus_bam_physical"; |
| interrupts = <0 163 0>, <0 164 0>; |
| interrupt-names = "slimbus_irq", "slimbus_bam_irq"; |
| qcom,apps-ch-pipes = <0x780000>; |
| qcom,ea-pc = <0x290>; |
| status = "disabled"; |
| }; |
| |
| slim_qca: slim@62e40000 { |
| cell-index = <3>; |
| compatible = "qcom,slim-ngd"; |
| reg = <0x62e40000 0x2c000>, |
| <0x62e04000 0x20000>; |
| reg-names = "slimbus_physical", "slimbus_bam_physical"; |
| interrupts = <0 291 0>, <0 292 0>; |
| interrupt-names = "slimbus_irq", "slimbus_bam_irq"; |
| status = "disabled"; |
| }; |
| |
| wdog: qcom,wdt@17980000{ |
| compatible = "qcom,msm-watchdog"; |
| reg = <0x17980000 0x1000>; |
| reg-names = "wdt-base"; |
| interrupts = <0 3 0>, <0 4 0>; |
| qcom,bark-time = <11000>; |
| qcom,pet-time = <10000>; |
| qcom,ipi-ping; |
| qcom,wakeup-enable; |
| }; |
| |
| qcom,msm-rtb { |
| compatible = "qcom,msm-rtb"; |
| qcom,rtb-size = <0x100000>; |
| }; |
| |
| qcom,msm-imem@146bf000 { |
| compatible = "qcom,msm-imem"; |
| reg = <0x146bf000 0x1000>; |
| ranges = <0x0 0x146bf000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mem_dump_table@10 { |
| compatible = "qcom,msm-imem-mem_dump_table"; |
| reg = <0x10 8>; |
| }; |
| |
| restart_reason@65c { |
| compatible = "qcom,msm-imem-restart_reason"; |
| reg = <0x65c 4>; |
| }; |
| |
| pil@94c { |
| compatible = "qcom,msm-imem-pil"; |
| reg = <0x94c 200>; |
| }; |
| |
| kaslr_offset@6d0 { |
| compatible = "qcom,msm-imem-kaslr_offset"; |
| reg = <0x6d0 12>; |
| }; |
| }; |
| |
| gpi_dma0: qcom,gpi-dma@0x800000 { |
| #dma-cells = <6>; |
| compatible = "qcom,gpi-dma"; |
| reg = <0x800000 0x60000>; |
| reg-names = "gpi-top"; |
| interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, |
| <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>, |
| <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>, |
| <0 256 0>; |
| qcom,max-num-gpii = <13>; |
| qcom,gpii-mask = <0xfa>; |
| qcom,ev-factor = <2>; |
| iommus = <&apps_smmu 0x0016 0x0>; |
| status = "ok"; |
| }; |
| |
| gpi_dma1: qcom,gpi-dma@0xa00000 { |
| #dma-cells = <6>; |
| compatible = "qcom,gpi-dma"; |
| reg = <0xa00000 0x60000>; |
| reg-names = "gpi-top"; |
| interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>, |
| <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>, |
| <0 295 0>, <0 296 0>, <0 297 0>, <0 298 0>, |
| <0 299 0>; |
| qcom,max-num-gpii = <13>; |
| qcom,gpii-mask = <0xfa>; |
| qcom,ev-factor = <2>; |
| iommus = <&apps_smmu 0x06d6 0x0>; |
| status = "ok"; |
| }; |
| |
| cpuss_dump { |
| compatible = "qcom,cpuss-dump"; |
| qcom,l1_i_cache0 { |
| qcom,dump-node = <&L1_I_0>; |
| qcom,dump-id = <0x60>; |
| }; |
| qcom,l1_i_cache100 { |
| qcom,dump-node = <&L1_I_100>; |
| qcom,dump-id = <0x61>; |
| }; |
| qcom,l1_i_cache200 { |
| qcom,dump-node = <&L1_I_200>; |
| qcom,dump-id = <0x62>; |
| }; |
| qcom,l1_i_cache300 { |
| qcom,dump-node = <&L1_I_300>; |
| qcom,dump-id = <0x63>; |
| }; |
| qcom,l1_i_cache400 { |
| qcom,dump-node = <&L1_I_400>; |
| qcom,dump-id = <0x64>; |
| }; |
| qcom,l1_i_cache500 { |
| qcom,dump-node = <&L1_I_500>; |
| qcom,dump-id = <0x65>; |
| }; |
| qcom,l1_i_cache600 { |
| qcom,dump-node = <&L1_I_600>; |
| qcom,dump-id = <0x66>; |
| }; |
| qcom,l1_i_cache700 { |
| qcom,dump-node = <&L1_I_700>; |
| qcom,dump-id = <0x67>; |
| }; |
| qcom,l1_d_cache0 { |
| qcom,dump-node = <&L1_D_0>; |
| qcom,dump-id = <0x80>; |
| }; |
| qcom,l1_d_cache100 { |
| qcom,dump-node = <&L1_D_100>; |
| qcom,dump-id = <0x81>; |
| }; |
| qcom,l1_d_cache200 { |
| qcom,dump-node = <&L1_D_200>; |
| qcom,dump-id = <0x82>; |
| }; |
| qcom,l1_d_cache300 { |
| qcom,dump-node = <&L1_D_300>; |
| qcom,dump-id = <0x83>; |
| }; |
| qcom,l1_d_cache400 { |
| qcom,dump-node = <&L1_D_400>; |
| qcom,dump-id = <0x84>; |
| }; |
| qcom,l1_d_cache500 { |
| qcom,dump-node = <&L1_D_500>; |
| qcom,dump-id = <0x85>; |
| }; |
| qcom,l1_d_cache600 { |
| qcom,dump-node = <&L1_D_600>; |
| qcom,dump-id = <0x86>; |
| }; |
| qcom,l1_d_cache700 { |
| qcom,dump-node = <&L1_D_700>; |
| qcom,dump-id = <0x87>; |
| }; |
| qcom,llcc1_d_cache { |
| qcom,dump-node = <&LLCC_1>; |
| qcom,dump-id = <0x140>; |
| }; |
| qcom,llcc2_d_cache { |
| qcom,dump-node = <&LLCC_2>; |
| qcom,dump-id = <0x141>; |
| }; |
| qcom,l1_tlb_dump0 { |
| qcom,dump-node = <&L1_TLB_0>; |
| qcom,dump-id = <0x20>; |
| }; |
| qcom,l1_tlb_dump100 { |
| qcom,dump-node = <&L1_TLB_100>; |
| qcom,dump-id = <0x21>; |
| }; |
| qcom,l1_tlb_dump200 { |
| qcom,dump-node = <&L1_TLB_200>; |
| qcom,dump-id = <0x22>; |
| }; |
| qcom,l1_tlb_dump300 { |
| qcom,dump-node = <&L1_TLB_300>; |
| qcom,dump-id = <0x23>; |
| }; |
| qcom,l1_tlb_dump400 { |
| qcom,dump-node = <&L1_TLB_400>; |
| qcom,dump-id = <0x24>; |
| }; |
| qcom,l1_tlb_dump500 { |
| qcom,dump-node = <&L1_TLB_500>; |
| qcom,dump-id = <0x25>; |
| }; |
| qcom,l1_tlb_dump600 { |
| qcom,dump-node = <&L1_TLB_600>; |
| qcom,dump-id = <0x26>; |
| }; |
| qcom,l1_tlb_dump700 { |
| qcom,dump-node = <&L1_TLB_700>; |
| qcom,dump-id = <0x27>; |
| }; |
| }; |
| |
| kryo3xx-erp { |
| compatible = "arm,arm64-kryo3xx-cpu-erp"; |
| interrupts = <1 6 4>, |
| <1 7 4>, |
| <0 34 4>, |
| <0 35 4>; |
| |
| interrupt-names = "l1-l2-faultirq", |
| "l1-l2-errirq", |
| "l3-scu-errirq", |
| "l3-scu-faultirq"; |
| }; |
| |
| qcom,ipc-spinlock@1f40000 { |
| compatible = "qcom,ipc-spinlock-sfpb"; |
| reg = <0x1f40000 0x8000>; |
| qcom,num-locks = <8>; |
| }; |
| |
| qcom,smem@86000000 { |
| compatible = "qcom,smem"; |
| reg = <0x86000000 0x200000>, |
| <0x17911008 0x4>, |
| <0x778000 0x7000>, |
| <0x1fd4000 0x8>; |
| reg-names = "smem", "irq-reg-base", "aux-mem1", |
| "smem_targ_info_reg"; |
| qcom,mpu-enabled; |
| }; |
| |
| qmp_aop: qcom,qmp-aop@c300000 { |
| compatible = "qcom,qmp-mbox"; |
| label = "aop"; |
| reg = <0xc300000 0x100000>, |
| <0x1799000c 0x4>; |
| reg-names = "msgram", "irq-reg-base"; |
| qcom,irq-mask = <0x1>; |
| interrupts = <0 389 1>; |
| priority = <0>; |
| mbox-desc-offset = <0x0>; |
| #mbox-cells = <1>; |
| }; |
| |
| qcom,glink-smem-native-xprt-modem@86000000 { |
| compatible = "qcom,glink-smem-native-xprt"; |
| reg = <0x86000000 0x200000>, |
| <0x1799000c 0x4>; |
| reg-names = "smem", "irq-reg-base"; |
| qcom,irq-mask = <0x1000>; |
| interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; |
| label = "mpss"; |
| }; |
| |
| qcom,glink-smem-native-xprt-adsp@86000000 { |
| compatible = "qcom,glink-smem-native-xprt"; |
| reg = <0x86000000 0x200000>, |
| <0x1799000c 0x4>; |
| reg-names = "smem", "irq-reg-base"; |
| qcom,irq-mask = <0x1000000>; |
| interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; |
| label = "lpass"; |
| qcom,qos-config = <&glink_qos_adsp>; |
| qcom,ramp-time = <0xaf>; |
| }; |
| |
| glink_qos_adsp: qcom,glink-qos-config-adsp { |
| compatible = "qcom,glink-qos-config"; |
| qcom,flow-info = <0x3c 0x0>, |
| <0x3c 0x0>, |
| <0x3c 0x0>, |
| <0x3c 0x0>; |
| qcom,mtu-size = <0x800>; |
| qcom,tput-stats-cycle = <0xa>; |
| }; |
| |
| glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp { |
| compatible = "qcom,glink-spi-xprt"; |
| label = "wdsp"; |
| qcom,remote-fifo-config = <&glink_fifo_wdsp>; |
| qcom,qos-config = <&glink_qos_wdsp>; |
| qcom,ramp-time = <0x10>, |
| <0x20>, |
| <0x30>, |
| <0x40>; |
| }; |
| |
| glink_fifo_wdsp: qcom,glink-fifo-config-wdsp { |
| compatible = "qcom,glink-fifo-config"; |
| qcom,out-read-idx-reg = <0x12000>; |
| qcom,out-write-idx-reg = <0x12004>; |
| qcom,in-read-idx-reg = <0x1200C>; |
| qcom,in-write-idx-reg = <0x12010>; |
| }; |
| |
| glink_qos_wdsp: qcom,glink-qos-config-wdsp { |
| compatible = "qcom,glink-qos-config"; |
| qcom,flow-info = <0x80 0x0>, |
| <0x70 0x1>, |
| <0x60 0x2>, |
| <0x50 0x3>; |
| qcom,mtu-size = <0x800>; |
| qcom,tput-stats-cycle = <0xa>; |
| }; |
| |
| qcom,glink-smem-native-xprt-cdsp@86000000 { |
| compatible = "qcom,glink-smem-native-xprt"; |
| reg = <0x86000000 0x200000>, |
| <0x1799000c 0x4>; |
| reg-names = "smem", "irq-reg-base"; |
| qcom,irq-mask = <0x10>; |
| interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; |
| label = "cdsp"; |
| }; |
| |
| glink_mpss: qcom,glink-ssr-modem { |
| compatible = "qcom,glink_ssr"; |
| label = "modem"; |
| qcom,edge = "mpss"; |
| qcom,notify-edges = <&glink_lpass>, <&glink_cdsp>; |
| qcom,xprt = "smem"; |
| }; |
| |
| glink_lpass: qcom,glink-ssr-adsp { |
| compatible = "qcom,glink_ssr"; |
| label = "adsp"; |
| qcom,edge = "lpass"; |
| qcom,notify-edges = <&glink_mpss>, <&glink_cdsp>; |
| qcom,xprt = "smem"; |
| }; |
| |
| glink_cdsp: qcom,glink-ssr-cdsp { |
| compatible = "qcom,glink_ssr"; |
| label = "cdsp"; |
| qcom,edge = "cdsp"; |
| qcom,notify-edges = <&glink_mpss>, <&glink_lpass>; |
| qcom,xprt = "smem"; |
| }; |
| |
| qcom,ipc_router { |
| compatible = "qcom,ipc_router"; |
| qcom,node-id = <1>; |
| }; |
| |
| qcom,ipc_router_modem_xprt { |
| compatible = "qcom,ipc_router_glink_xprt"; |
| qcom,ch-name = "IPCRTR"; |
| qcom,xprt-remote = "mpss"; |
| qcom,glink-xprt = "smem"; |
| qcom,xprt-linkid = <1>; |
| qcom,xprt-version = <1>; |
| qcom,fragmented-data; |
| }; |
| |
| qcom,ipc_router_q6_xprt { |
| compatible = "qcom,ipc_router_glink_xprt"; |
| qcom,ch-name = "IPCRTR"; |
| qcom,xprt-remote = "lpass"; |
| qcom,glink-xprt = "smem"; |
| qcom,xprt-linkid = <1>; |
| qcom,xprt-version = <1>; |
| qcom,fragmented-data; |
| }; |
| |
| qcom,ipc_router_cdsp_xprt { |
| compatible = "qcom,ipc_router_glink_xprt"; |
| qcom,ch-name = "IPCRTR"; |
| qcom,xprt-remote = "cdsp"; |
| qcom,glink-xprt = "smem"; |
| qcom,xprt-linkid = <1>; |
| qcom,xprt-version = <1>; |
| qcom,fragmented-data; |
| }; |
| |
| qcom,glink_pkt { |
| compatible = "qcom,glinkpkt"; |
| |
| qcom,glinkpkt-at-mdm0 { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DS"; |
| qcom,glinkpkt-dev-name = "at_mdm0"; |
| }; |
| |
| qcom,glinkpkt-loopback_cntl { |
| qcom,glinkpkt-transport = "lloop"; |
| qcom,glinkpkt-edge = "local"; |
| qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; |
| qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; |
| }; |
| |
| qcom,glinkpkt-loopback_data { |
| qcom,glinkpkt-transport = "lloop"; |
| qcom,glinkpkt-edge = "local"; |
| qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; |
| qcom,glinkpkt-dev-name = "glink_pkt_loopback"; |
| }; |
| |
| qcom,glinkpkt-apr-apps2 { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "adsp"; |
| qcom,glinkpkt-ch-name = "apr_apps2"; |
| qcom,glinkpkt-dev-name = "apr_apps2"; |
| }; |
| |
| qcom,glinkpkt-data40-cntl { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA40_CNTL"; |
| qcom,glinkpkt-dev-name = "smdcntl8"; |
| }; |
| |
| qcom,glinkpkt-data1 { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA1"; |
| qcom,glinkpkt-dev-name = "smd7"; |
| }; |
| |
| qcom,glinkpkt-data4 { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA4"; |
| qcom,glinkpkt-dev-name = "smd8"; |
| }; |
| |
| qcom,glinkpkt-data11 { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA11"; |
| qcom,glinkpkt-dev-name = "smd11"; |
| }; |
| }; |
| |
| qcom,chd_sliver { |
| compatible = "qcom,core-hang-detect"; |
| label = "silver"; |
| qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058 |
| 0x17e30058 0x17e40058 0x17e50058>; |
| qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060 |
| 0x17e30060 0x17e40060 0x17e50060>; |
| }; |
| |
| qcom,chd_gold { |
| compatible = "qcom,core-hang-detect"; |
| label = "gold"; |
| qcom,threshold-arr = <0x17e60058 0x17e70058>; |
| qcom,config-arr = <0x17e60060 0x17e70060>; |
| }; |
| |
| qcom,ghd { |
| compatible = "qcom,gladiator-hang-detect-v2"; |
| qcom,threshold-arr = <0x1799041c 0x17990420>; |
| qcom,config-reg = <0x17990434>; |
| }; |
| |
| qcom,msm-gladiator-v3@17900000 { |
| compatible = "qcom,msm-gladiator-v3"; |
| reg = <0x17900000 0xd080>; |
| reg-names = "gladiator_base"; |
| interrupts = <0 17 0>; |
| }; |
| |
| qcom,llcc@1100000 { |
| compatible = "qcom,llcc-core", "syscon", "simple-mfd"; |
| reg = <0x1100000 0x250000>; |
| reg-names = "llcc_base"; |
| qcom,llcc-banks-off = <0x0 0x80000 >; |
| qcom,llcc-broadcast-off = <0x200000>; |
| |
| llcc: qcom,sdm670-llcc { |
| compatible = "qcom,sdm670-llcc"; |
| #cache-cells = <1>; |
| max-slices = <32>; |
| qcom,dump-size = <0x80000>; |
| }; |
| |
| qcom,llcc-erp { |
| compatible = "qcom,llcc-erp"; |
| interrupt-names = "ecc_irq"; |
| interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| qcom,llcc-amon { |
| compatible = "qcom,llcc-amon"; |
| }; |
| |
| LLCC_1: llcc_1_dcache { |
| qcom,dump-size = <0xd8000>; |
| }; |
| |
| LLCC_2: llcc_2_dcache { |
| qcom,dump-size = <0xd8000>; |
| }; |
| }; |
| |
| cmd_db: qcom,cmd-db@c3f000c { |
| compatible = "qcom,cmd-db"; |
| reg = <0xc3f000c 0x8>; |
| }; |
| |
| apps_rsc: mailbox@179e0000 { |
| compatible = "qcom,tcs-drv"; |
| label = "apps_rsc"; |
| reg = <0x179e0000 0x100>, <0x179e0d00 0x3000>; |
| interrupts = <0 5 0>; |
| #mbox-cells = <1>; |
| qcom,drv-id = <2>; |
| qcom,tcs-config = <ACTIVE_TCS 2>, |
| <SLEEP_TCS 3>, |
| <WAKE_TCS 3>, |
| <CONTROL_TCS 1>; |
| }; |
| |
| disp_rsc: mailbox@af20000 { |
| compatible = "qcom,tcs-drv"; |
| label = "display_rsc"; |
| reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>; |
| interrupts = <0 129 0>; |
| #mbox-cells = <1>; |
| qcom,drv-id = <0>; |
| qcom,tcs-config = <SLEEP_TCS 1>, |
| <WAKE_TCS 1>, |
| <ACTIVE_TCS 0>, |
| <CONTROL_TCS 1>; |
| }; |
| |
| system_pm { |
| compatible = "qcom,system-pm"; |
| mboxes = <&apps_rsc 0>; |
| }; |
| |
| dcc: dcc_v2@10a2000 { |
| compatible = "qcom,dcc_v2"; |
| reg = <0x10a2000 0x1000>, |
| <0x10ae000 0x2000>; |
| reg-names = "dcc-base", "dcc-ram-base"; |
| |
| dcc-ram-offset = <0x6000>; |
| }; |
| |
| spmi_bus: qcom,spmi@c440000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0xc440000 0x1100>, |
| <0xc600000 0x2000000>, |
| <0xe600000 0x100000>, |
| <0xe700000 0xa0000>, |
| <0xc40a000 0x26000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| cell-index = <0>; |
| }; |
| |
| ufsphy_mem: ufsphy_mem@1d87000 { |
| reg = <0x1d87000 0xe00>; /* PHY regs */ |
| reg-names = "phy_mem"; |
| #phy-cells = <0>; |
| |
| lanes-per-direction = <1>; |
| |
| clock-names = "ref_clk_src", |
| "ref_clk", |
| "ref_aux_clk"; |
| clocks = <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, |
| <&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>; |
| |
| status = "disabled"; |
| }; |
| |
| ufshc_mem: ufshc@1d84000 { |
| compatible = "qcom,ufshc"; |
| reg = <0x1d84000 0x3000>; |
| interrupts = <0 265 0>; |
| phys = <&ufsphy_mem>; |
| phy-names = "ufsphy"; |
| |
| lanes-per-direction = <1>; |
| dev-ref-clk-freq = <0>; /* 19.2 MHz */ |
| |
| clock-names = |
| "core_clk", |
| "bus_aggr_clk", |
| "iface_clk", |
| "core_clk_unipro", |
| "core_clk_ice", |
| "ref_clk", |
| "tx_lane0_sync_clk", |
| "rx_lane0_sync_clk"; |
| clocks = |
| <&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>, |
| <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK>, |
| <&clock_gcc GCC_UFS_PHY_AHB_CLK>, |
| <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>, |
| <&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>, |
| <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; |
| freq-table-hz = |
| <50000000 200000000>, |
| <0 0>, |
| <0 0>, |
| <37500000 150000000>, |
| <75000000 300000000>, |
| <0 0>, |
| <0 0>, |
| <0 0>; |
| |
| resets = <&clock_gcc GCC_UFS_PHY_BCR>; |
| reset-names = "core_reset"; |
| |
| status = "disabled"; |
| }; |
| |
| qcom,lpass@62400000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x62400000 0x00100>; |
| interrupts = <0 162 1>; |
| |
| vdd_cx-supply = <&pm660l_l9_level>; |
| qcom,proxy-reg-names = "vdd_cx"; |
| qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| |
| clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| |
| qcom,pas-id = <1>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,smem-id = <423>; |
| qcom,sysmon-id = <1>; |
| qcom,ssctl-instance-id = <0x14>; |
| qcom,firmware-name = "adsp"; |
| memory-region = <&pil_adsp_mem>; |
| |
| /* GPIO inputs from lpass */ |
| qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; |
| qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; |
| qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; |
| qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>; |
| |
| /* GPIO output to lpass */ |
| qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; |
| status = "ok"; |
| }; |
| |
| qcom,rmnet-ipa { |
| compatible = "qcom,rmnet-ipa3"; |
| qcom,rmnet-ipa-ssr; |
| qcom,ipa-loaduC; |
| qcom,ipa-advertise-sg-support; |
| qcom,ipa-napi-enable; |
| }; |
| |
| ipa_hw: qcom,ipa@01e00000 { |
| compatible = "qcom,ipa"; |
| reg = <0x1e00000 0x34000>, |
| <0x1e04000 0x2c000>; |
| reg-names = "ipa-base", "gsi-base"; |
| interrupts = |
| <0 311 0>, |
| <0 432 0>; |
| interrupt-names = "ipa-irq", "gsi-irq"; |
| qcom,ipa-hw-ver = <13>; /* IPA core version = IPAv3.5.1 */ |
| qcom,ipa-hw-mode = <1>; |
| qcom,ee = <0>; |
| qcom,use-ipa-tethering-bridge; |
| qcom,modem-cfg-emb-pipe-flt; |
| qcom,ipa-wdi2; |
| qcom,use-64-bit-dma-mask; |
| qcom,arm-smmu; |
| qcom,smmu-s1-bypass; |
| qcom,bandwidth-vote-for-ipa; |
| qcom,msm-bus,name = "ipa"; |
| qcom,msm-bus,num-cases = <4>; |
| qcom,msm-bus,num-paths = <4>; |
| qcom,msm-bus,vectors-KBps = |
| /* No vote */ |
| <90 512 0 0>, |
| <90 585 0 0>, |
| <1 676 0 0>, |
| <143 777 0 0>, |
| /* SVS */ |
| <90 512 80000 640000>, |
| <90 585 80000 640000>, |
| <1 676 80000 80000>, |
| <143 777 0 150000>, |
| /* NOMINAL */ |
| <90 512 206000 960000>, |
| <90 585 206000 960000>, |
| <1 676 206000 160000>, |
| <143 777 0 300000>, |
| /* TURBO */ |
| <90 512 206000 3600000>, |
| <90 585 206000 3600000>, |
| <1 676 206000 300000>, |
| <143 777 0 355333>; |
| qcom,bus-vector-names = "MIN", "SVS", "NOMINAL", "TURBO"; |
| |
| /* IPA RAM mmap */ |
| qcom,ipa-ram-mmap = < |
| 0x280 /* ofst_start; */ |
| 0x0 /* nat_ofst; */ |
| 0x0 /* nat_size; */ |
| 0x288 /* v4_flt_hash_ofst; */ |
| 0x78 /* v4_flt_hash_size; */ |
| 0x4000 /* v4_flt_hash_size_ddr; */ |
| 0x308 /* v4_flt_nhash_ofst; */ |
| 0x78 /* v4_flt_nhash_size; */ |
| 0x4000 /* v4_flt_nhash_size_ddr; */ |
| 0x388 /* v6_flt_hash_ofst; */ |
| 0x78 /* v6_flt_hash_size; */ |
| 0x4000 /* v6_flt_hash_size_ddr; */ |
| 0x408 /* v6_flt_nhash_ofst; */ |
| 0x78 /* v6_flt_nhash_size; */ |
| 0x4000 /* v6_flt_nhash_size_ddr; */ |
| 0xf /* v4_rt_num_index; */ |
| 0x0 /* v4_modem_rt_index_lo; */ |
| 0x7 /* v4_modem_rt_index_hi; */ |
| 0x8 /* v4_apps_rt_index_lo; */ |
| 0xe /* v4_apps_rt_index_hi; */ |
| 0x488 /* v4_rt_hash_ofst; */ |
| 0x78 /* v4_rt_hash_size; */ |
| 0x4000 /* v4_rt_hash_size_ddr; */ |
| 0x508 /* v4_rt_nhash_ofst; */ |
| 0x78 /* v4_rt_nhash_size; */ |
| 0x4000 /* v4_rt_nhash_size_ddr; */ |
| 0xf /* v6_rt_num_index; */ |
| 0x0 /* v6_modem_rt_index_lo; */ |
| 0x7 /* v6_modem_rt_index_hi; */ |
| 0x8 /* v6_apps_rt_index_lo; */ |
| 0xe /* v6_apps_rt_index_hi; */ |
| 0x588 /* v6_rt_hash_ofst; */ |
| 0x78 /* v6_rt_hash_size; */ |
| 0x4000 /* v6_rt_hash_size_ddr; */ |
| 0x608 /* v6_rt_nhash_ofst; */ |
| 0x78 /* v6_rt_nhash_size; */ |
| 0x4000 /* v6_rt_nhash_size_ddr; */ |
| 0x688 /* modem_hdr_ofst; */ |
| 0x140 /* modem_hdr_size; */ |
| 0x7c8 /* apps_hdr_ofst; */ |
| 0x0 /* apps_hdr_size; */ |
| 0x800 /* apps_hdr_size_ddr; */ |
| 0x7d0 /* modem_hdr_proc_ctx_ofst; */ |
| 0x200 /* modem_hdr_proc_ctx_size; */ |
| 0x9d0 /* apps_hdr_proc_ctx_ofst; */ |
| 0x200 /* apps_hdr_proc_ctx_size; */ |
| 0x0 /* apps_hdr_proc_ctx_size_ddr; */ |
| 0x0 /* modem_comp_decomp_ofst; diff */ |
| 0x0 /* modem_comp_decomp_size; diff */ |
| 0xbd8 /* modem_ofst; */ |
| 0x1024 /* modem_size; */ |
| 0x2000 /* apps_v4_flt_hash_ofst; */ |
| 0x0 /* apps_v4_flt_hash_size; */ |
| 0x2000 /* apps_v4_flt_nhash_ofst; */ |
| 0x0 /* apps_v4_flt_nhash_size; */ |
| 0x2000 /* apps_v6_flt_hash_ofst; */ |
| 0x0 /* apps_v6_flt_hash_size; */ |
| 0x2000 /* apps_v6_flt_nhash_ofst; */ |
| 0x0 /* apps_v6_flt_nhash_size; */ |
| 0x80 /* uc_info_ofst; */ |
| 0x200 /* uc_info_size; */ |
| 0x2000 /* end_ofst; */ |
| 0x2000 /* apps_v4_rt_hash_ofst; */ |
| 0x0 /* apps_v4_rt_hash_size; */ |
| 0x2000 /* apps_v4_rt_nhash_ofst; */ |
| 0x0 /* apps_v4_rt_nhash_size; */ |
| 0x2000 /* apps_v6_rt_hash_ofst; */ |
| 0x0 /* apps_v6_rt_hash_size; */ |
| 0x2000 /* apps_v6_rt_nhash_ofst; */ |
| 0x0 /* apps_v6_rt_nhash_size; */ |
| 0x1c00 /* uc_event_ring_ofst; */ |
| 0x400 /* uc_event_ring_size; */ |
| >; |
| |
| /* smp2p gpio information */ |
| qcom,smp2pgpio_map_ipa_1_out { |
| compatible = "qcom,smp2pgpio-map-ipa-1-out"; |
| gpios = <&smp2pgpio_ipa_1_out 0 0>; |
| }; |
| |
| qcom,smp2pgpio_map_ipa_1_in { |
| compatible = "qcom,smp2pgpio-map-ipa-1-in"; |
| gpios = <&smp2pgpio_ipa_1_in 0 0>; |
| }; |
| |
| ipa_smmu_ap: ipa_smmu_ap { |
| compatible = "qcom,ipa-smmu-ap-cb"; |
| iommus = <&apps_smmu 0x720 0x0>; |
| qcom,iova-mapping = <0x20000000 0x40000000>; |
| }; |
| |
| ipa_smmu_wlan: ipa_smmu_wlan { |
| compatible = "qcom,ipa-smmu-wlan-cb"; |
| iommus = <&apps_smmu 0x721 0x0>; |
| }; |
| |
| ipa_smmu_uc: ipa_smmu_uc { |
| compatible = "qcom,ipa-smmu-uc-cb"; |
| iommus = <&apps_smmu 0x722 0x0>; |
| qcom,iova-mapping = <0x40000000 0x20000000>; |
| }; |
| }; |
| |
| qcom,ipa_fws { |
| compatible = "qcom,pil-tz-generic"; |
| qcom,pas-id = <0xf>; |
| qcom,firmware-name = "ipa_fws"; |
| }; |
| |
| pil_modem: qcom,mss@4080000 { |
| compatible = "qcom,pil-q6v55-mss"; |
| reg = <0x4080000 0x100>, |
| <0x1f63000 0x008>, |
| <0x1f65000 0x008>, |
| <0x1f64000 0x008>, |
| <0x4180000 0x020>, |
| <0xc2b0000 0x004>, |
| <0xb2e0100 0x004>, |
| <0x4180044 0x004>; |
| reg-names = "qdsp6_base", "halt_q6", "halt_modem", |
| "halt_nc", "rmb_base", "restart_reg", |
| "pdc_sync", "alt_reset"; |
| |
| clocks = <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_gcc GCC_MSS_CFG_AHB_CLK>, |
| <&clock_gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, |
| <&clock_gcc GCC_BOOT_ROM_AHB_CLK>, |
| <&clock_gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, |
| <&clock_gcc GCC_MSS_SNOC_AXI_CLK>, |
| <&clock_gcc GCC_MSS_MFAB_AXIS_CLK>, |
| <&clock_gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "xo", "iface_clk", "bus_clk", |
| "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", |
| "mnoc_axi_clk", "prng_clk"; |
| qcom,proxy-clock-names = "xo", "prng_clk"; |
| qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", |
| "gpll0_mss_clk", "snoc_axi_clk", |
| "mnoc_axi_clk"; |
| |
| interrupts = <0 266 1>; |
| vdd_cx-supply = <&pm660l_s3_level>; |
| vdd_cx-voltage = <RPMH_REGULATOR_LEVEL_TURBO>; |
| vdd_mx-supply = <&pm660l_s1_level>; |
| vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO>; |
| qcom,firmware-name = "modem"; |
| qcom,pil-self-auth; |
| qcom,sysmon-id = <0>; |
| qcom,ssctl-instance-id = <0x12>; |
| qcom,override-acc; |
| qcom,qdsp6v65-1-0; |
| status = "ok"; |
| memory-region = <&pil_modem_mem>; |
| qcom,mem-protect-id = <0xF>; |
| |
| /* GPIO inputs from mss */ |
| qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; |
| qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; |
| qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; |
| qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; |
| qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; |
| |
| /* GPIO output to mss */ |
| qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; |
| qcom,mba-mem@0 { |
| compatible = "qcom,pil-mba-mem"; |
| memory-region = <&pil_mba_mem>; |
| }; |
| }; |
| |
| qcom,venus@aae0000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0xaae0000 0x4000>; |
| |
| vdd-supply = <&venus_gdsc>; |
| qcom,proxy-reg-names = "vdd"; |
| |
| clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, |
| <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, |
| <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; |
| clock-names = "core_clk", "iface_clk", "bus_clk"; |
| qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk"; |
| |
| qcom,pas-id = <9>; |
| qcom,msm-bus,name = "pil-venus"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <63 512 0 0>, |
| <63 512 0 304000>; |
| qcom,proxy-timeout-ms = <100>; |
| qcom,firmware-name = "venus"; |
| memory-region = <&pil_video_mem>; |
| status = "ok"; |
| }; |
| |
| qcom,turing@8300000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x8300000 0x100000>; |
| interrupts = <0 578 1>; |
| |
| vdd_cx-supply = <&pm660l_s3_level>; |
| qcom,proxy-reg-names = "vdd_cx"; |
| qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| |
| clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| |
| qcom,pas-id = <18>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,smem-id = <601>; |
| qcom,sysmon-id = <7>; |
| qcom,ssctl-instance-id = <0x17>; |
| qcom,firmware-name = "cdsp"; |
| memory-region = <&pil_cdsp_mem>; |
| |
| /* GPIO inputs from turing */ |
| qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>; |
| qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>; |
| qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>; |
| qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>; |
| |
| /* GPIO output to turing*/ |
| qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>; |
| status = "ok"; |
| }; |
| |
| sdhc_1: sdhci@7c4000 { |
| compatible = "qcom,sdhci-msm-v5"; |
| reg = <0x7C4000 0x1000>, <0x7C5000 0x1000>; |
| reg-names = "hc_mem", "cmdq_mem"; |
| |
| interrupts = <0 641 0>, <0 644 0>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| qcom,bus-width = <8>; |
| qcom,large-address-bus; |
| |
| qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 |
| 192000000 384000000>; |
| qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; |
| |
| qcom,devfreq,freq-table = <50000000 200000000>; |
| |
| clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, |
| <&clock_gcc GCC_SDCC1_APPS_CLK>; |
| clock-names = "iface_clk", "core_clk"; |
| |
| qcom,nonremovable; |
| |
| qcom,scaling-lower-bus-speed-mode = "DDR52"; |
| status = "disabled"; |
| }; |
| |
| sdhc_2: sdhci@8804000 { |
| compatible = "qcom,sdhci-msm-v5"; |
| reg = <0x8804000 0x1000>; |
| reg-names = "hc_mem"; |
| |
| interrupts = <0 204 0>, <0 222 0>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| qcom,bus-width = <4>; |
| qcom,large-address-bus; |
| |
| qcom,clk-rates = <400000 20000000 25000000 |
| 50000000 100000000 201500000>; |
| qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", |
| "SDR104"; |
| |
| qcom,devfreq,freq-table = <50000000 201500000>; |
| clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, |
| <&clock_gcc GCC_SDCC2_APPS_CLK>; |
| clock-names = "iface_clk", "core_clk"; |
| |
| status = "disabled"; |
| }; |
| |
| qcom,msm-cdsp-loader { |
| compatible = "qcom,cdsp-loader"; |
| qcom,proc-img-to-load = "cdsp"; |
| }; |
| |
| qcom,msm-adsprpc-mem { |
| compatible = "qcom,msm-adsprpc-mem-region"; |
| memory-region = <&adsp_mem>; |
| }; |
| |
| qcom,msm_fastrpc { |
| compatible = "qcom,msm-fastrpc-compute"; |
| |
| qcom,msm_fastrpc_compute_cb1 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x1421 0x30>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb2 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x1422 0x30>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb3 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x1423 0x30>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb4 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x1424 0x30>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb5 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x1425 0x30>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb6 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x1426 0x30>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb7 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| qcom,secure-context-bank; |
| iommus = <&apps_smmu 0x1429 0x30>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb8 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| qcom,secure-context-bank; |
| iommus = <&apps_smmu 0x142A 0x30>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb9 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "adsprpc-smd"; |
| iommus = <&apps_smmu 0x1803 0x0>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb10 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "adsprpc-smd"; |
| iommus = <&apps_smmu 0x1804 0x0>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb11 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "adsprpc-smd"; |
| iommus = <&apps_smmu 0x1805 0x0>; |
| dma-coherent; |
| }; |
| }; |
| }; |
| |
| #include "sdm670-pinctrl.dtsi" |
| #include "msm-arm-smmu-sdm670.dtsi" |
| #include "msm-gdsc-sdm845.dtsi" |
| #include "sdm670-pm.dtsi" |
| |
| &usb30_prim_gdsc { |
| status = "ok"; |
| }; |
| |
| &ufs_phy_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_aggre_noc_mmu_tbu1_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_aggre_noc_mmu_tbu2_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { |
| status = "ok"; |
| }; |
| |
| &bps_gdsc { |
| status = "ok"; |
| }; |
| |
| &ife_0_gdsc { |
| status = "ok"; |
| }; |
| |
| &ife_1_gdsc { |
| status = "ok"; |
| }; |
| |
| &ipe_0_gdsc { |
| status = "ok"; |
| }; |
| |
| &ipe_1_gdsc { |
| status = "ok"; |
| }; |
| |
| &titan_top_gdsc { |
| status = "ok"; |
| }; |
| |
| &mdss_core_gdsc { |
| status = "ok"; |
| }; |
| |
| &gpu_cx_gdsc { |
| status = "ok"; |
| }; |
| |
| &gpu_gx_gdsc { |
| clock-names = "core_root_clk"; |
| clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>; |
| qcom,force-enable-root-clk; |
| parent-supply = <&pm660l_s2_level>; |
| status = "ok"; |
| }; |
| |
| &vcodec0_gdsc { |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| &vcodec1_gdsc { |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| &venus_gdsc { |
| status = "ok"; |
| }; |
| |
| #include "pm660.dtsi" |
| #include "pm660l.dtsi" |
| #include "sdm670-regulator.dtsi" |
| #include "sdm670-audio.dtsi" |
| #include "sdm670-usb.dtsi" |
| #include "sdm670-gpu.dtsi" |