commit 76bc09878fe57eed8fd4dac524ce8fe783a09294
author Steve Cohen <cohens@codeaurora.org> Tue Jun 20 13:19:04 2017 -0400
committer Gerrit - the friendly Code Review server <code-review@localhost> Tue Jul 25 07:38:55 2017 -0700
tree 5d44de2ca908aeefea5d24e1822a057bedea18a3
parent 814e5c69885da5c7863e094909fb7974016eb8fc

ARM: dts: msm: Add missing clock-ctrl setting for write-back on sdm845

SDE DRM driver reads this value for WB2 clock gating control. If not
present in device node, the current driver writes to a read-only
register (offset 0.0 from SSPP_TOP0). This patch fixes the bug.

CRs-Fixed: 2072416
Change-Id: I9d181fe9cf1b8b9955ef160924f1ca1f1b7e9efe
Signed-off-by: Steve Cohen <cohens@codeaurora.org>

arch/arm64/boot/dts/qcom/sdm845-sde.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
index 7ceb5b2..17adbf4 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
@@ -65,9 +65,10 @@
 
 		qcom,sde-wb-off = <0x66000>;
 		qcom,sde-wb-size = <0x2c8>;
-
 		qcom,sde-wb-xin-id = <6>;
 		qcom,sde-wb-id = <2>;
+		qcom,sde-wb-clk-ctrl = <0x3b8 24>;
+
 		qcom,sde-intf-off = <0x6b000 0x6b800
 					0x6c000 0x6c800>;
 		qcom,sde-intf-size = <0x280>;