Merge "msm: kgsl: Fix race condition between drawobj and context destroy"
diff --git a/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt b/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt
index f8329a9..31c5660 100644
--- a/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt
+++ b/Documentation/devicetree/bindings/pil/subsys-pil-tz.txt
@@ -70,6 +70,12 @@
- qcom,ignore-ssr-failure: Boolean. If set, SSR failures are not considered fatal.
- qcom,mas-crypto: Reference to the bus master of crypto core.
+- qcom,sequential-fw-load: Boolean. If set, PIL loads the firmware image blobs in a
+ serial fashion. Else, they are loaded in
+ parallel. The property is specially useful for
+ low-end (single core) systems to prevent it from
+ degrading the performance.
+
Example:
qcom,venus@fdce0000 {
compatible = "qcom,pil-tz-generic";
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 83ecdc7..20abd3d 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -63,6 +63,7 @@
during bus suspend.
- snps,usb3-u1u2-disable: If present, disable U1U2 low power modes in Superspeed mode
- snps,usb2-l1-disable: If present, disable L1 low power modes in Highspeed mode
+ - normal-eps-in-gsi-mode: If present, two normal EPS (1 In, 1 Out) can be used in GSI mode
This is usually a subnode to DWC3 glue to which it is connected.
diff --git a/arch/arm/boot/dts/qcom/sa415m-ccard.dtsi b/arch/arm/boot/dts/qcom/sa415m-ccard.dtsi
index aa708e6..d2e597d 100644
--- a/arch/arm/boot/dts/qcom/sa415m-ccard.dtsi
+++ b/arch/arm/boot/dts/qcom/sa415m-ccard.dtsi
@@ -54,6 +54,12 @@
};
};
+&spi_2 {
+ can-controller@0 {
+ qcom,max-can-channels = <2>;
+ };
+};
+
&wcd934x_cdc {
status = "disabled";
};
diff --git a/arch/arm/configs/sdxpoorwills-auto-perf_defconfig b/arch/arm/configs/sdxpoorwills-auto-perf_defconfig
index 1af9a91..b04fd97 100644
--- a/arch/arm/configs/sdxpoorwills-auto-perf_defconfig
+++ b/arch/arm/configs/sdxpoorwills-auto-perf_defconfig
@@ -180,6 +180,7 @@
CONFIG_RFKILL=y
CONFIG_IPC_ROUTER=y
CONFIG_IPC_ROUTER_SECURITY=y
+CONFIG_IPC_ROUTER_NODE_ID=2
CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=12
diff --git a/arch/arm/configs/sdxpoorwills-auto_defconfig b/arch/arm/configs/sdxpoorwills-auto_defconfig
index 572c46b..3d0cca3 100644
--- a/arch/arm/configs/sdxpoorwills-auto_defconfig
+++ b/arch/arm/configs/sdxpoorwills-auto_defconfig
@@ -181,6 +181,7 @@
CONFIG_RFKILL=y
CONFIG_IPC_ROUTER=y
CONFIG_IPC_ROUTER_SECURITY=y
+CONFIG_IPC_ROUTER_NODE_ID=2
CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=12
diff --git a/arch/arm/configs/spyro-perf_defconfig b/arch/arm/configs/spyro-perf_defconfig
index d0c6b05..70a0646 100644
--- a/arch/arm/configs/spyro-perf_defconfig
+++ b/arch/arm/configs/spyro-perf_defconfig
@@ -303,7 +303,6 @@
CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v26=y
CONFIG_SECURE_TOUCH_SYNAPTICS_DSX_V26=y
CONFIG_INPUT_MISC=y
-CONFIG_INPUT_HBTP_INPUT=y
CONFIG_INPUT_QPNP_POWER_ON=y
CONFIG_INPUT_QTI_HAPTICS=y
CONFIG_INPUT_UINPUT=y
diff --git a/arch/arm/configs/spyro_defconfig b/arch/arm/configs/spyro_defconfig
index 0e10212..a971fa1 100644
--- a/arch/arm/configs/spyro_defconfig
+++ b/arch/arm/configs/spyro_defconfig
@@ -310,7 +310,6 @@
CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v26=y
CONFIG_SECURE_TOUCH_SYNAPTICS_DSX_V26=y
CONFIG_INPUT_MISC=y
-CONFIG_INPUT_HBTP_INPUT=y
CONFIG_INPUT_QPNP_POWER_ON=y
CONFIG_INPUT_QTI_HAPTICS=y
CONFIG_INPUT_UINPUT=y
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2d36265..9bf544d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1549,6 +1549,7 @@
vdd_mss-supply = <&pm8005_s2_level>;
vdd_mss-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,firmware-name = "modem";
+ qcom,sequential-fw-load;
qcom,pil-self-auth;
qcom,sysmon-id = <0>;
qcom,minidump-id = <3>;
diff --git a/arch/arm64/configs/sdm670-perf_defconfig b/arch/arm64/configs/sdm670-perf_defconfig
index 58aabff..d75479e 100755
--- a/arch/arm64/configs/sdm670-perf_defconfig
+++ b/arch/arm64/configs/sdm670-perf_defconfig
@@ -37,7 +37,6 @@
# CONFIG_RD_LZ4 is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
@@ -72,12 +71,12 @@
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y
+CONFIG_ARM64_SW_TTBR0_PAN=y
# CONFIG_ARM64_VHE is not set
CONFIG_RANDOMIZE_BASE=y
# CONFIG_EFI is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_COMPAT=y
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -94,6 +93,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -276,6 +276,7 @@
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_BONDING=y
CONFIG_DUMMY=y
@@ -295,6 +296,7 @@
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_LAN78XX=y
CONFIG_USB_USBNET=y
CONFIG_WCNSS_MEM_PRE_ALLOC=y
diff --git a/arch/arm64/configs/sdm670_defconfig b/arch/arm64/configs/sdm670_defconfig
index a9f8f65..1eea891 100755
--- a/arch/arm64/configs/sdm670_defconfig
+++ b/arch/arm64/configs/sdm670_defconfig
@@ -39,7 +39,6 @@
# CONFIG_RD_LZ4 is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
@@ -77,11 +76,11 @@
CONFIG_SWP_EMULATION=y
CONFIG_CP15_BARRIER_EMULATION=y
CONFIG_SETEND_EMULATION=y
+CONFIG_ARM64_SW_TTBR0_PAN=y
# CONFIG_ARM64_VHE is not set
CONFIG_RANDOMIZE_BASE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_COMPAT=y
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -99,6 +98,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -284,6 +284,7 @@
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_BONDING=y
CONFIG_DUMMY=y
@@ -301,6 +302,7 @@
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_LAN78XX=y
CONFIG_USB_USBNET=y
CONFIG_WCNSS_MEM_PRE_ALLOC=y
diff --git a/drivers/char/diag/diagfwd_socket.c b/drivers/char/diag/diagfwd_socket.c
index 401dbb0f..d7d7366 100644
--- a/drivers/char/diag/diagfwd_socket.c
+++ b/drivers/char/diag/diagfwd_socket.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -496,7 +496,8 @@
if (!atomic_read(&info->opened))
return;
- if (bootup_req[info->peripheral] == PEPIPHERAL_SSR_UP) {
+ if ((bootup_req[info->peripheral] == PEPIPHERAL_SSR_UP) &&
+ (info->port_type == PORT_TYPE_SERVER)) {
DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
"diag: %s is up, stopping cleanup: bootup_req = %d\n",
info->name, (int)bootup_req[info->peripheral]);
diff --git a/drivers/hwmon/qpnp-adc-voltage.c b/drivers/hwmon/qpnp-adc-voltage.c
index 35d33de..086e706 100644
--- a/drivers/hwmon/qpnp-adc-voltage.c
+++ b/drivers/hwmon/qpnp-adc-voltage.c
@@ -107,8 +107,8 @@
#define QPNP_VADC_CONV_TIMEOUT_ERR 2
#define QPNP_VADC_CONV_TIME_MIN 1000
#define QPNP_VADC_CONV_TIME_MAX 1100
-#define QPNP_ADC_COMPLETION_TIMEOUT HZ
-#define QPNP_VADC_ERR_COUNT 20
+#define QPNP_ADC_COMPLETION_TIMEOUT msecs_to_jiffies(100)
+#define QPNP_VADC_ERR_COUNT 150
#define QPNP_OP_MODE_SHIFT 3
#define QPNP_VADC_THR_LSB_MASK(val) (val & 0xff)
@@ -161,7 +161,8 @@
*/
#define QPNP_VADC_HC1_CONV_TIME_MIN_US 213
#define QPNP_VADC_HC1_CONV_TIME_MAX_US 214
-#define QPNP_VADC_HC1_ERR_COUNT 1600
+#define QPNP_VADC_HC1_ERR_COUNT_POLL 705
+#define QPNP_VADC_HC1_ERR_COUNT 235
#define QPNP_VADC_CAL_DELAY_CTL_1 0x3744
#define QPNP_VADC_CAL_DELAY_MEAS_SLOW 0x73
@@ -363,11 +364,17 @@
return 0;
}
-static int qpnp_vadc_hc_check_conversion_status(struct qpnp_vadc_chip *vadc)
+static int qpnp_vadc_hc_check_conversion_status(struct qpnp_vadc_chip *vadc,
+ bool poll)
{
- int rc = 0, count = 0;
+ int rc = 0, count = 0, retry;
u8 status1 = 0;
+ if (poll)
+ retry = QPNP_VADC_HC1_ERR_COUNT_POLL;
+ else
+ retry = QPNP_VADC_HC1_ERR_COUNT;
+
while (status1 != QPNP_VADC_STATUS1_EOC) {
rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1);
if (rc < 0)
@@ -378,7 +385,7 @@
usleep_range(QPNP_VADC_HC1_CONV_TIME_MIN_US,
QPNP_VADC_HC1_CONV_TIME_MAX_US);
count++;
- if (count > QPNP_VADC_HC1_ERR_COUNT) {
+ if (count > retry) {
pr_err("retry error exceeded\n");
rc = qpnp_vadc_status_debug(vadc);
if (rc < 0)
@@ -429,7 +436,7 @@
int ret;
if (vadc->vadc_poll_eoc) {
- ret = qpnp_vadc_hc_check_conversion_status(vadc);
+ ret = qpnp_vadc_hc_check_conversion_status(vadc, true);
if (ret < 0) {
pr_err("polling mode conversion failed\n");
return ret;
@@ -439,7 +446,7 @@
&vadc->adc->adc_rslt_completion,
QPNP_ADC_COMPLETION_TIMEOUT);
if (!ret) {
- ret = qpnp_vadc_hc_check_conversion_status(vadc);
+ ret = qpnp_vadc_hc_check_conversion_status(vadc, false);
if (ret < 0) {
pr_err("interrupt mode conversion failed\n");
return ret;
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util_32.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util_32.c
index b5a6f44..c237ad2 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util_32.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util_32.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -1215,7 +1215,7 @@
for (i = 0; i < stream_cfg_cmd->num_streams; i++) {
if (HANDLE_TO_IDX(stream_cfg_cmd->stream_handle[i])
- > MAX_NUM_STREAM)
+ >= MAX_NUM_STREAM)
return;
stream_info =
&axi_data->stream_info[
diff --git a/drivers/net/usb/ax88179_178a.c b/drivers/net/usb/ax88179_178a.c
index 531536a..cb46d96 100644
--- a/drivers/net/usb/ax88179_178a.c
+++ b/drivers/net/usb/ax88179_178a.c
@@ -1660,6 +1660,19 @@
.tx_fixup = ax88179_tx_fixup,
};
+static const struct driver_info ax88178b_info = {
+ .description = "ASIX AX88178B USB 2.0 Gigabit Ethernet",
+ .bind = ax88179_bind,
+ .unbind = ax88179_unbind,
+ .status = ax88179_status,
+ .link_reset = ax88179_link_reset,
+ .reset = ax88179_reset,
+ .stop = ax88179_stop,
+ .flags = FLAG_ETHER | FLAG_FRAMING_AX,
+ .rx_fixup = ax88179_rx_fixup,
+ .tx_fixup = ax88179_tx_fixup,
+};
+
static const struct driver_info cypress_GX3_info = {
.description = "Cypress GX3 SuperSpeed to Gigabit Ethernet Controller",
.bind = ax88179_bind,
@@ -1735,6 +1748,10 @@
USB_DEVICE(0x0b95, 0x178a),
.driver_info = (unsigned long)&ax88178a_info,
}, {
+ /* ASIX AX88178A 10/100/1000 */
+ USB_DEVICE(0x0b95, 0x178b),
+ .driver_info = (unsigned long)&ax88178b_info,
+}, {
/* Cypress GX3 SuperSpeed to Gigabit Ethernet Bridge Controller */
USB_DEVICE(0x04b4, 0x3610),
.driver_info = (unsigned long)&cypress_GX3_info,
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c
index f8fdefd..6de07dc 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c
@@ -5130,6 +5130,7 @@
ipa3_ctx->use_ipa_teth_bridge = resource_p->use_ipa_teth_bridge;
ipa3_ctx->modem_cfg_emb_pipe_flt = resource_p->modem_cfg_emb_pipe_flt;
ipa3_ctx->ipa_wdi2 = resource_p->ipa_wdi2;
+ ipa3_ctx->ipa_config_is_auto = resource_p->ipa_config_is_auto;
ipa3_ctx->use_64_bit_dma_mask = resource_p->use_64_bit_dma_mask;
ipa3_ctx->wan_rx_ring_size = resource_p->wan_rx_ring_size;
ipa3_ctx->lan_rx_ring_size = resource_p->lan_rx_ring_size;
@@ -5701,6 +5702,7 @@
ipa_drv_res->ipa3_hw_mode = 0;
ipa_drv_res->modem_cfg_emb_pipe_flt = false;
ipa_drv_res->ipa_wdi2 = false;
+ ipa_drv_res->ipa_config_is_auto = false;
ipa_drv_res->ipa_mhi_dynamic_config = false;
ipa_drv_res->use_64_bit_dma_mask = false;
ipa_drv_res->use_bw_vote = false;
@@ -5785,6 +5787,13 @@
ipa_drv_res->ipa_wdi2
? "True" : "False");
+ ipa_drv_res->ipa_config_is_auto =
+ of_property_read_bool(pdev->dev.of_node,
+ "qcom,ipa-config-is-auto");
+ IPADBG(": ipa-config-is-auto = %s\n",
+ ipa_drv_res->ipa_config_is_auto
+ ? "True" : "False");
+
ipa_drv_res->use_64_bit_dma_mask =
of_property_read_bool(pdev->dev.of_node,
"qcom,use-64-bit-dma-mask");
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
index d145a4b..2caa54e 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
@@ -1446,6 +1446,7 @@
* @logbuf: ipc log buffer for high priority messages
* @logbuf_low: ipc log buffer for low priority messages
* @ipa_wdi2: using wdi-2.0
+ * @ipa_config_is_auto: is this AUTO use case
* @use_64_bit_dma_mask: using 64bits dma mask
* @ipa_bus_hdl: msm driver handle for the data path bus
* @ctrl: holds the core specific operations based on
@@ -1547,6 +1548,7 @@
bool use_ipa_teth_bridge;
bool modem_cfg_emb_pipe_flt;
bool ipa_wdi2;
+ bool ipa_config_is_auto;
bool use_64_bit_dma_mask;
/* featurize if memory footprint becomes a concern */
struct ipa3_stats stats;
@@ -1628,6 +1630,7 @@
u32 ee;
bool modem_cfg_emb_pipe_flt;
bool ipa_wdi2;
+ bool ipa_config_is_auto;
bool use_64_bit_dma_mask;
bool use_bw_vote;
u32 wan_rx_ring_size;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index 3e6b365..03b0c72 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -144,6 +144,7 @@
#define IPA_v4_0_GROUP_UL_DL (1)
#define IPA_v4_0_MHI_GROUP_DDR (1)
#define IPA_v4_0_MHI_GROUP_DMA (2)
+#define IPA_v4_0_GROUP_CV2X (2)
#define IPA_v4_0_GROUP_UC_RX_Q (3)
#define IPA_v4_0_SRC_GROUP_MAX (4)
#define IPA_v4_0_DST_GROUP_MAX (4)
@@ -216,6 +217,8 @@
IPA_3_5_1,
IPA_4_0,
IPA_4_0_MHI,
+ IPA_4_0_AUTO,
+ IPA_4_0_AUTO_MHI,
IPA_VER_MAX,
};
@@ -305,6 +308,32 @@
[IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
{14, 14}, {14, 14}, {14, 14}, {0, 0}, {0, 0}, {0, 0} },
},
+ [IPA_4_0_AUTO] = {
+ /*not-used UL_DL CV2X not-used, other are invalid */
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {
+ {0, 0}, {1, 255}, {1, 1}, {0, 0}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
+ {0, 0}, {10, 10}, {8, 8}, {0, 0}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {
+ {0, 0}, {14, 14}, {8, 8}, {0, 0}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {
+ {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
+ {0, 0}, {20, 20}, {14, 14}, {0, 0}, {0, 0}, {0, 0} },
+ },
+ [IPA_4_0_AUTO_MHI] = {
+ /* PCIE DDR DMA/CV2X not used, other are invalid */
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {
+ {4, 4}, {5, 5}, {1, 1}, {0, 0}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
+ {10, 10}, {10, 10}, {8, 8}, {0, 0}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_DESCRIPTOR_BUFF] = {
+ {12, 12}, {12, 12}, {8, 8}, {0, 0}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_HPS_DMARS] = {
+ {0, 255}, {0, 255}, {0, 255}, {0, 255}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_SRC_ACK_ENTRIES] = {
+ {14, 14}, {14, 14}, {14, 14}, {0, 0}, {0, 0}, {0, 0} },
+ },
};
static const struct rsrc_min_max ipa3_rsrc_dst_grp_config
@@ -353,6 +382,20 @@
[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
{2, 255}, {1, 255}, {1, 2}, {0, 2}, {0, 0}, {0, 0} },
},
+ [IPA_4_0_AUTO] = {
+ /*PCIE UL/DL/DPL DMA/CV2X, other are invalid */
+ [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {
+ {4, 4}, {4, 4}, {3, 3}, {2, 2}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
+ {2, 255}, {1, 255}, {1, 2}, {0, 2}, {0, 0}, {0, 0} },
+ },
+ [IPA_4_0_AUTO_MHI] = {
+ /*PCIE DDR DMA/CV2X, other are invalid */
+ [IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {
+ {4, 4}, {4, 4}, {3, 3}, {2, 2}, {0, 0}, {0, 0} },
+ [IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
+ {2, 255}, {1, 255}, {1, 2}, {0, 2}, {0, 0}, {0, 0} },
+ },
};
static const struct rsrc_min_max ipa3_rsrc_rx_grp_config
@@ -387,6 +430,16 @@
[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
{ 3, 3 }, { 7, 7 }, { 2, 2 }, { 0, 0 }, { 0, 0 }, { 0, 0 } },
},
+ [IPA_4_0_AUTO] = {
+ /*not-used UL_DL CV2X not-used, other are invalid */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
+ {0, 0}, {7, 7}, {2, 2}, {0, 0}, {0, 0}, {0, 0} },
+ },
+ [IPA_4_0_AUTO_MHI] = {
+ /* PCIE DDR DMA/CV2X not used, other are invalid */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {
+ { 3, 3 }, { 7, 7 }, { 2, 2 }, { 0, 0 }, { 0, 0 }, { 0, 0 } },
+ },
};
static const u32 ipa3_rsrc_rx_grp_hps_weight_config
@@ -415,6 +468,14 @@
/* PCIE DDR DMA unused N/A N/A */
[IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 3, 5, 1, 1, 0, 0 },
},
+ [IPA_4_0_AUTO] = {
+ /*not-used UL_DL CV2X not-used, other are invalid */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 0, 1, 1, 0, 0, 0 },
+ },
+ [IPA_4_0_AUTO_MHI] = {
+ /* PCIE DDR DMA/CV2X not used, other are invalid */
+ [IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 3, 5, 1, 0, 0, 0 },
+ },
};
enum ipa_ees {
@@ -1494,6 +1555,417 @@
IPA_DPS_HPS_SEQ_TYPE_INVALID,
QMB_MASTER_SELECT_DDR,
{ 31, 31, 8, 8, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+
+ /* IPA_4_0_AUTO */
+ [IPA_4_0_AUTO][IPA_CLIENT_WLAN1_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,
+ QMB_MASTER_SELECT_DDR,
+ { 6, 2, 8, 16, IPA_EE_UC, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO][IPA_CLIENT_USB_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,
+ QMB_MASTER_SELECT_DDR,
+ { 0, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_USB2_PROD] = {
+ true, IPA_v4_0_GROUP_CV2X,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+ QMB_MASTER_SELECT_DDR,
+ { 7, 3, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_APPS_LAN_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 8, 11, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_APPS_WAN_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,
+ QMB_MASTER_SELECT_DDR,
+ { 2, 4, 16, 32, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_APPS_CMD_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+ QMB_MASTER_SELECT_DDR,
+ { 5, 7, 20, 24, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO][IPA_CLIENT_ODU_PROD] = {
+ false, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,
+ QMB_MASTER_SELECT_DDR,
+ { 1, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_ETHERNET_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,
+ QMB_MASTER_SELECT_DDR,
+ { 9, 0, 8, 16, IPA_EE_UC, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO][IPA_CLIENT_Q6_WAN_PROD] = {
+ false, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 3, 0, 16, 32, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO][IPA_CLIENT_Q6_CMD_PROD] = {
+ false, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 4, 1, 20, 24, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS } },
+ /* Only for test purpose */
+ [IPA_4_0_AUTO][IPA_CLIENT_TEST_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {0, 8, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_TEST1_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {0, 8, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_TEST2_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 1, 0, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_TEST3_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 7, 9, 8, 16, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO][IPA_CLIENT_TEST4_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {8, 10, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+
+
+ [IPA_4_0_AUTO][IPA_CLIENT_WLAN1_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 18, 3, 6, 9, IPA_EE_UC, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO][IPA_CLIENT_WLAN2_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 20, 12, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_WLAN3_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 21, 13, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_USB_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 19, 6, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_USB_DPL_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 15, 10, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_MHI_DPL_CONS] = {
+ false, IPA_v4_0_MHI_GROUP_PCIE,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 12, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_APPS_LAN_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 10, 8, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_APPS_WAN_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 11, 9, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_USB2_CONS] = {
+ true, IPA_v4_0_GROUP_CV2X,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 17, 1, 9, 9, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO][IPA_CLIENT_ETHERNET_CONS] = {
+ true, IPA_v4_0_ETHERNET,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 22, 1, 9, 9, IPA_EE_UC, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO][IPA_CLIENT_Q6_LAN_CONS] = {
+ false, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 14, 4, 9, 9, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO][IPA_CLIENT_Q6_WAN_CONS] = {
+ false, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 13, 3, 9, 9, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO][IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS] = {
+ false, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 16, 5, 9, 9, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS } },
+ /* Only for test purpose */
+ /* MBIM aggregation test pipes should have the same QMB as USB_CONS */
+ [IPA_4_0_AUTO][IPA_CLIENT_TEST_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 11, 6, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_TEST1_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 11, 6, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_TEST2_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 12, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_TEST3_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 19, 12, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO][IPA_CLIENT_TEST4_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 21, 14, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ /* Dummy consumer (pipe 31) is used in L2TP rt rule */
+ [IPA_4_0_AUTO][IPA_CLIENT_DUMMY_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 31, 31, 8, 8, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+
+ /* IPA_4_0_AUTO_MHI */
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_APPS_WAN_PROD] = {
+ true, IPA_v4_0_MHI_GROUP_DDR,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 2, 4, 16, 32, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_APPS_CMD_PROD] = {
+ true, IPA_v4_0_MHI_GROUP_DDR,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+ QMB_MASTER_SELECT_DDR,
+ { 5, 7, 20, 24, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_MHI_PROD] = {
+ true, IPA_v4_0_MHI_GROUP_PCIE,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_PCIE,
+ { 0, 0, 8, 16, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_MHI2_PROD] = {
+ true, IPA_v4_0_GROUP_CV2X,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_PCIE,
+ { 6, 5, 8, 16, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_ETHERNET_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,
+ QMB_MASTER_SELECT_DDR,
+ { 9, 0, 8, 16, IPA_EE_UC, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_Q6_WAN_PROD] = {
+ false, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 3, 0, 16, 32, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_Q6_CMD_PROD] = {
+ false, IPA_v4_0_MHI_GROUP_PCIE,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 4, 1, 20, 24, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_PROD] = {
+ true, IPA_v4_0_MHI_GROUP_DMA,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+ QMB_MASTER_SELECT_DDR,
+ { 7, 3, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_PROD] = {
+ true, IPA_v4_0_MHI_GROUP_DMA,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,
+ QMB_MASTER_SELECT_DDR,
+ { 8, 11, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ /* Only for test purpose */
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_TEST_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {0, 8, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_TEST1_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {0, 8, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_TEST2_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 1, 0, 8, 16, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_TEST3_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ {7, 9, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_TEST4_PROD] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ true,
+ IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
+ QMB_MASTER_SELECT_DDR,
+ { 8, 10, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+
+
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_APPS_LAN_CONS] = {
+ true, IPA_v4_0_MHI_GROUP_DDR,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 10, 8, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_APPS_WAN_CONS] = {
+ true, IPA_v4_0_MHI_GROUP_DDR,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 11, 9, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_MHI_CONS] = {
+ true, IPA_v4_0_MHI_GROUP_PCIE,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 17, 1, 17, 17, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_MHI2_CONS] = {
+ true, IPA_v4_0_GROUP_CV2X,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 19, 6, 9, 9, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_ETHERNET_CONS] = {
+ true, IPA_v4_0_ETHERNET,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 22, 1, 9, 9, IPA_EE_UC, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_Q6_LAN_CONS] = {
+ false, IPA_v4_0_MHI_GROUP_DDR,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 14, 4, 9, 9, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_Q6_WAN_CONS] = {
+ false, IPA_v4_0_MHI_GROUP_DDR,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 13, 3, 9, 9, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_SYNC_CONS] = {
+ true, IPA_v4_0_MHI_GROUP_DMA,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 20, 12, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_MEMCPY_DMA_ASYNC_CONS] = {
+ true, IPA_v4_0_MHI_GROUP_DMA,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 21, 13, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_Q6_LTE_WIFI_AGGR_CONS] = {
+ false, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 16, 5, 9, 9, IPA_EE_Q6, GSI_USE_PREFETCH_BUFS } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_USB_DPL_CONS] = {
+ false, IPA_v4_0_MHI_GROUP_DDR,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 15, 10, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_MHI_DPL_CONS] = {
+ true, IPA_v4_0_MHI_GROUP_PCIE,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 12, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ /* Only for test purpose */
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_TEST_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 11, 6, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_TEST1_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 11, 6, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_TEST2_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 12, 2, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_TEST3_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 19, 12, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_TEST4_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_PCIE,
+ { 21, 14, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY } },
+ /* Dummy consumer (pipe 31) is used in L2TP rt rule */
+ [IPA_4_0_AUTO_MHI][IPA_CLIENT_DUMMY_CONS] = {
+ true, IPA_v4_0_GROUP_UL_DL,
+ false,
+ IPA_DPS_HPS_SEQ_TYPE_INVALID,
+ QMB_MASTER_SELECT_DDR,
+ { 31, 31, 8, 8, IPA_EE_AP, GSI_USE_PREFETCH_BUFS } },
};
/**
@@ -2131,6 +2603,14 @@
*/
if (ipa3_ctx->ipa_config_is_mhi)
hw_type_index = IPA_4_0_MHI;
+
+ if (ipa3_ctx->ipa_config_is_auto)
+ hw_type_index = IPA_4_0_AUTO;
+
+ if (ipa3_ctx->ipa_config_is_auto &&
+ ipa3_ctx->ipa_config_is_mhi)
+ hw_type_index = IPA_4_0_AUTO_MHI;
+
break;
default:
IPAERR("Incorrect IPA version %d\n", ipa3_ctx->ipa_hw_type);
@@ -4777,6 +5257,8 @@
break;
case IPA_4_0:
case IPA_4_0_MHI:
+ case IPA_4_0_AUTO:
+ case IPA_4_0_AUTO_MHI:
if (src) {
switch (group_index) {
case IPA_v4_0_GROUP_LWA_DL:
@@ -4926,6 +5408,13 @@
src_grp_idx_max = IPA_v4_0_SRC_GROUP_MAX;
dst_grp_idx_max = IPA_v4_0_DST_GROUP_MAX;
break;
+ case IPA_4_0_AUTO:
+ case IPA_4_0_AUTO_MHI:
+ src_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_SRC_MAX;
+ dst_rsrc_type_max = IPA_v4_0_RSRC_GRP_TYPE_DST_MAX;
+ src_grp_idx_max = IPA_v4_0_GROUP_CV2X;
+ dst_grp_idx_max = IPA_v4_0_GROUP_CV2X;
+ break;
default:
IPAERR("invalid hw type index\n");
WARN_ON(1);
diff --git a/drivers/soc/qcom/peripheral-loader.c b/drivers/soc/qcom/peripheral-loader.c
index 384ac58..1d5284e 100644
--- a/drivers/soc/qcom/peripheral-loader.c
+++ b/drivers/soc/qcom/peripheral-loader.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -36,6 +36,7 @@
#include <soc/qcom/subsystem_restart.h>
#include <soc/qcom/secure_buffer.h>
#include <soc/qcom/smem.h>
+#include <linux/kthread.h>
#include <linux/uaccess.h>
#include <asm/setup.h>
@@ -70,6 +71,9 @@
module_param(proxy_timeout_ms, int, 0644);
static bool disable_timeouts;
+
+static struct workqueue_struct *pil_wq;
+
/**
* struct pil_mdt - Representation of <name>.mdt file in memory
* @hdr: ELF32 header
@@ -127,6 +131,7 @@
struct wakeup_source ws;
char wname[32];
struct pil_desc *desc;
+ int num_segs;
struct list_head segs;
phys_addr_t entry_addr;
phys_addr_t base_addr;
@@ -723,6 +728,7 @@
pil_info(desc, "loading from %pa to %pa\n", &priv->region_start,
&priv->region_end);
+ priv->num_segs = 0;
for (i = 0; i < mdt->hdr.e_phnum; i++) {
phdr = &mdt->phdr[i];
if (!segment_is_loadable(phdr))
@@ -733,6 +739,7 @@
return PTR_ERR(seg);
list_add_tail(&seg->list, &priv->segs);
+ priv->num_segs++;
}
list_sort(NULL, &priv->segs, pil_cmp_seg);
@@ -922,6 +929,9 @@
}
}
desc->proxy_unvote_irq = clk_ready;
+
+ desc->sequential_load = of_property_read_bool(ofnode,
+ "qcom,sequential-fw-load");
return 0;
}
@@ -945,6 +955,89 @@
/* Synchronize request_firmware() with suspend */
static DECLARE_RWSEM(pil_pm_rwsem);
+struct pil_seg_data {
+ struct pil_desc *desc;
+ struct pil_seg *seg;
+ struct work_struct load_seg_work;
+ int retval;
+};
+
+static void pil_load_seg_work_fn(struct work_struct *work)
+{
+ struct pil_seg_data *pil_seg_data = container_of(work,
+ struct pil_seg_data,
+ load_seg_work);
+ struct pil_desc *desc = pil_seg_data->desc;
+ struct pil_seg *seg = pil_seg_data->seg;
+
+ pil_seg_data->retval = pil_load_seg(desc, seg);
+}
+
+static int pil_load_segs(struct pil_desc *desc)
+{
+ int ret = 0;
+ int seg_id = 0;
+ struct pil_priv *priv = desc->priv;
+ struct pil_seg_data *pil_seg_data;
+ struct pil_seg *seg;
+ unsigned long *err_map;
+
+ err_map = kcalloc(BITS_TO_LONGS(priv->num_segs), sizeof(unsigned long),
+ GFP_KERNEL);
+ if (!err_map)
+ return -ENOMEM;
+
+ pil_seg_data = kcalloc(priv->num_segs, sizeof(*pil_seg_data),
+ GFP_KERNEL);
+ if (!pil_seg_data) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ /* Initialize and spawn a thread for each segment */
+ list_for_each_entry(seg, &desc->priv->segs, list) {
+ pil_seg_data[seg_id].desc = desc;
+ pil_seg_data[seg_id].seg = seg;
+
+ INIT_WORK(&pil_seg_data[seg_id].load_seg_work,
+ pil_load_seg_work_fn);
+ queue_work(pil_wq, &pil_seg_data[seg_id].load_seg_work);
+
+ seg_id++;
+ }
+
+ bitmap_zero(err_map, priv->num_segs);
+
+ /* Wait for the parallel loads to finish */
+ seg_id = 0;
+ list_for_each_entry(seg, &desc->priv->segs, list) {
+ flush_work(&pil_seg_data[seg_id].load_seg_work);
+
+ /*
+ * Don't exit if one of the thread fails. Wait for others to
+ * complete. Bitmap the return codes we get from the threads.
+ */
+ if (pil_seg_data[seg_id].retval) {
+ pil_err(desc,
+ "Failed to load the segment[%d]. ret = %d\n",
+ seg_id, pil_seg_data[seg_id].retval);
+ __set_bit(seg_id, err_map);
+ }
+
+ seg_id++;
+ }
+
+ kfree(pil_seg_data);
+
+ /* Each segment can fail due to different reason. Send a generic err */
+ if (!bitmap_empty(err_map, priv->num_segs))
+ ret = -EFAULT;
+
+out:
+ kfree(err_map);
+ return ret;
+}
+
/**
* pil_boot() - Load a peripheral image into memory and boot it
* @desc: descriptor from pil_desc_init()
@@ -955,9 +1048,9 @@
{
int ret;
char fw_name[30];
+ struct pil_seg *seg;
const struct pil_mdt *mdt;
const struct elf32_hdr *ehdr;
- struct pil_seg *seg;
const struct firmware *fw;
struct pil_priv *priv = desc->priv;
bool mem_protect = false;
@@ -1066,8 +1159,15 @@
}
trace_pil_event("before_load_seg", desc);
- list_for_each_entry(seg, &desc->priv->segs, list) {
- ret = pil_load_seg(desc, seg);
+
+ if (desc->sequential_load) {
+ list_for_each_entry(seg, &desc->priv->segs, list) {
+ ret = pil_load_seg(desc, seg);
+ if (ret)
+ goto err_deinit_image;
+ }
+ } else {
+ ret = pil_load_segs(desc);
if (ret)
goto err_deinit_image;
}
@@ -1364,6 +1464,11 @@
pr_err("SMEM is not initialized.\n");
return -EPROBE_DEFER;
}
+
+ pil_wq = alloc_workqueue("pil_workqueue", WQ_HIGHPRI | WQ_UNBOUND, 0);
+ if (!pil_wq)
+ pr_warn("pil: Defaulting to sequential firmware loading.\n");
+
out:
return register_pm_notifier(&pil_pm_notifier);
}
@@ -1371,6 +1476,8 @@
static void __exit msm_pil_exit(void)
{
+ if (pil_wq)
+ destroy_workqueue(pil_wq);
unregister_pm_notifier(&pil_pm_notifier);
if (pil_info_base)
iounmap(pil_info_base);
diff --git a/drivers/soc/qcom/peripheral-loader.h b/drivers/soc/qcom/peripheral-loader.h
index 6ea6b2a..9f3e006 100644
--- a/drivers/soc/qcom/peripheral-loader.h
+++ b/drivers/soc/qcom/peripheral-loader.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -41,6 +41,8 @@
* @modem_ssr: true if modem is restarting, false if booting for first time.
* @clear_fw_region: Clear fw region on failure in loading.
* @subsys_vmid: memprot id for the subsystem.
+ * @sequential_load: Load the firmware blobs sequentially if set. Else, load
+ * them in parallel.
*/
struct pil_desc {
const char *name;
@@ -67,6 +69,7 @@
struct md_ss_toc *minidump_ss;
struct md_ss_toc *minidump_pdr;
int minidump_id;
+ bool sequential_load;
};
/**
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 02839e2..146fe3e 100755
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1284,6 +1284,8 @@
"snps,usb3-u1u2-disable");
dwc->usb2_l1_disable = device_property_read_bool(dev,
"snps,usb2-l1-disable");
+ dwc->normal_eps_in_gsi_mode = device_property_read_bool(dev,
+ "normal-eps-in-gsi-mode");
if (dwc->enable_bus_suspend) {
pm_runtime_set_autosuspend_delay(dev, 500);
pm_runtime_use_autosuspend(dev);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 89d7ee0..80386d2 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -620,6 +620,7 @@
* @dbg_ep_events_ts: timestamp for previous event counters
* @fifo_depth: allocated TXFIFO depth
* @ep_cfg_init_params: Used by GSI EP to save EP_CFG init_cmd params
+ * @gsi_db_reg_addr: Address of GSI DB register mapped to this EP
*/
struct dwc3_ep {
struct usb_ep endpoint;
@@ -676,6 +677,7 @@
struct timespec dbg_ep_events_ts;
int fifo_depth;
struct dwc3_gadget_ep_cmd_params ep_cfg_init_params;
+ void __iomem *gsi_db_reg_addr;
};
enum dwc3_phy {
@@ -989,6 +991,8 @@
* @create_reg_debugfs: create debugfs entry to allow dwc3 register dump
* @xhci_imod_value: imod value to use with xhci
* @core_id: usb core id to differentiate different controller
+ * @normal_eps_in_gsi_mode: if true, two normal EPS (1 In, 1 Out) can be used in
+ * GSI mode
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -1191,6 +1195,7 @@
u32 xhci_imod_value;
int core_id;
int retries_on_error;
+ bool normal_eps_in_gsi_mode;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index af704b7..37c4e7e 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -203,7 +203,7 @@
"ENABLE_GSI", "UPDATE_XFER", "RING_DB",
"END_XFER", "GET_CH_INFO", "GET_XFER_IDX", "PREPARE_TRBS",
"FREE_TRBS", "SET_CLR_BLOCK_DBL", "CHECK_FOR_SUSP",
- "EP_DISABLE" };
+ "EP_DISABLE", "EP_UPDATE_DB" };
/* Input bits to state machine (mdwc->inputs) */
@@ -312,6 +312,8 @@
u64 dummy_gsi_db;
dma_addr_t dummy_gsi_db_dma;
+ u64 dummy_gevntcnt;
+ dma_addr_t dummy_gevntcnt_dma;
};
#define USB_HSPHY_3P3_VOL_MIN 3050000 /* uV */
@@ -864,6 +866,7 @@
int last_trb_index = 0;
struct dwc3 *dwc = dep->dwc;
struct usb_gsi_request *request = ch_info->ch_req;
+ struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent);
/* Provide physical USB addresses for DEPCMD and GEVENTCNT registers */
ch_info->depcmd_low_addr = (u32)(dwc->reg_phys +
@@ -898,14 +901,28 @@
/* Store last 16 bits of LINK TRB address as per GSI hw requirement */
ch_info->last_trb_addr = (dwc3_trb_dma_offset(dep,
&dep->trb_pool[last_trb_index - 1]) & 0x0000FFFF);
- ch_info->gevntcount_low_addr = (u32)(dwc->reg_phys +
- DWC3_GEVNTCOUNT(ep->ep_intr_num));
- ch_info->gevntcount_hi_addr = 0;
+ dev_dbg(dwc->dev, "depcmd_laddr=%x last_trb_addr=%x\n",
+ ch_info->depcmd_low_addr, ch_info->last_trb_addr);
- dev_dbg(dwc->dev,
- "depcmd_laddr=%x last_trb_addr=%x gevtcnt_laddr=%x gevtcnt_haddr=%x",
- ch_info->depcmd_low_addr, ch_info->last_trb_addr,
- ch_info->gevntcount_low_addr, ch_info->gevntcount_hi_addr);
+ /*
+ * Check if NORMAL EP is used with GSI. In that case USB driver
+ * processes events and GSI shouldn't access GEVNTCOUNT(0) register.
+ */
+ if (ep->ep_intr_num) {
+ ch_info->gevntcount_low_addr = (u32)(dwc->reg_phys +
+ DWC3_GEVNTCOUNT(ep->ep_intr_num));
+ ch_info->gevntcount_hi_addr = 0;
+ dev_dbg(dwc->dev, "gevtcnt_laddr=%x gevtcnt_haddr=%x\n",
+ ch_info->gevntcount_low_addr, ch_info->gevntcount_hi_addr);
+ } else {
+ ch_info->gevntcount_low_addr = (u32)mdwc->dummy_gevntcnt_dma;
+ ch_info->gevntcount_hi_addr =
+ (u32)((u64)mdwc->dummy_gevntcnt_dma >> 32);
+ dev_dbg(dwc->dev, "Dummy GEVNTCNT Addr %pK: %llx %x (LSB)\n",
+ &mdwc->dummy_gevntcnt,
+ (unsigned long long)mdwc->dummy_gevntcnt_dma,
+ (u32)mdwc->dummy_gevntcnt_dma);
+ }
}
/*
@@ -929,8 +946,15 @@
}
memset(¶ms, 0, sizeof(params));
- params.param0 = GSI_TRB_ADDR_BIT_53_MASK | GSI_TRB_ADDR_BIT_55_MASK;
- params.param0 |= (ep->ep_intr_num << 16);
+ /*
+ * Check if NORMAL EP is used with GSI. In that case USB driver
+ * updates GSI doorbell and USB GSI wrapper h/w isn't involved.
+ */
+ if (ep->ep_intr_num) {
+ params.param0 = GSI_TRB_ADDR_BIT_53_MASK |
+ GSI_TRB_ADDR_BIT_55_MASK;
+ params.param0 |= (ep->ep_intr_num << 16);
+ }
params.param1 = lower_32_bits(dwc3_trb_dma_offset(dep,
&dep->trb_pool[0]));
cmd = DWC3_DEPCMD_STARTTRANSFER;
@@ -957,7 +981,18 @@
struct dwc3_ep *dep = to_dwc3_ep(ep);
struct dwc3 *dwc = dep->dwc;
struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent);
- int n = ep->ep_intr_num - 1;
+ int n;
+
+ /*
+ * Check if NORMAL EP is used with GSI. In that case USB driver
+ * updates GSI doorbell and USB GSI wrapper h/w isn't involved.
+ */
+ if (!ep->ep_intr_num) {
+ dev_dbg(mdwc->dev, "%s: is no-op for normal EP\n", __func__);
+ return;
+ }
+
+ n = ep->ep_intr_num - 1;
dwc3_msm_write_reg(mdwc->base, GSI_RING_BASE_ADDR_L(n),
dwc3_trb_dma_offset(dep, &dep->trb_pool[0]));
@@ -991,6 +1026,21 @@
dwc3_msm_read_reg(mdwc->base, GSI_DBL_ADDR_L(n)));
}
+static void dwc3_msm_gsi_db_update(struct dwc3_ep *dep, dma_addr_t offset)
+{
+ struct dwc3 *dwc = dep->dwc;
+ struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent);
+
+ if (!dep->gsi_db_reg_addr) {
+ dev_err(mdwc->dev, "Failed to update GSI DBL\n");
+ return;
+ }
+
+ writel_relaxed(offset, dep->gsi_db_reg_addr);
+ dev_dbg(mdwc->dev, "Writing TRB addr: %pa to %pK\n",
+ &offset, dep->gsi_db_reg_addr);
+}
+
/*
* Rings Doorbell for GSI Channel
*
@@ -1016,6 +1066,8 @@
return;
}
+ dep->gsi_db_reg_addr = gsi_dbl_address_lsb;
+
gsi_dbl_address_msb = devm_ioremap_nocache(mdwc->dev,
request->db_reg_phs_addr_msb, sizeof(u32));
if (!gsi_dbl_address_msb) {
@@ -1399,6 +1451,15 @@
struct dwc3 *dwc = dep->dwc;
struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent);
+ /*
+ * Check if NORMAL EP is used with GSI. In that case USB driver
+ * updates GSI doorbell and USB GSI wrapper h/w isn't involved.
+ */
+ if (!ep->ep_intr_num) {
+ dev_dbg(mdwc->dev, "%s: is no-op for normal EP\n", __func__);
+ return;
+ }
+
dwc3_msm_write_reg_field(mdwc->base,
GSI_GENERAL_CFG_REG, GSI_CLK_EN_MASK, 1);
dwc3_msm_write_reg_field(mdwc->base,
@@ -1435,6 +1496,12 @@
else
gsi_enable_ep_events(ep);
+ /* Nothing to be done if NORMAL EP is used with GSI */
+ if (!ep->ep_intr_num) {
+ dev_dbg(mdwc->dev, "%s: is no-op for normal EP\n", __func__);
+ return;
+ }
+
dwc3_msm_write_reg_field(mdwc->base,
GSI_GENERAL_CFG_REG, BLOCK_GSI_WR_GO_MASK, block_db);
}
@@ -1490,6 +1557,7 @@
struct gsi_channel_info *ch_info;
bool block_db;
unsigned long flags;
+ dma_addr_t offset;
dbg_log_string("%s(%d):%s", ep->name, ep->ep_num, gsi_op_to_string(op));
@@ -1555,6 +1623,10 @@
case GSI_EP_OP_DISABLE:
ret = ep->ops->disable(ep);
break;
+ case GSI_EP_OP_UPDATE_DB:
+ offset = *(dma_addr_t *)op_data;
+ dwc3_msm_gsi_db_update(dep, offset);
+ break;
default:
dev_err(mdwc->dev, "%s: Invalid opcode GSI EP\n", __func__);
}
@@ -2065,6 +2137,19 @@
dev_err(dwc->dev, "failed to map dummy doorbell buffer\n");
mdwc->dummy_gsi_db_dma = (dma_addr_t)NULL;
}
+
+ /*
+ * Set-up dummy GEVNTCOUNT address to be passed on to GSI for
+ * normal (non HW-accelerated) EPs.
+ */
+ mdwc->dummy_gevntcnt_dma = dma_map_single(dwc->sysdev,
+ &mdwc->dummy_gevntcnt,
+ sizeof(mdwc->dummy_gevntcnt),
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(dwc->sysdev, mdwc->dummy_gevntcnt_dma)) {
+ dev_err(dwc->dev, "failed to map dummy geventcount\n");
+ mdwc->dummy_gevntcnt_dma = (dma_addr_t)NULL;
+ }
break;
case DWC3_GSI_EVT_BUF_SETUP:
dev_dbg(mdwc->dev, "DWC3_GSI_EVT_BUF_SETUP\n");
@@ -2138,6 +2223,12 @@
dma_free_coherent(dwc->sysdev, evt->length,
evt->buf, evt->dma);
}
+ if (mdwc->dummy_gevntcnt_dma) {
+ dma_unmap_single(dwc->sysdev, mdwc->dummy_gevntcnt_dma,
+ sizeof(mdwc->dummy_gevntcnt),
+ DMA_FROM_DEVICE);
+ mdwc->dummy_gevntcnt_dma = (dma_addr_t)NULL;
+ }
if (mdwc->dummy_gsi_db_dma) {
dma_unmap_single(dwc->sysdev, mdwc->dummy_gsi_db_dma,
sizeof(mdwc->dummy_gsi_db),
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index e8d270d..d0391b4 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2390,8 +2390,8 @@
/* -------------------------------------------------------------------------- */
-#define NUM_GSI_OUT_EPS 1
-#define NUM_GSI_IN_EPS 2
+#define NUM_GSI_OUT_EPS(dwc) (dwc->normal_eps_in_gsi_mode ? 2 : 1)
+#define NUM_GSI_IN_EPS(dwc) (dwc->normal_eps_in_gsi_mode ? 3 : 2)
static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
u8 num, u32 direction)
@@ -2399,13 +2399,13 @@
struct dwc3_ep *dep;
u8 i, gsi_ep_count, gsi_ep_index = 0;
- gsi_ep_count = NUM_GSI_OUT_EPS + NUM_GSI_IN_EPS;
+ gsi_ep_count = NUM_GSI_OUT_EPS(dwc) + NUM_GSI_IN_EPS(dwc);
/* OUT GSI EPs based on direction field */
if (gsi_ep_count && !direction)
- gsi_ep_count = NUM_GSI_OUT_EPS;
+ gsi_ep_count = NUM_GSI_OUT_EPS(dwc);
/* IN GSI EPs */
else if (gsi_ep_count && direction)
- gsi_ep_count = NUM_GSI_IN_EPS;
+ gsi_ep_count = NUM_GSI_IN_EPS(dwc);
for (i = 0; i < num; i++) {
u8 epnum = (i << 1) | (direction ? 1 : 0);
@@ -2710,6 +2710,25 @@
return 1;
}
+static void dwc3_gsi_ep_transfer_complete(struct dwc3 *dwc, struct dwc3_ep *dep)
+{
+ struct usb_ep *ep = &dep->endpoint;
+ struct dwc3_trb *trb;
+ dma_addr_t offset;
+
+ trb = &dep->trb_pool[dep->trb_dequeue];
+ while (trb->ctrl & DWC3_TRBCTL_LINK_TRB) {
+ dwc3_ep_inc_trb(&dep->trb_dequeue);
+ trb = &dep->trb_pool[dep->trb_dequeue];
+ }
+
+ if (!(trb->ctrl & DWC3_TRB_CTRL_HWO)) {
+ offset = dwc3_trb_dma_offset(dep, trb);
+ usb_gsi_ep_op(ep, (void *)&offset, GSI_EP_OP_UPDATE_DB);
+ dwc3_ep_inc_trb(&dep->trb_dequeue);
+ }
+}
+
static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
{
@@ -2721,6 +2740,15 @@
if (event->status & DEPEVT_STATUS_BUSERR)
status = -ECONNRESET;
+ /*
+ * Check if NORMAL EP is used with GSI.
+ * In that case dwc3 driver recevies EP events from hardware and
+ * updates GSI doorbell with completed TRB.
+ */
+ if (dep->endpoint.ep_type == EP_TYPE_GSI) {
+ dwc3_gsi_ep_transfer_complete(dwc, dep);
+ return;
+ }
clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c
index ffd5952..d58b20a 100644
--- a/drivers/usb/gadget/function/f_gsi.c
+++ b/drivers/usb/gadget/function/f_gsi.c
@@ -572,9 +572,11 @@
GSI_EP_OP_GET_CH_INFO);
log_event_dbg("%s: USB GSI IN OPS Completed", __func__);
- in_params->client =
- (gsi->prot_id != USB_PROT_DIAG_IPA) ? IPA_CLIENT_USB_CONS :
- IPA_CLIENT_USB_DPL_CONS;
+ if (gsi->prot_id != USB_PROT_DIAG_IPA)
+ in_params->client = (gsi->prot_id != USB_PROT_RMNET_V2X_IPA) ?
+ IPA_CLIENT_USB_CONS : IPA_CLIENT_USB2_CONS;
+ else
+ in_params->client = IPA_CLIENT_USB_DPL_CONS;
in_params->ipa_ep_cfg.mode.mode = IPA_BASIC;
in_params->teth_prot = (enum ipa_usb_teth_prot)gsi->prot_id;
in_params->gevntcount_low_addr =
@@ -627,7 +629,8 @@
usb_gsi_ep_op(d_port->out_ep, (void *)&gsi_channel_info,
GSI_EP_OP_GET_CH_INFO);
log_event_dbg("%s: USB GSI OUT OPS Completed", __func__);
- out_params->client = IPA_CLIENT_USB_PROD;
+ out_params->client = (gsi->prot_id != USB_PROT_RMNET_V2X_IPA) ?
+ IPA_CLIENT_USB_PROD : IPA_CLIENT_USB2_PROD;
out_params->ipa_ep_cfg.mode.mode = IPA_BASIC;
out_params->teth_prot = (enum ipa_usb_teth_prot)gsi->prot_id;
out_params->gevntcount_low_addr =
@@ -1521,6 +1524,7 @@
case GSI_MBIM_GPS_USB_STATUS:
val = atomic_read(&gsi->connected);
if (gsi->prot_id == USB_PROT_RMNET_IPA ||
+ gsi->prot_id == USB_PROT_RMNET_V2X_IPA ||
gsi->prot_id == USB_PROT_RMNET_ETHER)
val = gsi->rmnet_dtr_status;
@@ -1701,6 +1705,9 @@
case USB_PROT_RMNET_IPA:
cdev_name = GSI_RMNET_CTRL_NAME;
break;
+ case USB_PROT_RMNET_V2X_IPA:
+ cdev_name = GSI_RMNET_V2X_CTRL_NAME;
+ break;
case USB_PROT_RMNET_ETHER:
cdev_name = ETHER_RMNET_CTRL_NAME;
break;
@@ -2190,6 +2197,7 @@
| USB_CDC_REQ_SET_CONTROL_LINE_STATE:
line_state = (w_value & GSI_CTRL_DTR ? true : false);
if (gsi->prot_id == USB_PROT_RMNET_IPA ||
+ gsi->prot_id == USB_PROT_RMNET_V2X_IPA ||
gsi->prot_id == USB_PROT_RMNET_ETHER)
gsi->rmnet_dtr_status = line_state;
log_event_dbg("%s: USB_CDC_REQ_SET_CONTROL_LINE_STATE DTR:%d\n",
@@ -2293,6 +2301,7 @@
/* RNDIS, RMNET and DPL only support alt 0*/
if (intf == gsi->ctrl_id || gsi->prot_id == USB_PROT_RNDIS_IPA ||
gsi->prot_id == USB_PROT_RMNET_IPA ||
+ gsi->prot_id == USB_PROT_RMNET_V2X_IPA ||
gsi->prot_id == USB_PROT_DIAG_IPA ||
is_ext_prot_ether(gsi->prot_id))
return 0;
@@ -2414,6 +2423,7 @@
/* Control interface has only altsetting 0 */
if (intf == gsi->ctrl_id || gsi->prot_id == USB_PROT_RMNET_IPA ||
+ gsi->prot_id == USB_PROT_RMNET_V2X_IPA ||
gsi->prot_id == USB_PROT_RMNET_ETHER) {
if (alt != 0)
goto fail;
@@ -2450,6 +2460,7 @@
/* for rndis and rmnet alt is always 0 update alt accordingly */
if (gsi->prot_id == USB_PROT_RNDIS_IPA ||
gsi->prot_id == USB_PROT_RMNET_IPA ||
+ gsi->prot_id == USB_PROT_RMNET_V2X_IPA ||
gsi->prot_id == USB_PROT_DIAG_IPA ||
is_ext_prot_ether(gsi->prot_id))
alt = 1;
@@ -2480,9 +2491,11 @@
/* Configure EPs for GSI */
if (gsi->d_port.in_ep &&
- gsi->prot_id <= USB_PROT_DIAG_IPA) {
+ gsi->prot_id <= USB_PROT_RMNET_V2X_IPA) {
if (gsi->prot_id == USB_PROT_DIAG_IPA)
gsi->d_port.in_ep->ep_intr_num = 3;
+ else if (gsi->prot_id == USB_PROT_RMNET_V2X_IPA)
+ gsi->d_port.in_ep->ep_intr_num = 0;
else
gsi->d_port.in_ep->ep_intr_num = 2;
usb_gsi_ep_op(gsi->d_port.in_ep,
@@ -2491,8 +2504,11 @@
}
if (gsi->d_port.out_ep &&
- gsi->prot_id <= USB_PROT_DIAG_IPA) {
- gsi->d_port.out_ep->ep_intr_num = 1;
+ gsi->prot_id <= USB_PROT_RMNET_V2X_IPA) {
+ if (gsi->prot_id == USB_PROT_RMNET_V2X_IPA)
+ gsi->d_port.out_ep->ep_intr_num = 0;
+ else
+ gsi->d_port.out_ep->ep_intr_num = 1;
usb_gsi_ep_op(gsi->d_port.out_ep,
&gsi->d_port.out_request,
GSI_EP_OP_CONFIG);
@@ -2587,6 +2603,7 @@
rndis_uninit(gsi->params);
if (gsi->prot_id == USB_PROT_RMNET_IPA ||
+ gsi->prot_id == USB_PROT_RMNET_V2X_IPA ||
gsi->prot_id == USB_PROT_RMNET_ETHER)
gsi->rmnet_dtr_status = false;
@@ -2817,7 +2834,7 @@
info->data_nop_desc->bInterfaceNumber = gsi->data_id;
/* allocate instance-specific endpoints */
- if (info->fs_in_desc && gsi->prot_id <= USB_PROT_DIAG_IPA) {
+ if (info->fs_in_desc && gsi->prot_id <= USB_PROT_RMNET_V2X_IPA) {
ep = usb_ep_autoconfig_by_name(cdev->gadget,
info->fs_in_desc, info->in_epname);
if (!ep)
@@ -2835,7 +2852,7 @@
}
}
- if (info->fs_out_desc && gsi->prot_id <= USB_PROT_DIAG_IPA) {
+ if (info->fs_out_desc && gsi->prot_id <= USB_PROT_RMNET_V2X_IPA) {
ep = usb_ep_autoconfig_by_name(cdev->gadget,
info->fs_out_desc, info->out_epname);
if (!ep)
@@ -3011,6 +3028,7 @@
if (gsi->prot_id == USB_PROT_RMNET_IPA ||
+ gsi->prot_id == USB_PROT_RMNET_V2X_IPA ||
gsi->prot_id == USB_PROT_DIAG_IPA ||
is_ext_prot_ether(gsi->prot_id))
gsi->ctrl_id = -ENODEV;
@@ -3222,6 +3240,7 @@
}
break;
case USB_PROT_RMNET_IPA:
+ case USB_PROT_RMNET_V2X_IPA:
case USB_PROT_RMNET_ETHER:
info.string_defs = rmnet_gsi_string_defs;
info.data_desc = &rmnet_gsi_interface_desc;
@@ -3487,6 +3506,7 @@
gsi->function.strings = ecm_gsi_strings;
break;
case USB_PROT_RMNET_IPA:
+ case USB_PROT_RMNET_V2X_IPA:
case USB_PROT_RMNET_ETHER:
gsi->function.name = "rmnet";
gsi->function.strings = rmnet_gsi_strings;
@@ -3885,6 +3905,7 @@
switch (gsi->prot_id) {
case USB_PROT_RMNET_IPA:
+ case USB_PROT_RMNET_V2X_IPA:
case USB_PROT_RMNET_ETHER:
str = gsi->rmnet_dtr_status ? "connected" : "disconnected";
break;
diff --git a/drivers/usb/gadget/function/f_gsi.h b/drivers/usb/gadget/function/f_gsi.h
index b7e8fe8..02be58d 100644
--- a/drivers/usb/gadget/function/f_gsi.h
+++ b/drivers/usb/gadget/function/f_gsi.h
@@ -32,6 +32,7 @@
#include "configfs.h"
#define GSI_RMNET_CTRL_NAME "rmnet_ctrl"
+#define GSI_RMNET_V2X_CTRL_NAME "rmnet_v2x_ctrl"
#define GSI_MBIM_CTRL_NAME "android_mbim"
#define GSI_DPL_CTRL_NAME "dpl_ctrl"
#define ETHER_RMNET_CTRL_NAME "rmnet_ctrl0"
@@ -125,6 +126,7 @@
USB_PROT_RMNET_IPA,
USB_PROT_MBIM_IPA,
USB_PROT_DIAG_IPA,
+ USB_PROT_RMNET_V2X_IPA,
/* non-accelerated */
USB_PROT_RMNET_ETHER,
@@ -339,6 +341,8 @@
return USB_PROT_MBIM_IPA;
if (!strncasecmp(name, "dpl", MAX_INST_NAME_LEN))
return USB_PROT_DIAG_IPA;
+ if (!strncasecmp(name, "rmnet.v2x", MAX_INST_NAME_LEN))
+ return USB_PROT_RMNET_V2X_IPA;
if (!strncasecmp(name, "rmnet.ether", MAX_INST_NAME_LEN))
return USB_PROT_RMNET_ETHER;
if (!strncasecmp(name, "dpl.ether", MAX_INST_NAME_LEN))
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index 0267bed..418978e 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -67,6 +67,7 @@
GSI_EP_OP_SET_CLR_BLOCK_DBL,
GSI_EP_OP_CHECK_FOR_SUSPEND,
GSI_EP_OP_DISABLE,
+ GSI_EP_OP_UPDATE_DB,
};
/*
diff --git a/include/uapi/linux/msm_ipa.h b/include/uapi/linux/msm_ipa.h
index 96523b5..e64942a 100644
--- a/include/uapi/linux/msm_ipa.h
+++ b/include/uapi/linux/msm_ipa.h
@@ -152,6 +152,11 @@
#define QMI_IPA_MAX_CLIENT_DST_PIPES 4
/**
+ * New feature flag for CV2X config
+ */
+#define IPA_CV2X_SUPPORT
+
+/**
* the attributes of the rule (routing or filtering)
*/
#define IPA_FLT_TOS (1ul << 0)
@@ -326,11 +331,14 @@
/* RESERVERD PROD = 84, */
IPA_CLIENT_WIGIG4_CONS = 85,
+
+ IPA_CLIENT_MHI2_PROD = 86,
+ IPA_CLIENT_MHI2_CONS = 87,
};
#define IPA_CLIENT_DUMMY_CONS IPA_CLIENT_DUMMY_CONS1
#define IPA_CLIENT_WIGIG4_CONS IPA_CLIENT_WIGIG4_CONS
-#define IPA_CLIENT_MAX (IPA_CLIENT_WIGIG4_CONS + 1)
+#define IPA_CLIENT_MAX (IPA_CLIENT_MHI2_CONS + 1)
#define IPA_CLIENT_IS_APPS_CONS(client) \
((client) == IPA_CLIENT_APPS_LAN_CONS || \
diff --git a/kernel/sched/walt.c b/kernel/sched/walt.c
index 48f64aa..9a85525 100644
--- a/kernel/sched/walt.c
+++ b/kernel/sched/walt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -323,14 +323,19 @@
int register_cpu_cycle_counter_cb(struct cpu_cycle_counter_cb *cb)
{
+ unsigned long flags;
+
mutex_lock(&cluster_lock);
if (!cb->get_cpu_cycle_counter) {
mutex_unlock(&cluster_lock);
return -EINVAL;
}
+ acquire_rq_locks_irqsave(cpu_possible_mask, &flags);
cpu_cycle_counter_cb = *cb;
use_cycle_counter = true;
+ release_rq_locks_irqrestore(cpu_possible_mask, &flags);
+
mutex_unlock(&cluster_lock);
return 0;