Merge "ARM: dts: msm: Add initial dts support for QCM2150 QRD"
diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt b/Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt
new file mode 100644
index 0000000..aeed60f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt
@@ -0,0 +1,102 @@
+* Qualcomm Technologies, Inc. MSM camera PPI
+
+=======================
+Required Node Structure
+=======================
+The camera PPI node must be described in First level of device nodes. The
+first level describe the overall PPI node structure.
+
+======================================
+First Level Node - PPI device
+======================================
+
+- compatible
+ Usage: required
+ Value type: <string>
+ Definition: Should be "qcom,ppi-v1.0",
+ "qcom,ppi-v1.1", "qcom,ppi-v1.2",
+ "qcom,ppi-v2.0", "qcom,ppi".
+
+- cell-index: ppi hardware core index
+ Usage: required
+ Value type: <u32>
+ Definition: Should specify the Hardware index id.
+
+- reg
+ Usage: required
+ Value type: <u32>
+ Definition: offset and length of the register set
+ for the device for the ppi operating in
+ compatible mode.
+
+- reg-names
+ Usage: required
+ Value type: <string>
+ Definition: Should specify relevant names to each
+ reg property defined.
+
+- reg-cam-base
+ Usage: required
+ Value type: <string>
+ Definition: offset of PPI in camera hw block
+
+- interrupts
+ Usage: required
+ Value type: <u32>
+ Definition: Interrupt associated with PPI HW.
+
+- interrupt-names
+ Usage: required
+ Value type: <string>
+ Definition: Name of the interrupt.
+
+- clock-names
+ Usage: required
+ Value type: <string>
+ Definition: List of clock names required for PPI HW.
+
+- clock-rates
+ Usage: required
+ Value type: <u32>
+ Definition: List of clock rates in Hz for PPI HW.
+
+- clock-cntl-level
+ Usage: required
+ Value type: <string>
+ Definition: All different clock level node can support.
+
+- clocks
+ Usage: required
+ Value type: <phandle>
+ Definition: all clock phandle and source clocks.
+
+- regulator-names
+ Usage: required
+ Value type: <string>
+ Definition: name of the voltage regulators required for the device.
+
+- gdscr-supply
+ Usage: required
+ Value type: <phandle>
+ Definition: should contain gdsr regulator used for PPI clocks.
+
+Example:
+ qcom,ppi0@ace0000 {
+ cell-index = <0>;
+ compatible = "qcom,ppi170";
+ reg-names = "ppi";
+ reg = <0xace0000 0x200>;
+ reg-cam-base = <0xe0000>;
+ interrupt-names = "ppi";
+ interrupts = <0 202 0>;
+ regulator-names = "gdscr", "refgen";
+ gdscr-supply = <&titan_top_gdsc>;
+ clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_PPI0_CLK>,
+ <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src", "ppi0_clk"
+ clock-rates = <400000000 0 300000000 0>;
+ clock-cntl-level = "turbo";
+ status = "ok";
+};
diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile
index ff0ae9a..d1edfd9 100644
--- a/arch/arm/boot/dts/qcom/Makefile
+++ b/arch/arm/boot/dts/qcom/Makefile
@@ -3,7 +3,6 @@
sdxpoorwills-cdp.dtb \
sdxpoorwills-mtp.dtb \
sdxpoorwills-atp.dtb \
- sa415m-ttp.dtb \
sdxpoorwills-cdp-256.dtb \
sdxpoorwills-mtp-256.dtb \
sdxpoorwills-dualwifi-cdp.dtb \
@@ -16,12 +15,17 @@
sdxpoorwills-v2-cdp.dtb \
sdxpoorwills-v2-dualwifi-mtp.dtb \
sdxpoorwills-v2-dualwifi-cdp.dtb \
+ sdxpoorwills-v2-pcie-ep-mtp-256.dtb \
+ sdxpoorwills-v2-pcie-ep-mtp.dtb \
+ sa415m-ttp.dtb \
sa415m-ccard.dtb \
sa415m-ccard-pcie-ep.dtb \
sa415m-ccard-usb-ep.dtb \
sa415m-ttp-usb-ep.dtb \
- sdxpoorwills-v2-pcie-ep-mtp-256.dtb \
- sdxpoorwills-v2-pcie-ep-mtp.dtb
+ sa415m-mtp-256.dtb \
+ sa415m-cdp.dtb \
+ sa415m-v2-cdp.dtb \
+ sa415m-v2-mtp.dtb
dtb-$(CONFIG_ARCH_MDM9650) += mdm9650-nand-mtp.dtb \
mdm9650-ttp.dtb \
diff --git a/arch/arm/boot/dts/qcom/sa415m-cdp.dts b/arch/arm/boot/dts/qcom/sa415m-cdp.dts
new file mode 100644
index 0000000..b9e7d49
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/sa415m-cdp.dts
@@ -0,0 +1,32 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "sdxpoorwills-cdp.dtsi"
+#include "sdxpoorwills-display.dtsi"
+#include "qpic-panel-ili-hvga.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SA415M CDP";
+ compatible = "qcom,sdxpoorwills-cdp",
+ "qcom,sdxpoorwills", "qcom,cdp";
+ qcom,board-id = <1 0x104>;
+};
+
+&blsp1_uart2b_hs {
+ status = "okay";
+};
+
+&mss_mem {
+ reg = <0x86400000 0x9300000>;
+};
diff --git a/arch/arm/boot/dts/qcom/sa415m-mtp-256.dts b/arch/arm/boot/dts/qcom/sa415m-mtp-256.dts
new file mode 100644
index 0000000..09a8ea0
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/sa415m-mtp-256.dts
@@ -0,0 +1,30 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "sdxpoorwills-mtp-256.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SA415M MTP (256MB)";
+ compatible = "qcom,sdxpoorwills-mtp",
+ "qcom,sdxpoorwills", "qcom,mtp";
+ qcom,board-id = <8 0x106>;
+};
+
+&blsp1_uart2b_hs {
+ status = "okay";
+};
+
+&mss_mem {
+ reg = <0x86400000 0x9300000>;
+};
diff --git a/arch/arm/boot/dts/qcom/sa415m-v2-cdp.dts b/arch/arm/boot/dts/qcom/sa415m-v2-cdp.dts
new file mode 100644
index 0000000..c8b7891
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/sa415m-v2-cdp.dts
@@ -0,0 +1,33 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "sdxpoorwills-cdp.dtsi"
+#include "sdxpoorwills-v2.dtsi"
+#include "sdxpoorwills-display.dtsi"
+#include "qpic-panel-ili-hvga.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SA415M CDP V2";
+ compatible = "qcom,sdxpoorwills-cdp",
+ "qcom,sdxpoorwills", "qcom,cdp";
+ qcom,board-id = <1 0x104>;
+};
+
+&blsp1_uart2b_hs {
+ status = "okay";
+};
+
+&mss_mem {
+ reg = <0x86400000 0x9300000>;
+};
diff --git a/arch/arm/boot/dts/qcom/sa415m-v2-mtp.dts b/arch/arm/boot/dts/qcom/sa415m-v2-mtp.dts
new file mode 100644
index 0000000..c7cbbd1
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/sa415m-v2-mtp.dts
@@ -0,0 +1,35 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "sdxpoorwills-mtp.dtsi"
+#include "sdxpoorwills-v2.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SA415M MTP V2";
+ compatible = "qcom,sdxpoorwills-mtp",
+ "qcom,sdxpoorwills", "qcom,mtp";
+ qcom,board-id = <8 0x106>;
+};
+
+&qcom_seecom {
+ status = "okay";
+};
+
+&blsp1_uart2b_hs {
+ status = "okay";
+};
+
+&mss_mem {
+ reg = <0x86400000 0x9300000>;
+};
diff --git a/arch/arm/configs/msm8937-perf_defconfig b/arch/arm/configs/msm8937-perf_defconfig
index f9fcc7c..15bd01d 100755
--- a/arch/arm/configs/msm8937-perf_defconfig
+++ b/arch/arm/configs/msm8937-perf_defconfig
@@ -39,7 +39,6 @@
# CONFIG_RD_LZ4 is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
@@ -90,7 +89,6 @@
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -98,6 +96,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -107,6 +106,7 @@
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=y
CONFIG_INET_AH=y
@@ -219,6 +219,7 @@
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
@@ -276,6 +277,7 @@
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
@@ -294,11 +296,13 @@
CONFIG_PPP_MPPE=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=y
+CONFIG_PPTP=y
CONFIG_PPPOL2TP=y
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
diff --git a/arch/arm/configs/msm8937_defconfig b/arch/arm/configs/msm8937_defconfig
index 502de4451..12254aa 100755
--- a/arch/arm/configs/msm8937_defconfig
+++ b/arch/arm/configs/msm8937_defconfig
@@ -40,7 +40,6 @@
# CONFIG_RD_LZ4 is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
@@ -92,7 +91,6 @@
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -101,6 +99,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -110,6 +109,7 @@
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_IPVTI=y
CONFIG_INET_AH=y
@@ -222,6 +222,7 @@
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
@@ -280,6 +281,7 @@
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
@@ -298,11 +300,13 @@
CONFIG_PPP_MPPE=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=y
+CONFIG_PPTP=y
CONFIG_PPPOL2TP=y
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
diff --git a/arch/arm/configs/msm8937go-perf_defconfig b/arch/arm/configs/msm8937go-perf_defconfig
index 9667e5f..8420285 100755
--- a/arch/arm/configs/msm8937go-perf_defconfig
+++ b/arch/arm/configs/msm8937go-perf_defconfig
@@ -40,7 +40,6 @@
CONFIG_KALLSYMS_ALL=y
# CONFIG_BASE_FULL is not set
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
@@ -90,7 +89,6 @@
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -98,6 +96,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -107,10 +106,12 @@
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IPVTI=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
CONFIG_INET_DIAG_DESTROY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
@@ -216,6 +217,7 @@
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
@@ -272,6 +274,7 @@
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_ANDROID_VERITY_AT_MOST_ONCE_DEFAULT_ENABLED=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
@@ -290,11 +293,13 @@
CONFIG_PPP_MPPE=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=y
+CONFIG_PPTP=y
CONFIG_PPPOL2TP=y
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
diff --git a/arch/arm/configs/msm8937go_defconfig b/arch/arm/configs/msm8937go_defconfig
index 7b15381..b9cdd7e 100755
--- a/arch/arm/configs/msm8937go_defconfig
+++ b/arch/arm/configs/msm8937go_defconfig
@@ -41,7 +41,6 @@
CONFIG_KALLSYMS_ALL=y
# CONFIG_BASE_FULL is not set
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
@@ -92,7 +91,6 @@
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -101,6 +99,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -110,10 +109,12 @@
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IPVTI=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
CONFIG_INET_DIAG_DESTROY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
@@ -219,6 +220,7 @@
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
@@ -276,6 +278,7 @@
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
CONFIG_DM_ANDROID_VERITY_AT_MOST_ONCE_DEFAULT_ENABLED=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
@@ -294,11 +297,13 @@
CONFIG_PPP_MPPE=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=y
+CONFIG_PPTP=y
CONFIG_PPPOL2TP=y
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
diff --git a/arch/arm/configs/msm8953-perf_defconfig b/arch/arm/configs/msm8953-perf_defconfig
index 3bda5c1..714cab1 100755
--- a/arch/arm/configs/msm8953-perf_defconfig
+++ b/arch/arm/configs/msm8953-perf_defconfig
@@ -37,7 +37,6 @@
# CONFIG_RD_LZ4 is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
@@ -85,7 +84,6 @@
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -93,6 +91,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -102,10 +101,12 @@
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IPVTI=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
CONFIG_INET_DIAG_DESTROY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
@@ -211,6 +212,7 @@
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
@@ -266,6 +268,7 @@
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
@@ -284,11 +287,13 @@
CONFIG_PPP_MPPE=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=y
+CONFIG_PPTP=y
CONFIG_PPPOL2TP=y
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
diff --git a/arch/arm/configs/msm8953_defconfig b/arch/arm/configs/msm8953_defconfig
index f7bc2ed..0697744 100755
--- a/arch/arm/configs/msm8953_defconfig
+++ b/arch/arm/configs/msm8953_defconfig
@@ -38,7 +38,6 @@
# CONFIG_RD_LZ4 is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
@@ -88,7 +87,6 @@
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -97,6 +95,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -106,10 +105,12 @@
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=y
CONFIG_NET_IPVTI=y
CONFIG_INET_AH=y
CONFIG_INET_ESP=y
CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
CONFIG_INET_DIAG_DESTROY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
@@ -215,6 +216,7 @@
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
@@ -271,6 +273,7 @@
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
@@ -289,11 +292,13 @@
CONFIG_PPP_MPPE=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPPOE=y
+CONFIG_PPTP=y
CONFIG_PPPOL2TP=y
CONFIG_PPPOLAC=y
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
diff --git a/arch/arm64/boot/dts/qcom/sdm429-spyro-qrd-evt.dtsi b/arch/arm64/boot/dts/qcom/sdm429-spyro-qrd-evt.dtsi
index 0f73bd9..9014166 100644
--- a/arch/arm64/boot/dts/qcom/sdm429-spyro-qrd-evt.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm429-spyro-qrd-evt.dtsi
@@ -233,7 +233,7 @@
&secure_mem {
alignment = <0 0x400000>;
- size = <0 0x400000>;
+ size = <0 0x800000>;
status = "okay";
};
diff --git a/arch/arm64/configs/msm8937-perf_defconfig b/arch/arm64/configs/msm8937-perf_defconfig
index c1b861c..2ea4bd0 100755
--- a/arch/arm64/configs/msm8937-perf_defconfig
+++ b/arch/arm64/configs/msm8937-perf_defconfig
@@ -38,7 +38,6 @@
# CONFIG_RD_LZ4 is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
@@ -80,7 +79,6 @@
CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_COMPAT=y
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -97,6 +95,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -218,6 +217,7 @@
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
@@ -275,6 +275,7 @@
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
@@ -299,6 +300,7 @@
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
diff --git a/arch/arm64/configs/msm8937_defconfig b/arch/arm64/configs/msm8937_defconfig
index b172fe3..c6312ed 100755
--- a/arch/arm64/configs/msm8937_defconfig
+++ b/arch/arm64/configs/msm8937_defconfig
@@ -39,7 +39,6 @@
# CONFIG_RD_LZ4 is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
@@ -83,7 +82,6 @@
CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_COMPAT=y
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -101,6 +99,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -223,6 +222,7 @@
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
@@ -281,6 +281,7 @@
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
@@ -305,6 +306,7 @@
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
@@ -340,6 +342,7 @@
# CONFIG_SERIO_SERPORT is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVMEM is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
diff --git a/arch/arm64/configs/msm8953-perf_defconfig b/arch/arm64/configs/msm8953-perf_defconfig
index 79b92b8..4374ef3 100755
--- a/arch/arm64/configs/msm8953-perf_defconfig
+++ b/arch/arm64/configs/msm8953-perf_defconfig
@@ -38,7 +38,6 @@
# CONFIG_RD_LZ4 is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
@@ -79,7 +78,6 @@
CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_COMPAT=y
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -96,6 +94,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -215,6 +214,7 @@
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
@@ -273,6 +273,7 @@
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
@@ -296,6 +297,7 @@
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
diff --git a/arch/arm64/configs/msm8953_defconfig b/arch/arm64/configs/msm8953_defconfig
index 02eea30..66ae8cf 100755
--- a/arch/arm64/configs/msm8953_defconfig
+++ b/arch/arm64/configs/msm8953_defconfig
@@ -39,7 +39,6 @@
# CONFIG_RD_LZ4 is not set
CONFIG_KALLSYMS_ALL=y
CONFIG_BPF_SYSCALL=y
-# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
@@ -82,7 +81,6 @@
CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_COMPAT=y
-CONFIG_PM_AUTOSLEEP=y
CONFIG_PM_WAKELOCKS=y
CONFIG_PM_WAKELOCKS_LIMIT=0
# CONFIG_PM_WAKELOCKS_GC is not set
@@ -100,6 +98,7 @@
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
CONFIG_XFRM_STATISTICS=y
CONFIG_NET_KEY=y
CONFIG_INET=y
@@ -220,6 +219,7 @@
CONFIG_NET_SCHED=y
CONFIG_NET_SCH_HTB=y
CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
CONFIG_NET_CLS_FW=y
CONFIG_NET_CLS_U32=y
CONFIG_CLS_U32_MARK=y
@@ -279,6 +279,7 @@
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_TUN=y
@@ -303,6 +304,7 @@
CONFIG_PPPOPNS=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
CONFIG_USB_USBNET=y
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c
index dba81f9..f62d96d 100644
--- a/drivers/char/adsprpc.c
+++ b/drivers/char/adsprpc.c
@@ -744,15 +744,14 @@
}
if (map->flags == ADSP_MMAP_HEAP_ADDR ||
map->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) {
- unsigned long dma_attrs = 0;
if (me->dev == NULL) {
pr_err("failed to free remote heap allocation\n");
return;
}
if (map->phys) {
- dma_attrs |=
- DMA_ATTR_SKIP_ZEROING | DMA_ATTR_NO_KERNEL_MAPPING;
+ unsigned long dma_attrs = DMA_ATTR_SKIP_ZEROING |
+ DMA_ATTR_NO_KERNEL_MAPPING;
dma_free_attrs(me->dev, map->size, (void *)map->va,
(dma_addr_t)map->phys, dma_attrs);
}
@@ -2451,29 +2450,34 @@
{
int err = 0;
struct fastrpc_apps *me = &gfa;
+ int tgid = 0;
int destVM[1] = {VMID_HLOS};
int destVMperm[1] = {PERM_READ | PERM_WRITE | PERM_EXEC};
if (flags == ADSP_MMAP_HEAP_ADDR) {
struct fastrpc_ioctl_invoke_crc ioctl;
struct scm_desc desc = {0};
- remote_arg_t ra[1];
- int err = 0;
+ remote_arg_t ra[2];
+
struct {
uint8_t skey;
} routargs;
- ra[0].buf.pv = (void *)&routargs;
- ra[0].buf.len = sizeof(routargs);
+ if (fl == NULL)
+ goto bail;
+ tgid = fl->tgid;
+ ra[0].buf.pv = (void *)&tgid;
+ ra[0].buf.len = sizeof(tgid);
+ ra[1].buf.pv = (void *)&routargs;
+ ra[1].buf.len = sizeof(routargs);
ioctl.inv.handle = FASTRPC_STATIC_HANDLE_KERNEL;
- ioctl.inv.sc = REMOTE_SCALARS_MAKE(7, 0, 1);
+ ioctl.inv.sc = REMOTE_SCALARS_MAKE(9, 1, 1);
ioctl.inv.pra = ra;
ioctl.fds = NULL;
ioctl.attrs = NULL;
ioctl.crc = NULL;
- if (fl == NULL)
- goto bail;
+
VERIFY(err, 0 == (err = fastrpc_internal_invoke(fl,
FASTRPC_MODE_PARALLEL, 1, &ioctl)));
diff --git a/drivers/char/diag/diagfwd_peripheral.c b/drivers/char/diag/diagfwd_peripheral.c
index 560f0df..d99f984 100644
--- a/drivers/char/diag/diagfwd_peripheral.c
+++ b/drivers/char/diag/diagfwd_peripheral.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -1436,9 +1436,6 @@
if (!fwd_info)
return -EIO;
- if (fwd_info->type == TYPE_CNTL)
- flush_workqueue(driver->cntl_wq);
-
mutex_lock(&driver->diagfwd_channel_mutex[fwd_info->peripheral]);
fwd_info->ch_open = 0;
if (fwd_info && fwd_info->c_ops && fwd_info->c_ops->close)
diff --git a/drivers/char/diag/diagfwd_socket.c b/drivers/char/diag/diagfwd_socket.c
index d7d7366..3451aba 100644
--- a/drivers/char/diag/diagfwd_socket.c
+++ b/drivers/char/diag/diagfwd_socket.c
@@ -496,7 +496,7 @@
if (!atomic_read(&info->opened))
return;
- if ((bootup_req[info->peripheral] == PEPIPHERAL_SSR_UP) &&
+ if ((bootup_req[info->peripheral] == PERIPHERAL_SSR_UP) &&
(info->port_type == PORT_TYPE_SERVER)) {
DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
"diag: %s is up, stopping cleanup: bootup_req = %d\n",
@@ -504,9 +504,10 @@
return;
}
- memset(&info->remote_addr, 0, sizeof(struct sockaddr_msm_ipc));
- diagfwd_channel_close(info->fwd_ctxt);
-
+ if (info->type != TYPE_CNTL) {
+ memset(&info->remote_addr, 0, sizeof(struct sockaddr_msm_ipc));
+ diagfwd_channel_close(info->fwd_ctxt);
+ }
atomic_set(&info->opened, 0);
/* Don't close the server. Server should always remain open */
@@ -955,6 +956,7 @@
void *_cmd)
{
struct restart_notifier_block *notifier;
+ struct diag_socket_info *info = NULL;
notifier = container_of(this,
struct restart_notifier_block, nb);
@@ -964,22 +966,31 @@
return NOTIFY_DONE;
}
- mutex_lock(&driver->diag_notifier_mutex);
DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
"%s: ssr for processor %d ('%s')\n",
__func__, notifier->processor, notifier->name);
+ info = &socket_cntl[notifier->processor];
switch (code) {
case SUBSYS_BEFORE_SHUTDOWN:
DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
"diag: %s: SUBSYS_BEFORE_SHUTDOWN\n", __func__);
- bootup_req[notifier->processor] = PEPIPHERAL_SSR_DOWN;
+ mutex_lock(&driver->diag_notifier_mutex);
+ bootup_req[notifier->processor] = PERIPHERAL_SSR_DOWN;
+ DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
+ "diag: bootup_req[%s] = %d\n",
+ notifier->name, (int)bootup_req[notifier->processor]);
+ mutex_unlock(&driver->diag_notifier_mutex);
break;
case SUBSYS_AFTER_SHUTDOWN:
DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
"diag: %s: SUBSYS_AFTER_SHUTDOWN\n", __func__);
+ mutex_lock(&driver->diag_notifier_mutex);
+ memset(&info->remote_addr, 0, sizeof(struct sockaddr_msm_ipc));
+ diagfwd_channel_close(info->fwd_ctxt);
+ mutex_unlock(&driver->diag_notifier_mutex);
break;
case SUBSYS_BEFORE_POWERUP:
@@ -990,11 +1001,20 @@
case SUBSYS_AFTER_POWERUP:
DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
"diag: %s: SUBSYS_AFTER_POWERUP\n", __func__);
+ mutex_lock(&driver->diag_notifier_mutex);
if (!bootup_req[notifier->processor]) {
- bootup_req[notifier->processor] = PEPIPHERAL_SSR_DOWN;
+ bootup_req[notifier->processor] = PERIPHERAL_SSR_DOWN;
+ DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
+ "diag: bootup_req[%s] = %d\n",
+ notifier->name, (int)bootup_req[notifier->processor]);
+ mutex_unlock(&driver->diag_notifier_mutex);
break;
}
- bootup_req[notifier->processor] = PEPIPHERAL_SSR_UP;
+ bootup_req[notifier->processor] = PERIPHERAL_SSR_UP;
+ DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
+ "diag: bootup_req[%s] = %d\n",
+ notifier->name, (int)bootup_req[notifier->processor]);
+ mutex_unlock(&driver->diag_notifier_mutex);
break;
default:
@@ -1002,10 +1022,6 @@
"diag: code: %lu\n", code);
break;
}
- mutex_unlock(&driver->diag_notifier_mutex);
- DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
- "diag: bootup_req[%s] = %d\n",
- notifier->name, (int)bootup_req[notifier->processor]);
return NOTIFY_DONE;
}
@@ -1165,8 +1181,12 @@
if (read_len <= 0)
goto fail;
- if (!atomic_read(&info->opened) &&
- info->port_type == PORT_TYPE_SERVER) {
+ if (info->type == TYPE_CNTL) {
+ memcpy(&info->remote_addr, &src_addr, sizeof(src_addr));
+ if (!atomic_read(&info->opened))
+ __socket_open_channel(info);
+ } else if (!atomic_read(&info->opened) &&
+ info->port_type == PORT_TYPE_SERVER) {
/*
* This is the first packet from the client. Copy its
* address to the connection object. Consider this
diff --git a/drivers/char/diag/diagfwd_socket.h b/drivers/char/diag/diagfwd_socket.h
index c42be06..128c2be 100644
--- a/drivers/char/diag/diagfwd_socket.h
+++ b/drivers/char/diag/diagfwd_socket.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2017, 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -24,9 +24,9 @@
#define PORT_TYPE_SERVER 0
#define PORT_TYPE_CLIENT 1
-#define PEPIPHERAL_AFTER_BOOT 0
-#define PEPIPHERAL_SSR_DOWN 1
-#define PEPIPHERAL_SSR_UP 2
+#define PERIPHERAL_AFTER_BOOT 0
+#define PERIPHERAL_SSR_DOWN 1
+#define PERIPHERAL_SSR_UP 2
#define CNTL_CMD_NEW_SERVER 4
#define CNTL_CMD_REMOVE_SERVER 5
diff --git a/drivers/hwmon/qpnp-adc-voltage.c b/drivers/hwmon/qpnp-adc-voltage.c
index 086e706..772aac1 100644
--- a/drivers/hwmon/qpnp-adc-voltage.c
+++ b/drivers/hwmon/qpnp-adc-voltage.c
@@ -749,7 +749,7 @@
QPNP_VADC_CAL_DELAY_CTL_1, &val, 1);
if (rc < 0) {
pr_err("qpnp adc write cal_delay failed with %d\n", rc);
- return rc;
+ goto fail_unlock;
}
}
diff --git a/drivers/i2c/busses/i2c-msm-v2.c b/drivers/i2c/busses/i2c-msm-v2.c
index 631169b..ad999a2 100644
--- a/drivers/i2c/busses/i2c-msm-v2.c
+++ b/drivers/i2c/busses/i2c-msm-v2.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -2144,8 +2144,12 @@
{
struct i2c_msm_xfer_buf *cur_buf = &ctrl->xfer.cur_buf;
struct i2c_msg *cur_msg = ctrl->xfer.msgs + cur_buf->msg_idx;
- int bc_rem = cur_msg->len - cur_buf->end_idx;
+ int bc_rem = 0;
+ if (!cur_msg)
+ return false;
+
+ bc_rem = cur_msg->len - cur_buf->end_idx;
if (cur_buf->is_init && cur_buf->end_idx && bc_rem) {
/* not the first buffer in a message */
@@ -2321,17 +2325,12 @@
struct i2c_msm_ctrl *ctrl = i2c_get_adapdata(adap);
struct i2c_msm_xfer *xfer = &ctrl->xfer;
- if (num < 1) {
+ if (IS_ERR_OR_NULL(msgs) || num < 1) {
dev_err(ctrl->dev,
- "error on number of msgs(%d) received\n", num);
+ "Error on msgs Accessing invalid message pointer or message buffer\n");
return -EINVAL;
}
- if (IS_ERR_OR_NULL(msgs)) {
- dev_err(ctrl->dev, " error on msgs Accessing invalid pointer location\n");
- return PTR_ERR(msgs);
- }
-
/* if system is suspended just bail out */
if (ctrl->pwr_state == I2C_MSM_PM_SYS_SUSPENDED) {
dev_err(ctrl->dev,
diff --git a/drivers/input/touchscreen/cyttsp5/cyttsp5_core.c b/drivers/input/touchscreen/cyttsp5/cyttsp5_core.c
index 44bb9ba..f2b2bce 100644
--- a/drivers/input/touchscreen/cyttsp5/cyttsp5_core.c
+++ b/drivers/input/touchscreen/cyttsp5/cyttsp5_core.c
@@ -3765,6 +3765,7 @@
/* Ensure watchdog and startup works stopped */
cyttsp5_stop_wd_timer(cd);
cancel_work_sync(&cd->startup_work);
+ cancel_work_sync(&cd->resume_work);
cyttsp5_stop_wd_timer(cd);
if (cd->cpdata->flags & CY_CORE_FLAG_POWEROFF_ON_SLEEP)
@@ -5965,6 +5966,19 @@
}
EXPORT_SYMBOL(cyttsp5_get_module_data);
+static void cyttsp5_resume_work(struct work_struct *work)
+{
+ struct cyttsp5_core_data *cd = container_of(work,
+ struct cyttsp5_core_data, resume_work);
+
+ #ifdef USE_FB_SUSPEND_RESUME
+ cyttsp5_core_resume(cd->dev);
+ cd->wake_initiated_by_device = 0;
+ #endif
+ call_atten_cb(cd, CY_ATTEN_RESUME, 0);
+ cd->fb_state = FB_ON;
+}
+
#ifdef CONFIG_HAS_EARLYSUSPEND
static void cyttsp5_early_suspend(struct early_suspend *h)
{
@@ -6008,12 +6022,7 @@
case FB_BLANK_UNBLANK:
dev_dbg(cd->dev, "%s: UNBLANK!\n", __func__);
if (cd->fb_state != FB_ON) {
- #ifdef USE_FB_SUSPEND_RESUME
- cyttsp5_core_resume(cd->dev);
- cd->wake_initiated_by_device = 0;
- #endif
- call_atten_cb(cd, CY_ATTEN_RESUME, 0);
- cd->fb_state = FB_ON;
+ schedule_work(&cd->resume_work);
}
break;
@@ -6305,6 +6314,7 @@
/* Initialize works */
INIT_WORK(&cd->startup_work, cyttsp5_startup_work_function);
+ INIT_WORK(&cd->resume_work, cyttsp5_resume_work);
INIT_WORK(&cd->watchdog_work, cyttsp5_watchdog_work);
/* Initialize HID specific data */
@@ -6448,6 +6458,7 @@
pm_runtime_disable(dev);
device_init_wakeup(dev, 0);
cancel_work_sync(&cd->startup_work);
+ cancel_work_sync(&cd->resume_work);
cyttsp5_stop_wd_timer(cd);
remove_sysfs_interfaces(dev);
error_attr_create:
@@ -6498,6 +6509,7 @@
pm_runtime_disable(dev);
cancel_work_sync(&cd->startup_work);
+ cancel_work_sync(&cd->resume_work);
cyttsp5_stop_wd_timer(cd);
diff --git a/drivers/input/touchscreen/cyttsp5/cyttsp5_loader.c b/drivers/input/touchscreen/cyttsp5/cyttsp5_loader.c
index 9f3f586..c7dbafa 100644
--- a/drivers/input/touchscreen/cyttsp5/cyttsp5_loader.c
+++ b/drivers/input/touchscreen/cyttsp5/cyttsp5_loader.c
@@ -751,7 +751,7 @@
parade_debug(dev, DEBUG_LEVEL_2,
"%s: Enabling firmware class loader\n", __func__);
- retval = request_firmware_nowait(THIS_MODULE, FW_ACTION_NOHOTPLUG,
+ retval = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
CY_FW_MANUAL_UPGRADE_FILE_NAME, dev, GFP_KERNEL, dev,
_cyttsp5_firmware_cont);
if (retval < 0) {
diff --git a/drivers/input/touchscreen/cyttsp5/cyttsp5_regs.h b/drivers/input/touchscreen/cyttsp5/cyttsp5_regs.h
index e7b16db..9502c7a 100644
--- a/drivers/input/touchscreen/cyttsp5/cyttsp5_regs.h
+++ b/drivers/input/touchscreen/cyttsp5/cyttsp5_regs.h
@@ -168,7 +168,7 @@
#else
#define CY_HID_OUTPUT_TIMEOUT 200
#endif
-#define CY_HID_OUTPUT_START_BOOTLOADER_TIMEOUT 2000
+#define CY_HID_OUTPUT_START_BOOTLOADER_TIMEOUT 200
#define CY_HID_OUTPUT_USER_TIMEOUT 8000
#define CY_HID_OUTPUT_GET_SYSINFO_TIMEOUT 3000
#define CY_HID_OUTPUT_CALIBRATE_IDAC_TIMEOUT 5000
@@ -991,6 +991,7 @@
struct notifier_block pm_notifier;
#endif
struct work_struct startup_work;
+ struct work_struct resume_work;
struct cyttsp5_sysinfo sysinfo;
void *exclusive_dev;
int exclusive_waits;
diff --git a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c
index 576d5d6..e63c79a 100644
--- a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c
+++ b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c
@@ -1571,12 +1571,6 @@
pr_debug("DEBUG_R1: 0x%x\n",
msm_camera_io_r(cpp_dev->cpp_hw_base + 0x8C));
- /* Update bandwidth usage to enable AXI/ABH clock,
- * which will help to reset CPP AXI.Bandwidth will be
- * made zero at cpp_release_hardware.
- */
- msm_cpp_update_bandwidth(cpp_dev, 0x1000, 0x1000);
-
/* mask IRQ status */
msm_camera_io_w(0xB, cpp_dev->cpp_hw_base + 0xC);
@@ -3657,6 +3651,8 @@
} else {
ioctl_cmd = VIDIOC_MSM_BUF_MNGR_IOCTL_CMD;
idx = MSM_CAMERA_BUF_MNGR_IOCTL_ID_GET_BUF_BY_IDX;
+ buff_mgr_info.index =
+ frame_info.output_buffer_info[0].index;
}
rc = msm_cpp_buffer_ops(cpp_dev, ioctl_cmd, idx,
&buff_mgr_info);
@@ -4370,6 +4366,8 @@
memset(&k64_frame_info, 0, sizeof(k64_frame_info));
k64_frame_info.identity = k32_frame_info.identity;
k64_frame_info.frame_id = k32_frame_info.frame_id;
+ k64_frame_info.output_buffer_info[0].index =
+ k32_frame_info.output_buffer_info[0].index;
kp_ioctl.ioctl_ptr = (__force void __user *)&k64_frame_info;
diff --git a/drivers/media/platform/msm/camera_v3/cam_core/cam_hw_mgr_intf.h b/drivers/media/platform/msm/camera_v3/cam_core/cam_hw_mgr_intf.h
index 6b7a900..2afdafb0 100644
--- a/drivers/media/platform/msm/camera_v3/cam_core/cam_hw_mgr_intf.h
+++ b/drivers/media/platform/msm/camera_v3/cam_core/cam_hw_mgr_intf.h
@@ -262,6 +262,16 @@
bool *mem_found;
};
+/**
+ * struct cam_hw_reset_args -hw reset arguments
+ *
+ * @ctxt_to_hw_map: HW context from the acquire
+ *
+ */
+struct cam_hw_reset_args {
+ void *ctxt_to_hw_map;
+};
+
/* enum cam_hw_mgr_command - Hardware manager command type */
enum cam_hw_mgr_command {
CAM_HW_MGR_CMD_INTERNAL,
@@ -313,6 +323,7 @@
* @hw_open: Function pointer for HW init
* @hw_close: Function pointer for HW deinit
* @hw_flush: Function pointer for HW flush
+ * @hw_reset: Function pointer for HW reset
*
*/
struct cam_hw_mgr_intf {
@@ -333,6 +344,7 @@
int (*hw_open)(void *hw_priv, void *fw_download_args);
int (*hw_close)(void *hw_priv, void *hw_close_args);
int (*hw_flush)(void *hw_priv, void *hw_flush_args);
+ int (*hw_reset)(void *hw_priv, void *hw_reset_args);
};
#endif /* _CAM_HW_MGR_INTF_H_ */
diff --git a/drivers/media/platform/msm/camera_v3/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/media/platform/msm/camera_v3/cam_cpas/cpas_top/cam_cpastop_hw.c
index 719fb12..aaa435d 100644
--- a/drivers/media/platform/msm/camera_v3/cam_cpas/cpas_top/cam_cpastop_hw.c
+++ b/drivers/media/platform/msm/camera_v3/cam_cpas/cpas_top/cam_cpastop_hw.c
@@ -21,6 +21,7 @@
#include "cam_cpas_soc.h"
#include "cpastop100.h"
#include "cpastop_v150_100.h"
+#include "cpastop_v150_110.h"
#include "cpastop_v170_110.h"
#include "cpastop_v175_100.h"
#include "cpastop_v175_101.h"
@@ -117,6 +118,10 @@
(hw_caps->cpas_version.minor == 0) &&
(hw_caps->cpas_version.incr == 0))
soc_info->hw_version = CAM_CPAS_TITAN_150_V100;
+ else if ((hw_caps->cpas_version.major == 1) &&
+ (hw_caps->cpas_version.minor == 1) &&
+ (hw_caps->cpas_version.incr == 0))
+ soc_info->hw_version = CAM_CPAS_TITAN_150_V110;
}
CAM_DBG(CAM_CPAS, "CPAS HW VERSION %x", soc_info->hw_version);
@@ -668,6 +673,9 @@
case CAM_CPAS_TITAN_150_V100:
camnoc_info = &cam150_cpas100_camnoc_info;
break;
+ case CAM_CPAS_TITAN_150_V110:
+ camnoc_info = &cam150_cpas110_camnoc_info;
+ break;
default:
CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d",
hw_caps->camera_version.major,
diff --git a/drivers/media/platform/msm/camera_v3/cam_cpas/cpas_top/cpastop_v150_110.h b/drivers/media/platform/msm/camera_v3/cam_cpas/cpas_top/cpastop_v150_110.h
new file mode 100644
index 0000000..734f378
--- /dev/null
+++ b/drivers/media/platform/msm/camera_v3/cam_cpas/cpas_top/cpastop_v150_110.h
@@ -0,0 +1,537 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPASTOP_V150_110_H_
+#define _CPASTOP_V150_110_H_
+
+#define TEST_IRQ_ENABLE 0
+
+static struct cam_camnoc_irq_sbm cam_cpas_v150_110_irq_sbm = {
+ .sbm_enable = {
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .enable = true,
+ .offset = 0x2040, /* SBM_FAULTINEN0_LOW */
+ .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
+ 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */
+ 0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
+ 0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
+ 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
+ 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */
+ (TEST_IRQ_ENABLE ?
+ 0x100 : /* SBM_FAULTINEN0_LOW_PORT8_MASK */
+ 0x0),
+ },
+ .sbm_status = {
+ .access_type = CAM_REG_TYPE_READ,
+ .enable = true,
+ .offset = 0x2048, /* SBM_FAULTINSTATUS0_LOW */
+ },
+ .sbm_clear = {
+ .access_type = CAM_REG_TYPE_WRITE,
+ .enable = true,
+ .offset = 0x2080, /* SBM_FLAGOUTCLR0_LOW */
+ .value = TEST_IRQ_ENABLE ? 0x6 : 0x2,
+ }
+};
+
+static struct cam_camnoc_irq_err
+ cam_cpas_v150_110_irq_err[] = {
+ {
+ .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
+ .enable = true,
+ .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
+ .err_enable = {
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .enable = true,
+ .offset = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
+ .value = 1,
+ },
+ .err_status = {
+ .access_type = CAM_REG_TYPE_READ,
+ .enable = true,
+ .offset = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
+ },
+ .err_clear = {
+ .access_type = CAM_REG_TYPE_WRITE,
+ .enable = true,
+ .offset = 0x2718, /* ERRLOGGER_ERRCLR_LOW */
+ .value = 1,
+ },
+ },
+ {
+ .irq_type = CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR,
+ .enable = true,
+ .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
+ .err_enable = {
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .enable = true,
+ .offset = 0x5a0, /* SPECIFIC_IFE02_ENCERREN_LOW */
+ .value = 1,
+ },
+ .err_status = {
+ .access_type = CAM_REG_TYPE_READ,
+ .enable = true,
+ .offset = 0x590, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */
+ },
+ .err_clear = {
+ .access_type = CAM_REG_TYPE_WRITE,
+ .enable = true,
+ .offset = 0x598, /* SPECIFIC_IFE02_ENCERRCLR_LOW */
+ .value = 1,
+ },
+ },
+ {
+ .irq_type = CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR,
+ .enable = true,
+ .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
+ .err_enable = {
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .enable = true,
+ .offset = 0x9a0, /* SPECIFIC_IFE13_ENCERREN_LOW */
+ .value = 1,
+ },
+ .err_status = {
+ .access_type = CAM_REG_TYPE_READ,
+ .enable = true,
+ .offset = 0x990, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */
+ },
+ .err_clear = {
+ .access_type = CAM_REG_TYPE_WRITE,
+ .enable = true,
+ .offset = 0x998, /* SPECIFIC_IFE13_ENCERRCLR_LOW */
+ .value = 1,
+ },
+ },
+ {
+ .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR,
+ .enable = true,
+ .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
+ .err_enable = {
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .enable = true,
+ .offset = 0xd20, /* SPECIFIC_IBL_RD_DECERREN_LOW */
+ .value = 1,
+ },
+ .err_status = {
+ .access_type = CAM_REG_TYPE_READ,
+ .enable = true,
+ .offset = 0xd10, /* SPECIFIC_IBL_RD_DECERRSTATUS_LOW */
+ },
+ .err_clear = {
+ .access_type = CAM_REG_TYPE_WRITE,
+ .enable = true,
+ .offset = 0xd18, /* SPECIFIC_IBL_RD_DECERRCLR_LOW */
+ .value = 1,
+ },
+ },
+ {
+ .irq_type = CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR,
+ .enable = true,
+ .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
+ .err_enable = {
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .enable = true,
+ .offset = 0x11a0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
+ .value = 1,
+ },
+ .err_status = {
+ .access_type = CAM_REG_TYPE_READ,
+ .enable = true,
+ .offset = 0x1190,
+ /* SPECIFIC_IBL_WR_ENCERRSTATUS_LOW */
+ },
+ .err_clear = {
+ .access_type = CAM_REG_TYPE_WRITE,
+ .enable = true,
+ .offset = 0x1198, /* SPECIFIC_IBL_WR_ENCERRCLR_LOW */
+ .value = 1,
+ },
+ },
+ {
+ .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
+ .enable = true,
+ .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
+ .err_enable = {
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .enable = true,
+ .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
+ .value = 0x1,
+ },
+ .err_status = {
+ .access_type = CAM_REG_TYPE_READ,
+ .enable = true,
+ .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
+ },
+ .err_clear = {
+ .enable = false,
+ },
+ },
+ {
+ .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
+ .enable = false,
+ },
+ {
+ .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
+ .enable = false,
+ },
+ {
+ .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
+ .enable = TEST_IRQ_ENABLE ? true : false,
+ .sbm_port = 0x100, /* SBM_FAULTINSTATUS0_LOW_PORT8_MASK */
+ .err_enable = {
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .enable = true,
+ .offset = 0x2088, /* SBM_FLAGOUTSET0_LOW */
+ .value = 0x5,
+ },
+ .err_status = {
+ .access_type = CAM_REG_TYPE_READ,
+ .enable = true,
+ .offset = 0x2090, /* SBM_FLAGOUTSTATUS0_LOW */
+ },
+ .err_clear = {
+ .enable = false,
+ },
+ },
+};
+
+static struct cam_camnoc_specific
+ cam_cpas_v150_110_camnoc_specific[] = {
+ {
+ .port_type = CAM_CAMNOC_CDM,
+ .enable = true,
+ .priority_lut_low = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x30, /* SPECIFIC_CDM_PRIORITYLUT_LOW */
+ .value = 0x22222222,
+ },
+ .priority_lut_high = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x34, /* SPECIFIC_CDM_PRIORITYLUT_HIGH */
+ .value = 0x22222222,
+ },
+ .urgency = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 1,
+ .offset = 0x38, /* SPECIFIC_CDM_URGENCY_LOW */
+ .mask = 0x7, /* SPECIFIC_CDM_URGENCY_LOW_READ_MASK */
+ .shift = 0x0, /* SPECIFIC_CDM_URGENCY_LOW_READ_SHIFT */
+ .value = 0x2,
+ },
+ .danger_lut = {
+ .enable = false,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x40, /* SPECIFIC_CDM_DANGERLUT_LOW */
+ .value = 0x0,
+ },
+ .safe_lut = {
+ .enable = false,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x48, /* SPECIFIC_CDM_SAFELUT_LOW */
+ .value = 0x0,
+ },
+ .ubwc_ctl = {
+ .enable = false,
+ },
+ },
+ {
+ .port_type = CAM_CAMNOC_IFE02,
+ .enable = true,
+ .priority_lut_low = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x430, /* SPECIFIC_IFE02_PRIORITYLUT_LOW */
+ .value = 0x66665433,
+ },
+ .priority_lut_high = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x434, /* SPECIFIC_IFE02_PRIORITYLUT_HIGH */
+ .value = 0x66666666,
+ },
+ .urgency = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 1,
+ .offset = 0x438, /* SPECIFIC_IFE02_URGENCY_LOW */
+ /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_MASK */
+ .mask = 0x70,
+ /* SPECIFIC_IFE02_URGENCY_LOW_WRITE_SHIFT */
+ .shift = 0x4,
+ .value = 0x30,
+ },
+ .danger_lut = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .offset = 0x440, /* SPECIFIC_IFE02_DANGERLUT_LOW */
+ .value = 0xFFFFFF00,
+ },
+ .safe_lut = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .offset = 0x448, /* SPECIFIC_IFE02_SAFELUT_LOW */
+ .value = 0x1,
+ },
+ .ubwc_ctl = {
+ .enable = false,
+ },
+ },
+ {
+ .port_type = CAM_CAMNOC_IFE13,
+ .enable = true,
+ .priority_lut_low = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x830, /* SPECIFIC_IFE13_PRIORITYLUT_LOW */
+ .value = 0x66665433,
+ },
+ .priority_lut_high = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x834, /* SPECIFIC_IFE13_PRIORITYLUT_HIGH */
+ .value = 0x66666666,
+ },
+ .urgency = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 1,
+ .offset = 0x838, /* SPECIFIC_IFE13_URGENCY_LOW */
+ /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_MASK */
+ .mask = 0x70,
+ /* SPECIFIC_IFE13_URGENCY_LOW_WRITE_SHIFT */
+ .shift = 0x4,
+ .value = 0x30,
+ },
+ .danger_lut = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .offset = 0x840, /* SPECIFIC_IFE13_DANGERLUT_LOW */
+ .value = 0xFFFFFF00,
+ },
+ .safe_lut = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .offset = 0x848, /* SPECIFIC_IFE13_SAFELUT_LOW */
+ .value = 0x1,
+ },
+ .ubwc_ctl = {
+ .enable = false,
+ },
+ },
+ {
+ .port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
+ .enable = true,
+ .priority_lut_low = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0xc30, /* SPECIFIC_IBL_RD_PRIORITYLUT_LOW */
+ .value = 0x33333333,
+ },
+ .priority_lut_high = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0xc34, /* SPECIFIC_IBL_RD_PRIORITYLUT_HIGH */
+ .value = 0x33333333,
+ },
+ .urgency = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 1,
+ .offset = 0xc38, /* SPECIFIC_IBL_RD_URGENCY_LOW */
+ /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_MASK */
+ .mask = 0x7,
+ /* SPECIFIC_IBL_RD_URGENCY_LOW_READ_SHIFT */
+ .shift = 0x0,
+ .value = 3,
+ },
+ .danger_lut = {
+ .enable = false,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0xc40, /* SPECIFIC_IBL_RD_DANGERLUT_LOW */
+ .value = 0x0,
+ },
+ .safe_lut = {
+ .enable = false,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0xc48, /* SPECIFIC_IBL_RD_SAFELUT_LOW */
+ .value = 0x0,
+ },
+ .ubwc_ctl = {
+ .enable = false,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
+ .value = 1,
+ },
+ },
+ {
+ .port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
+ .enable = true,
+ .priority_lut_low = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x1030, /* SPECIFIC_IBL_WR_PRIORITYLUT_LOW */
+ .value = 0x33333333,
+ },
+ .priority_lut_high = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x1034, /* SPECIFIC_IBL_WR_PRIORITYLUT_HIGH */
+ .value = 0x33333333,
+ },
+ .urgency = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 1,
+ .offset = 0x1038, /* SPECIFIC_IBL_WR_URGENCY_LOW */
+ /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_MASK */
+ .mask = 0x70,
+ /* SPECIFIC_IBL_WR_URGENCY_LOW_WRITE_SHIFT */
+ .shift = 0x4,
+ .value = 0x30,
+ },
+ .danger_lut = {
+ .enable = false,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x1040, /* SPECIFIC_IBL_WR_DANGERLUT_LOW */
+ .value = 0x0,
+ },
+ .safe_lut = {
+ .enable = false,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x1048, /* SPECIFIC_IBL_WR_SAFELUT_LOW */
+ .value = 0x0,
+ },
+ .ubwc_ctl = {
+ .enable = false,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
+ .value = 0x5,
+ },
+ },
+ {
+ .port_type = CAM_CAMNOC_JPEG,
+ .enable = true,
+ .priority_lut_low = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x1430, /* SPECIFIC_JPEG_PRIORITYLUT_LOW */
+ .value = 0x22222222,
+ },
+ .priority_lut_high = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x1434, /* SPECIFIC_JPEG_PRIORITYLUT_HIGH */
+ .value = 0x22222222,
+ },
+ .urgency = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x1438, /* SPECIFIC_JPEG_URGENCY_LOW */
+ .value = 0x22,
+ },
+ .danger_lut = {
+ .enable = false,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x1440, /* SPECIFIC_JPEG_DANGERLUT_LOW */
+ .value = 0x0,
+ },
+ .safe_lut = {
+ .enable = false,
+ .access_type = CAM_REG_TYPE_READ_WRITE,
+ .masked_value = 0,
+ .offset = 0x1448, /* SPECIFIC_JPEG_SAFELUT_LOW */
+ .value = 0x0,
+ },
+ .ubwc_ctl = {
+ .enable = false,
+ },
+ },
+ {
+ .port_type = CAM_CAMNOC_FD,
+ .enable = false,
+ },
+ {
+ .port_type = CAM_CAMNOC_ICP,
+ .enable = true,
+ .flag_out_set0_low = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_WRITE,
+ .masked_value = 0,
+ .offset = 0x2088,
+ .value = 0x100000,
+ },
+ },
+};
+
+static struct cam_camnoc_err_logger_info cam150_cpas110_err_logger_offsets = {
+ .mainctrl = 0x2708, /* ERRLOGGER_MAINCTL_LOW */
+ .errvld = 0x2710, /* ERRLOGGER_ERRVLD_LOW */
+ .errlog0_low = 0x2720, /* ERRLOGGER_ERRLOG0_LOW */
+ .errlog0_high = 0x2724, /* ERRLOGGER_ERRLOG0_HIGH */
+ .errlog1_low = 0x2728, /* ERRLOGGER_ERRLOG1_LOW */
+ .errlog1_high = 0x272c, /* ERRLOGGER_ERRLOG1_HIGH */
+ .errlog2_low = 0x2730, /* ERRLOGGER_ERRLOG2_LOW */
+ .errlog2_high = 0x2734, /* ERRLOGGER_ERRLOG2_HIGH */
+ .errlog3_low = 0x2738, /* ERRLOGGER_ERRLOG3_LOW */
+ .errlog3_high = 0x273c, /* ERRLOGGER_ERRLOG3_HIGH */
+};
+
+static struct cam_cpas_hw_errata_wa_list cam150_cpas110_errata_wa_list = {
+ .camnoc_flush_slave_pending_trans = {
+ .enable = false,
+ .data.reg_info = {
+ .access_type = CAM_REG_TYPE_READ,
+ .offset = 0x2100, /* SidebandManager_SenseIn0_Low */
+ .mask = 0xE0000, /* Bits 17, 18, 19 */
+ .value = 0, /* expected to be 0 */
+ },
+ },
+};
+
+static struct cam_camnoc_info cam150_cpas110_camnoc_info = {
+ .specific = &cam_cpas_v150_110_camnoc_specific[0],
+ .specific_size = sizeof(cam_cpas_v150_110_camnoc_specific) /
+ sizeof(cam_cpas_v150_110_camnoc_specific[0]),
+ .irq_sbm = &cam_cpas_v150_110_irq_sbm,
+ .irq_err = &cam_cpas_v150_110_irq_err[0],
+ .irq_err_size = sizeof(cam_cpas_v150_110_irq_err) /
+ sizeof(cam_cpas_v150_110_irq_err[0]),
+ .err_logger = &cam150_cpas110_err_logger_offsets,
+ .errata_wa_list = &cam150_cpas110_errata_wa_list,
+};
+
+#endif /* _CPASTOP_V150_110_H_ */
diff --git a/drivers/media/platform/msm/camera_v3/cam_cpas/include/cam_cpas_api.h b/drivers/media/platform/msm/camera_v3/cam_cpas/include/cam_cpas_api.h
index 7b534a9..f285863 100644
--- a/drivers/media/platform/msm/camera_v3/cam_cpas/include/cam_cpas_api.h
+++ b/drivers/media/platform/msm/camera_v3/cam_cpas/include/cam_cpas_api.h
@@ -43,6 +43,7 @@
enum cam_cpas_hw_version {
CAM_CPAS_TITAN_NONE = 0,
CAM_CPAS_TITAN_150_V100 = 0x150100,
+ CAM_CPAS_TITAN_150_V110 = 0x150110,
CAM_CPAS_TITAN_170_V100 = 0x170100,
CAM_CPAS_TITAN_170_V110 = 0x170110,
CAM_CPAS_TITAN_170_V120 = 0x170120,
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/cam_isp_context.c b/drivers/media/platform/msm/camera_v3/cam_isp/cam_isp_context.c
index 94d531d..53c1c0f 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/cam_isp_context.c
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/cam_isp_context.c
@@ -452,6 +452,14 @@
trace_cam_buf_done("ISP", ctx, req);
req_isp = (struct cam_isp_ctx_req *) req->req_priv;
+ if (ctx_isp->frame_id == 1)
+ ctx_isp->irq_timestamps = done->irq_mono_boot_time;
+ else if (ctx_isp->fps && ((done->irq_mono_boot_time -
+ ctx_isp->irq_timestamps) > ((1000*1000)/ctx_isp->fps)))
+ ctx_isp->irq_delay_detect = true;
+
+ ctx_isp->irq_timestamps = done->irq_mono_boot_time;
+
for (i = 0; i < done->num_handles; i++) {
for (j = 0; j < req_isp->num_fence_map_out; j++) {
if (done->resource_handle[i] ==
@@ -565,6 +573,26 @@
ctx_isp->substate_activated);
}
+ if (ctx_isp->active_req_cnt && ctx_isp->irq_delay_detect) {
+ CAM_ERR(CAM_ISP, "isp req[%lld] IRQ buf done got delayed",
+ req->request_id);
+ req = list_first_entry(&ctx->active_req_list,
+ struct cam_ctx_request, list);
+ req_isp = (struct cam_isp_ctx_req *) req->req_priv;
+
+ for (j = 0; j < req_isp->num_fence_map_out; j++) {
+ rc = cam_sync_signal(req_isp->fence_map_out[j].sync_id,
+ CAM_SYNC_STATE_SIGNALED_ERROR);
+ if (rc)
+ CAM_DBG(CAM_ISP, "Sync failed with rc = %d",
+ rc);
+ req_isp->fence_map_out[j].sync_id = -1;
+ }
+ list_del_init(&req->list);
+ list_add_tail(&req->list, &ctx->free_req_list);
+ ctx_isp->active_req_cnt--;
+ }
+ ctx_isp->irq_delay_detect = false;
end:
return rc;
}
@@ -643,12 +671,47 @@
static int __cam_isp_ctx_reg_upd_in_epoch_state(
struct cam_isp_context *ctx_isp, void *evt_data)
{
- if (ctx_isp->frame_id == 1)
+ struct cam_isp_hw_reg_update_event_data *rup_event_data = evt_data;
+
+ struct cam_context *ctx = ctx_isp->base;
+ struct cam_ctx_request *req = NULL;
+ struct cam_isp_ctx_req *req_isp = NULL;
+
+ if (ctx_isp->frame_id == 1) {
CAM_DBG(CAM_ISP, "Reg update for early PCR");
- else
+ if (!list_empty(&ctx->active_req_list)) {
+ req = list_first_entry(&ctx->active_req_list,
+ struct cam_ctx_request, list);
+ req_isp = (struct cam_isp_ctx_req *) req->req_priv;
+ } else if (!list_empty(&ctx->wait_req_list)) {
+ req = list_first_entry(&ctx->active_req_list,
+ struct cam_ctx_request, list);
+ req_isp = (struct cam_isp_ctx_req *) req->req_priv;
+ }
+ } else {
+ if (!list_empty(&ctx->wait_req_list)) {
+ req = list_first_entry(&ctx->active_req_list,
+ struct cam_ctx_request, list);
+ req_isp = (struct cam_isp_ctx_req *) req->req_priv;
+ }
CAM_WARN(CAM_ISP,
"Unexpected reg update in activated substate:%d for frame_id:%lld",
ctx_isp->substate_activated, ctx_isp->frame_id);
+ }
+
+ if (req_isp && req_isp->hw_update_data.fps) {
+ ctx_isp->fps = req_isp->hw_update_data.fps;
+ CAM_DBG(CAM_ISP, "req_isp %pK, Upadting ctx_isp->fps %d",
+ req_isp, ctx_isp->fps);
+ }
+
+ if (ctx_isp->frame_id == 1)
+ ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time;
+ else if (ctx_isp->fps && ((rup_event_data->irq_mono_boot_time -
+ ctx_isp->irq_timestamps) > ((1000*1000)/ctx_isp->fps)))
+ ctx_isp->irq_delay_detect = true;
+
+ ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time;
return 0;
}
@@ -658,7 +721,8 @@
int rc = 0;
struct cam_ctx_request *req;
struct cam_context *ctx = ctx_isp->base;
- struct cam_isp_ctx_req *req_isp;
+ struct cam_isp_ctx_req *req_isp = NULL;
+ struct cam_isp_hw_reg_update_event_data *rup_event_data = evt_data;
if (list_empty(&ctx->wait_req_list)) {
CAM_ERR(CAM_ISP, "Reg upd ack with no waiting request");
@@ -683,13 +747,22 @@
req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id);
}
+ if (req_isp && req_isp->hw_update_data.fps)
+ ctx_isp->fps = req_isp->hw_update_data.fps;
+
/*
* This function only called directly from applied and bubble applied
* state so change substate here.
*/
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_EPOCH;
CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated);
+ if (ctx_isp->frame_id == 1)
+ ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time;
+ else if (ctx_isp->fps && ((rup_event_data->irq_mono_boot_time -
+ ctx_isp->irq_timestamps) > ((1000*1000)/ctx_isp->fps)))
+ ctx_isp->irq_delay_detect = true;
+ ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time;
end:
return rc;
}
@@ -817,6 +890,14 @@
ctx_isp->sof_timestamp_val = sof_event_data->timestamp;
ctx_isp->boot_timestamp = sof_event_data->boot_time;
+ if (ctx_isp->frame_id == 1)
+ ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time;
+ else if (ctx_isp->fps && ((sof_event_data->irq_mono_boot_time -
+ ctx_isp->irq_timestamps) > ((1000*1000)/ctx_isp->fps)))
+ ctx_isp->irq_delay_detect = true;
+
+ ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time;
+
CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx, ctx %u",
ctx_isp->frame_id, ctx_isp->sof_timestamp_val, ctx->ctx_id);
@@ -828,8 +909,9 @@
{
int rc = 0;
struct cam_ctx_request *req = NULL;
- struct cam_isp_ctx_req *req_isp;
+ struct cam_isp_ctx_req *req_isp = NULL;
struct cam_context *ctx = ctx_isp->base;
+ struct cam_isp_hw_reg_update_event_data *rup_event_data = evt_data;
if (ctx->state != CAM_CTX_ACTIVATED && ctx_isp->frame_id > 1) {
CAM_DBG(CAM_ISP, "invalid RUP");
@@ -852,6 +934,16 @@
"receive rup in unexpected state");
}
+ if (req_isp && req_isp->hw_update_data.fps)
+ ctx_isp->fps = req_isp->hw_update_data.fps;
+
+ if (ctx_isp->frame_id == 1)
+ ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time;
+ else if (ctx_isp->fps && ((rup_event_data->irq_mono_boot_time -
+ ctx_isp->irq_timestamps) > ((1000*1000)/ctx_isp->fps)))
+ ctx_isp->irq_delay_detect = true;
+
+ ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time;
end:
return rc;
}
@@ -860,9 +952,10 @@
void *evt_data)
{
struct cam_ctx_request *req;
- struct cam_isp_ctx_req *req_isp;
+ struct cam_isp_ctx_req *req_isp = NULL;
struct cam_context *ctx = ctx_isp->base;
uint64_t request_id = 0;
+ struct cam_isp_hw_epoch_event_data *epoch_hw_event_data = evt_data;
if (list_empty(&ctx->wait_req_list)) {
/*
@@ -928,6 +1021,15 @@
ctx_isp->substate_activated);
end:
+ if (ctx_isp->frame_id == 1)
+ ctx_isp->irq_timestamps =
+ epoch_hw_event_data->irq_mono_boot_time;
+ else if (ctx_isp->fps && ((epoch_hw_event_data->irq_mono_boot_time -
+ ctx_isp->irq_timestamps) > ((1000*1000)/ctx_isp->fps)))
+ ctx_isp->irq_delay_detect = true;
+
+ ctx_isp->irq_timestamps = epoch_hw_event_data->irq_mono_boot_time;
+
return 0;
}
@@ -960,6 +1062,14 @@
ctx_isp->sof_timestamp_val = sof_event_data->timestamp;
ctx_isp->boot_timestamp = sof_event_data->boot_time;
+ if (ctx_isp->frame_id == 1)
+ ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time;
+ else if (ctx_isp->fps && ((sof_event_data->irq_mono_boot_time -
+ ctx_isp->irq_timestamps) > ((1000*1000)/ctx_isp->fps)))
+ ctx_isp->irq_delay_detect = true;
+
+ ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time;
+
if (list_empty(&ctx->active_req_list))
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF;
else
@@ -1442,7 +1552,7 @@
{
int rc = 0;
struct cam_ctx_request *req = NULL;
- struct cam_isp_ctx_req *req_isp;
+ struct cam_isp_ctx_req *req_isp = NULL;
struct cam_context *ctx = ctx_isp->base;
if (ctx->state != CAM_CTX_ACTIVATED && ctx_isp->frame_id > 1) {
@@ -1466,6 +1576,9 @@
"receive rup in unexpected state");
}
+ if (req_isp && req_isp->hw_update_data.fps)
+ ctx_isp->fps = req_isp->hw_update_data.fps;
+
end:
return rc;
}
@@ -1476,7 +1589,7 @@
int rc = 0;
struct cam_ctx_request *req = NULL;
struct cam_context *ctx = ctx_isp->base;
- struct cam_isp_ctx_req *req_isp;
+ struct cam_isp_ctx_req *req_isp = NULL;
struct cam_req_mgr_trigger_notify notify;
uint64_t request_id = 0;
@@ -1499,6 +1612,9 @@
list_add_tail(&req->list, &ctx->free_req_list);
}
+ if (req_isp && req_isp->hw_update_data.fps)
+ ctx_isp->fps = req_isp->hw_update_data.fps;
+
/*
* This function only called directly from applied and bubble applied
* state so change substate here.
@@ -1922,16 +2038,19 @@
struct cam_req_mgr_flush_request *flush_req)
{
int rc = 0;
- struct cam_isp_context *ctx_isp;
-
- ctx_isp = (struct cam_isp_context *) ctx->ctx_priv;
+ struct cam_isp_context *ctx_isp =
+ (struct cam_isp_context *) ctx->ctx_priv;
+ struct cam_isp_stop_args stop_isp;
+ struct cam_hw_stop_args stop_args;
+ struct cam_isp_start_args start_isp;
+ struct cam_hw_reset_args reset_args;
if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) {
- CAM_INFO(CAM_ISP, "Last request id to flush is %lld",
- flush_req->req_id);
+ CAM_INFO(CAM_ISP, "ctx id:%d Last request id to flush is %lld",
+ ctx->ctx_id, flush_req->req_id);
ctx->last_flush_req = flush_req->req_id;
}
- CAM_DBG(CAM_ISP, "try to flush pending list");
+ CAM_DBG(CAM_ISP, "ctx id:%d try to flush pending list", ctx->ctx_id);
spin_lock_bh(&ctx->lock);
rc = __cam_isp_ctx_flush_req(ctx, &ctx->pending_req_list, flush_req);
@@ -1954,6 +2073,57 @@
spin_unlock_bh(&ctx->lock);
atomic_set(&ctx_isp->process_bubble, 0);
+ if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) {
+ /* if active and wait list are empty, return */
+ spin_lock_bh(&ctx->lock);
+ if ((list_empty(&ctx->wait_req_list)) &&
+ (list_empty(&ctx->active_req_list))) {
+ spin_unlock_bh(&ctx->lock);
+ CAM_DBG(CAM_ISP, "ctx id:%d active,wait list are empty",
+ ctx->ctx_id);
+ goto end;
+ }
+ spin_unlock_bh(&ctx->lock);
+
+ /* Stop hw first before active list flush */
+ CAM_DBG(CAM_ISP, "ctx id:%d try to stop hw", ctx->ctx_id);
+ stop_args.ctxt_to_hw_map = ctx_isp->hw_ctx;
+ stop_isp.hw_stop_cmd = CAM_ISP_HW_STOP_AT_FRAME_BOUNDARY;
+ stop_isp.stop_only = true;
+ stop_args.args = (void *)&stop_isp;
+ ctx->hw_mgr_intf->hw_stop(ctx->hw_mgr_intf->hw_mgr_priv,
+ &stop_args);
+
+ spin_lock_bh(&ctx->lock);
+ CAM_DBG(CAM_ISP, "try to flush wait list");
+ rc = __cam_isp_ctx_flush_req(ctx, &ctx->wait_req_list,
+ flush_req);
+ CAM_DBG(CAM_ISP, "try to flush active list");
+ rc = __cam_isp_ctx_flush_req(ctx, &ctx->active_req_list,
+ flush_req);
+ ctx_isp->active_req_cnt = 0;
+ spin_unlock_bh(&ctx->lock);
+
+ CAM_DBG(CAM_ISP, "try to reset hw");
+ /* Reset hw */
+ reset_args.ctxt_to_hw_map = ctx_isp->hw_ctx;
+ rc = ctx->hw_mgr_intf->hw_reset(ctx->hw_mgr_intf->hw_mgr_priv,
+ &reset_args);
+ if (rc)
+ goto end;
+
+ CAM_DBG(CAM_ISP, "ctx id%d try to start hw", ctx->ctx_id);
+ /* Start hw */
+ start_isp.hw_config.ctxt_to_hw_map = ctx_isp->hw_ctx;
+ start_isp.start_only = true;
+ start_isp.hw_config.priv = NULL;
+
+ rc = ctx->hw_mgr_intf->hw_start(ctx->hw_mgr_intf->hw_mgr_priv,
+ &start_isp);
+ }
+
+end:
+ ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF;
return rc;
}
@@ -2339,7 +2509,7 @@
{
struct cam_ctx_request *req;
struct cam_context *ctx = ctx_isp->base;
- struct cam_isp_ctx_req *req_isp;
+ struct cam_isp_ctx_req *req_isp = NULL;
struct cam_req_mgr_trigger_notify notify;
uint64_t request_id = 0;
@@ -2394,6 +2564,9 @@
jiffies_to_msecs(jiffies);
}
+ if (req_isp && req_isp->hw_update_data.fps)
+ ctx_isp->fps = req_isp->hw_update_data.fps;
+
__cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id,
CAM_REQ_MGR_SOF_EVENT_SUCCESS);
CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated);
@@ -2669,7 +2842,7 @@
{
int rc = 0, i;
struct cam_ctx_request *req = NULL;
- struct cam_isp_ctx_req *req_isp;
+ struct cam_isp_ctx_req *req_isp = NULL;
uintptr_t packet_addr;
struct cam_packet *packet;
size_t len = 0;
@@ -2758,6 +2931,7 @@
rc = -EFAULT;
goto free_cpu_buf;
}
+
req_isp->num_cfg = cfg.num_hw_update_entries;
req_isp->num_fence_map_out = cfg.num_out_map_entries;
req_isp->num_fence_map_in = cfg.num_in_map_entries;
@@ -2814,6 +2988,7 @@
CAM_ERR(CAM_ISP, "Recevied Update in wrong state");
}
}
+
if (rc)
goto put_ref;
@@ -3595,8 +3770,6 @@
return rc;
}
-
-
static int __cam_isp_ctx_handle_irq_in_activated(void *context,
uint32_t evt_id, void *evt_data)
{
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/cam_isp_context.h b/drivers/media/platform/msm/camera_v3/cam_isp/cam_isp_context.h
index a4f4e5a..cb73252 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/cam_isp_context.h
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/cam_isp_context.h
@@ -35,6 +35,11 @@
#define CAM_ISP_CTX_CFG_MAX 22
/*
+ * Defalut fps value set to 30
+ */
+#define CAM_ISP_CTX_DEFAULT_FPS 30
+
+/*
* Maximum entries in state monitoring array for error logging
*/
#define CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES 20
@@ -180,6 +185,9 @@
* @hw_acquired: Indicate whether HW resources are acquired
* @init_received: Indicate whether init config packet is received
* @split_acquire: Indicate whether a separate acquire is expected
+ * @irq_delay_detect: Indicate whether a irq delay has detected or not
+ * @irq_timestamps: Timestamp from last handled IRQ
+ * @fps: Current FPS for the activated state.
*
*/
struct cam_isp_context {
@@ -209,6 +217,9 @@
bool hw_acquired;
bool init_received;
bool split_acquire;
+ bool irq_delay_detect;
+ uint64_t irq_timestamps;
+ uint32_t fps;
};
/**
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
index cfc902a..91e1e74 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
@@ -146,6 +146,74 @@
return rc;
}
+static const char *cam_ife_hw_mgr_get_res_id(
+ enum cam_ife_pix_path_res_id csid_res_id)
+{
+ char *res_name = NULL;
+
+ switch (csid_res_id) {
+ case CAM_IFE_PIX_PATH_RES_RDI_0:
+ res_name = "RDI_0";
+ break;
+ case CAM_IFE_PIX_PATH_RES_RDI_1:
+ res_name = "RDI_1";
+ break;
+ case CAM_IFE_PIX_PATH_RES_RDI_2:
+ res_name = "RDI_2";
+ break;
+ case CAM_IFE_PIX_PATH_RES_RDI_3:
+ res_name = "RDI_3";
+ break;
+ case CAM_IFE_PIX_PATH_RES_IPP:
+ res_name = "IPP";
+ break;
+ case CAM_IFE_PIX_PATH_RES_PPP:
+ res_name = "PPP";
+ break;
+ case CAM_IFE_PIX_PATH_RES_MAX:
+ res_name = "Invalid Max res";
+ break;
+ default:
+ res_name = "Invalid";
+ break;
+ }
+ return res_name;
+}
+
+static const char *cam_ife_hw_mgr_get_res_type(
+ enum cam_isp_resource_type csid_res_type)
+{
+ char *res_type = NULL;
+
+ switch (csid_res_type) {
+ case CAM_ISP_RESOURCE_UNINT:
+ res_type = "Unint";
+ break;
+ case CAM_ISP_RESOURCE_SRC:
+ res_type = "Src";
+ break;
+ case CAM_ISP_RESOURCE_CID:
+ res_type = "Cid";
+ break;
+ case CAM_ISP_RESOURCE_PIX_PATH:
+ res_type = "Pix Path";
+ break;
+ case CAM_ISP_RESOURCE_VFE_IN:
+ res_type = "Vfe In";
+ break;
+ case CAM_ISP_RESOURCE_VFE_OUT:
+ res_type = "Vfe Out";
+ break;
+ case CAM_ISP_RESOURCE_MAX:
+ res_type = "Invalid Max res";
+ break;
+ default:
+ res_type = "Invalid";
+ break;
+ }
+ return res_type;
+}
+
static int cam_ife_hw_mgr_reset_csid_res(
struct cam_ife_hw_mgr_res *isp_hw_res)
{
@@ -599,6 +667,61 @@
return rc;
}
+static void cam_ife_hw_mgr_dump_all_ctx(
+ struct cam_ife_hw_mgr_ctx *ife_ctx)
+{
+ uint32_t i;
+ struct cam_ife_hw_mgr_ctx *ctx;
+ struct cam_ife_hw_mgr_res *hw_mgr;
+
+ mutex_lock(&g_ife_hw_mgr.ctx_mutex);
+ list_for_each_entry(ctx, &g_ife_hw_mgr.used_ctx_list, list) {
+ CAM_ERR_RATE_LIMIT(CAM_ISP,
+ "ctx id:%d dual:%d in src:%d num_base:%d rdi only:%d",
+ ctx->ctx_index,
+ ctx->res_list_ife_in.is_dual_vfe,
+ ctx->res_list_ife_in.res_id,
+ ctx->num_base, ctx->is_rdi_only_context);
+ list_for_each_entry(hw_mgr, &ctx->res_list_ife_csid,
+ list) {
+ for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
+ if (!hw_mgr->hw_res[i])
+ continue;
+ CAM_ERR_RATE_LIMIT(CAM_ISP,
+ "csid:%d res_type:%s id:%s state:%d",
+ hw_mgr->hw_res[i]->hw_intf->hw_idx,
+ cam_ife_hw_mgr_get_res_type(
+ hw_mgr->hw_res[i]->res_type),
+ cam_ife_hw_mgr_get_res_id(
+ hw_mgr->hw_res[i]->res_id),
+ hw_mgr->hw_res[i]->res_state);
+ }
+ }
+ list_for_each_entry(hw_mgr, &ctx->res_list_ife_src,
+ list) {
+ for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
+ if (!hw_mgr->hw_res[i])
+ continue;
+ CAM_ERR_RATE_LIMIT(CAM_ISP,
+ "Src IFE:%d res_type:%s id:%s state:%d",
+ hw_mgr->hw_res[i]->hw_intf->hw_idx,
+ cam_ife_hw_mgr_get_res_type(
+ hw_mgr->hw_res[i]->res_type),
+ cam_ife_hw_mgr_get_res_id(
+ hw_mgr->hw_res[i]->res_id),
+ hw_mgr->hw_res[i]->res_state);
+ }
+ }
+ }
+ CAM_ERR_RATE_LIMIT(CAM_ISP,
+ "Current ctx id:%d dual:%d in src:%d num_base:%d rdi only:%d",
+ ife_ctx->ctx_index,
+ ife_ctx->res_list_ife_in.is_dual_vfe,
+ ife_ctx->res_list_ife_in.res_id,
+ ife_ctx->num_base, ife_ctx->is_rdi_only_context);
+ mutex_unlock(&g_ife_hw_mgr.ctx_mutex);
+}
+
static void cam_ife_mgr_add_base_info(
struct cam_ife_hw_mgr_ctx *ctx,
enum cam_isp_hw_split_id split_id,
@@ -1509,8 +1632,9 @@
&csid_acquire, sizeof(csid_acquire));
if (rc) {
CAM_ERR(CAM_ISP,
- "Cannot acquire ife csid pxl path rsrc %s",
- (is_ipp) ? "IPP" : "PPP");
+ "Cannot acquire ife csid pxl path rsrc %s, hw=%d rc=%d",
+ (is_ipp) ? "IPP" : "PPP",
+ hw_intf->hw_idx, rc);
goto put_res;
}
@@ -1622,7 +1746,6 @@
"CSID Path reserve failed hw=%d rc=%d cid=%d",
hw_intf->hw_idx, rc,
cid_res->hw_res[0]->res_id);
-
goto put_res;
}
@@ -2018,6 +2141,8 @@
return 0;
free_res:
+ /*Dump all the current acquired resources */
+ cam_ife_hw_mgr_dump_all_ctx(ife_ctx);
cam_ife_hw_mgr_release_hw_for_ctx(ife_ctx);
free_cdm:
cam_cdm_release(ife_ctx->cdm_handle);
@@ -2172,11 +2297,13 @@
ife_ctx->ctx_in_use = 1;
cam_ife_hw_mgr_put_ctx(&ife_hw_mgr->used_ctx_list, &ife_ctx);
-
CAM_DBG(CAM_ISP, "Exit...(success)");
return 0;
+
free_res:
+ /*Dump all the current acquired resources */
+ cam_ife_hw_mgr_dump_all_ctx(ife_ctx);
cam_ife_hw_mgr_release_hw_for_ctx(ife_ctx);
cam_cdm_release(ife_ctx->cdm_handle);
free_ctx:
@@ -2572,6 +2699,11 @@
return cam_ife_mgr_bw_control(ctx, CAM_VFE_BW_CONTROL_EXCLUDE);
}
+static int cam_ife_mgr_resume_hw(struct cam_ife_hw_mgr_ctx *ctx)
+{
+ return cam_ife_mgr_bw_control(ctx, CAM_VFE_BW_CONTROL_INCLUDE);
+}
+
/* entry function: stop_hw */
static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args)
{
@@ -2925,6 +3057,9 @@
CAM_DBG(CAM_ISP, "START IFE OUT ... in ctx id:%d",
ctx->ctx_index);
+ if (start_isp->start_only)
+ cam_ife_mgr_resume_hw(ctx);
+
/* start the IFE out devices */
for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) {
rc = cam_ife_hw_mgr_start_hw_res(
@@ -3025,6 +3160,44 @@
return -EPERM;
}
+static int cam_ife_mgr_reset(void *hw_mgr_priv, void *hw_reset_args)
+{
+ struct cam_ife_hw_mgr *hw_mgr = hw_mgr_priv;
+ struct cam_hw_reset_args *reset_args = hw_reset_args;
+ struct cam_ife_hw_mgr_ctx *ctx;
+ struct cam_ife_hw_mgr_res *hw_mgr_res;
+ uint32_t i;
+ int rc = 0;
+
+ if (!hw_mgr_priv || !hw_reset_args) {
+ CAM_ERR(CAM_ISP, "Invalid arguments");
+ return -EINVAL;
+ }
+
+ ctx = (struct cam_ife_hw_mgr_ctx *)reset_args->ctxt_to_hw_map;
+ if (!ctx || !ctx->ctx_in_use) {
+ CAM_ERR(CAM_ISP, "Invalid context is used");
+ return -EPERM;
+ }
+
+ CAM_DBG(CAM_ISP, "reset csid and vfe hw");
+ list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid,
+ list) {
+ rc = cam_ife_hw_mgr_reset_csid_res(hw_mgr_res);
+ if (rc) {
+ CAM_ERR(CAM_ISP, "Failed RESET (%d) rc:%d",
+ hw_mgr_res->res_id, rc);
+ goto end;
+ }
+ }
+
+ for (i = 0; i < ctx->num_base; i++)
+ rc = cam_ife_mgr_reset_vfe_hw(hw_mgr, ctx->base[i].idx);
+
+end:
+ return rc;
+}
+
static int cam_ife_mgr_release_hw(void *hw_mgr_priv,
void *release_hw_args)
{
@@ -3152,6 +3325,54 @@
return rc;
}
+static int cam_isp_blob_fps_config(
+ uint32_t blob_type,
+ struct cam_isp_generic_blob_info *blob_info,
+ struct cam_fps_config *fps_config,
+ struct cam_hw_prepare_update_args *prepare)
+{
+ struct cam_ife_hw_mgr_ctx *ctx = NULL;
+ struct cam_ife_hw_mgr_res *hw_mgr_res;
+ struct cam_hw_intf *hw_intf;
+ struct cam_vfe_fps_config_args fps_config_args;
+ int rc = -EINVAL;
+ uint32_t i;
+
+ ctx = prepare->ctxt_to_hw_map;
+
+ list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) {
+ for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
+ if (!hw_mgr_res->hw_res[i])
+ continue;
+
+ if (hw_mgr_res->res_id == CAM_ISP_HW_VFE_IN_CAMIF) {
+ hw_intf = hw_mgr_res->hw_res[i]->hw_intf;
+ if (hw_intf && hw_intf->hw_ops.process_cmd) {
+ fps_config_args.fps =
+ fps_config->fps;
+ fps_config_args.node_res =
+ hw_mgr_res->hw_res[i];
+
+ rc = hw_intf->hw_ops.process_cmd(
+ hw_intf->hw_priv,
+ CAM_ISP_HW_CMD_FPS_CONFIG,
+ &fps_config_args,
+ sizeof(
+ struct cam_vfe_fps_config_args)
+ );
+ if (rc)
+ CAM_ERR(CAM_ISP,
+ "Failed fps config:%d",
+ fps_config->fps);
+ } else
+ CAM_WARN(CAM_ISP, "NULL hw_intf!");
+ }
+ }
+ }
+
+ return rc;
+}
+
static int cam_isp_blob_ubwc_update(
uint32_t blob_type,
struct cam_isp_generic_blob_info *blob_info,
@@ -3528,6 +3749,75 @@
return rc;
}
+static int cam_isp_blob_sensor_config(
+ uint32_t blob_type,
+ struct cam_isp_generic_blob_info *blob_info,
+ struct cam_isp_sensor_config *dim_config,
+ struct cam_hw_prepare_update_args *prepare)
+{
+ struct cam_ife_hw_mgr_ctx *ctx = NULL;
+ struct cam_ife_hw_mgr_res *hw_mgr_res;
+ struct cam_hw_intf *hw_intf;
+ struct cam_ife_sensor_dimension_update_args update_args;
+ int rc = -EINVAL, found = 0;
+ uint32_t i, j;
+ struct cam_isp_sensor_dimension *path_config;
+
+ ctx = prepare->ctxt_to_hw_map;
+
+ list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) {
+ for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
+ if (!hw_mgr_res->hw_res[i])
+ continue;
+ found = 1;
+ hw_intf = hw_mgr_res->hw_res[i]->hw_intf;
+ if (hw_intf && hw_intf->hw_ops.process_cmd) {
+ path_config = &(dim_config->ipp_path);
+ update_args.ipp_path.width =
+ path_config->width;
+ update_args.ipp_path.height =
+ path_config->height;
+ update_args.ipp_path.measure_enabled =
+ path_config->measure_enabled;
+ path_config = &(dim_config->ppp_path);
+ update_args.ppp_path.width =
+ path_config->width;
+ update_args.ppp_path.height =
+ path_config->height;
+ update_args.ppp_path.measure_enabled =
+ path_config->measure_enabled;
+ for (j = 0; j < CAM_IFE_RDI_NUM_MAX; j++) {
+ path_config =
+ &(dim_config->rdi_path[j]);
+ update_args.rdi_path[j].width =
+ path_config->width;
+ update_args.rdi_path[j].height =
+ path_config->height;
+ update_args.rdi_path[j].measure_enabled =
+ path_config->measure_enabled;
+ }
+ rc = hw_intf->hw_ops.process_cmd(
+ hw_intf->hw_priv,
+ CAM_IFE_CSID_SET_SENSOR_DIMENSION_CFG,
+ &update_args,
+ sizeof(
+ struct
+ cam_ife_sensor_dimension_update_args)
+ );
+ if (rc)
+ CAM_ERR(CAM_ISP,
+ "Dimension Update failed");
+ } else
+ CAM_ERR(CAM_ISP, "hw_intf is NULL");
+ }
+ if (found)
+ break;
+ }
+
+ return rc;
+}
+
+
void fill_res_bitmap(uint32_t resource_type, unsigned long *res_bitmap)
{
@@ -3620,12 +3910,6 @@
return -EINVAL;
}
- if (blob_type >= CAM_ISP_GENERIC_BLOB_TYPE_MAX) {
- CAM_WARN(CAM_ISP, "Invalid Blob Type %d Max %d", blob_type,
- CAM_ISP_GENERIC_BLOB_TYPE_MAX);
- return 0;
- }
-
prepare = blob_info->prepare;
if (!prepare) {
CAM_ERR(CAM_ISP, "Failed. prepare is NULL, blob_type %d",
@@ -3633,7 +3917,6 @@
return -EINVAL;
}
- CAM_DBG(CAM_ISP, "FS2: BLOB Type: %d", blob_type);
switch (blob_type) {
case CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG: {
struct cam_isp_resource_hfr_config *hfr_config;
@@ -3868,6 +4151,50 @@
CAM_ERR(CAM_ISP, "Init Frame drop Update Failed");
}
break;
+ case CAM_ISP_GENERIC_BLOB_TYPE_SENSOR_DIMENSION_CONFIG: {
+ struct cam_isp_sensor_config *csid_dim_config;
+
+ if (blob_size < sizeof(struct cam_isp_sensor_config)) {
+ CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu",
+ blob_size,
+ sizeof(struct cam_isp_sensor_config));
+ return -EINVAL;
+ }
+
+ csid_dim_config =
+ (struct cam_isp_sensor_config *)blob_data;
+
+ rc = cam_isp_blob_sensor_config(blob_type, blob_info,
+ csid_dim_config, prepare);
+ if (rc)
+ CAM_ERR(CAM_ISP,
+ "Sensor Dimension Update Failed rc: %d", rc);
+ }
+ break;
+ case CAM_ISP_GENERIC_BLOB_TYPE_FPS_CONFIG: {
+ struct cam_fps_config *fps_config;
+ struct cam_isp_prepare_hw_update_data *prepare_hw_data;
+
+ if (blob_size < sizeof(struct cam_fps_config)) {
+ CAM_ERR(CAM_ISP,
+ "Invalid fps blob size %u expected %lu",
+ blob_size, sizeof(struct cam_fps_config));
+ return -EINVAL;
+ }
+
+ fps_config = (struct cam_fps_config *)blob_data;
+ prepare_hw_data = (struct cam_isp_prepare_hw_update_data *)
+ prepare->priv;
+
+ prepare_hw_data->fps = fps_config->fps;
+
+ rc = cam_isp_blob_fps_config(blob_type, blob_info,
+ fps_config, prepare);
+ if (rc)
+ CAM_ERR(CAM_ISP, "FPS Update Failed rc: %d", rc);
+
+ }
+ break;
default:
CAM_WARN(CAM_ISP, "Invalid blob type %d", blob_type);
break;
@@ -4025,10 +4352,6 @@
return rc;
}
-static int cam_ife_mgr_resume_hw(struct cam_ife_hw_mgr_ctx *ctx)
-{
- return cam_ife_mgr_bw_control(ctx, CAM_VFE_BW_CONTROL_INCLUDE);
-}
static int cam_ife_mgr_sof_irq_debug(
struct cam_ife_hw_mgr_ctx *ctx,
@@ -4766,6 +5089,8 @@
break;
if (!rup_status) {
+ rup_event_data.irq_mono_boot_time =
+ evt_payload->ts.time_usecs;
ife_hwr_irq_rup_cb(
ife_hwr_mgr_ctx->common.cb_priv,
CAM_ISP_HW_EVENT_REG_UPDATE,
@@ -4795,6 +5120,8 @@
if (atomic_read(&ife_hwr_mgr_ctx->overflow_pending))
break;
if (!rup_status) {
+ rup_event_data.irq_mono_boot_time =
+ evt_payload->ts.time_usecs;
/* Send the Reg update hw event */
ife_hwr_irq_rup_cb(
ife_hwr_mgr_ctx->common.cb_priv,
@@ -5154,6 +5481,8 @@
ife_hw_mgr_ctx,
&sof_done_event_data.timestamp,
&sof_done_event_data.boot_time);
+ sof_done_event_data.irq_mono_boot_time =
+ evt_payload->ts.time_usecs;
ife_hw_irq_sof_cb(
ife_hw_mgr_ctx->common.cb_priv,
@@ -5177,6 +5506,8 @@
ife_hw_mgr_ctx,
&sof_done_event_data.timestamp,
&sof_done_event_data.boot_time);
+ sof_done_event_data.irq_mono_boot_time =
+ evt_payload->ts.time_usecs;
ife_hw_irq_sof_cb(
ife_hw_mgr_ctx->common.cb_priv,
@@ -5262,13 +5593,15 @@
if (atomic_read(
&ife_hwr_mgr_ctx->overflow_pending))
break;
- if (!eof_status)
+ if (!eof_status) {
+ eof_done_event_data.irq_mono_boot_time =
+ evt_payload->ts.time_usecs;
ife_hwr_irq_eof_cb(
ife_hwr_mgr_ctx->common.cb_priv,
CAM_ISP_HW_EVENT_EOF,
&eof_done_event_data);
+ }
}
-
break;
/* Handling dual VFE Scenario */
case 1:
@@ -5309,11 +5642,14 @@
if (atomic_read(&ife_hwr_mgr_ctx->overflow_pending))
break;
- if (!rc)
+ if (!rc) {
+ eof_done_event_data.irq_mono_boot_time =
+ evt_payload->ts.time_usecs;
ife_hwr_irq_eof_cb(
ife_hwr_mgr_ctx->common.cb_priv,
CAM_ISP_HW_EVENT_EOF,
&eof_done_event_data);
+ }
break;
@@ -5413,6 +5749,8 @@
if (atomic_read(&ife_hwr_mgr_ctx->overflow_pending))
break;
+ buf_done_event_data.irq_mono_boot_time =
+ evt_payload->ts.time_usecs;
/* Report for Successful buf_done event if any */
if (buf_done_event_data.num_handles > 0 &&
ife_hwr_irq_wm_done_cb) {
@@ -5852,6 +6190,7 @@
hw_mgr_intf->hw_prepare_update = cam_ife_mgr_prepare_hw_update;
hw_mgr_intf->hw_config = cam_ife_mgr_config_hw;
hw_mgr_intf->hw_cmd = cam_ife_mgr_cmd;
+ hw_mgr_intf->hw_reset = cam_ife_mgr_reset;
if (iommu_hdl)
*iommu_hdl = g_ife_hw_mgr.mgr_common.img_iommu_hdl;
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h
index 096e0f1..1ab9361 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h
@@ -130,6 +130,7 @@
* @bw_config: BW config information
* @bw_config_valid: Flag indicating whether the bw_config at the index
* is valid or not
+ * @fps: fps vaue which has been updated in hw
*
*/
struct cam_isp_prepare_hw_update_data {
@@ -137,40 +138,47 @@
struct cam_isp_bw_config_internal bw_config[CAM_IFE_HW_NUM_MAX];
struct cam_isp_bw_config_internal_ab bw_config_ab[CAM_IFE_HW_NUM_MAX];
bool bw_config_valid[CAM_IFE_HW_NUM_MAX];
+ uint32_t fps;
};
/**
* struct cam_isp_hw_sof_event_data - Event payload for CAM_HW_EVENT_SOF
*
- * @timestamp: Time stamp for the sof event
- * @boot_time: Boot time stamp for the sof event
+ * @timestamp: Time stamp for the sof event
+ * @boot_time: Boot time stamp for the sof event
+ * @irq_mono_boot_time: Time stamp till the execution of IRQ wrt event started
*
*/
struct cam_isp_hw_sof_event_data {
uint64_t timestamp;
uint64_t boot_time;
+ uint64_t irq_mono_boot_time;
};
/**
* struct cam_isp_hw_reg_update_event_data - Event payload for
* CAM_HW_EVENT_REG_UPDATE
*
- * @timestamp: Time stamp for the reg update event
+ * @timestamp: Time stamp for the reg update event
+ * @irq_mono_boot_time: Time stamp till the execution of IRQ wrt event started
*
*/
struct cam_isp_hw_reg_update_event_data {
uint64_t timestamp;
+ uint64_t irq_mono_boot_time;
};
/**
* struct cam_isp_hw_epoch_event_data - Event payload for CAM_HW_EVENT_EPOCH
*
- * @timestamp: Time stamp for the epoch event
+ * @timestamp: Time stamp for the epoch event
+ * @irq_mono_boot_time: Time stamp till the execution of this event started
*
*/
struct cam_isp_hw_epoch_event_data {
uint64_t timestamp;
+ uint64_t irq_mono_boot_time;
};
/**
@@ -179,6 +187,7 @@
* @num_handles: Number of resource handeles
* @resource_handle: Resource handle array
* @timestamp: Timestamp for the buf done event
+ * @irq_mono_boot_time: Time stamp till the execution of this event started
*
*/
struct cam_isp_hw_done_event_data {
@@ -186,16 +195,19 @@
uint32_t resource_handle[
CAM_NUM_OUT_PER_COMP_IRQ_MAX];
uint64_t timestamp;
+ uint64_t irq_mono_boot_time;
};
/**
* struct cam_isp_hw_eof_event_data - Event payload for CAM_HW_EVENT_EOF
*
* @timestamp: Timestamp for the eof event
+ * @irq_mono_boot_time: Time stamp till the execution of this event started
*
*/
struct cam_isp_hw_eof_event_data {
uint64_t timestamp;
+ uint64_t irq_mono_boot_time;
};
/**
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile
index 25bdc51d..719bbe7 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile
@@ -8,5 +8,6 @@
ccflags-y += -Idrivers/media/platform/msm/camera_v3/cam_smmu/
ccflags-y += -Idrivers/media/platform/msm/camera_v3/cam_req_mgr/
+obj-$(CONFIG_SPECTRA_CAMERA) += cam_csid_ppi_dev.o cam_csid_ppi_core.o cam_csid_ppi170.o
obj-$(CONFIG_SPECTRA_CAMERA) += cam_ife_csid_dev.o cam_ife_csid_soc.o cam_ife_csid_core.o
obj-$(CONFIG_SPECTRA_CAMERA) += cam_ife_csid17x.o cam_ife_csid_lite17x.o
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi170.c b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi170.c
new file mode 100644
index 0000000..2051292
--- /dev/null
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi170.c
@@ -0,0 +1,58 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include "cam_csid_ppi_core.h"
+#include "cam_csid_ppi170.h"
+#include "cam_csid_ppi_dev.h"
+
+#define CAM_PPI_DRV_NAME "ppi_170"
+#define CAM_PPI_VERSION_V170 0x10070000
+
+static struct cam_csid_ppi_hw_info cam_csid_ppi170_hw_info = {
+ .ppi_reg = &cam_csid_ppi_170_reg_offset,
+};
+
+static const struct of_device_id cam_csid_ppi170_dt_match[] = {
+ {
+ .compatible = "qcom,ppi170",
+ .data = &cam_csid_ppi170_hw_info,
+ },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, cam_csid_ppi170_dt_match);
+
+static struct platform_driver cam_csid_ppi170_driver = {
+ .probe = cam_csid_ppi_probe,
+ .remove = cam_csid_ppi_remove,
+ .driver = {
+ .name = CAM_PPI_DRV_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = cam_csid_ppi170_dt_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+static int __init cam_csid_ppi170_init_module(void)
+{
+ return platform_driver_register(&cam_csid_ppi170_driver);
+}
+
+static void __exit cam_csid_ppi170_exit_module(void)
+{
+ platform_driver_unregister(&cam_csid_ppi170_driver);
+}
+
+module_init(cam_csid_ppi170_init_module);
+MODULE_DESCRIPTION("CAM CSID_PPI170 driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi170.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi170.h
new file mode 100644
index 0000000..0ec7672
--- /dev/null
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi170.h
@@ -0,0 +1,32 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CAM_CSID_PPI_170_H_
+#define _CAM_CSID_PPI_170_H_
+
+#include "cam_csid_ppi_core.h"
+
+static struct cam_csid_ppi_reg_offset cam_csid_ppi_170_reg_offset = {
+ .ppi_hw_version_addr = 0,
+ .ppi_module_cfg_addr = 0x60,
+ .ppi_irq_status_addr = 0x68,
+ .ppi_irq_mask_addr = 0x6c,
+ .ppi_irq_set_addr = 0x70,
+ .ppi_irq_clear_addr = 0x74,
+ .ppi_irq_cmd_addr = 0x78,
+ .ppi_rst_cmd_addr = 0x7c,
+ .ppi_test_bus_ctrl_addr = 0x1f4,
+ .ppi_debug_addr = 0x1f8,
+ .ppi_spare_addr = 0x1fc,
+};
+
+#endif /*_CAM_CSID_PPI_170_H_ */
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_core.c b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_core.c
new file mode 100644
index 0000000..058a4e9
--- /dev/null
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_core.c
@@ -0,0 +1,404 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/iopoll.h>
+#include <linux/slab.h>
+#include <uapi/media/cam_defs.h>
+
+#include "cam_csid_ppi_core.h"
+#include "cam_csid_ppi_dev.h"
+#include "cam_soc_util.h"
+#include "cam_debug_util.h"
+#include "cam_io_util.h"
+
+static int cam_csid_ppi_reset(struct cam_csid_ppi_hw *ppi_hw)
+{
+ struct cam_hw_soc_info *soc_info;
+ const struct cam_csid_ppi_reg_offset *ppi_reg;
+ int rc = 0;
+
+ uint32_t val = 0;
+ uint32_t clear_mask;
+ uint32_t status;
+
+ soc_info = &ppi_hw->hw_info->soc_info;
+ ppi_reg = ppi_hw->ppi_info->ppi_reg;
+
+ CAM_DBG(CAM_ISP, "PPI:%d reset", ppi_hw->hw_intf->hw_idx);
+
+ /* Mask all interrupts */
+ cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_mask_addr);
+
+ /* clear all interrupts */
+ clear_mask = PPI_IRQ_FIFO0_OVERFLOW | PPI_IRQ_FIFO1_OVERFLOW |
+ PPI_IRQ_FIFO2_OVERFLOW;
+ cam_io_w_mb(clear_mask, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_clear_addr);
+ cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_cmd_addr);
+
+ /* perform the top PPI HW registers reset */
+ cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_rst_cmd_addr);
+
+ rc = readl_poll_timeout(soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_status_addr, status,
+ (status & 0x1) == 0x1, 1000, 100000);
+ if (rc < 0) {
+ CAM_ERR(CAM_ISP, "PPI:%d ppi_reset fail rc = %d",
+ ppi_hw->hw_intf->hw_idx, rc);
+ rc = -ETIMEDOUT;
+ }
+ CAM_DBG(CAM_ISP, "PPI: reset status %d", status);
+
+ val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_mask_addr);
+ if (val != 0)
+ CAM_ERR(CAM_ISP, "PPI:%d IRQ value after reset rc = %d",
+ ppi_hw->hw_intf->hw_idx, val);
+
+ return rc;
+}
+
+static int cam_csid_ppi_enable_hw(struct cam_csid_ppi_hw *ppi_hw)
+{
+ int rc = 0;
+ uint32_t i;
+ uint64_t val;
+
+ const struct cam_csid_ppi_reg_offset *ppi_reg;
+ struct cam_hw_soc_info *soc_info;
+
+ ppi_reg = ppi_hw->ppi_info->ppi_reg;
+ soc_info = &ppi_hw->hw_info->soc_info;
+
+ CAM_DBG(CAM_ISP, "PPI:%d init PPI HW", ppi_hw->hw_intf->hw_idx);
+
+ for (i = 0; i < soc_info->num_clk; i++) {
+ /* Passing zero in clk_rate results in setting no clk_rate */
+ rc = cam_soc_util_clk_enable(soc_info->clk[i],
+ soc_info->clk_name[i], 0);
+ if (rc)
+ goto clk_disable;
+ }
+
+ rc = cam_soc_util_irq_enable(soc_info);
+ if (rc)
+ goto clk_disable;
+
+ /* Reset PPI */
+ rc = cam_csid_ppi_reset(ppi_hw);
+ if (rc)
+ goto irq_disable;
+
+ /* Clear the RST done IRQ */
+ cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_clear_addr);
+ cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_cmd_addr);
+
+ val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_hw_version_addr);
+ CAM_DBG(CAM_ISP, "PPI:%d PPI HW version: 0x%x",
+ ppi_hw->hw_intf->hw_idx, val);
+
+ ppi_hw->device_enabled = 1;
+ return 0;
+irq_disable:
+ cam_soc_util_irq_disable(soc_info);
+clk_disable:
+ for (i--; i >= 0; i--) {
+ cam_soc_util_clk_disable(soc_info->clk[i],
+ soc_info->clk_name[i]);
+ }
+ return rc;
+}
+
+static int cam_csid_ppi_disable_hw(struct cam_csid_ppi_hw *ppi_hw)
+{
+ int rc = 0;
+ int i;
+ struct cam_hw_soc_info *soc_info;
+ const struct cam_csid_ppi_reg_offset *ppi_reg;
+ uint64_t ppi_cfg_val = 0;
+
+ CAM_DBG(CAM_ISP, "PPI:%d De-init PPI HW",
+ ppi_hw->hw_intf->hw_idx);
+
+ soc_info = &ppi_hw->hw_info->soc_info;
+ ppi_reg = ppi_hw->ppi_info->ppi_reg;
+
+ CAM_DBG(CAM_ISP, "%s:Calling PPI Reset\n", __func__);
+ cam_csid_ppi_reset(ppi_hw);
+ CAM_DBG(CAM_ISP, "%s:PPI Reset Done\n", __func__);
+
+ /* disable the clocks */
+ for (i = 0; i < soc_info->num_clk; i++) {
+ cam_soc_util_clk_disable(soc_info->clk[i],
+ soc_info->clk_name[i]);
+ }
+
+ /* disable the interrupt */
+ cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_mask_addr);
+ cam_soc_util_irq_disable(soc_info);
+
+ /* disable lanes */
+ for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++)
+ ppi_cfg_val &= ~PPI_CFG_CPHY_DLX_EN(i);
+
+ cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_module_cfg_addr);
+
+ ppi_hw->device_enabled = 0;
+
+ return rc;
+}
+
+static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args,
+ uint32_t arg_size)
+{
+ int i, rc = 0;
+ uint32_t num_lanes;
+ uint32_t lanes[CAM_CSID_PPI_HW_MAX] = {0, 0, 0, 0};
+ uint32_t cphy;
+ bool dl0, dl1;
+ uint32_t ppi_cfg_val = 0;
+ struct cam_csid_ppi_hw *ppi_hw;
+ struct cam_hw_info *ppi_hw_info;
+ const struct cam_csid_ppi_reg_offset *ppi_reg;
+ struct cam_hw_soc_info *soc_info;
+ struct cam_csid_ppi_cfg ppi_cfg;
+
+ if (!hw_priv || !init_args ||
+ (arg_size != sizeof(struct cam_csid_ppi_cfg))) {
+ CAM_ERR(CAM_ISP, "PPI: Invalid args");
+ rc = -EINVAL;
+ goto end;
+ }
+
+ dl0 = dl1 = false;
+ ppi_hw_info = (struct cam_hw_info *)hw_priv;
+ ppi_hw = (struct cam_csid_ppi_hw *)ppi_hw_info->core_info;
+ ppi_reg = ppi_hw->ppi_info->ppi_reg;
+ ppi_cfg = *((struct cam_csid_ppi_cfg *)init_args);
+
+ /* Initialize the ppi hardware */
+ rc = cam_csid_ppi_enable_hw(ppi_hw);
+ if (rc)
+ goto end;
+
+ /* Do lane configuration here*/
+ num_lanes = ppi_cfg.lane_num;
+ /* lane_type = 1 refers to cphy */
+ cphy = ppi_cfg.lane_type;
+ CAM_DBG(CAM_ISP, "lane_cfg 0x%x | num_lanes 0x%x | lane_type 0x%x",
+ ppi_cfg.lane_cfg, num_lanes, cphy);
+
+ for (i = 0; i < num_lanes; i++) {
+ lanes[i] = ppi_cfg.lane_cfg & (0x3 << (4 * i));
+ (lanes[i] < 2) ? (dl0 = true) : (dl1 = true);
+ CAM_DBG(CAM_ISP, "lanes[%d] %d", i, lanes[i]);
+ }
+
+ if (num_lanes) {
+ if (cphy) {
+ for (i = 0; i < num_lanes; i++) {
+ /* Select Cphy */
+ ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(lanes[i]);
+ /* Enable lane Cphy */
+ ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(lanes[i]);
+ }
+ } else {
+ if (dl0)
+ /* Enable lane 0 */
+ ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(0);
+ if (dl1)
+ /* Enable lane 1 */
+ ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(1);
+ }
+ } else {
+ CAM_ERR(CAM_ISP,
+ "Number of lanes to enable is cannot be zero");
+ rc = -1;
+ goto end;
+ }
+
+ CAM_DBG(CAM_ISP, "ppi_cfg_val 0x%x", ppi_cfg_val);
+ soc_info = &ppi_hw->hw_info->soc_info;
+ cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_module_cfg_addr);
+end:
+ return rc;
+}
+
+static int cam_csid_ppi_deinit_hw(void *hw_priv, void *deinit_args,
+ uint32_t arg_size)
+{
+ int rc = 0;
+ struct cam_csid_ppi_hw *ppi_hw;
+ struct cam_hw_info *ppi_hw_info;
+
+ CAM_DBG(CAM_ISP, "Enter");
+
+ if (!hw_priv) {
+ CAM_ERR(CAM_ISP, "PPI:Invalid arguments");
+ rc = -EINVAL;
+ goto end;
+ }
+
+ ppi_hw_info = (struct cam_hw_info *)hw_priv;
+ ppi_hw = (struct cam_csid_ppi_hw *)ppi_hw_info->core_info;
+
+ CAM_DBG(CAM_ISP, "Disabling PPI Hw\n");
+ rc = cam_csid_ppi_disable_hw(ppi_hw);
+ if (rc < 0)
+ CAM_DBG(CAM_ISP, "%s: Exit with %d\n", __func__, rc);
+end:
+ return rc;
+}
+
+int cam_csid_ppi_hw_probe_init(struct cam_hw_intf *ppi_hw_intf,
+ uint32_t ppi_idx)
+{
+ int rc = -EINVAL;
+ struct cam_hw_info *ppi_hw_info;
+ struct cam_csid_ppi_hw *csid_ppi_hw = NULL;
+
+ if (ppi_idx >= CAM_CSID_PPI_HW_MAX) {
+ CAM_ERR(CAM_ISP, "Invalid ppi index:%d", ppi_idx);
+ goto err;
+ }
+
+ ppi_hw_info = (struct cam_hw_info *) ppi_hw_intf->hw_priv;
+ csid_ppi_hw = (struct cam_csid_ppi_hw *) ppi_hw_info->core_info;
+
+ csid_ppi_hw->hw_intf = ppi_hw_intf;
+ csid_ppi_hw->hw_info = ppi_hw_info;
+
+ CAM_DBG(CAM_ISP, "type %d index %d",
+ csid_ppi_hw->hw_intf->hw_type, ppi_idx);
+
+ rc = cam_csid_ppi_init_soc_resources(&csid_ppi_hw->hw_info->soc_info,
+ cam_csid_ppi_irq, csid_ppi_hw);
+ if (rc < 0) {
+ CAM_ERR(CAM_ISP, "PPI:%d Failed to init_soc", ppi_idx);
+ goto err;
+ }
+
+ csid_ppi_hw->hw_intf->hw_ops.init = cam_csid_ppi_init_hw;
+ csid_ppi_hw->hw_intf->hw_ops.deinit = cam_csid_ppi_deinit_hw;
+ return 0;
+err:
+ return rc;
+}
+
+int cam_csid_ppi_init_soc_resources(struct cam_hw_soc_info *soc_info,
+ irq_handler_t ppi_irq_handler, void *irq_data)
+{
+ int rc = 0;
+
+ rc = cam_soc_util_get_dt_properties(soc_info);
+ if (rc) {
+ CAM_ERR(CAM_ISP, "PPI: Failed to get dt properties");
+ goto end;
+ }
+
+ rc = cam_soc_util_request_platform_resource(soc_info, ppi_irq_handler,
+ irq_data);
+ if (rc) {
+ CAM_ERR(CAM_ISP,
+ "PPI: Error Request platform resources failed rc=%d",
+ rc);
+ goto err;
+ }
+end:
+ return rc;
+err:
+ cam_soc_util_release_platform_resource(soc_info);
+ return rc;
+}
+
+irqreturn_t cam_csid_ppi_irq(int irq_num, void *data)
+{
+ uint32_t irq_status = 0;
+ uint32_t i, ppi_cfg_val = 0;
+ bool fatal_err_detected = false;
+
+ struct cam_csid_ppi_hw *ppi_hw;
+ struct cam_hw_soc_info *soc_info;
+ const struct cam_csid_ppi_reg_offset *ppi_reg;
+
+ if (!data) {
+ CAM_ERR(CAM_ISP, "PPI: Invalid arguments");
+ return IRQ_HANDLED;
+ }
+
+ ppi_hw = (struct cam_csid_ppi_hw *)data;
+ CAM_DBG(CAM_ISP, "PPI %d IRQ Handling", ppi_hw->hw_intf->hw_idx);
+ ppi_reg = ppi_hw->ppi_info->ppi_reg;
+ soc_info = &ppi_hw->hw_info->soc_info;
+
+ /* read */
+ irq_status = cam_io_r_mb(soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_status_addr);
+
+ /* clear */
+ cam_io_w_mb(irq_status, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_clear_addr);
+
+ cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_irq_cmd_addr);
+
+ CAM_DBG(CAM_ISP, "PPI %d irq status 0x%x", ppi_hw->hw_intf->hw_idx,
+ irq_status);
+
+ if (ppi_hw->device_enabled == 1) {
+ if (irq_status & PPI_IRQ_RST_DONE) {
+ CAM_DBG(CAM_ISP, "PPI Reset Done");
+ goto ret;
+ }
+ if ((irq_status & PPI_IRQ_FIFO0_OVERFLOW) ||
+ (irq_status & PPI_IRQ_FIFO1_OVERFLOW) ||
+ (irq_status & PPI_IRQ_FIFO2_OVERFLOW)) {
+ fatal_err_detected = true;
+ goto handle_fatal_error;
+ }
+ }
+
+handle_fatal_error:
+ if (fatal_err_detected) {
+ CAM_ERR(CAM_ISP, "PPI: %d irq_status:0x%x",
+ ppi_hw->hw_intf->hw_idx, irq_status);
+ /* disable lanes */
+ for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++)
+ ppi_cfg_val &= ~PPI_CFG_CPHY_DLX_EN(i);
+
+ cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base +
+ ppi_reg->ppi_module_cfg_addr);
+ }
+ret:
+ CAM_DBG(CAM_ISP, "IRQ Handling exit");
+ return IRQ_HANDLED;
+}
+
+int cam_csid_ppi_hw_deinit(struct cam_csid_ppi_hw *csid_ppi_hw)
+{
+ if (!csid_ppi_hw) {
+ CAM_ERR(CAM_ISP, "Invalid param");
+ return -EINVAL;
+ }
+ /* release the privdate data memory from resources */
+ return cam_soc_util_release_platform_resource(
+ &csid_ppi_hw->hw_info->soc_info);
+}
+
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_core.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_core.h
new file mode 100644
index 0000000..058c242
--- /dev/null
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_core.h
@@ -0,0 +1,103 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CAM_CSID_PPI_HW_H_
+#define _CAM_CSID_PPI_HW_H_
+
+#include "cam_hw.h"
+#include "cam_hw_intf.h"
+
+#define CAM_CSID_PPI_HW_MAX 4
+#define CAM_CSID_PPI_LANES_MAX 3
+
+#define PPI_IRQ_RST_DONE BIT(0)
+#define PPI_IRQ_FIFO0_OVERFLOW BIT(1)
+#define PPI_IRQ_FIFO1_OVERFLOW BIT(2)
+#define PPI_IRQ_FIFO2_OVERFLOW BIT(3)
+
+#define PPI_IRQ_CMD_SET BIT(0)
+
+#define PPI_IRQ_CMD_CLEAR BIT(0)
+
+#define PPI_RST_CONTROL BIT(0)
+/*
+ * Select the PHY (CPHY set '1' or DPHY set '0')
+ */
+#define PPI_CFG_CPHY_DLX_SEL(X) ((X < 2) ? BIT(X) : 0)
+
+#define PPI_CFG_CPHY_DLX_EN(X) BIT(4+X)
+
+struct cam_csid_ppi_reg_offset {
+ uint32_t ppi_hw_version_addr;
+ uint32_t ppi_module_cfg_addr;
+
+ uint32_t ppi_irq_status_addr;
+ uint32_t ppi_irq_mask_addr;
+ uint32_t ppi_irq_set_addr;
+ uint32_t ppi_irq_clear_addr;
+ uint32_t ppi_irq_cmd_addr;
+ uint32_t ppi_rst_cmd_addr;
+ uint32_t ppi_test_bus_ctrl_addr;
+ uint32_t ppi_debug_addr;
+ uint32_t ppi_spare_addr;
+};
+
+/**
+ * struct cam_csid_ppi_hw_info- ppi HW info
+ *
+ * @ppi_reg: ppi register offsets
+ *
+ */
+struct cam_csid_ppi_hw_info {
+ const struct cam_csid_ppi_reg_offset *ppi_reg;
+};
+
+/**
+ * struct cam_csid_ppi_hw- ppi hw device resources data
+ *
+ * @hw_intf: contain the ppi hw interface information
+ * @hw_info: ppi hw device information
+ * @ppi_info: ppi hw specific information
+ * @device_enabled Device enabled will set once ppi powered on and
+ * initial configuration are done.
+ * @lock_state ppi spin lock
+ *
+ */
+struct cam_csid_ppi_hw {
+ struct cam_hw_intf *hw_intf;
+ struct cam_hw_info *hw_info;
+ struct cam_csid_ppi_hw_info *ppi_info;
+ uint32_t device_enabled;
+};
+
+/**
+ * struct cam_csid_ppi_cfg - ppi lane configuration data
+ * @lane_type: lane type: c-phy or d-phy
+ * @lane_num : active lane number
+ * @lane_cfg: lane configurations: 4 bits per lane
+ *
+ */
+struct cam_csid_ppi_cfg {
+ uint32_t lane_type;
+ uint32_t lane_num;
+ uint32_t lane_cfg;
+};
+
+int cam_csid_ppi_hw_probe_init(struct cam_hw_intf *ppi_hw_intf,
+ uint32_t ppi_idx);
+int cam_csid_ppi_hw_deinit(struct cam_csid_ppi_hw *csid_ppi_hw);
+int cam_csid_ppi_init_soc_resources(struct cam_hw_soc_info *soc_info,
+ irq_handler_t ppi_irq_handler, void *irq_data);
+int cam_csid_ppi_deinit_soc_resources(struct cam_hw_soc_info *soc_info);
+int cam_csid_ppi_hw_init(struct cam_hw_intf **csid_ppi_hw,
+ uint32_t hw_idx);
+#endif /* _CAM_CSID_PPI_HW_H_ */
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_dev.c b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_dev.c
new file mode 100644
index 0000000..1a4e145
--- /dev/null
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_dev.c
@@ -0,0 +1,147 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/slab.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of_device.h>
+
+#include "cam_isp_hw.h"
+#include "cam_hw_intf.h"
+#include "cam_csid_ppi_core.h"
+#include "cam_csid_ppi_dev.h"
+#include "cam_debug_util.h"
+
+static struct cam_hw_intf *cam_csid_ppi_hw_list[CAM_CSID_PPI_HW_MAX] = {
+ 0, 0, 0, 0};
+static char ppi_dev_name[8];
+
+int cam_csid_ppi_probe(struct platform_device *pdev)
+{
+ struct cam_hw_intf *ppi_hw_intf;
+ struct cam_hw_info *ppi_hw_info;
+ struct cam_csid_ppi_hw *ppi_dev = NULL;
+ const struct of_device_id *match_dev = NULL;
+ struct cam_csid_ppi_hw_info *ppi_hw_data = NULL;
+ uint32_t ppi_dev_idx;
+ int rc = 0;
+
+ CAM_DBG(CAM_ISP, "PPI probe called");
+
+ ppi_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL);
+ if (!ppi_hw_intf) {
+ rc = -ENOMEM;
+ goto err;
+ }
+
+ ppi_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL);
+ if (!ppi_hw_info) {
+ rc = -ENOMEM;
+ goto free_hw_intf;
+ }
+
+ ppi_dev = kzalloc(sizeof(struct cam_csid_ppi_hw), GFP_KERNEL);
+ if (!ppi_dev) {
+ rc = -ENOMEM;
+ goto free_hw_info;
+ }
+
+ /* get csid ppi hw index */
+ of_property_read_u32(pdev->dev.of_node, "cell-index", &ppi_dev_idx);
+
+ /* get csid ppi hw information */
+ match_dev = of_match_device(pdev->dev.driver->of_match_table,
+ &pdev->dev);
+ if (!match_dev) {
+ CAM_ERR(CAM_ISP, "No matching table for the CSID PPI HW!");
+ rc = -EINVAL;
+ goto free_dev;
+ }
+
+ memset(ppi_dev_name, 0, sizeof(ppi_dev_name));
+ snprintf(ppi_dev_name, sizeof(ppi_dev_name), "ppi%1u", ppi_dev_idx);
+
+ ppi_hw_intf->hw_idx = ppi_dev_idx;
+ ppi_hw_intf->hw_priv = ppi_hw_info;
+
+ ppi_hw_info->core_info = ppi_dev;
+ ppi_hw_info->soc_info.pdev = pdev;
+ ppi_hw_info->soc_info.dev = &pdev->dev;
+ ppi_hw_info->soc_info.dev_name = ppi_dev_name;
+ ppi_hw_info->soc_info.index = ppi_dev_idx;
+
+ ppi_hw_data = (struct cam_csid_ppi_hw_info *)match_dev->data;
+ /* need to setup the pdev before call the csid ppi hw probe init */
+ ppi_dev->ppi_info = ppi_hw_data;
+
+ rc = cam_csid_ppi_hw_probe_init(ppi_hw_intf, ppi_dev_idx);
+ if (rc) {
+ CAM_ERR(CAM_ISP, "PPI: Probe init failed!");
+ goto free_dev;
+ }
+
+ platform_set_drvdata(pdev, ppi_dev);
+ CAM_DBG(CAM_ISP, "PPI:%d probe successful",
+ ppi_hw_intf->hw_idx);
+
+ if (ppi_hw_intf->hw_idx < CAM_CSID_PPI_HW_MAX)
+ cam_csid_ppi_hw_list[ppi_hw_intf->hw_idx] = ppi_hw_intf;
+ else
+ goto free_dev;
+
+ return 0;
+free_dev:
+ kfree(ppi_dev);
+free_hw_info:
+ kfree(ppi_hw_info);
+free_hw_intf:
+ kfree(ppi_hw_intf);
+err:
+ return rc;
+}
+
+int cam_csid_ppi_remove(struct platform_device *pdev)
+{
+ struct cam_csid_ppi_hw *ppi_dev = NULL;
+ struct cam_hw_intf *ppi_hw_intf;
+ struct cam_hw_info *ppi_hw_info;
+
+ ppi_dev = (struct cam_csid_ppi_hw *)platform_get_drvdata(pdev);
+ ppi_hw_intf = ppi_dev->hw_intf;
+ ppi_hw_info = ppi_dev->hw_info;
+
+ CAM_DBG(CAM_ISP, "PPI:%d remove", ppi_dev->hw_intf->hw_idx);
+
+ cam_csid_ppi_hw_deinit(ppi_dev);
+
+ /* release the ppi device memory */
+ kfree(ppi_dev);
+ kfree(ppi_hw_info);
+ kfree(ppi_hw_intf);
+ return 0;
+}
+
+int cam_csid_ppi_hw_init(struct cam_hw_intf **csid_ppi_hw,
+ uint32_t hw_idx)
+{
+ int rc = 0;
+
+ if (cam_csid_ppi_hw_list[hw_idx]) {
+ *csid_ppi_hw = cam_csid_ppi_hw_list[hw_idx];
+ } else {
+ *csid_ppi_hw = NULL;
+ rc = -1;
+ }
+
+ return rc;
+}
+EXPORT_SYMBOL(cam_csid_ppi_hw_init);
+
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_dev.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_dev.h
new file mode 100644
index 0000000..b2ebeaf
--- /dev/null
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_csid_ppi_dev.h
@@ -0,0 +1,22 @@
+/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CAM_CSID_PPI_DEV_H_
+#define _CAM_CSID_PPI_DEV_H_
+
+#include "cam_isp_hw.h"
+
+irqreturn_t cam_csid_ppi_irq(int irq_num, void *data);
+int cam_csid_ppi_probe(struct platform_device *pdev);
+int cam_csid_ppi_remove(struct platform_device *pdev);
+
+#endif /*_CAM_CSID_PPI_DEV_H_ */
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h
index 576e8cb..6254b97 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h
@@ -293,6 +293,10 @@
.ppp_irq_mask_all = 0x0,
.measure_en_hbi_vbi_cnt_mask = 0xC,
.format_measure_en_val = 1,
+ .format_measure_height_mask_val = 0xFFFF,
+ .format_measure_height_shift_val = 0x10,
+ .format_measure_width_mask_val = 0xFFFF,
+ .format_measure_width_shift_val = 0x0,
};
static struct cam_ife_csid_reg_offset cam_ife_csid_170_reg_offset = {
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175.h
index 42f0f29..ed2857b 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175.h
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175.h
@@ -334,6 +334,10 @@
.ppp_irq_mask_all = 0xFFFF,
.measure_en_hbi_vbi_cnt_mask = 0xC,
.format_measure_en_val = 1,
+ .format_measure_height_mask_val = 0xFFFF,
+ .format_measure_height_shift_val = 0x10,
+ .format_measure_width_mask_val = 0xFFFF,
+ .format_measure_width_shift_val = 0x0,
};
static struct cam_ife_csid_reg_offset cam_ife_csid_175_reg_offset = {
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h
index 8a78fe0..d430cee 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h
@@ -350,6 +350,10 @@
.ppp_irq_mask_all = 0xFFFF,
.measure_en_hbi_vbi_cnt_mask = 0xC,
.format_measure_en_val = 1,
+ .format_measure_height_mask_val = 0xFFFF,
+ .format_measure_height_shift_val = 0x10,
+ .format_measure_width_mask_val = 0xFFFF,
+ .format_measure_width_shift_val = 0x0,
};
static struct cam_ife_csid_reg_offset cam_ife_csid_175_200_reg_offset = {
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
index 3431a64..7541d06 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
@@ -16,6 +16,7 @@
#include <uapi/media/cam_defs.h>
#include "cam_ife_csid_core.h"
+#include "cam_csid_ppi_core.h"
#include "cam_isp_hw.h"
#include "cam_soc_util.h"
#include "cam_io_util.h"
@@ -78,7 +79,7 @@
static int cam_ife_csid_get_format_rdi(
uint32_t in_format, uint32_t out_format,
- uint32_t *decode_fmt, uint32_t *plain_fmt)
+ uint32_t *decode_fmt, uint32_t *plain_fmt, uint32_t *in_bpp)
{
int rc = 0;
@@ -96,6 +97,7 @@
rc = -EINVAL;
break;
}
+ *in_bpp = 6;
break;
case CAM_FORMAT_MIPI_RAW_8:
switch (out_format) {
@@ -111,6 +113,7 @@
rc = -EINVAL;
break;
}
+ *in_bpp = 8;
break;
case CAM_FORMAT_MIPI_RAW_10:
switch (out_format) {
@@ -126,6 +129,7 @@
rc = -EINVAL;
break;
}
+ *in_bpp = 10;
break;
case CAM_FORMAT_MIPI_RAW_12:
switch (out_format) {
@@ -140,6 +144,7 @@
rc = -EINVAL;
break;
}
+ *in_bpp = 12;
break;
case CAM_FORMAT_MIPI_RAW_14:
switch (out_format) {
@@ -154,6 +159,7 @@
rc = -EINVAL;
break;
}
+ *in_bpp = 14;
break;
case CAM_FORMAT_MIPI_RAW_16:
switch (out_format) {
@@ -168,6 +174,7 @@
rc = -EINVAL;
break;
}
+ *in_bpp = 16;
break;
case CAM_FORMAT_MIPI_RAW_20:
switch (out_format) {
@@ -182,6 +189,7 @@
rc = -EINVAL;
break;
}
+ *in_bpp = 20;
break;
case CAM_FORMAT_DPCM_10_6_10:
*decode_fmt = 0x7;
@@ -566,10 +574,6 @@
init_completion(complete);
reset_strb_val = csid_reg->cmn_reg->path_rst_stb_all;
- /* Enable the Test gen before reset */
- cam_io_w_mb(1, csid_hw->hw_info->soc_info.reg_map[0].mem_base +
- csid_reg->tpg_reg->csid_tpg_ctrl_addr);
-
/* Reset the corresponding ife csid path */
cam_io_w_mb(reset_strb_val, soc_info->reg_map[0].mem_base +
reset_strb_addr);
@@ -584,10 +588,6 @@
rc = -ETIMEDOUT;
}
- /* Disable Test Gen after reset*/
- cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
- csid_reg->tpg_reg->csid_tpg_ctrl_addr);
-
end:
return rc;
@@ -1166,6 +1166,11 @@
for (i = 0; i < CAM_IFE_PIX_PATH_RES_MAX; i++)
csid_hw->res_sof_cnt[i] = 0;
+ csid_hw->ipp_path_config.measure_enabled = 0;
+ csid_hw->ppp_path_config.measure_enabled = 0;
+ for (i = 0; i <= CAM_IFE_PIX_PATH_RES_RDI_3; i++)
+ csid_hw->rdi_path_config[i].measure_enabled = 0;
+
csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN;
csid_hw->error_irq_count = 0;
csid_hw->first_sof_ts = 0;
@@ -1422,10 +1427,12 @@
struct cam_isp_resource_node *res)
{
int rc = 0;
- const struct cam_ife_csid_reg_offset *csid_reg;
- struct cam_hw_soc_info *soc_info;
- struct cam_ife_csid_cid_data *cid_data;
+ const struct cam_ife_csid_reg_offset *csid_reg;
+ struct cam_hw_soc_info *soc_info;
+ struct cam_ife_csid_cid_data *cid_data;
+ struct cam_csid_ppi_cfg ppi_lane_cfg;
uint32_t val = 0;
+ uint32_t ppi_index = 0;
csid_reg = csid_hw->csid_info->csid_reg;
soc_info = &csid_hw->hw_info->soc_info;
@@ -1516,6 +1523,24 @@
cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr);
+ ppi_index = csid_hw->csi2_rx_cfg.phy_sel;
+ if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) {
+ ppi_lane_cfg.lane_type = csid_hw->csi2_rx_cfg.lane_type;
+ ppi_lane_cfg.lane_num = csid_hw->csi2_rx_cfg.lane_num;
+ ppi_lane_cfg.lane_cfg = csid_hw->csi2_rx_cfg.lane_cfg;
+
+ CAM_DBG(CAM_ISP, "ppi_index to init %d", ppi_index);
+ rc = csid_hw->ppi_hw_intf[ppi_index]->hw_ops.init(
+ csid_hw->ppi_hw_intf[ppi_index]->hw_priv,
+ &ppi_lane_cfg,
+ sizeof(struct cam_csid_ppi_cfg));
+ if (rc < 0) {
+ CAM_ERR(CAM_ISP, "PPI:%d Init Failed",
+ ppi_index);
+ return rc;
+ }
+ }
+
return 0;
}
@@ -1523,8 +1548,10 @@
struct cam_ife_csid_hw *csid_hw,
struct cam_isp_resource_node *res)
{
- const struct cam_ife_csid_reg_offset *csid_reg;
- struct cam_hw_soc_info *soc_info;
+ int rc = 0;
+ const struct cam_ife_csid_reg_offset *csid_reg;
+ struct cam_hw_soc_info *soc_info;
+ uint32_t ppi_index = 0;
if (res->res_id >= CAM_IFE_CSID_CID_MAX) {
CAM_ERR(CAM_ISP, "CSID:%d Invalid res id :%d",
@@ -1555,6 +1582,19 @@
res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED;
+ ppi_index = csid_hw->csi2_rx_cfg.phy_sel;
+ if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) {
+ /* De-Initialize the PPI bridge */
+ CAM_DBG(CAM_ISP, "ppi_index to de-init %d\n", ppi_index);
+ rc = csid_hw->ppi_hw_intf[ppi_index]->hw_ops.deinit(
+ csid_hw->ppi_hw_intf[ppi_index]->hw_priv,
+ NULL, 0);
+ if (rc < 0) {
+ CAM_ERR(CAM_ISP, "PPI:%d De-Init Failed", ppi_index);
+ return rc;
+ }
+ }
+
return 0;
}
@@ -1589,6 +1629,7 @@
const struct cam_ife_csid_pxl_reg_offset *pxl_reg = NULL;
bool is_ipp;
uint32_t decode_format = 0, plain_format = 0, val = 0;
+ struct cam_isp_sensor_dimension *path_config;
path_data = (struct cam_ife_csid_path_cfg *) res->res_priv;
csid_reg = csid_hw->csid_info->csid_reg;
@@ -1597,9 +1638,11 @@
if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) {
is_ipp = true;
pxl_reg = csid_reg->ipp_reg;
+ path_config = &(csid_hw->ipp_path_config);
} else {
is_ipp = false;
pxl_reg = csid_reg->ppp_reg;
+ path_config = &(csid_hw->ppp_path_config);
}
if (!pxl_reg) {
@@ -1668,6 +1711,24 @@
}
}
+ /* configure pixel format measure */
+ if (path_config->measure_enabled) {
+ val = (((path_config->height &
+ csid_reg->cmn_reg->format_measure_height_mask_val) <<
+ csid_reg->cmn_reg->format_measure_height_shift_val) |
+ (path_config->width &
+ csid_reg->cmn_reg->format_measure_width_mask_val));
+ CAM_DBG(CAM_ISP, "CSID:%d format measure cfg1 value : 0x%x",
+ csid_hw->hw_intf->hw_idx, val);
+
+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
+ pxl_reg->csid_pxl_format_measure_cfg1_addr);
+
+ /* enable pixel and line counter */
+ cam_io_w_mb(3, soc_info->reg_map[0].mem_base +
+ pxl_reg->csid_pxl_format_measure_cfg0_addr);
+ }
+
/* set frame drop pattern to 0 and period to 1 */
cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
pxl_reg->csid_pxl_frm_drop_period_addr);
@@ -1813,6 +1874,7 @@
const struct cam_ife_csid_pxl_reg_offset *pxl_reg = NULL;
bool is_ipp;
uint32_t val = 0, path_status;
+ struct cam_isp_sensor_dimension *path_config;
path_data = (struct cam_ife_csid_path_cfg *) res->res_priv;
csid_reg = csid_hw->csid_info->csid_reg;
@@ -1821,9 +1883,11 @@
if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP) {
is_ipp = true;
pxl_reg = csid_reg->ipp_reg;
+ path_config = &(csid_hw->ipp_path_config);
} else {
is_ipp = false;
pxl_reg = csid_reg->ppp_reg;
+ path_config = &(csid_hw->ppp_path_config);
}
if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) {
@@ -1884,6 +1948,10 @@
if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)
val |= CSID_PATH_INFO_INPUT_EOF;
+ if (path_config->measure_enabled)
+ val |= (CSID_PATH_ERROR_PIX_COUNT |
+ CSID_PATH_ERROR_LINE_COUNT);
+
cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
pxl_reg->csid_pxl_irq_mask_addr);
@@ -1984,7 +2052,7 @@
struct cam_ife_csid_path_cfg *path_data;
const struct cam_ife_csid_reg_offset *csid_reg;
struct cam_hw_soc_info *soc_info;
- uint32_t path_format = 0, plain_fmt = 0, val = 0, id;
+ uint32_t path_format = 0, plain_fmt = 0, val = 0, id, in_bpp = 0;
uint32_t format_measure_addr;
path_data = (struct cam_ife_csid_path_cfg *) res->res_priv;
@@ -1999,7 +2067,7 @@
}
rc = cam_ife_csid_get_format_rdi(path_data->in_format,
- path_data->out_format, &path_format, &plain_fmt);
+ path_data->out_format, &path_format, &plain_fmt, &in_bpp);
if (rc)
return rc;
@@ -2048,6 +2116,32 @@
CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x",
csid_hw->hw_intf->hw_idx, val);
}
+
+ /* configure pixel format measure */
+ if (csid_hw->rdi_path_config[id].measure_enabled) {
+ val = ((csid_hw->rdi_path_config[id].height &
+ csid_reg->cmn_reg->format_measure_height_mask_val) <<
+ csid_reg->cmn_reg->format_measure_height_shift_val);
+
+ if (path_format == 0xF)
+ val |= (((csid_hw->rdi_path_config[id].width *
+ in_bpp) / 8) &
+ csid_reg->cmn_reg->format_measure_width_mask_val);
+ else
+ val |= (csid_hw->rdi_path_config[id].width &
+ csid_reg->cmn_reg->format_measure_width_mask_val);
+
+ CAM_DBG(CAM_ISP, "CSID:%d format measure cfg1 value : 0x%x",
+ csid_hw->hw_intf->hw_idx, val);
+
+ cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
+ csid_reg->rdi_reg[id]->csid_rdi_format_measure_cfg1_addr);
+
+ /* enable pixel and line counter */
+ cam_io_w_mb(3, soc_info->reg_map[0].mem_base +
+ csid_reg->rdi_reg[id]->csid_rdi_format_measure_cfg0_addr);
+ }
+
/* set frame drop pattern to 0 and period to 1 */
cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
csid_reg->rdi_reg[id]->csid_rdi_frm_drop_period_addr);
@@ -2220,6 +2314,10 @@
if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)
val |= CSID_PATH_INFO_INPUT_EOF;
+ if (csid_hw->rdi_path_config[id].measure_enabled)
+ val |= (CSID_PATH_ERROR_PIX_COUNT |
+ CSID_PATH_ERROR_LINE_COUNT);
+
cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr);
@@ -2673,6 +2771,13 @@
case CAM_ISP_RESOURCE_PIX_PATH:
res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE;
cam_ife_csid_reset_init_frame_drop(csid_hw);
+ if (res->res_id == CAM_IFE_PIX_PATH_RES_IPP)
+ csid_hw->ipp_path_config.measure_enabled = 0;
+ else if (res->res_id == CAM_IFE_PIX_PATH_RES_PPP)
+ csid_hw->ppp_path_config.measure_enabled = 0;
+ else
+ csid_hw->rdi_path_config[res->res_id].measure_enabled
+ = 0;
break;
default:
CAM_ERR(CAM_ISP, "CSID:%d Invalid res type:%d res id%d",
@@ -3103,6 +3208,57 @@
return 0;
}
+static int cam_ife_csid_set_sensor_dimension(
+ struct cam_ife_csid_hw *csid_hw, void *cmd_args)
+{
+ struct cam_ife_sensor_dimension_update_args *dimension_update = NULL;
+ uint32_t i;
+
+ if (!csid_hw)
+ return -EINVAL;
+
+ dimension_update =
+ (struct cam_ife_sensor_dimension_update_args *)cmd_args;
+ csid_hw->ipp_path_config.measure_enabled =
+ dimension_update->ipp_path.measure_enabled;
+ if (dimension_update->ipp_path.measure_enabled) {
+ csid_hw->ipp_path_config.width =
+ dimension_update->ipp_path.width;
+ csid_hw->ipp_path_config.height =
+ dimension_update->ipp_path.height;
+ CAM_DBG(CAM_ISP, "CSID ipp path width %d height %d",
+ csid_hw->ipp_path_config.width,
+ csid_hw->ipp_path_config.height);
+ }
+ csid_hw->ppp_path_config.measure_enabled =
+ dimension_update->ppp_path.measure_enabled;
+ if (dimension_update->ppp_path.measure_enabled) {
+ csid_hw->ppp_path_config.width =
+ dimension_update->ppp_path.width;
+ csid_hw->ppp_path_config.height =
+ dimension_update->ppp_path.height;
+ CAM_DBG(CAM_ISP, "CSID ppp path width %d height %d",
+ csid_hw->ppp_path_config.width,
+ csid_hw->ppp_path_config.height);
+ }
+ for (i = 0; i <= CAM_IFE_PIX_PATH_RES_RDI_3; i++) {
+ csid_hw->rdi_path_config[i].measure_enabled
+ = dimension_update->rdi_path[i].measure_enabled;
+ if (csid_hw->rdi_path_config[i].measure_enabled) {
+ csid_hw->rdi_path_config[i].width =
+ dimension_update->rdi_path[i].width;
+ csid_hw->rdi_path_config[i].height =
+ dimension_update->rdi_path[i].height;
+ CAM_DBG(CAM_ISP,
+ "CSID rdi path[%d] width %d height %d",
+ i, csid_hw->rdi_path_config[i].width,
+ csid_hw->rdi_path_config[i].height);
+ }
+ }
+
+ return 0;
+}
+
static int cam_ife_csid_process_cmd(void *hw_priv,
uint32_t cmd_type, void *cmd_args, uint32_t arg_size)
{
@@ -3140,6 +3296,9 @@
case CAM_IFE_CSID_SET_INIT_FRAME_DROP:
rc = cam_ife_csid_set_init_frame_drop(csid_hw, cmd_args);
break;
+ case CAM_IFE_CSID_SET_SENSOR_DIMENSION_CFG:
+ rc = cam_ife_csid_set_sensor_dimension(csid_hw, cmd_args);
+ break;
default:
CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d",
csid_hw->hw_intf->hw_idx, cmd_type);
@@ -3162,20 +3321,19 @@
const struct cam_ife_csid_rdi_reg_offset *rdi_reg;
uint32_t i, irq_status_top, irq_status_rx, irq_status_ipp = 0;
uint32_t irq_status_rdi[4] = {0, 0, 0, 0};
- uint32_t val, irq_status_ppp = 0;
+ uint32_t val, val2, irq_status_ppp = 0;
bool fatal_err_detected = false;
uint32_t sof_irq_debug_en = 0;
unsigned long flags;
- csid_hw = (struct cam_ife_csid_hw *)data;
-
- CAM_DBG(CAM_ISP, "CSID %d IRQ Handling", csid_hw->hw_intf->hw_idx);
-
if (!data) {
CAM_ERR(CAM_ISP, "CSID: Invalid arguments");
return IRQ_HANDLED;
}
+ csid_hw = (struct cam_ife_csid_hw *)data;
+ CAM_DBG(CAM_ISP, "CSID %d IRQ Handling", csid_hw->hw_intf->hw_idx);
+
csid_reg = csid_hw->csid_info->csid_reg;
soc_info = &csid_hw->hw_info->soc_info;
csi2_reg = csid_reg->csi2_reg;
@@ -3218,7 +3376,7 @@
cam_io_w_mb(1, soc_info->reg_map[0].mem_base +
csid_reg->cmn_reg->csid_irq_cmd_addr);
- CAM_DBG(CAM_ISP,
+ CAM_ERR_RATE_LIMIT(CAM_ISP,
"CSID %d irq status 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x",
csid_hw->hw_intf->hw_idx, irq_status_top,
irq_status_rx, irq_status_ipp, irq_status_ppp,
@@ -3455,6 +3613,25 @@
csid_reg->ipp_reg->csid_pxl_ctrl_addr);
}
}
+
+ if ((irq_status_ipp & CSID_PATH_ERROR_PIX_COUNT) ||
+ (irq_status_ipp & CSID_PATH_ERROR_LINE_COUNT)) {
+ val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
+ csid_reg->ipp_reg->csid_pxl_format_measure0_addr);
+
+ CAM_ERR(CAM_ISP,
+ "CSID:%d irq_status_ipp:0x%x",
+ csid_hw->hw_intf->hw_idx, irq_status_ipp);
+ CAM_ERR(CAM_ISP,
+ "Expected sz 0x%x*0x%x actual sz 0x%x*0x%x",
+ csid_hw->ipp_path_config.height,
+ csid_hw->ipp_path_config.width,
+ ((val >>
+ csid_reg->cmn_reg->format_measure_height_shift_val) &
+ csid_reg->cmn_reg->format_measure_height_mask_val),
+ val &
+ csid_reg->cmn_reg->format_measure_width_mask_val);
+ }
}
/*read PPP errors */
@@ -3536,6 +3713,25 @@
csid_reg->ppp_reg->csid_pxl_ctrl_addr);
}
}
+
+ if ((irq_status_ppp & CSID_PATH_ERROR_PIX_COUNT) ||
+ (irq_status_ppp & CSID_PATH_ERROR_LINE_COUNT)) {
+ val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
+ csid_reg->ppp_reg->csid_pxl_format_measure0_addr);
+
+ CAM_ERR(CAM_ISP,
+ "CSID:%d irq_status_ppp:0x%x",
+ csid_hw->hw_intf->hw_idx, irq_status_ppp);
+ CAM_ERR(CAM_ISP,
+ "Expected sz 0x%x*0x%x actual sz 0x%x*0x%x",
+ csid_hw->ppp_path_config.height,
+ csid_hw->ppp_path_config.width,
+ ((val >>
+ csid_reg->cmn_reg->format_measure_height_shift_val) &
+ csid_reg->cmn_reg->format_measure_height_mask_val),
+ val &
+ csid_reg->cmn_reg->format_measure_width_mask_val);
+ }
}
for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) {
@@ -3602,6 +3798,31 @@
soc_info->reg_map[0].mem_base +
csid_reg->rdi_reg[i]->csid_rdi_ctrl_addr);
}
+
+ if ((irq_status_rdi[i] & CSID_PATH_ERROR_PIX_COUNT) ||
+ (irq_status_rdi[i] & CSID_PATH_ERROR_LINE_COUNT)) {
+ val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
+ csid_reg->rdi_reg[i]->csid_rdi_format_measure0_addr);
+ val2 = cam_io_r_mb(soc_info->reg_map[0].mem_base +
+ csid_reg->rdi_reg[i]->csid_rdi_format_measure_cfg1_addr
+ );
+ CAM_ERR(CAM_ISP,
+ "CSID:%d irq_status_rdi[%d]:0x%x",
+ csid_hw->hw_intf->hw_idx, i,
+ irq_status_rdi[i]);
+ CAM_ERR(CAM_ISP,
+ "Expected sz 0x%x*0x%x actual sz 0x%x*0x%x",
+ ((val2 >>
+ csid_reg->cmn_reg->format_measure_height_shift_val) &
+ csid_reg->cmn_reg->format_measure_height_mask_val),
+ val2 &
+ csid_reg->cmn_reg->format_measure_width_mask_val,
+ ((val >>
+ csid_reg->cmn_reg->format_measure_height_shift_val) &
+ csid_reg->cmn_reg->format_measure_height_mask_val),
+ val &
+ csid_reg->cmn_reg->format_measure_width_mask_val);
+ }
}
if (csid_hw->irq_debug_cnt >= CAM_CSID_IRQ_SOF_DEBUG_CNT_MAX) {
@@ -3638,7 +3859,6 @@
CAM_DBG(CAM_ISP, "type %d index %d",
ife_csid_hw->hw_intf->hw_type, csid_idx);
-
ife_csid_hw->device_enabled = 0;
ife_csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN;
mutex_init(&ife_csid_hw->hw_info->hw_mutex);
@@ -3653,7 +3873,6 @@
for (i = 0; i < CAM_IFE_CSID_RDI_MAX; i++)
init_completion(&ife_csid_hw->csid_rdin_complete[i]);
-
rc = cam_ife_csid_init_soc_resources(&ife_csid_hw->hw_info->soc_info,
cam_ife_csid_irq, ife_csid_hw);
if (rc < 0) {
@@ -3747,8 +3966,27 @@
ife_csid_hw->csid_debug = 0;
ife_csid_hw->error_irq_count = 0;
ife_csid_hw->first_sof_ts = 0;
+ ife_csid_hw->ipp_path_config.measure_enabled = 0;
+ ife_csid_hw->ppp_path_config.measure_enabled = 0;
+ for (i = 0; i <= CAM_IFE_PIX_PATH_RES_RDI_3; i++)
+ ife_csid_hw->rdi_path_config[i].measure_enabled = 0;
- return 0;
+ /* Check if ppi bridge is present or not? */
+ ife_csid_hw->ppi_enable = of_property_read_bool(
+ csid_hw_info->soc_info.pdev->dev.of_node,
+ "ppi-enable");
+
+ if (!ife_csid_hw->ppi_enable)
+ return 0;
+
+ /* Initialize the PPI bridge */
+ for (i = 0; i < CAM_CSID_PPI_HW_MAX; i++) {
+ rc = cam_csid_ppi_hw_init(&ife_csid_hw->ppi_hw_intf[i], i);
+ if (rc < 0) {
+ CAM_ERR(CAM_ISP, "PPI init failed for PPI %d", i);
+ break;
+ }
+ }
err:
if (rc) {
kfree(ife_csid_hw->ipp_res.res_priv);
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h
index 9b4d5c3..f2173f1 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h
@@ -16,6 +16,7 @@
#include "cam_hw.h"
#include "cam_ife_csid_hw_intf.h"
#include "cam_ife_csid_soc.h"
+#include "cam_csid_ppi_core.h"
#define CAM_IFE_CSID_HW_RES_MAX 4
#define CAM_IFE_CSID_CID_RES_MAX 4
@@ -309,6 +310,10 @@
uint32_t ppp_irq_mask_all;
uint32_t measure_en_hbi_vbi_cnt_mask;
uint32_t format_measure_en_val;
+ uint32_t format_measure_width_shift_val;
+ uint32_t format_measure_width_mask_val;
+ uint32_t format_measure_height_shift_val;
+ uint32_t format_measure_height_mask_val;
};
/**
@@ -468,6 +473,11 @@
* @csid_debug: csid debug information to enable the SOT, EOT,
* SOF, EOF, measure etc in the csid hw
* @clk_rate Clock rate
+ * @ipp_path ipp path configuration
+ * @ppp_path ppp path configuration
+ * @rdi_path RDI path configuration
+ * @hbi Horizontal blanking
+ * @vbi Vertical blanking
* @sof_irq_triggered: Flag is set on receiving event to enable sof irq
* incase of SOF freeze.
* @irq_debug_cnt: Counter to track sof irq's when above flag is set.
@@ -481,7 +491,9 @@
* @res_sof_cnt path resource sof count value. it used for initial
* frame drop
* @first_sof_ts flag to mark the first sof has been registered
- *
+ * @ppi_hw_intf interface to ppi hardware
+ * @ppi_enabled flag to specify if the hardware has ppi bridge
+ * or not
*/
struct cam_ife_csid_hw {
struct cam_hw_intf *hw_intf;
@@ -504,6 +516,11 @@
struct completion csid_rdin_complete[CAM_IFE_CSID_RDI_MAX];
uint64_t csid_debug;
uint64_t clk_rate;
+ struct cam_isp_sensor_dimension ipp_path_config;
+ struct cam_isp_sensor_dimension ppp_path_config;
+ struct cam_isp_sensor_dimension rdi_path_config[4];
+ uint32_t hbi;
+ uint32_t vbi;
bool sof_irq_triggered;
uint32_t irq_debug_cnt;
uint32_t error_irq_count;
@@ -513,6 +530,8 @@
uint32_t init_frame_drop;
uint32_t res_sof_cnt[CAM_IFE_PIX_PATH_RES_MAX];
uint32_t first_sof_ts;
+ struct cam_hw_intf *ppi_hw_intf[CAM_CSID_PPI_HW_MAX];
+ bool ppi_enable;
};
int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf,
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h
index 0c45bd1..8d34020 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h
@@ -158,6 +158,7 @@
CAM_IFE_CSID_SET_CSID_DEBUG,
CAM_IFE_CSID_SOF_IRQ_DEBUG,
CAM_IFE_CSID_SET_INIT_FRAME_DROP,
+ CAM_IFE_CSID_SET_SENSOR_DIMENSION_CFG,
CAM_IFE_CSID_CMD_MAX,
};
@@ -181,5 +182,17 @@
uint64_t clk_rate;
};
+/*
+ * struct cam_ife_sensor_dim_update_args:
+ *
+ * @ppp_path: expected ppp path configuration
+ * @ipp_path: expected ipp path configuration
+ * @rdi_path: expected rdi path configuration
+ */
+struct cam_ife_sensor_dimension_update_args {
+ struct cam_isp_sensor_dimension ppp_path;
+ struct cam_isp_sensor_dimension ipp_path;
+ struct cam_isp_sensor_dimension rdi_path[4];
+};
#endif /* _CAM_CSID_HW_INTF_H_ */
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h
index b230147..d90030d 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h
@@ -20,17 +20,21 @@
#include "cam_irq_controller.h"
#include <uapi/media/cam_isp.h>
+#define CAM_ISP_FPS_60 60
+
/*
* struct cam_isp_timestamp:
*
* @mono_time: Monotonic boot time
* @vt_time: AV Timer time
* @ticks: Qtimer ticks
+ * @time_usecs: time in micro seconds
*/
struct cam_isp_timestamp {
struct timeval mono_time;
struct timeval vt_time;
uint64_t ticks;
+ uint64_t time_usecs;
};
/*
@@ -105,6 +109,7 @@
CAM_ISP_HW_CMD_FE_UPDATE_IN_RD,
CAM_ISP_HW_CMD_FE_UPDATE_BUS_RD,
CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP,
+ CAM_ISP_HW_CMD_FPS_CONFIG,
CAM_ISP_HW_CMD_MAX,
};
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h
index 9d6bcb7..3bcedc9 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h
@@ -178,6 +178,17 @@
};
/*
+ * struct cam_vfe_fps_config_args:
+ *
+ * @node_res: Resource to get the fps value
+ * @fps: FPS value to configure EPOCH
+ */
+struct cam_vfe_fps_config_args {
+ struct cam_isp_resource_node *node_res;
+ uint32_t fps;
+};
+
+/*
* struct cam_vfe_bw_update_args:
*
* @node_res: Resource to get the BW
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c
index a26c112..162ddad 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c
@@ -444,6 +444,8 @@
get_monotonic_boottime(&ts);
time_stamp->mono_time.tv_sec = ts.tv_sec;
time_stamp->mono_time.tv_usec = ts.tv_nsec/1000;
+ time_stamp->time_usecs = ts.tv_sec * 1000000 +
+ time_stamp->mono_time.tv_usec;
}
static int cam_vfe_irq_top_half(uint32_t evt_id,
@@ -761,6 +763,7 @@
case CAM_ISP_HW_CMD_BW_UPDATE:
case CAM_ISP_HW_CMD_BW_CONTROL:
case CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP:
+ case CAM_ISP_HW_CMD_FPS_CONFIG:
rc = core_info->vfe_top->hw_ops.process_cmd(
core_info->vfe_top->top_priv, cmd_type, cmd_args,
arg_size);
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c
index 4e9a975..a70f0bb 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c
@@ -44,6 +44,7 @@
bool enable_sof_irq_debug;
uint32_t irq_debug_cnt;
uint32_t camif_debug;
+ uint32_t fps;
};
static int cam_vfe_camif_validate_pix_pattern(uint32_t pattern)
@@ -265,9 +266,15 @@
case CAM_CPAS_TITAN_170_V110:
case CAM_CPAS_TITAN_170_V120:
default:
- epoch0_irq_mask = (((rsrc_data->last_line -
+ if (rsrc_data->fps == CAM_ISP_FPS_60) {
+ epoch0_irq_mask = ((rsrc_data->last_line -
+ rsrc_data->first_line) / 2) +
+ rsrc_data->first_line;
+ } else {
+ epoch0_irq_mask = (((rsrc_data->last_line -
rsrc_data->first_line) * 2) / 3) +
rsrc_data->first_line;
+ }
epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg &
0xFFFF;
computed_epoch_line_cfg = (epoch0_irq_mask << 16) |
@@ -514,6 +521,20 @@
return 0;
}
+static int cam_vfe_camif_set_fps_config(
+ struct cam_isp_resource_node *rsrc_node, void *cmd_args)
+{
+ struct cam_vfe_mux_camif_data *camif_priv = NULL;
+ struct cam_vfe_fps_config_args *fps_args = cmd_args;
+
+ camif_priv =
+ (struct cam_vfe_mux_camif_data *)rsrc_node->res_priv;
+
+ camif_priv->fps = fps_args->fps;
+
+ return 0;
+
+}
static int cam_vfe_camif_process_cmd(struct cam_isp_resource_node *rsrc_node,
uint32_t cmd_type, void *cmd_args, uint32_t arg_size)
@@ -545,6 +566,9 @@
case CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP:
rc = cam_vfe_camif_irq_reg_dump(rsrc_node);
break;
+ case CAM_ISP_HW_CMD_FPS_CONFIG:
+ rc = cam_vfe_camif_set_fps_config(rsrc_node, cmd_args);
+ break;
default:
CAM_ERR(CAM_ISP,
"unsupported process command:%d", cmd_type);
diff --git a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c
index b0ac94b..9d03cba 100644
--- a/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c
+++ b/drivers/media/platform/msm/camera_v3/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c
@@ -283,6 +283,22 @@
return 0;
}
+static int cam_vfe_top_fps_config(
+ struct cam_vfe_top_ver2_priv *top_priv,
+ void *cmd_args, uint32_t arg_size)
+{
+ struct cam_vfe_fps_config_args *cmd_update = NULL;
+
+ cmd_update =
+ (struct cam_vfe_fps_config_args *)cmd_args;
+
+ if (cmd_update->node_res->process_cmd)
+ return cmd_update->node_res->process_cmd(cmd_update->node_res,
+ CAM_ISP_HW_CMD_FPS_CONFIG, cmd_args, arg_size);
+
+ return 0;
+}
+
static int cam_vfe_top_clock_update(
struct cam_vfe_top_ver2_priv *top_priv,
void *cmd_args, uint32_t arg_size)
@@ -740,6 +756,10 @@
rc = cam_vfe_get_irq_register_dump(top_priv,
cmd_args, arg_size);
break;
+ case CAM_ISP_HW_CMD_FPS_CONFIG:
+ rc = cam_vfe_top_fps_config(top_priv, cmd_args,
+ arg_size);
+ break;
default:
rc = -EINVAL;
CAM_ERR(CAM_ISP, "Error! Invalid cmd:%d", cmd_type);
diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index 1fcafc1..8a76b64 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -1497,20 +1497,17 @@
else
qclk = &qseecom.ce_drv;
- if (qclk->clk_access_cnt > 2) {
+ if (qclk->clk_access_cnt > 0) {
+ qclk->clk_access_cnt--;
+ } else {
pr_err("Invalid clock ref count %d\n", qclk->clk_access_cnt);
ret = -EINVAL;
- goto err_dec_ref_cnt;
}
- if (qclk->clk_access_cnt == 2)
- qclk->clk_access_cnt--;
-err_dec_ref_cnt:
mutex_unlock(&clk_access_lock);
return ret;
}
-
static int qseecom_scale_bus_bandwidth_timer(uint32_t mode)
{
int32_t ret = 0;
@@ -7537,6 +7534,13 @@
break;
}
case QSEECOM_IOCTL_APP_LOADED_QUERY_REQ: {
+ if ((data->type != QSEECOM_GENERIC) &&
+ (data->type != QSEECOM_CLIENT_APP)) {
+ pr_err("app loaded query req: invalid handle (%d)\n",
+ data->type);
+ ret = -EINVAL;
+ break;
+ }
data->type = QSEECOM_CLIENT_APP;
mutex_lock(&app_access_lock);
atomic_inc(&data->ioctl_count);
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c
index a1dab55..b8a8a92 100644
--- a/drivers/pci/host/pci-msm.c
+++ b/drivers/pci/host/pci-msm.c
@@ -517,6 +517,7 @@
struct platform_device *pdev;
struct pci_dev *dev;
struct regulator *gdsc;
+ struct regulator *vreg_pcie;
struct regulator *gdsc_smmu;
struct msm_pcie_vreg_info_t vreg[MSM_PCIE_MAX_VREG];
struct msm_pcie_gpio_info_t gpio[MSM_PCIE_MAX_GPIO];
@@ -633,7 +634,6 @@
bool use_pinctrl;
struct pinctrl *pinctrl;
struct pinctrl_state *pins_default;
- struct pinctrl_state *pins_power_on;
struct pinctrl_state *pins_sleep;
struct msm_pcie_device_info pcidev_table[MAX_DEVICE_NUM];
};
@@ -3422,6 +3422,18 @@
}
}
+ dev->vreg_pcie = devm_regulator_get(&pdev->dev, "vreg-pcie");
+
+ if (IS_ERR(dev->vreg_pcie)) {
+ PCIE_ERR(dev, "PCIe: RC%d Failed to get %s VREG_PCIE:%ld\n",
+ dev->rc_idx, dev->pdev->name, PTR_ERR(dev->gdsc));
+ if (PTR_ERR(dev->vreg_pcie) == -EPROBE_DEFER)
+ PCIE_DBG(dev, "PCIe: EPROBE_DEFER for %s VREG_PCIE\n",
+ dev->pdev->name);
+ ret = PTR_ERR(dev->vreg_pcie);
+ goto out;
+ }
+
dev->gdsc = devm_regulator_get(&pdev->dev, "gdsc-vdd");
if (IS_ERR(dev->gdsc)) {
@@ -4287,6 +4299,19 @@
}
if (!dev->enumerated) {
+
+ /*Open the PCIE VCC before enable the pcie */
+ if (dev->vreg_pcie) {
+ ret = regulator_enable(dev->vreg_pcie);
+
+ if (ret) {
+ PCIE_ERR(dev,
+ "PCIe: fail to open vcc for RC%d (%s)\n",
+ dev->rc_idx, dev->pdev->name);
+ return ret;
+ }
+ }
+
ret = msm_pcie_enable(dev, PM_ALL);
/* kick start ARM PCI configuration framework */
@@ -6013,16 +6038,6 @@
msm_pcie_dev[rc_idx].pins_default = NULL;
}
- msm_pcie_dev[rc_idx].pins_power_on =
- pinctrl_lookup_state(msm_pcie_dev[rc_idx].pinctrl,
- "slot_power_on");
- if (IS_ERR(msm_pcie_dev[rc_idx].pins_power_on)) {
- PCIE_ERR(&msm_pcie_dev[rc_idx],
- "PCIe: RC%d could not get pinctrl power_on state\n",
- rc_idx);
- msm_pcie_dev[rc_idx].pins_power_on = NULL;
- }
-
msm_pcie_dev[rc_idx].pins_sleep =
pinctrl_lookup_state(msm_pcie_dev[rc_idx].pinctrl,
"sleep");
@@ -6050,11 +6065,6 @@
msm_pcie_sysfs_init(&msm_pcie_dev[rc_idx]);
msm_pcie_dev[rc_idx].drv_ready = true;
- if (msm_pcie_dev[rc_idx].use_pinctrl &&
- msm_pcie_dev[rc_idx].pins_power_on) {
- pinctrl_select_state(msm_pcie_dev[rc_idx].pinctrl,
- msm_pcie_dev[rc_idx].pins_power_on);
- }
if (msm_pcie_dev[rc_idx].boot_option &
MSM_PCIE_NO_PROBE_ENUMERATION) {
@@ -6122,6 +6132,15 @@
msm_pcie_gpio_deinit(&msm_pcie_dev[rc_idx]);
msm_pcie_release_resources(&msm_pcie_dev[rc_idx]);
+ /*Close the PCIE VCC when remove the pcie*/
+ if (msm_pcie_dev[rc_idx].vreg_pcie) {
+ ret = regulator_disable(msm_pcie_dev[rc_idx].vreg_pcie);
+
+ if (ret)
+ pr_err("%s: PCIe: fail to close VCC.\n", __func__);
+
+ }
+
out:
mutex_unlock(&pcie_drv.drv_lock);
diff --git a/fs/crypto/keyinfo.c b/fs/crypto/keyinfo.c
index cfe9117..9f38e7f 100755
--- a/fs/crypto/keyinfo.c
+++ b/fs/crypto/keyinfo.c
@@ -606,8 +606,6 @@
if (res)
goto out;
- memzero_explicit(crypt_info->ci_raw_key,
- sizeof(crypt_info->ci_raw_key));
do_ice:
if (cmpxchg(&inode->i_crypt_info, NULL, crypt_info) == NULL)
crypt_info = NULL;
@@ -615,6 +613,7 @@
if (res == -ENOKEY)
res = 0;
put_crypt_info(crypt_info);
+ kzfree(raw_key);
return res;
}
EXPORT_SYMBOL(fscrypt_get_encryption_info);
diff --git a/include/uapi/media/cam_isp.h b/include/uapi/media/cam_isp.h
index 7489b72..50d95c4 100644
--- a/include/uapi/media/cam_isp.h
+++ b/include/uapi/media/cam_isp.h
@@ -84,14 +84,16 @@
#define CAM_ISP_DSP_MODE_ROUND 2
/* ISP Generic Cmd Buffer Blob types */
-#define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0
-#define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1
-#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2
-#define CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG 3
-#define CAM_ISP_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 4
-#define CAM_ISP_GENERIC_BLOB_TYPE_FE_CONFIG 5
-#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG_V2 6
-#define CAM_ISP_GENERIC_BLOB_TYPE_INIT_FRAME_DROP 10
+#define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0
+#define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1
+#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2
+#define CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG 3
+#define CAM_ISP_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 4
+#define CAM_ISP_GENERIC_BLOB_TYPE_FE_CONFIG 5
+#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG_V2 6
+#define CAM_ISP_GENERIC_BLOB_TYPE_INIT_FRAME_DROP 10
+#define CAM_ISP_GENERIC_BLOB_TYPE_SENSOR_DIMENSION_CONFIG 11
+#define CAM_ISP_GENERIC_BLOB_TYPE_FPS_CONFIG 12
/* Per Path Usage Data */
#define CAM_ISP_USAGE_INVALID 0
@@ -464,6 +466,36 @@
uint32_t latency_buf_size;
} __attribute__((packed));
+/**
+ * struct cam_isp_sensor_path_dimension
+ *
+ * @width expected width
+ * @height expected height
+ * @measure_enabled flag to indicate if pixel measurement is to be enabled
+ */
+struct cam_isp_sensor_dimension {
+ uint32_t width;
+ uint32_t height;
+ uint32_t measure_enabled;
+} __attribute__((packed));
+
+/**
+ * struct cam_isp_sensor_config - Sensor Dimension configuration
+ *
+ * @pix_path: expected ppp path configuration
+ * @pix_path: expected ipp path configuration
+ * @rdi_path: expected rdi path configuration
+ * @hbi: HBI value
+ * @vbi: VBI value
+ */
+struct cam_isp_sensor_config {
+ struct cam_isp_sensor_dimension ppp_path;
+ struct cam_isp_sensor_dimension ipp_path;
+ struct cam_isp_sensor_dimension rdi_path[4];
+ uint32_t hbi;
+ uint32_t vbi;
+} __attribute__((packed));
+
/* Acquire Device/HW v2 */
/**
@@ -489,6 +521,15 @@
uint64_t data;
};
+/**
+ * struct cam_fps_config - FPS blob support
+ *
+ * @fps: FPS value
+ */
+struct cam_fps_config {
+ uint32_t fps;
+} __attribute__((packed));
+
#define CAM_ISP_ACQUIRE_COMMON_VER0 0x1000
#define CAM_ISP_ACQUIRE_COMMON_SIZE_VER0 0x0
diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c
index 0745029..cfe4f40 100644
--- a/kernel/sched/cpufreq_schedutil.c
+++ b/kernel/sched/cpufreq_schedutil.c
@@ -154,7 +154,7 @@
trace_cpu_frequency(next_freq, smp_processor_id());
} else {
sg_policy->work_in_progress = true;
- irq_work_queue(&sg_policy->irq_work);
+ sched_irq_work_queue(&sg_policy->irq_work);
}
}