| menuconfig ARCH_TEGRA |
| bool "NVIDIA Tegra" if ARCH_MULTI_V7 |
| select ARCH_REQUIRE_GPIOLIB |
| select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS |
| select ARM_GIC |
| select CLKSRC_MMIO |
| select HAVE_ARM_SCU if SMP |
| select HAVE_ARM_TWD if SMP |
| select PINCTRL |
| select ARCH_HAS_RESET_CONTROLLER |
| select RESET_CONTROLLER |
| select SOC_BUS |
| select USB_ULPI if USB_PHY |
| select USB_ULPI_VIEWPORT if USB_PHY |
| help |
| This enables support for NVIDIA Tegra based systems. |
| |
| if ARCH_TEGRA |
| |
| config ARCH_TEGRA_2x_SOC |
| bool "Enable support for Tegra20 family" |
| select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP |
| select ARM_ERRATA_720789 |
| select ARM_ERRATA_754327 if SMP |
| select ARM_ERRATA_764369 if SMP |
| select PINCTRL_TEGRA20 |
| select PL310_ERRATA_727915 if CACHE_L2X0 |
| select PL310_ERRATA_769419 if CACHE_L2X0 |
| help |
| Support for NVIDIA Tegra AP20 and T20 processors, based on the |
| ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
| |
| config ARCH_TEGRA_3x_SOC |
| bool "Enable support for Tegra30 family" |
| select ARM_ERRATA_754322 |
| select ARM_ERRATA_764369 if SMP |
| select PINCTRL_TEGRA30 |
| select PL310_ERRATA_769419 if CACHE_L2X0 |
| help |
| Support for NVIDIA Tegra T30 processor family, based on the |
| ARM CortexA9MP CPU and the ARM PL310 L2 cache controller |
| |
| config ARCH_TEGRA_114_SOC |
| bool "Enable support for Tegra114 family" |
| select ARM_ERRATA_798181 if SMP |
| select ARM_L1_CACHE_SHIFT_6 |
| select HAVE_ARM_ARCH_TIMER |
| select PINCTRL_TEGRA114 |
| help |
| Support for NVIDIA Tegra T114 processor family, based on the |
| ARM CortexA15MP CPU |
| |
| config ARCH_TEGRA_124_SOC |
| bool "Enable support for Tegra124 family" |
| select ARM_L1_CACHE_SHIFT_6 |
| select HAVE_ARM_ARCH_TIMER |
| select PINCTRL_TEGRA124 |
| help |
| Support for NVIDIA Tegra T124 processor family, based on the |
| ARM CortexA15MP CPU |
| |
| config TEGRA_AHB |
| bool "Enable AHB driver for NVIDIA Tegra SoCs" |
| default y |
| help |
| Adds AHB configuration functionality for NVIDIA Tegra SoCs, |
| which controls AHB bus master arbitration and some |
| performance parameters(priority, prefech size). |
| |
| endif |