| /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include "sdm845.dtsi" |
| #include "sdm845-v2-camera.dtsi" |
| |
| / { |
| model = "Qualcomm Technologies, Inc. SDM845 V2"; |
| qcom,msm-id = <321 0x20000>; |
| }; |
| |
| &sdhc_2 { |
| /delete-property/ qcom,sdr104-wa; |
| }; |
| |
| /delete-node/ &apc0_cpr; |
| /delete-node/ &apc1_cpr; |
| |
| &soc { |
| /* CPR controller regulators */ |
| apc0_cpr: cprh-ctrl@17dc0000 { |
| compatible = "qcom,cprh-sdm845-v2-kbss-regulator"; |
| reg = <0x17dc0000 0x4000>, |
| <0x00784000 0x1000>, |
| <0x17840000 0x1000>; |
| reg-names = "cpr_ctrl", "fuse_base", "saw"; |
| clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>; |
| clock-names = "core_clk"; |
| qcom,cpr-ctrl-name = "apc0"; |
| qcom,cpr-controller-id = <0>; |
| |
| qcom,cpr-sensor-time = <1000>; |
| qcom,cpr-loop-time = <5000000>; |
| qcom,cpr-idle-cycles = <15>; |
| qcom,cpr-up-down-delay-time = <3000>; |
| qcom,cpr-step-quot-init-min = <11>; |
| qcom,cpr-step-quot-init-max = <12>; |
| qcom,cpr-count-mode = <0>; /* All at once */ |
| qcom,cpr-count-repeat = <20>; |
| qcom,cpr-down-error-step-limit = <1>; |
| qcom,cpr-up-error-step-limit = <1>; |
| qcom,cpr-corner-switch-delay-time = <1042>; |
| qcom,cpr-voltage-settling-time = <1760>; |
| qcom,cpr-reset-step-quot-loop-en; |
| |
| qcom,voltage-step = <4000>; |
| qcom,voltage-base = <352000>; |
| qcom,cpr-saw-use-unit-mV; |
| |
| qcom,saw-avs-ctrl = <0x101C031>; |
| qcom,saw-avs-limit = <0x3B803B8>; |
| |
| qcom,cpr-enable; |
| qcom,cpr-hw-closed-loop; |
| |
| qcom,cpr-panic-reg-addr-list = |
| <0x17dc3a84 0x17dc3a88 0x17840c18>; |
| qcom,cpr-panic-reg-name-list = |
| "APSS_SILVER_CPRH_STATUS_0", |
| "APSS_SILVER_CPRH_STATUS_1", |
| "SILVER_SAW4_PMIC_STS"; |
| |
| qcom,cpr-aging-ref-voltage = <1000000>; |
| vdd-supply = <&pm8998_s13>; |
| |
| thread@0 { |
| qcom,cpr-thread-id = <0>; |
| qcom,cpr-consecutive-up = <0>; |
| qcom,cpr-consecutive-down = <0>; |
| qcom,cpr-up-threshold = <2>; |
| qcom,cpr-down-threshold = <2>; |
| |
| apc0_pwrcl_vreg: regulator { |
| regulator-name = "apc0_pwrcl_corner"; |
| regulator-min-microvolt = <1>; |
| regulator-max-microvolt = <18>; |
| |
| qcom,cpr-fuse-corners = <4>; |
| qcom,cpr-fuse-combos = <16>; |
| qcom,cpr-speed-bins = <2>; |
| qcom,cpr-speed-bin-corners = <18 18>; |
| qcom,cpr-corners = <18>; |
| |
| qcom,cpr-corner-fmax-map = <6 12 15 18>; |
| |
| qcom,cpr-voltage-ceiling = |
| <828000 828000 828000 828000 828000 |
| 828000 828000 828000 828000 828000 |
| 828000 828000 828000 828000 828000 |
| 932000 1000000 1000000>; |
| |
| qcom,cpr-voltage-floor = |
| <568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000>; |
| |
| qcom,cpr-floor-to-ceiling-max-range = |
| <32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 40000 40000>; |
| |
| qcom,corner-frequencies = |
| <300000000 403200000 480000000 |
| 576000000 652800000 748800000 |
| 825600000 902400000 979200000 |
| 1056000000 1132800000 1228800000 |
| 1324800000 1420800000 1516800000 |
| 1612800000 1689600000 1766400000>; |
| |
| qcom,cpr-ro-scaling-factor = |
| <2594 2795 2576 2761 2469 2673 2198 |
| 2553 3188 3255 3191 2962 3055 2984 |
| 2043 2947>, |
| <2594 2795 2576 2761 2469 2673 2198 |
| 2553 3188 3255 3191 2962 3055 2984 |
| 2043 2947>, |
| <2259 2389 2387 2531 2294 2464 2218 |
| 2476 2525 2855 2817 2836 2740 2490 |
| 1950 2632>, |
| <2259 2389 2387 2531 2294 2464 2218 |
| 2476 2525 2855 2817 2836 2740 2490 |
| 1950 2632>; |
| |
| qcom,cpr-open-loop-voltage-fuse-adjustment = |
| < 0 0 12000 12000>; |
| |
| qcom,cpr-closed-loop-voltage-fuse-adjustment = |
| < 0 0 12000 10000>; |
| |
| qcom,allow-voltage-interpolation; |
| qcom,allow-quotient-interpolation; |
| qcom,cpr-scaled-open-loop-voltage-as-ceiling; |
| |
| qcom,cpr-aging-max-voltage-adjustment = <15000>; |
| qcom,cpr-aging-ref-corner = <18>; |
| qcom,cpr-aging-ro-scaling-factor = <1620>; |
| qcom,allow-aging-voltage-adjustment = |
| /* Speed bin 0 */ |
| <0 1 1 1 1 1 1 1>, |
| /* Speed bin 1 */ |
| <0 1 1 1 1 1 1 1>; |
| qcom,allow-aging-open-loop-voltage-adjustment = |
| <1>; |
| }; |
| }; |
| |
| thread@1 { |
| qcom,cpr-thread-id = <1>; |
| qcom,cpr-consecutive-up = <0>; |
| qcom,cpr-consecutive-down = <0>; |
| qcom,cpr-up-threshold = <2>; |
| qcom,cpr-down-threshold = <2>; |
| |
| apc0_l3_vreg: regulator { |
| regulator-name = "apc0_l3_corner"; |
| regulator-min-microvolt = <1>; |
| regulator-max-microvolt = <15>; |
| |
| qcom,cpr-fuse-corners = <4>; |
| qcom,cpr-fuse-combos = <16>; |
| qcom,cpr-speed-bins = <2>; |
| qcom,cpr-speed-bin-corners = <14 15>; |
| qcom,cpr-corners = |
| /* Speed bin 0 */ |
| <14 14 14 14 14 14 14 14>, |
| /* Speed bin 1 */ |
| <15 15 15 15 15 15 15 15>; |
| |
| qcom,cpr-corner-fmax-map = |
| /* Speed bin 0 */ |
| <4 8 11 14>, |
| /* Speed bin 1 */ |
| <4 8 11 15>; |
| |
| qcom,cpr-voltage-ceiling = |
| /* Speed bin 0 */ |
| <828000 828000 828000 828000 828000 |
| 828000 828000 828000 828000 828000 |
| 828000 932000 932000 1000000>, |
| /* Speed bin 1 */ |
| <828000 828000 828000 828000 828000 |
| 828000 828000 828000 828000 828000 |
| 828000 932000 932000 1000000 |
| 1000000>; |
| |
| qcom,cpr-voltage-floor = |
| /* Speed bin 0 */ |
| <568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000>, |
| /* Speed bin 1 */ |
| <568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 |
| 568000>; |
| |
| qcom,cpr-floor-to-ceiling-max-range = |
| /* Speed bin 0 */ |
| <32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 32000 40000>, |
| /* Speed bin 1 */ |
| <32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 32000 40000 40000>; |
| |
| qcom,corner-frequencies = |
| /* Speed bin 0 */ |
| <300000000 403200000 480000000 |
| 576000000 652800000 748800000 |
| 844800000 940800000 1036800000 |
| 1132800000 1209600000 1305600000 |
| 1401600000 1478400000>, |
| /* Speed bin 1 */ |
| <300000000 403200000 480000000 |
| 576000000 652800000 748800000 |
| 844800000 940800000 1036800000 |
| 1132800000 1209600000 1305600000 |
| 1401600000 1497600000 1593600000>; |
| |
| qcom,cpr-ro-scaling-factor = |
| <2857 3056 2828 2952 2699 2796 2447 |
| 2631 2630 2579 2244 3343 3287 3137 |
| 3164 2656>, |
| <2857 3056 2828 2952 2699 2796 2447 |
| 2631 2630 2579 2244 3343 3287 3137 |
| 3164 2656>, |
| <2439 2577 2552 2667 2461 2577 2394 |
| 2536 2132 2307 2191 2903 2838 2912 |
| 2501 2095>, |
| <2439 2577 2552 2667 2461 2577 2394 |
| 2536 2132 2307 2191 2903 2838 2912 |
| 2501 2095>; |
| |
| qcom,cpr-open-loop-voltage-fuse-adjustment = |
| < 8000 16000 16000 12000>; |
| |
| qcom,cpr-closed-loop-voltage-fuse-adjustment = |
| < 6000 14000 16000 12000>; |
| |
| qcom,allow-voltage-interpolation; |
| qcom,allow-quotient-interpolation; |
| qcom,cpr-scaled-open-loop-voltage-as-ceiling; |
| |
| qcom,cpr-aging-max-voltage-adjustment = <15000>; |
| qcom,cpr-aging-ref-corner = <14 15>; |
| qcom,cpr-aging-ro-scaling-factor = <1620>; |
| qcom,allow-aging-voltage-adjustment = |
| /* Speed bin 0 */ |
| <0 1 1 1 1 1 1 1>, |
| /* Speed bin 1 */ |
| <0 1 1 1 1 1 1 1>; |
| qcom,allow-aging-open-loop-voltage-adjustment = |
| <1>; |
| }; |
| }; |
| }; |
| |
| apc1_cpr: cprh-ctrl@17db0000 { |
| compatible = "qcom,cprh-sdm845-v2-kbss-regulator"; |
| reg = <0x17db0000 0x4000>, |
| <0x00784000 0x1000>, |
| <0x17830000 0x1000>; |
| reg-names = "cpr_ctrl", "fuse_base", "saw"; |
| clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>; |
| clock-names = "core_clk"; |
| qcom,cpr-ctrl-name = "apc1"; |
| qcom,cpr-controller-id = <1>; |
| |
| qcom,cpr-sensor-time = <1000>; |
| qcom,cpr-loop-time = <5000000>; |
| qcom,cpr-idle-cycles = <15>; |
| qcom,cpr-up-down-delay-time = <3000>; |
| qcom,cpr-step-quot-init-min = <9>; |
| qcom,cpr-step-quot-init-max = <14>; |
| qcom,cpr-count-mode = <0>; /* All at once */ |
| qcom,cpr-count-repeat = <20>; |
| qcom,cpr-down-error-step-limit = <1>; |
| qcom,cpr-up-error-step-limit = <1>; |
| qcom,cpr-corner-switch-delay-time = <1042>; |
| qcom,cpr-voltage-settling-time = <1760>; |
| qcom,cpr-reset-step-quot-loop-en; |
| |
| qcom,apm-threshold-voltage = <800000>; |
| qcom,apm-crossover-voltage = <880000>; |
| qcom,mem-acc-threshold-voltage = <852000>; |
| qcom,mem-acc-crossover-voltage = <852000>; |
| |
| qcom,voltage-step = <4000>; |
| qcom,voltage-base = <352000>; |
| qcom,cpr-saw-use-unit-mV; |
| |
| qcom,saw-avs-ctrl = <0x101C031>; |
| qcom,saw-avs-limit = <0x4700470>; |
| |
| qcom,cpr-enable; |
| qcom,cpr-hw-closed-loop; |
| |
| qcom,cpr-panic-reg-addr-list = |
| <0x17db3a84 0x17830c18>; |
| qcom,cpr-panic-reg-name-list = |
| "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS"; |
| |
| qcom,cpr-aging-ref-voltage = <1136000>; |
| vdd-supply = <&pm8998_s12>; |
| |
| thread@0 { |
| qcom,cpr-thread-id = <0>; |
| qcom,cpr-consecutive-up = <0>; |
| qcom,cpr-consecutive-down = <0>; |
| qcom,cpr-up-threshold = <2>; |
| qcom,cpr-down-threshold = <2>; |
| |
| apc1_perfcl_vreg: regulator { |
| regulator-name = "apc1_perfcl_corner"; |
| regulator-min-microvolt = <1>; |
| regulator-max-microvolt = <33>; |
| |
| qcom,cpr-fuse-corners = <5>; |
| qcom,cpr-fuse-combos = <16>; |
| qcom,cpr-speed-bins = <2>; |
| qcom,cpr-speed-bin-corners = <28 31>; |
| qcom,cpr-corners = |
| /* Speed bin 0 */ |
| <28 28 28 28 28 28 28 28>, |
| /* Speed bin 1 */ |
| <31 31 31 31 31 31 31 31>; |
| |
| qcom,cpr-corner-fmax-map = |
| /* Speed bin 0 */ |
| <7 14 22 27 28>, |
| /* Speed bin 1 */ |
| <7 14 22 27 31>; |
| |
| qcom,cpr-voltage-ceiling = |
| /* Speed bin 0 */ |
| <828000 828000 828000 828000 828000 |
| 828000 828000 828000 828000 828000 |
| 828000 828000 828000 828000 828000 |
| 828000 828000 828000 932000 932000 |
| 932000 932000 1104000 1104000 1104000 |
| 1104000 1136000 1136000>, |
| /* Speed bin 1 */ |
| <828000 828000 828000 828000 828000 |
| 828000 828000 828000 828000 828000 |
| 828000 828000 828000 828000 828000 |
| 828000 828000 828000 932000 932000 |
| 932000 932000 1104000 1104000 1104000 |
| 1104000 1136000 1136000 1136000 1136000 |
| 1136000>; |
| |
| qcom,cpr-voltage-floor = |
| /* Speed bin 0 */ |
| <568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000>, |
| /* Speed bin 1 */ |
| <568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000 568000 568000 568000 568000 |
| 568000>; |
| |
| qcom,cpr-floor-to-ceiling-max-range = |
| /* Speed bin 0 */ |
| <32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 32000>, |
| /* Speed bin 1 */ |
| <32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 32000 32000 32000 |
| 32000 32000 40000 40000 40000 |
| 40000>; |
| |
| qcom,corner-frequencies = |
| /* Speed bin 0 */ |
| <300000000 403200000 480000000 |
| 576000000 652800000 748800000 |
| 825600000 902400000 979200000 |
| 1056000000 1132800000 1209600000 |
| 1286400000 1363200000 1459200000 |
| 1536000000 1612800000 1689600000 |
| 1766400000 1843200000 1920000000 |
| 1996800000 2092800000 2169600000 |
| 2246400000 2323200000 2400000000 |
| 2400000000>, |
| /* Speed bin 1 */ |
| <300000000 403200000 480000000 |
| 576000000 652800000 748800000 |
| 825600000 902400000 979200000 |
| 1056000000 1132800000 1209600000 |
| 1286400000 1363200000 1459200000 |
| 1536000000 1612800000 1689600000 |
| 1766400000 1843200000 1920000000 |
| 1996800000 2092800000 2169600000 |
| 2246400000 2323200000 2400000000 |
| 2476800000 2553600000 2649600000 |
| 2707200000>; |
| |
| qcom,cpr-ro-scaling-factor = |
| <2857 3056 2828 2952 2699 2796 2447 |
| 2631 2630 2579 2244 3343 3287 3137 |
| 3164 2656>, |
| <2857 3056 2828 2952 2699 2796 2447 |
| 2631 2630 2579 2244 3343 3287 3137 |
| 3164 2656>, |
| <2086 2208 2273 2408 2203 2327 2213 |
| 2340 1755 2039 2049 2474 2437 2618 |
| 2003 1675>, |
| <2086 2208 2273 2408 2203 2327 2213 |
| 2340 1755 2039 2049 2474 2437 2618 |
| 2003 1675>, |
| <2086 2208 2273 2408 2203 2327 2213 |
| 2340 1755 2039 2049 2474 2437 2618 |
| 2003 1675>; |
| |
| qcom,cpr-open-loop-voltage-fuse-adjustment = |
| /* Speed bin 0 */ |
| < 8000 8000 8000 0 0>, |
| /* Speed bin 1 */ |
| < 8000 8000 8000 0 16000>; |
| |
| qcom,cpr-closed-loop-voltage-fuse-adjustment = |
| /* Speed bin 0 */ |
| < 6000 6000 8000 0 0>, |
| /* Speed bin 1 */ |
| < 6000 6000 8000 0 16000>; |
| |
| qcom,allow-voltage-interpolation; |
| qcom,allow-quotient-interpolation; |
| qcom,cpr-scaled-open-loop-voltage-as-ceiling; |
| |
| qcom,cpr-aging-max-voltage-adjustment = <15000>; |
| qcom,cpr-aging-ref-corner = <27 31>; |
| qcom,cpr-aging-ro-scaling-factor = <1700>; |
| qcom,allow-aging-voltage-adjustment = |
| /* Speed bin 0 */ |
| <0 1 1 1 1 1 1 1>, |
| /* Speed bin 1 */ |
| <0 1 1 1 1 1 1 1>; |
| qcom,allow-aging-open-loop-voltage-adjustment = |
| <1>; |
| }; |
| }; |
| }; |
| |
| gpu_gx_domain_addr: syscon@0x5091508 { |
| compatible = "syscon"; |
| reg = <0x5091508 0x4>; |
| }; |
| |
| gpu_gx_sw_reset: syscon@0x5091008 { |
| compatible = "syscon"; |
| reg = <0x5091008 0x4>; |
| }; |
| }; |
| |
| &pil_modem { |
| qcom,mss_pdc_offset = <9>; |
| }; |
| |
| /* VDD_APC0 */ |
| &pm8998_s13 { |
| regulator-min-microvolt = <568000>; |
| regulator-max-microvolt = <1000000>; |
| }; |
| |
| /* VDD_APC1 */ |
| &pm8998_s12 { |
| regulator-min-microvolt = <568000>; |
| regulator-max-microvolt = <1136000>; |
| }; |
| |
| &clock_cpucc { |
| compatible = "qcom,clk-cpu-osm-v2"; |
| |
| vdd-l3-supply = <&apc0_l3_vreg>; |
| vdd-pwrcl-supply = <&apc0_pwrcl_vreg>; |
| vdd-perfcl-supply = <&apc1_perfcl_vreg>; |
| |
| qcom,l3-speedbin0-v0 = |
| < 300000000 0x000c000f 0x00002020 0x1 1 >, |
| < 403200000 0x500c0115 0x00002020 0x1 2 >, |
| < 480000000 0x50140219 0x00002020 0x1 3 >, |
| < 576000000 0x5014031e 0x00002020 0x1 4 >, |
| < 652800000 0x401c0422 0x00002020 0x1 5 >, |
| < 748800000 0x401c0527 0x00002020 0x1 6 >, |
| < 844800000 0x4024062c 0x00002323 0x2 7 >, |
| < 940800000 0x40240731 0x00002727 0x2 8 >, |
| < 1036800000 0x40240836 0x00002b2b 0x2 9 >, |
| < 1132800000 0x402c093b 0x00002f2f 0x2 10 >, |
| < 1209600000 0x402c0a3f 0x00003232 0x2 11 >, |
| < 1305600000 0x40340b44 0x00003636 0x2 12 >, |
| < 1401600000 0x40340c49 0x00003a3a 0x2 13 >, |
| < 1478400000 0x403c0d4d 0x00003e3e 0x2 14 >; |
| |
| qcom,l3-speedbin1-v0 = |
| < 300000000 0x000c000f 0x00002020 0x1 1 >, |
| < 403200000 0x500c0115 0x00002020 0x1 2 >, |
| < 480000000 0x50140219 0x00002020 0x1 3 >, |
| < 576000000 0x5014031e 0x00002020 0x1 4 >, |
| < 652800000 0x401c0422 0x00002020 0x1 5 >, |
| < 748800000 0x401c0527 0x00002020 0x1 6 >, |
| < 844800000 0x4024062c 0x00002323 0x2 7 >, |
| < 940800000 0x40240731 0x00002727 0x2 8 >, |
| < 1036800000 0x40240836 0x00002b2b 0x2 9 >, |
| < 1132800000 0x402c093b 0x00002f2f 0x2 10 >, |
| < 1209600000 0x402c0a3f 0x00003232 0x2 11 >, |
| < 1305600000 0x40340b44 0x00003636 0x2 12 >, |
| < 1401600000 0x40340c49 0x00003a3a 0x2 13 >, |
| < 1497600000 0x403c0d4e 0x00003e3e 0x2 14 >, |
| < 1593600000 0x403c0e53 0x00004242 0x2 15 >; |
| |
| qcom,pwrcl-speedbin0-v0 = |
| < 300000000 0x000c000f 0x00002020 0x1 1 >, |
| < 403200000 0x500c0115 0x00002020 0x1 2 >, |
| < 480000000 0x50140219 0x00002020 0x1 3 >, |
| < 576000000 0x5014031e 0x00002020 0x1 4 >, |
| < 652800000 0x401c0422 0x00002020 0x1 5 >, |
| < 748800000 0x401c0527 0x00002020 0x1 6 >, |
| < 825600000 0x401c062b 0x00002222 0x1 7 >, |
| < 902400000 0x4024072f 0x00002626 0x1 8 >, |
| < 979200000 0x40240833 0x00002929 0x1 9 >, |
| < 1056000000 0x402c0937 0x00002c2c 0x2 10 >, |
| < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >, |
| < 1228800000 0x402c0b40 0x00003333 0x2 12 >, |
| < 1324800000 0x40340c45 0x00003737 0x2 13 >, |
| < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >, |
| < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >, |
| < 1612800000 0x403c0f54 0x00004343 0x2 16 >, |
| < 1689600000 0x40441058 0x00004646 0x2 17 >, |
| < 1766400000 0x4044115c 0x00004a4a 0x2 18 >; |
| |
| qcom,pwrcl-speedbin1-v0 = |
| < 300000000 0x000c000f 0x00002020 0x1 1 >, |
| < 403200000 0x500c0115 0x00002020 0x1 2 >, |
| < 480000000 0x50140219 0x00002020 0x1 3 >, |
| < 576000000 0x5014031e 0x00002020 0x1 4 >, |
| < 652800000 0x401c0422 0x00002020 0x1 5 >, |
| < 748800000 0x401c0527 0x00002020 0x1 6 >, |
| < 825600000 0x401c062b 0x00002222 0x1 7 >, |
| < 902400000 0x4024072f 0x00002626 0x1 8 >, |
| < 979200000 0x40240833 0x00002929 0x1 9 >, |
| < 1056000000 0x402c0937 0x00002c2c 0x2 10 >, |
| < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >, |
| < 1228800000 0x402c0b40 0x00003333 0x2 12 >, |
| < 1324800000 0x40340c45 0x00003737 0x2 13 >, |
| < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >, |
| < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >, |
| < 1612800000 0x403c0f54 0x00004343 0x2 16 >, |
| < 1689600000 0x40441058 0x00004646 0x2 17 >, |
| < 1766400000 0x4044115c 0x00004a4a 0x2 18 >; |
| |
| qcom,perfcl-speedbin0-v0 = |
| < 300000000 0x000c000f 0x00002020 0x1 1 >, |
| < 403200000 0x500c0115 0x00002020 0x1 2 >, |
| < 480000000 0x50140219 0x00002020 0x1 3 >, |
| < 576000000 0x5014031e 0x00002020 0x1 4 >, |
| < 652800000 0x401c0422 0x00002020 0x1 5 >, |
| < 748800000 0x401c0527 0x00002020 0x1 6 >, |
| < 825600000 0x401c062b 0x00002222 0x1 7 >, |
| < 902400000 0x4024072f 0x00002626 0x1 8 >, |
| < 979200000 0x40240833 0x00002929 0x1 9 >, |
| < 1056000000 0x402c0937 0x00002c2c 0x1 10 >, |
| < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >, |
| < 1209600000 0x402c0b3f 0x00003232 0x2 12 >, |
| < 1286400000 0x40340c43 0x00003636 0x2 13 >, |
| < 1363200000 0x40340d47 0x00003939 0x2 14 >, |
| < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >, |
| < 1536000000 0x403c0f50 0x00004040 0x2 16 >, |
| < 1612800000 0x403c1054 0x00004343 0x2 17 >, |
| < 1689600000 0x40441158 0x00004646 0x2 18 >, |
| < 1766400000 0x4044125c 0x00004a4a 0x2 19 >, |
| < 1843200000 0x40441360 0x00004d4d 0x2 20 >, |
| < 1920000000 0x404c1464 0x00005050 0x2 21 >, |
| < 1996800000 0x404c1568 0x00005353 0x2 22 >, |
| < 2092800000 0x4054166d 0x00005757 0x2 23 >, |
| < 2169600000 0x40541771 0x00005a5a 0x2 24 >, |
| < 2246400000 0x40541875 0x00005e5e 0x2 25 >, |
| < 2323200000 0x40541979 0x00006161 0x2 26 >, |
| < 2400000000 0x40541a7d 0x00006464 0x2 27 >; |
| |
| qcom,perfcl-speedbin1-v0 = |
| < 300000000 0x000c000f 0x00002020 0x1 1 >, |
| < 403200000 0x500c0115 0x00002020 0x1 2 >, |
| < 480000000 0x50140219 0x00002020 0x1 3 >, |
| < 576000000 0x5014031e 0x00002020 0x1 4 >, |
| < 652800000 0x401c0422 0x00002020 0x1 5 >, |
| < 748800000 0x401c0527 0x00002020 0x1 6 >, |
| < 825600000 0x401c062b 0x00002222 0x1 7 >, |
| < 902400000 0x4024072f 0x00002626 0x1 8 >, |
| < 979200000 0x40240833 0x00002929 0x1 9 >, |
| < 1056000000 0x402c0937 0x00002c2c 0x1 10 >, |
| < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >, |
| < 1209600000 0x402c0b3f 0x00003232 0x2 12 >, |
| < 1286400000 0x40340c43 0x00003636 0x2 13 >, |
| < 1363200000 0x40340d47 0x00003939 0x2 14 >, |
| < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >, |
| < 1536000000 0x403c0f50 0x00004040 0x2 16 >, |
| < 1612800000 0x403c1054 0x00004343 0x2 17 >, |
| < 1689600000 0x40441158 0x00004646 0x2 18 >, |
| < 1766400000 0x4044125c 0x00004a4a 0x2 19 >, |
| < 1843200000 0x40441360 0x00004d4d 0x2 20 >, |
| < 1920000000 0x404c1464 0x00005050 0x2 21 >, |
| < 1996800000 0x404c1568 0x00005353 0x2 22 >, |
| < 2092800000 0x4054166d 0x00005757 0x2 23 >, |
| < 2169600000 0x40541771 0x00005a5a 0x2 24 >, |
| < 2246400000 0x40541875 0x00005e5e 0x2 25 >, |
| < 2323200000 0x40541979 0x00006161 0x2 26 >, |
| < 2400000000 0x40541a7d 0x00006464 0x2 27 >, |
| < 2476800000 0x40541b81 0x00006767 0x2 28 >, |
| < 2553600000 0x40541c85 0x00006a6a 0x2 29 >, |
| < 2649600000 0x40541d8a 0x00006e6e 0x2 30 >, |
| < 2745600000 0x40511e8f 0x00007272 0x2 31 >; |
| |
| qcom,l3-memacc-level-vc-bin0 = <8 13>; |
| qcom,l3-memacc-level-vc-bin1 = <8 13>; |
| |
| qcom,pwrcl-memacc-level-vc-bin0 = <12 16>; |
| qcom,pwrcl-memacc-level-vc-bin1 = <12 16>; |
| |
| qcom,perfcl-memacc-level-vc-bin0 = <14 22>; |
| qcom,perfcl-memacc-level-vc-bin1 = <14 22>; |
| }; |
| |
| &pcie1 { |
| qcom,phy-sequence = <0x1804 0x03 0x0 |
| 0x00dc 0x27 0x0 |
| 0x0014 0x01 0x0 |
| 0x0020 0x31 0x0 |
| 0x0024 0x01 0x0 |
| 0x0028 0xde 0x0 |
| 0x002c 0x07 0x0 |
| 0x0034 0x4c 0x0 |
| 0x0038 0x06 0x0 |
| 0x0054 0x18 0x0 |
| 0x0058 0xb0 0x0 |
| 0x006c 0x8c 0x0 |
| 0x0070 0x20 0x0 |
| 0x0078 0x14 0x0 |
| 0x007c 0x34 0x0 |
| 0x00b4 0x06 0x0 |
| 0x00b8 0x06 0x0 |
| 0x00c0 0x16 0x0 |
| 0x00c4 0x16 0x0 |
| 0x00cc 0x36 0x0 |
| 0x00d0 0x36 0x0 |
| 0x00f0 0x05 0x0 |
| 0x00f8 0x42 0x0 |
| 0x0100 0x82 0x0 |
| 0x0108 0x68 0x0 |
| 0x011c 0x55 0x0 |
| 0x0120 0x55 0x0 |
| 0x0124 0x03 0x0 |
| 0x0128 0xab 0x0 |
| 0x012c 0xaa 0x0 |
| 0x0130 0x02 0x0 |
| 0x0150 0x3f 0x0 |
| 0x0158 0x3f 0x0 |
| 0x0178 0x10 0x0 |
| 0x01cc 0x04 0x0 |
| 0x01d0 0x30 0x0 |
| 0x01e0 0x04 0x0 |
| 0x01e8 0x73 0x0 |
| 0x01f0 0x1c 0x0 |
| 0x01fc 0x15 0x0 |
| 0x021c 0x04 0x0 |
| 0x0224 0x01 0x0 |
| 0x0228 0x22 0x0 |
| 0x022c 0x00 0x0 |
| 0x0098 0x05 0x0 |
| 0x080c 0x00 0x0 |
| 0x0818 0x0d 0x0 |
| 0x0860 0x01 0x0 |
| 0x0864 0x3a 0x0 |
| 0x087c 0x2f 0x0 |
| 0x08c0 0x09 0x0 |
| 0x08c4 0x09 0x0 |
| 0x08c8 0x1a 0x0 |
| 0x08d0 0x01 0x0 |
| 0x08d4 0x07 0x0 |
| 0x08d8 0x31 0x0 |
| 0x08dc 0x31 0x0 |
| 0x08e0 0x03 0x0 |
| 0x08fc 0x02 0x0 |
| 0x0900 0x01 0x0 |
| 0x0908 0x12 0x0 |
| 0x0914 0x25 0x0 |
| 0x0918 0x00 0x0 |
| 0x091c 0x05 0x0 |
| 0x0920 0x01 0x0 |
| 0x0924 0x26 0x0 |
| 0x0928 0x12 0x0 |
| 0x0930 0x04 0x0 |
| 0x0934 0x04 0x0 |
| 0x0938 0x09 0x0 |
| 0x0954 0x15 0x0 |
| 0x0960 0x32 0x0 |
| 0x0968 0x7f 0x0 |
| 0x096c 0x07 0x0 |
| 0x0978 0x04 0x0 |
| 0x0980 0x70 0x0 |
| 0x0984 0x8b 0x0 |
| 0x0988 0x08 0x0 |
| 0x098c 0x09 0x0 |
| 0x0990 0x03 0x0 |
| 0x0994 0x04 0x0 |
| 0x0998 0x02 0x0 |
| 0x099c 0x0c 0x0 |
| 0x09a4 0x02 0x0 |
| 0x09c0 0x5c 0x0 |
| 0x09c4 0x3e 0x0 |
| 0x09c8 0x3f 0x0 |
| 0x0a30 0x01 0x0 |
| 0x0a34 0xa0 0x0 |
| 0x0a38 0x08 0x0 |
| 0x0aa4 0x01 0x0 |
| 0x0aac 0xc3 0x0 |
| 0x0ab0 0x00 0x0 |
| 0x0ab8 0x8c 0x0 |
| 0x0ac0 0x7f 0x0 |
| 0x0ac4 0x2a 0x0 |
| 0x0810 0x0c 0x0 |
| 0x0814 0x00 0x0 |
| 0x0acc 0x04 0x0 |
| 0x093c 0x20 0x0 |
| 0x100c 0x00 0x0 |
| 0x1018 0x0d 0x0 |
| 0x1060 0x01 0x0 |
| 0x1064 0x3a 0x0 |
| 0x107c 0x2f 0x0 |
| 0x10c0 0x09 0x0 |
| 0x10c4 0x09 0x0 |
| 0x10c8 0x1a 0x0 |
| 0x10d0 0x01 0x0 |
| 0x10d4 0x07 0x0 |
| 0x10d8 0x31 0x0 |
| 0x10dc 0x31 0x0 |
| 0x10e0 0x03 0x0 |
| 0x10fc 0x02 0x0 |
| 0x1100 0x01 0x0 |
| 0x1108 0x12 0x0 |
| 0x1114 0x25 0x0 |
| 0x1118 0x00 0x0 |
| 0x111c 0x05 0x0 |
| 0x1120 0x01 0x0 |
| 0x1124 0x26 0x0 |
| 0x1128 0x12 0x0 |
| 0x1130 0x04 0x0 |
| 0x1134 0x04 0x0 |
| 0x1138 0x09 0x0 |
| 0x1154 0x15 0x0 |
| 0x1160 0x32 0x0 |
| 0x1168 0x7f 0x0 |
| 0x116c 0x07 0x0 |
| 0x1178 0x04 0x0 |
| 0x1180 0x70 0x0 |
| 0x1184 0x8b 0x0 |
| 0x1188 0x08 0x0 |
| 0x118c 0x09 0x0 |
| 0x1190 0x03 0x0 |
| 0x1194 0x04 0x0 |
| 0x1198 0x02 0x0 |
| 0x119c 0x0c 0x0 |
| 0x11a4 0x02 0x0 |
| 0x11c0 0x5c 0x0 |
| 0x11c4 0x3e 0x0 |
| 0x11c8 0x3f 0x0 |
| 0x1230 0x01 0x0 |
| 0x1234 0xa0 0x0 |
| 0x1238 0x08 0x0 |
| 0x12a4 0x01 0x0 |
| 0x12ac 0xc3 0x0 |
| 0x12b0 0x00 0x0 |
| 0x12b8 0x8c 0x0 |
| 0x12c0 0x7f 0x0 |
| 0x12c4 0x2a 0x0 |
| 0x1010 0x0c 0x0 |
| 0x1014 0x0f 0x0 |
| 0x12cc 0x04 0x0 |
| 0x113c 0x20 0x0 |
| 0x195c 0x3f 0x0 |
| 0x1974 0x50 0x0 |
| 0x196c 0x9f 0x0 |
| 0x182c 0x19 0x0 |
| 0x1840 0x07 0x0 |
| 0x1854 0x17 0x0 |
| 0x1868 0x09 0x0 |
| 0x1800 0x00 0x0 |
| 0x0aa8 0x01 0x0 |
| 0x12a8 0x01 0x0 |
| 0x1808 0x01 0x0>; |
| }; |
| |
| &devfreq_l3lat_0 { |
| qcom,core-dev-table = |
| < 300000 300000000 >, |
| < 480000 403200000 >, |
| < 652800 480000000 >, |
| < 748800 576000000 >, |
| < 902400 652800000 >, |
| < 979200 748800000 >, |
| < 1132800 844800000 >, |
| < 1228800 940800000 >, |
| < 1324800 1036800000 >, |
| < 1420800 1132800000 >, |
| < 1516800 1209600000 >, |
| < 1612800 1401600000 >, |
| < 1689600 1497600000 >, |
| < 1766400 1593600000 >; |
| }; |
| |
| &devfreq_l3lat_4 { |
| qcom,core-dev-table = |
| < 300000 300000000 >, |
| < 825600 576000000 >, |
| < 1132800 748800000 >, |
| < 1363200 940800000 >, |
| < 1689600 1209600000 >, |
| < 1996800 1401600000 >, |
| < 2400000 1593600000 >; |
| }; |
| |
| &bwmon { |
| qcom,count-unit = <0x10000>; |
| }; |
| |
| &cpubw { |
| qcom,bw-tbl = |
| < MHZ_TO_MBPS(150, 16) >, /* 2288 MB/s */ |
| < MHZ_TO_MBPS(300, 16) >, /* 4577 MB/s */ |
| < MHZ_TO_MBPS(426, 16) >, /* 6500 MB/s */ |
| < MHZ_TO_MBPS(533, 16) >, /* 8132 MB/s */ |
| < MHZ_TO_MBPS(600, 16) >, /* 9155 MB/s */ |
| < MHZ_TO_MBPS(806, 16) >, /* 12298 MB/s */ |
| < MHZ_TO_MBPS(933, 16) >; /* 14236 MB/s */ |
| }; |
| |
| &devfreq_cpufreq { |
| mincpubw-cpufreq { |
| cpu-to-dev-map-4 = |
| < 1881600 MHZ_TO_MBPS(200, 4) >, |
| < 2400000 MHZ_TO_MBPS(681, 4) >; |
| }; |
| }; |
| |
| &clock_gcc { |
| compatible = "qcom,gcc-sdm845-v2", "syscon"; |
| }; |
| |
| &clock_camcc { |
| compatible = "qcom,cam_cc-sdm845-v2", "syscon"; |
| qcom,cam_cc_csi3phytimer_clk_src-opp-handle = <&cam_csiphy3>; |
| }; |
| |
| &clock_dispcc { |
| compatible = "qcom,dispcc-sdm845-v2", "syscon"; |
| }; |
| |
| &clock_gpucc { |
| compatible = "qcom,gpucc-sdm845-v2", "syscon"; |
| }; |
| |
| &clock_gfx { |
| compatible = "qcom,gfxcc-sdm845-v2"; |
| }; |
| |
| &clock_videocc { |
| compatible = "qcom,video_cc-sdm845-v2", "syscon"; |
| }; |
| |
| &msm_vidc { |
| qcom,allowed-clock-rates = <100000000 200000000 330000000 |
| 404000000 444000000 533000000>; |
| }; |
| |
| &refgen { |
| status = "ok"; |
| regulator-always-on; |
| }; |
| |
| &spss_utils { |
| qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */ |
| qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */ |
| qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */ |
| }; |
| |
| &mdss_mdp { |
| clock-max-rate = <0 0 0 0 430000000 19200000 0>; |
| qcom,sde-min-core-ib-kbps = <4800000>; |
| }; |
| |
| &energy_costs { |
| CPU_COST_0: core-cost0 { |
| busy-cost-data = < |
| 300000 12 |
| 403200 17 |
| 480000 21 |
| 576000 27 |
| 652800 31 |
| 748800 37 |
| 825600 42 |
| 902400 47 |
| 979200 52 |
| 1056000 57 |
| 1132800 62 |
| 1228800 70 |
| 1324800 78 |
| 1420800 89 |
| 1516800 103 |
| 1612800 122 |
| 1689600 141 |
| 1766400 160 |
| >; |
| idle-cost-data = < |
| 22 18 14 12 |
| >; |
| }; |
| CPU_COST_1: core-cost1 { |
| busy-cost-data = < |
| 300000 189 |
| 403200 523 |
| 480000 763 |
| 576000 1052 |
| 652800 1273 |
| 748800 1536 |
| 825600 1736 |
| 902400 1926 |
| 979200 2108 |
| 1056000 2284 |
| 1132800 2456 |
| 1209600 2628 |
| 1286400 2804 |
| 1363200 2992 |
| 1459200 3255 |
| 1536000 3499 |
| 1612800 3786 |
| 1689600 4128 |
| 1766400 4535 |
| 1843200 5019 |
| 1920000 5583 |
| 1996800 6226 |
| 2092800 7120 |
| 2169600 7876 |
| 2246400 8628 |
| 2323200 9344 |
| 2400000 10030 |
| 2476800 10806 |
| 2553600 12045 |
| 2649600 15686 |
| 2745600 25586 |
| >; |
| idle-cost-data = < |
| 100 80 60 40 |
| >; |
| }; |
| CLUSTER_COST_0: cluster-cost0 { |
| busy-cost-data = < |
| 300000 3 |
| 403200 4 |
| 480000 4 |
| 576000 4 |
| 652800 5 |
| 748800 5 |
| 825600 6 |
| 902400 7 |
| 979200 7 |
| 1056000 8 |
| 1132800 9 |
| 1228800 9 |
| 1324800 10 |
| 1420800 11 |
| 1516800 12 |
| 1612800 13 |
| 1689600 15 |
| 1766400 17 |
| >; |
| idle-cost-data = < |
| 4 3 2 1 |
| >; |
| }; |
| CLUSTER_COST_1: cluster-cost1 { |
| busy-cost-data = < |
| 300000 24 |
| 403200 24 |
| 480000 25 |
| 576000 25 |
| 652800 26 |
| 748800 27 |
| 825600 28 |
| 902400 29 |
| 979200 30 |
| 1056000 32 |
| 1132800 34 |
| 1209600 37 |
| 1286400 40 |
| 1363200 45 |
| 1459200 50 |
| 1536000 57 |
| 1612800 64 |
| 1689600 74 |
| 1766400 84 |
| 1843200 96 |
| 1920000 106 |
| 1996800 113 |
| 2092800 120 |
| 2169600 125 |
| 2246400 127 |
| 2323200 130 |
| 2400000 135 |
| 2476800 140 |
| 2553600 145 |
| 2649600 150 |
| 2745600 155 |
| >; |
| idle-cost-data = < |
| 4 3 2 1 |
| >; |
| }; |
| }; |
| |
| &gpu_gx_gdsc { |
| domain-addr = <&gpu_gx_domain_addr>; |
| sw-reset = <&gpu_gx_sw_reset>; |
| qcom,reset-aon-logic; |
| }; |
| |
| /* GPU overrides */ |
| &msm_gpu { |
| /* Updated chip ID */ |
| qcom,chipid = <0x06030001>; |
| qcom,initial-pwrlevel = <5>; |
| |
| qcom,gpu-pwrlevels { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compatible = "qcom,gpu-pwrlevels"; |
| |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <675000000>; |
| qcom,bus-freq = <12>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <12>; |
| }; |
| |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <596000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <11>; |
| }; |
| |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <520000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <414000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <342000000>; |
| qcom,bus-freq = <6>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <7>; |
| }; |
| |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <257000000>; |
| qcom,bus-freq = <4>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <5>; |
| }; |
| |
| qcom,gpu-pwrlevel@6 { |
| reg = <6>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| }; |
| |
| &gmu { |
| qcom,gmu-pwrlevels { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compatible = "qcom,gmu-pwrlevels"; |
| |
| qcom,gmu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gmu-freq = <500000000>; |
| }; |
| |
| qcom,gmu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gmu-freq = <200000000>; |
| }; |
| |
| qcom,gmu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gmu-freq = <0>; |
| }; |
| }; |
| }; |