| /* |
| * Copyright 2012 Freescale Semiconductor, Inc. |
| * Copyright 2011 Linaro Ltd. |
| * |
| * The code contained herein is licensed under the GNU General Public |
| * License. You may obtain a copy of the GNU General Public License |
| * Version 2 or later at the following locations: |
| * |
| * http://www.opensource.org/licenses/gpl-license.html |
| * http://www.gnu.org/copyleft/gpl.html |
| */ |
| |
| / { |
| memory { |
| reg = <0x10000000 0x80000000>; |
| }; |
| }; |
| |
| &ecspi1 { |
| fsl,spi-num-chipselects = <1>; |
| cs-gpios = <&gpio3 19 0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>; |
| status = "disabled"; /* pin conflict with WEIM NOR */ |
| |
| flash: m25p80@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "st,m25p32"; |
| spi-max-frequency = <20000000>; |
| reg = <0>; |
| }; |
| }; |
| |
| &fec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet_2>; |
| phy-mode = "rgmii"; |
| status = "okay"; |
| }; |
| |
| &gpmi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpmi_nand_1>; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| hog { |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 |
| MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 |
| >; |
| }; |
| }; |
| |
| ecspi1 { |
| pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 |
| >; |
| }; |
| }; |
| }; |
| |
| &uart4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart4_1>; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc3_1>; |
| cd-gpios = <&gpio6 15 0>; |
| wp-gpios = <&gpio1 13 0>; |
| status = "okay"; |
| }; |
| |
| &weim { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| ranges = <0 0 0x08000000 0x08000000>; |
| status = "disabled"; /* pin conflict with SPI NOR */ |
| |
| nor@0,0 { |
| compatible = "cfi-flash"; |
| reg = <0 0 0x02000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| bank-width = <2>; |
| fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 |
| 0x0000c000 0x1404a38e 0x00000000>; |
| }; |
| }; |