| /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,gcc-msm8996.h> |
| #include <dt-bindings/clock/qcom,mmcc-msm8996.h> |
| |
| / { |
| model = "Qualcomm Technologies, Inc. MSM8996"; |
| |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| chosen { }; |
| |
| memory { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the reg */ |
| reg = <0 0 0 0>; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_0>; |
| L2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| }; |
| }; |
| |
| CPU1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| CPU2: cpu@100 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_1>; |
| L2_1: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| }; |
| }; |
| |
| CPU3: cpu@101 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo"; |
| reg = <0x0 0x101>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_1>; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&CPU2>; |
| }; |
| |
| core1 { |
| cpu = <&CPU3>; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| clocks { |
| xo_board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <19200000>; |
| clock-output-names = "xo_board"; |
| }; |
| |
| sleep_clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32764>; |
| clock-output-names = "sleep_clk"; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| soc: soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| |
| intc: interrupt-controller@9bc0000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x40000>; |
| reg = <0x09bc0000 0x10000>, |
| <0x09c00000 0x100000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| gcc: clock-controller@300000 { |
| compatible = "qcom,gcc-msm8996"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| reg = <0x300000 0x90000>; |
| }; |
| |
| blsp1_spi0: spi@07575000 { |
| compatible = "qcom,spi-qup-v2.2.1"; |
| reg = <0x07575000 0x600>; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp1_spi0_default>; |
| pinctrl-1 = <&blsp1_spi0_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp2_i2c0: i2c@075b5000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x075b5000 0x1000>; |
| interrupts = <GIC_SPI 101 0>; |
| clocks = <&gcc GCC_BLSP2_AHB_CLK>, |
| <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; |
| clock-names = "iface", "core"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_i2c0_default>; |
| pinctrl-1 = <&blsp2_i2c0_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp2_uart1: serial@75b0000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x75b0000 0x1000>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| blsp2_i2c1: i2c@075b6000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x075b6000 0x1000>; |
| interrupts = <GIC_SPI 102 0>; |
| clocks = <&gcc GCC_BLSP2_AHB_CLK>, |
| <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; |
| clock-names = "iface", "core"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_i2c1_default>; |
| pinctrl-1 = <&blsp2_i2c1_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp2_uart2: serial@75b1000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x075b1000 0x1000>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| blsp1_i2c2: i2c@07577000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x07577000 0x1000>; |
| interrupts = <GIC_SPI 97 0>; |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>, |
| <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; |
| clock-names = "iface", "core"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp1_i2c2_default>; |
| pinctrl-1 = <&blsp1_i2c2_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp2_spi5: spi@075ba000{ |
| compatible = "qcom,spi-qup-v2.2.1"; |
| reg = <0x075ba000 0x600>; |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_spi5_default>; |
| pinctrl-1 = <&blsp2_spi5_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| sdhc2: sdhci@74a4900 { |
| status = "disabled"; |
| compatible = "qcom,sdhci-msm-v4"; |
| reg = <0x74a4900 0x314>, <0x74a4000 0x800>; |
| reg-names = "hc_mem", "core_mem"; |
| |
| interrupts = <0 125 0>, <0 221 0>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| clock-names = "iface", "core"; |
| clocks = <&gcc GCC_SDCC2_AHB_CLK>, |
| <&gcc GCC_SDCC2_APPS_CLK>; |
| bus-width = <4>; |
| }; |
| |
| msmgpio: pinctrl@1010000 { |
| compatible = "qcom,msm8996-pinctrl"; |
| reg = <0x01010000 0x300000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| timer@09840000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x09840000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@9850000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x09850000 0x1000>, |
| <0x09860000 0x1000>; |
| }; |
| |
| frame@9870000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x09870000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@9880000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x09880000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@9890000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x09890000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@98a0000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x098a0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@98b0000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x098b0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@98c0000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x098c0000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| spmi_bus: qcom,spmi@400f000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0x400f000 0x1000>, |
| <0x4400000 0x800000>, |
| <0x4c00000 0x800000>, |
| <0x5800000 0x200000>, |
| <0x400a000 0x002100>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| }; |
| |
| mmcc: clock-controller@8c0000 { |
| compatible = "qcom,mmcc-msm8996"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| reg = <0x8c0000 0x40000>; |
| assigned-clocks = <&mmcc MMPLL9_PLL>, |
| <&mmcc MMPLL1_PLL>, |
| <&mmcc MMPLL3_PLL>, |
| <&mmcc MMPLL4_PLL>, |
| <&mmcc MMPLL5_PLL>; |
| assigned-clock-rates = <624000000>, |
| <810000000>, |
| <980000000>, |
| <960000000>, |
| <825000000>; |
| }; |
| }; |
| }; |
| #include "msm8996-pins.dtsi" |