| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| */ |
| |
| #define pr_fmt(fmt) "dsi-hw:" fmt |
| |
| #include "dsi_ctrl_hw.h" |
| #include "dsi_ctrl_reg.h" |
| #include "dsi_hw.h" |
| #include "dsi_catalog.h" |
| |
| /* Equivalent to register DISP_CC_MISC_CMD */ |
| #define DISP_CC_CLAMP_REG_OFF 0x00 |
| |
| /* register to configure DMA scheduling */ |
| #define DSI_DMA_SCHEDULE_CTRL 0x100 |
| |
| /** |
| * dsi_ctrl_hw_22_phy_reset_config() - to configure clamp control during ulps |
| * @ctrl: Pointer to the controller host hardware. |
| * @enable: boolean to specify enable/disable. |
| */ |
| void dsi_ctrl_hw_22_phy_reset_config(struct dsi_ctrl_hw *ctrl, |
| bool enable) |
| { |
| u32 reg = 0; |
| |
| reg = DSI_DISP_CC_R32(ctrl, DISP_CC_CLAMP_REG_OFF); |
| |
| /* Mask/unmask disable PHY reset bit */ |
| if (enable) |
| reg &= ~BIT(ctrl->index); |
| else |
| reg |= BIT(ctrl->index); |
| DSI_DISP_CC_W32(ctrl, DISP_CC_CLAMP_REG_OFF, reg); |
| } |
| |
| /** |
| * dsi_ctrl_hw_22_schedule_dma_cmd() - to schedule DMA command transfer |
| * @ctrl: Pointer to the controller host hardware. |
| * @line_no: Line number at which command needs to be sent. |
| */ |
| void dsi_ctrl_hw_22_schedule_dma_cmd(struct dsi_ctrl_hw *ctrl, int line_no) |
| { |
| u32 reg = 0; |
| |
| reg = DSI_R32(ctrl, DSI_DMA_SCHEDULE_CTRL); |
| reg |= BIT(28); |
| reg |= (line_no & 0xffff); |
| |
| DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL, reg); |
| } |
| |
| /* |
| * dsi_ctrl_hw_22_get_cont_splash_status() - to verify whether continuous |
| * splash is enabled or not |
| * @ctrl: Pointer to the controller host hardware. |
| * |
| * Return: Return Continuous splash status |
| */ |
| bool dsi_ctrl_hw_22_get_cont_splash_status(struct dsi_ctrl_hw *ctrl) |
| { |
| u32 reg = 0; |
| |
| /** |
| * DSI scratch register 1 is used to notify whether continuous |
| * splash is enabled or not by bootloader |
| */ |
| reg = DSI_R32(ctrl, DSI_SCRATCH_REGISTER_1); |
| return reg == 0x1 ? true : false; |
| } |