blob: aa90bc413cb86f044aaa68dc7bcdb019fcff9ece [file] [log] [blame]
Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding
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Required properties :
- compatible : shall contain only one of the following:
"qcom,gpucc-sdm845",
"qcom,gpucc-sdm845-v2",
"qcom,gfxcc-sdm845",
"qcom,gfxcc-sdm845-v2"
"qcom,gpucc-sdm670",
"qcom,gfxcc-sdm670"
- reg : shall contain base register offset and size.
- #clock-cells : shall contain 1.
- #reset-cells : shall contain 1.
- #vdd_<rail>-supply : The logic rail supply.
Optional properties :
- #power-domain-cells : shall contain 1.
Example:
clock_gfx: qcom,gfxcc@5090000 {
compatible = "qcom,gfxcc-sdm845";
reg = <0x5090000 0x9000>;
vdd_gfx-supply = <&pm8005_s1_level>;
vdd_mx-supply = <&pm8998_s6_level>;
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_gpucc: qcom,gpucc@5090000 {
compatible = "qcom,gpucc-sdm845";
reg = <0x5090000 0x9000>;
vdd_cx-supply = <&pm8998_s9_level>;
#clock-cells = <1>;
#reset-cells = <1>;
};