Merge "ARM: dts: msm: add histogram feature DT entry for SDM670"
diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt
index 765b5e4..327a7d4 100644
--- a/Documentation/devicetree/bindings/arm/msm/msm.txt
+++ b/Documentation/devicetree/bindings/arm/msm/msm.txt
@@ -166,6 +166,8 @@
- VR device:
compatible = "qcom,qvr"
+- HDK device:
+ compatible = "qcom,hdk"
Boards (SoC type + board variant):
@@ -279,9 +281,11 @@
compatible = "qcom,sda845-cdp"
compatible = "qcom,sda845-mtp"
compatible = "qcom,sda845-qrd"
+compatible = "qcom,sda845-hdk"
compatible = "qcom,sdm670-rumi"
compatible = "qcom,sdm670-cdp"
compatible = "qcom,sdm670-mtp"
+compatible = "qcom,sdm670-qrd"
compatible = "qcom,qcs605-cdp"
compatible = "qcom,qcs605-mtp"
compatible = "qcom,sda670-cdp"
@@ -321,3 +325,5 @@
compatible = "qcom,apq8009-cdp"
compatible = "qcom,apq8009-mtp"
compatible = "qcom,sdxpoorwills-rumi"
+compatible = "qcom,sdxpoorwills-mtp"
+compatible = "qcom,sdxpoorwills-cdp"
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt
index cc4c3cc..ea749a6 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt
@@ -14,392 +14,21 @@
- reg
Usage: required
Value type: <prop-encoded-array>
- Definition: Addresses and sizes for the memory of the OSM controller,
- cluster PLL management, and APCS common register regions.
- Optionally, the address of the efuse registers used to
- determine the pwrcl or perfcl speed-bins and/or the ACD
- register space to initialize prior to enabling OSM.
+ Definition: Addresses and sizes for the memory of the OSM controller.
- reg-names
Usage: required
Value type: <stringlist>
Definition: Address names. Must be "osm_l3_base", "osm_pwrcl_base",
- "osm_perfcl_base", "l3_pll", "pwrcl_pll", "perfcl_pll",
- "l3_sequencer", "pwrcl_sequencer", or "perfcl_sequencer".
- Optionally, "l3_efuse", "pwrcl_efuse", "perfcl_efuse",
- "pwrcl_acd", "perfcl_acd", "l3_acd".
+ "osm_perfcl_base".
Must be specified in the same order as the corresponding
addresses are specified in the reg property.
-- vdd-l3-supply
- Usage: required
+- l3-devs
+ Usage: optional
Value type: <phandle>
- Definition: phandle of the underlying regulator device that manages
- the voltage supply of the L3 cluster.
-
-- vdd-pwrcl-supply
- Usage: required
- Value type: <phandle>
- Definition: phandle of the underlying regulator device that manages
- the voltage supply of the Power cluster.
-
-- vdd-perfcl-supply
- Usage: required
- Value type: <phandle>
- Definition: phandle of the underlying regulator device that manages
- the voltage supply of the Performance cluster.
-
-- interrupts
- Usage: required
- Value type: <prop-encoded-array>
- Definition: OSM interrupt specifier.
-
-- interrupt-names
- Usage: required
- Value type: <stringlist>
- Definition: Interrupt names. this list must match up 1-to-1 with the
- interrupts specified in the 'interrupts' property.
- "pwrcl-irq" and "perfcl-irq" must be specified.
-
-- qcom,l3-speedbinX-v0
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the frequency in Hertz, frequency,
- PLL override data, ACC level, and virtual corner used
- by the OSM hardware for each supported DCVS setpoint
- of the L3 cluster.
-
-- qcom,pwrcl-speedbinX-v0
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the frequency in Hertz, frequency,
- PLL override data, ACC level, and virtual corner used
- by the OSM hardware for each supported DCVS setpoint
- of the Power cluster.
-
-- qcom,perfcl-speedbinX-v0
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the frequency in Hertz, frequency,
- PLL override data, ACC level and virtual corner used
- by the OSM hardware for each supported DCVS setpoint
- of the Performance cluster.
-
-- qcom,osm-no-tz
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates that there is no programming
- of the OSM hardware performed by the secure world.
-
-- qcom,osm-pll-setup
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates that the PLL setup sequence
- must be executed for each clock domain managed by the OSM
- controller.
-
-- qcom,up-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the DCVS up timer value in nanoseconds
- for each of the three clock domains managed by the OSM
- controller.
-
-- qcom,down-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the DCVS down timer value in nanoseconds
- for each of the three clock domains managed by the OSM
- controller.
-
-- qcom,pc-override-index
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the OSM performance index to be used
- when each cluster enters certain low power modes.
-
-- qcom,set-ret-inactive
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if domains in retention must
- be treated as inactive.
-
-- qcom,enable-llm-freq-vote
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if Limits hardware frequency
- votes must be honored by OSM.
-
-- qcom,llm-freq-up-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the LLM frequency up timer value in
- nanoseconds for each of the three clock domains managed by
- the OSM controller.
-
-- qcom,llm-freq-down-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the LLM frequency down timer value in
- nanoseconds for each of the three clock domains managed by
- the OSM controller.
-
-- qcom,enable-llm-volt-vote
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if Limits hardware voltage
- votes must be honored by OSM.
-
-- qcom,llm-volt-up-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the LLM voltage up timer value in
- nanoseconds for each of the three clock domains managed by
- the OSM controller.
-
-- qcom,llm-volt-down-timer
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: Array which defines the LLM voltage down timer value in
- nanoseconds for each of the three clock domains managed by
- the OSM controller.
-
-- qcom,cc-reads
- Usage: optional
- Value type: <integer>
- Definition: Defines the number of times the cycle counters must be
- read to determine the performance level of each clock
- domain.
-
-- qcom,l-val-base
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the register addresses of the L_VAL
- control register for each of the three clock domains
- managed by the OSM controller.
-
-- qcom,apcs-pll-user-ctl
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the register addresses of the PLL
- user control register for each of the three clock domains
- managed by the OSM controller.
-
-- qcom,perfcl-apcs-apm-threshold-voltage
- Usage: required
- Value type: <u32>
- Definition: Specifies the APM threshold voltage in microvolts. If the
- VDD_APCC supply voltage is above or at this level, then the
- APM is switched to use VDD_APCC. If VDD_APCC is below
- this level, then the APM is switched to use VDD_MX.
-
-- qcom,apm-mode-ctl
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the register addresses of the APM
- control register for each of the two clusters managed
- by the OSM controller.
-
-- qcom,apm-status-ctrl
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the register addresses of the APM
- controller status register for each of the three clock
- domains managed by the OSM controller.
-
-- qcom,perfcl-isense-addr
- Usage: required
- Value type: <u32>
- Definition: Contains the ISENSE register address.
-
-- qcom,l3-mem-acc-addr
- Usage: required if qcom,osm-no-tz is specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the addresses of the mem-acc
- configuration registers for the L3 cluster.
- The array must contain exactly three elements.
-
-- qcom,pwrcl-mem-acc-addr
- Usage: required if qcom,osm-no-tz is specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the addresses of the mem-acc
- configuration registers for the Power cluster.
- The array must contain exactly three elements.
-
-- qcom,perfcl-mem-acc-addr
- Usage: required if qcom,osm-no-tz is specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the addresses of the mem-acc
- configuration registers for the Performance cluster.
- The array must contain exactly three elements.
-
-- qcom,perfcl-apcs-mem-acc-threshold-voltage
- Usage: optional
- Value type: <u32>
- Definition: Specifies the highest MEM ACC threshold voltage in
- microvolts for the Performance cluster. This voltage is
- used to determine which MEM ACC setting is used for the
- highest frequencies. If specified, the voltage must match
- the MEM ACC threshold voltage specified for the
- corresponding CPRh device.
-
-- qcom,l3-memacc-level-vc-binX
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the NOM and TURBO VCs for the L3 clock
- on that BIN part.
- The array must contain exactly two elements.
-
-- qcom,pwrcl-memacc-level-vc-binX
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the NOM and TURBO VCs for the Power
- cluster clock on that BIN part.
- The array must contain exactly two elements.
-
-- qcom,perfcl-memacc-level-vc-binX
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the NOM and TURBO VCs for the
- Performance cluster clock on that BIN part.
- The array must contain exactly two elements.
-
-- qcom,apcs-cbc-addr
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the addresses of the APCS_CBC_ADDR
- registers for all three clock domains.
-
-- qcom,apcs-ramp-ctl-addr
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Array which defines the addresses of the APCS_RAMP_CTL_ADDR
- registers for all three clock domains.
-
-- qcom,red-fsm-en
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the reduction FSM
- should be enabled.
-
-- qcom,boost-fsm-en
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the boost FSM should
- be enabled.
-
-- qcom,safe-fsm-en
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the safe FSM should
- be enabled.
-
-- qcom,ps-fsm-en
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the PS FSM should be
- enabled.
-
-- qcom,droop-fsm-en
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the droop FSM should
- be enabled.
-
-- qcom,set-c3-active
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the cores in C3 are to
- be treated as active for core count calculations.
-
-- qcom,set-c2-active
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if the cores in C2 are to
- be treated as active for core count calculations.
-
-- qcom,disable-cc-dvcs
- Usage: optional
- Value type: <empty>
- Definition: Boolean flag which indicates if core count based DCVS is
- to be disabled.
-
-- qcom,apcs-pll-min-freq
- Usage: required
- Value type: <u32>
- Definition: Contains the addresses of the RAILx_CLKDOMy_PLL_MIN_FREQ
- registers for the three clock domains.
-
-- qcom,acdtd-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the values to program to the ACD
- Tunable-Length Delay register for the L3, power and
- performance clusters.
-
-- qcom,acdcr-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD control register
- for the L3, power and performance clusters.
-
-- qcom,acdsscr-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD Soft Start Control
- register for the L3, power and performance clusters.
-
-- qcom,acdextint0-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the initial values for the ACD
- external interface configuration register for the L3, power
- and performance clusters.
-
-- qcom,acdextint1-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the final values for the ACD
- external interface configuration register for the L3, power
- and performance clusters.
-
-- qcom,acdautoxfer-val
- Usage: required if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD auto transfer
- control register for the L3, power and performance clusters.
-
-- qcom,acdavg-init
- Usage: optional if pwrcl_acd, perfcl_acd or l3_acd registers are
- specified
- Value type: <prop-encoded-array>
- Definition: Array which defines if the AVG feature for ACD should be
- initialized for the L3, power and performance clusters.
- Valid values are 0 or 1.
-
-- qcom,acdavgcfg0-val
- Usage: required if qcom,acdavg-init is true for an ACD clock domain
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD AVG CFG0
- registers for the L3, power and performance clusters.
-
-- qcom,acdavgcfg1-val
- Usage: required if qcom,acdavg-init is true for an ACD clock domain
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD AVG CFG1
- registers for the L3, power and performance clusters.
-
-- qcom,acdavgcfg2-val
- Usage: required if qcom,acdavg-init is true for an ACD clock domain
- Value type: <prop-encoded-array>
- Definition: Array which defines the values for the ACD AVG CFG2
- registers for the L3, power and performance clusters.
+ Definition: List of phandles to devices that the OPP tables with the L3
+ frequency and voltage mappings are loaded for.
- clock-names
Usage: required
@@ -416,156 +45,12 @@
compatible = "qcom,clk-cpu-osm";
reg = <0x17d41000 0x1400>,
<0x17d43000 0x1400>,
- <0x17d45800 0x1400>,
- <0x178d0000 0x1000>,
- <0x178c0000 0x1000>,
- <0x178b0000 0x1000>,
- <0x17d42400 0x0c00>,
- <0x17d44400 0x0c00>,
- <0x17d46c00 0x0c00>,
- <0x17930000 0x10000>,
- <0x17920000 0x10000>,
- <0x17910000 0x10000>;
- reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base",
- "l3_pll", "pwrcl_pll", "perfcl_pll",
- "l3_sequencer", "pwrcl_sequencer",
- "perfcl_sequencer", "l3_acd", "pwrcl_acd",
- "perfcl_acd";
+ <0x17d45800 0x1400>;
+ reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
- /* ACD configurations for L3, Silver, and Gold clusters */
- qcom,acdtd-val = <0x0000b411 0x0000b411 0x0000b411>;
- qcom,acdcr-val = <0x002c5ffd 0x002c5ffd 0x002c5ffd>;
- qcom,acdsscr-val = <0x00000901 0x00000901 0x00000901>;
- qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8 0x2cf9ae8>;
- qcom,acdextint1-val = <0x2cf9afe 0x2cf9afe 0x2cf9afe>;
- qcom,acdautoxfer-val = <0x00000015 0x00000015 0x00000015>;
- qcom,acdavgcfg2-val = <0x0 0x56a38822 0x56a38822>;
- qcom,acdavgcfg1-val = <0x0 0x27104e20 0x27104e20>;
- qcom,acdavgcfg0-val = <0x0 0xa08007a1 0xa08007a1>;
- qcom,acdavg-init = <0 1 1>;
-
- vdd-l3-supply = <&apc0_l3_vreg>;
- vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
- vdd-perfcl-supply = <&apc1_perfcl_vreg>;
-
- qcom,l3-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x501c0422 0x00002020 0x1 5 >,
- < 729600000 0x501c0526 0x00002020 0x1 6 >,
- < 806400000 0x501c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072b 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x2 9 >;
-
- qcom,pwrcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x501c0422 0x00002020 0x1 5 >,
- < 748800000 0x501c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003333 0x1 12 >,
- < 1286400000 0x40340c43 0x00003636 0x1 13 >,
- < 1363200000 0x40340d47 0x00003939 0x1 14 >,
- < 1440000000 0x403c0e4b 0x00003c3c 0x1 15 >,
- < 1516800000 0x403c0f4f 0x00004040 0x2 16 >,
- < 1593600000 0x403c1053 0x00004343 0x2 17 >;
-
- qcom,perfcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x501c0422 0x00002020 0x1 5 >,
- < 729600000 0x501c0526 0x00002020 0x1 6 >,
- < 806400000 0x501c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072b 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
- < 1190400000 0x402c0b3e 0x00003232 0x1 12 >,
- < 1267200000 0x40340c42 0x00003535 0x1 13 >,
- < 1344000000 0x40340d46 0x00003838 0x1 14 >,
- < 1420800000 0x40340e4a 0x00003b3b 0x1 15 >,
- < 1497600000 0x403c0f4e 0x00003e3e 0x1 16 >,
- < 1574400000 0x403c1052 0x00004242 0x2 17 >,
- < 1651200000 0x403c1156 0x00004545 0x2 18 >,
- < 1728000000 0x4044125a 0x00004848 0x2 19 >,
- < 1804800000 0x4044135e 0x00004b4b 0x2 20 >,
- < 1881600000 0x404c1462 0x00004e4e 0x2 21 >,
- < 1958400000 0x404c1566 0x00005252 0x3 22 >;
-
- qcom,l3-memacc-level-vc-bin0 = <7 63>;
- qcom,l3-memacc-level-vc-bin1 = <7 9>;
- qcom,l3-memacc-level-vc-bin2 = <7 9>;
-
- qcom,pwrcl-memacc-level-vc-bin0 = <12 63>;
- qcom,pwrcl-memacc-level-vc-bin1 = <12 17>;
- qcom,pwrcl-memacc-level-vc-bin2 = <12 17>;
-
- qcom,perfcl-memacc-level-vc-bin0 = <12 18>;
- qcom,perfcl-memacc-level-vc-bin1 = <12 18>;
- qcom,perfcl-memacc-level-vc-bin2 = <12 18>;
-
- qcom,up-timer =
- <1000 1000 1000>;
- qcom,down-timer =
- <100000 100000 100000>;
- qcom,pc-override-index =
- <0 0 0>;
- qcom,set-ret-inactive;
- qcom,enable-llm-freq-vote;
- qcom,llm-freq-up-timer =
- <1000 1000 1000>;
- qcom,llm-freq-down-timer =
- <327675 327675 327675>;
- qcom,enable-llm-volt-vote;
- qcom,llm-volt-up-timer =
- <1000 1000 1000>;
- qcom,llm-volt-down-timer =
- <327675 327675 327675>;
- qcom,cc-reads = <10>;
- qcom,cc-delay = <5>;
- qcom,cc-factor = <100>;
- qcom,osm-clk-rate = <100000000>;
- qcom,xo-clk-rate = <19200000>;
-
- qcom,l-val-base =
- <0x178d0004 0x178c0004 0x178b0004>;
- qcom,apcs-pll-user-ctl =
- <0x178d000c 0x178c000c 0x178b000c>;
- qcom,apcs-pll-min-freq =
- <0x17d41094 0x17d43094 0x17d45894>;
- qcom,apm-mode-ctl =
- <0x0 0x0 0x17d20010>;
- qcom,apm-status-ctrl =
- <0x0 0x0 0x17d20000>;
- qcom,perfcl-isense-addr = <0x17871480>;
- qcom,l3-mem-acc-addr = <0x17990170 0x17990170 0x17990170>;
- qcom,pwrcl-mem-acc-addr = <0x17990160 0x17990164 0x17990164>;
- qcom,perfcl-mem-acc-addr = <0x17990168 0x1799016c 0x1799016c>;
- qcom,cfg-gfmux-addr =<0x178d0084 0x178c0084 0x178b0084>;
- qcom,apcs-cbc-addr = <0x178d008c 0x178c008c 0x178b008c>;
- qcom,apcs-ramp-ctl-addr = <0x17840904 0x17840904 0x17830904>;
-
- qcom,perfcl-apcs-apm-threshold-voltage = <800000>;
- qcom,perfcl-apcs-mem-acc-threshold-voltage = <852000>;
- qcom,boost-fsm-en;
- qcom,safe-fsm-en;
- qcom,ps-fsm-en;
- qcom,droop-fsm-en;
- qcom,osm-no-tz;
- qcom,osm-pll-setup;
+ l3-devs = <&phandle0 &phandle1 &phandle2>;
clock-names = "xo_ao";
clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
#clock-cells = <1>;
- #reset-cells = <1>;
};
diff --git a/Documentation/devicetree/bindings/crypto/msm/ice.txt b/Documentation/devicetree/bindings/crypto/msm/ice.txt
index 2d0e580..fe8671f 100644
--- a/Documentation/devicetree/bindings/crypto/msm/ice.txt
+++ b/Documentation/devicetree/bindings/crypto/msm/ice.txt
@@ -5,16 +5,22 @@
- reg : <register mapping>
Optional properties:
- - interrupt-names : name describing the interrupts for ICE IRQ
- - interrupts : <interrupt mapping for ICE IRQ>
- - qcom,enable-ice-clk : should enable clocks for ICE HW
- - clocks : List of phandle and clock specifier pairs
- - clock-names : List of clock input name strings sorted in the same
- order as the clocks property.
- - qocm,op-freq-hz : max clock speed sorted in the same order as the clocks
- property.
- - qcom,instance-type : describe the storage type for which ICE node is defined
- currently, only "ufs" and "sdcc" are supported storage type
+ - interrupt-names : name describing the interrupts for ICE IRQ
+ - interrupts : <interrupt mapping for ICE IRQ>
+ - qcom,enable-ice-clk : should enable clocks for ICE HW
+ - clocks : List of phandle and clock specifier pairs
+ - clock-names : List of clock input name strings sorted in the same
+ order as the clocks property.
+ - qocm,op-freq-hz : max clock speed sorted in the same order as the clocks
+ property.
+ - qcom,instance-type : describe the storage type for which ICE node is defined
+ currently, only "ufs" and "sdcc" are supported storage type
+ - vdd-hba-supply : regulated supply to be used by ICE HW
+ - qcom,msm-bus,name : bus for ICE transactions
+ - qcom,msm-bus,num-cases : bus case mapping for ICE HW
+ - qcom,msm-bus,num-paths : bus path mapping for iCE HW
+ - qcom,msm-bus,vectors-KBps : bus bandwidth to be voted
+ - qcom,bus-vector-names : bus vectors mapping
Example:
ufs_ice: ufsice@630000 {
@@ -30,3 +36,26 @@
qcom,instance-type = "ufs";
status = "disabled";
};
+
+ ufs_card_ice: ufscardice@1db0000 {
+ compatible = "qcom,ice_card";
+ reg = <0x1db0000 0x8000>;
+ qcom,enable-ice-clk;
+ clock-names = "ufs_core_clk", "bus_clk",
+ "iface_clk", "ice_core_clk";
+ clocks = <&clock_gcc GCC_UFS_CARD_AXI_CLK>,
+ <&clock_gcc GCC_UFS_CARD_CLKREF_CLK>,
+ <&clock_gcc GCC_UFS_CARD_AHB_CLK>,
+ <&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>;
+ qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
+ vdd-hba-supply = <&ufs_card_gdsc>;
+ qcom,msm-bus,name = "ufs_card_ice_noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 650 0 0>, /* No vote */
+ <1 650 1000 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN",
+ "MAX";
+ qcom,instance-type = "ufs_card";
+ };
diff --git a/Documentation/devicetree/bindings/devfreq/arm-memlat-mon.txt b/Documentation/devicetree/bindings/devfreq/arm-memlat-mon.txt
index 67dc991..6f2fac7 100644
--- a/Documentation/devicetree/bindings/devfreq/arm-memlat-mon.txt
+++ b/Documentation/devicetree/bindings/devfreq/arm-memlat-mon.txt
@@ -15,6 +15,8 @@
Defaults to 0x17 if not specified.
- qcom,inst-ev: The instruction count event that this monitor is supposed to measure.
Defaults to 0x08 if not specified.
+- qcom,stall-cycle-ev: The stall cycle count that this monitor is supposed to measure.
+ Assumes 100% stall if not specified.
Example:
@@ -24,6 +26,7 @@
qcom,target-dev = <&memlat0>;
qcom,cachemiss-ev = <0x2A>;
qcom,inst-ev = <0x08>;
+ qcom,stall-cycle-ev = <0xE7>;
qcom,core-dev-table =
< 300000 1525>,
< 499200 3143>,
diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 2782428..3b45562 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -367,6 +367,14 @@
match the number of xin-ids defined in
property: qcom,sde-inline-rot-xin
- #power-domain-cells: Number of cells in a power-domain specifier and should contain 0.
+- qcom,sde-mixer-display-pref: A string array indicating the preferred display type
+ for the mixer block. Possible values:
+ "primary" - preferred for primary display
+ "none" - no preference on display
+- qcom,sde-ctl-display-pref: A string array indicating the preferred display type
+ for the ctl block. Possible values:
+ "primary" - preferred for primary display
+ "none" - no preference on display
Bus Scaling Subnodes:
- qcom,sde-reg-bus: Property to provide Bus scaling for register access for
@@ -452,8 +460,12 @@
qcom,sde-off = <0x1000>;
qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400
0x00002600 0x00002800>;
+ qcom,sde-ctl-display-pref = "primary", "none", "none",
+ "none", "none";
qcom,sde-mixer-off = <0x00045000 0x00046000
0x00047000 0x0004a000>;
+ qcom,sde-mixer-display-pref = "primary", "none",
+ "none", "none";
qcom,sde-dspp-top-off = <0x1300>;
qcom,sde-dspp-off = <0x00055000 0x00057000>;
qcom,sde-dspp-ad-off = <0x24000 0x22800>;
diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt
index 2a5096f..6af2bac 100644
--- a/Documentation/devicetree/bindings/pci/msm_pcie.txt
+++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt
@@ -95,6 +95,9 @@
and assign for each endpoint.
- qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become
stable after power on, before de-assert the PERST to the endpoint.
+ - qcom,switch-latency: The time (unit: ms) to wait for the PCIe endpoint's link
+ training with switch downstream port after the link between switch upstream
+ port and RC is up.
- qcom,wr-halt-size: With base 2, this exponent determines the size of the
data that PCIe core will halt on for each write transaction.
- qcom,slv-addr-space-size: The memory space size of PCIe Root Complex.
@@ -268,6 +271,7 @@
qcom,smmu-exist;
qcom,smmu-sid-base = <0x1480>;
qcom,ep-latency = <100>;
+ qcom,switch-latency = <100>;
qcom,wr-halt-size = <0xa>; /* 1KB */
qcom,slv-addr-space-size = <0x1000000>; /* 16MB */
qcom,cpl-timeout = <0x2>;
diff --git a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
index 85b0fe9..abbc560 100644
--- a/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
+++ b/Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt
@@ -32,6 +32,7 @@
This may be a shared regulator that is already voted
on in the PIL proxy voting code (and also managed by the
modem on its own), hence we mark it as as optional.
+- vdd_mss-uV: Voltage to set for vdd_mss.
- vdd_pll-supply: Reference to the regulator that supplies the PLL's rail.
- qcom,vdd_pll: Voltage to be set for the PLL's rail.
- reg-names: "cxrail_bhs_reg" - control register for modem power
diff --git a/Documentation/devicetree/bindings/platform/msm/ipa.txt b/Documentation/devicetree/bindings/platform/msm/ipa.txt
index e821feb..aede546 100644
--- a/Documentation/devicetree/bindings/platform/msm/ipa.txt
+++ b/Documentation/devicetree/bindings/platform/msm/ipa.txt
@@ -28,7 +28,6 @@
- qcom,lan-rx-ring-size: size of LAN rx ring, default is 192
- qcom,arm-smmu: SMMU is present and ARM SMMU driver is used
- qcom,msm-smmu: SMMU is present and QSMMU driver is used
-- qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass
- qcom,smmu-fast-map: Boolean context flag to set SMMU to fastpath mode
- ipa_smmu_ap: AP general purpose SMMU device
compatible "qcom,ipa-smmu-ap-cb"
@@ -122,6 +121,9 @@
-compatible: "qcom,ipa-smmu-uc-cb" - represents IPA uC context bank (for uC
offload scenarios).
+
+- qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass.
+
- iommus : the phandle and stream IDs for the SMMU used by this root
- qcom,iova-mapping: specifies the start address and size of iova space.
diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt
index d205b0b..f50fd88 100644
--- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt
+++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt
@@ -208,14 +208,14 @@
Value type: <u32>
Definition: Lower limit of battery temperature to start the capacity
learning. If this is not specified, then the default value
- used will be 150. Unit is in decidegC.
+ used will be 150 (15 C). Unit is in decidegC.
- qcom,cl-max-temp
Usage: optional
Value type: <u32>
Definition: Upper limit of battery temperature to start the capacity
learning. If this is not specified, then the default value
- used will be 450 (45C). Unit is in decidegC.
+ used will be 500 (50 C). Unit is in decidegC.
- qcom,cl-max-increment
Usage: optional
diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg.txt
new file mode 100644
index 0000000..f6a7a1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg.txt
@@ -0,0 +1,275 @@
+QTI's QPNP PMIC Fuel Gauge Device
+
+QPNP PMIC FG provides interface to clients to read properties related
+to the battery. Its main function is to retrieve the State of Charge (SOC),
+a 0-100 percentage representing the amount of charge left in the battery.
+
+There are two required peripherals in the FG driver, both implemented as
+subnodes in the example. These peripherals must not be disabled if the FG
+device is to enabled:
+
+- qcom,fg-soc : The main FG device. Supports battery fuel gauge controls and
+ sensors.
+- qcom,fg-batt : The FG battery device supports interrupts and controls with
+ respect to the state of the connected battery.For example: the
+ peripheral informs the driver if the battery has been identified
+ by the fuel gauge based on a given battery resistance range.
+
+Optionally ADC nodes can be added
+- qcom,revid-tp-rev: A subnode with a register address for the TP_REV register
+ in the REVID peripheral. This is used to apply workarounds that
+ may depend on the trim program.
+- qcom,fg-adc-vbat : A subnode with a register address for the FG_ADC_USR
+ peripheral which is used mainly for battery current limiting (BCL).
+ This node maps out the VBAT reading register which allows to have
+ a +/- 32 mV accurate reading of VBAT.
+- qcom,fg-adc-ibat : A subnode with a register address for the FG_ADC_USR
+ peripheral which is used mainly for battery current limiting (BCL).
+ This node maps out the IBAT current reading register which allows
+ to have a +/- 32 mA accurate reading of IBAT.
+
+Parent node required properties:
+- compatible : should be "qcom,qpnp-fg" for the FG driver.
+- qcom,pmic-revid : Should specify the phandle of PMIC
+ revid module. This is used to identify
+ the PMIC subtype.
+
+Parent node optional properties:
+- qcom,warm-bat-decidegc: Warm battery temperature in decidegC.
+- qcom,cool-bat-decidegc: Cool battery temperature in decidegC.
+- qcom,hot-bat-decidegc: Hot battery temperature in decidegC.
+- qcom,cold-bat-decidegc: Cold battery temperature in decidegC.
+- qcom,cold-hot-jeita-hysteresis: A tuple of 2. Index[0] is cold
+ hysteresis and index[1] is hot
+ hysterisis(in decidegC).
+- qcom,ext-sense-type: Current sense channel used by the FG.
+ Set this to use external rsense.
+- qcom,thermal-coefficients: Byte array of thermal coefficients for
+ reading battery thermistor. This should
+ be exactly 6 bytes in length.
+ Example: [01 02 03 04 05 06]
+- qcom,resume-soc: soc to resume charging in percentage.
+- qcom,resume-soc-raw: soc to resume charging in the scale of
+ [0-255]. This overrides qcom,resume-soc
+ if defined.
+- qcom,hold-soc-while-full: A boolean property that when defined
+ holds SOC at 100% when the battery is
+ full.
+- qcom,bcl-lm-threshold-ma: BCL LPM to MPM mode transition threshold
+ in milliAmpere.
+- qcom,bcl-mh-threshold-ma: BCL MPM to HPM mode transition threshold
+ in milliAmpere.
+- qcom,use-otp-profile: Specify this flag to avoid RAM loading
+ any battery profile.
+- qcom,sw-rbias-control: Boolean property which defines whether
+ the Rbias needs to be controlled by
+ software. If this is not set, it will
+ be controlled by hardware (default).
+- qcom,fg-iterm-ma: Battery current at which the fuel gauge
+ will try to scale 100% towards. When
+ the charge current goes above this, the
+ SoC should be at 100%.
+- qcom,fg-chg-iterm-ma: Battery current at which the fuel gauge
+ will issue end of charge if the charger
+ is configured to use the fuel gauge
+ ADCs for end of charge detection. This
+ property is in milliamps and should be
+ positive (e.g. 100mA to terminate at
+ -100mA).
+- qcom,irq-volt-empty-mv: The voltage threshold that the empty
+ soc interrupt will be triggered. When
+ the empty soc interrupt fires, battery
+ soc will be pulled to 0 and the
+ userspace will be notified via the
+ power supply framework. The userspace
+ will read 0% soc and immediately
+ shutdown.
+- qcom,fg-cutoff-voltage-mv: The voltage where the fuel gauge will
+ steer the SOC to be zero. For example,
+ if the cutoff voltage is set to 3400mv,
+ the fuel gauge will try to count SoC so
+ that the battery SoC will be 0 when it
+ is 3400mV.
+- qcom,fg-vbat-estimate-diff-mv: If the estimated voltage based on SoC
+ and battery current/resistance differs
+ from the actual voltage by more than
+ this amount, the fuel gauge will
+ redo the first SoC estimate when the
+ driver probes.
+- qcom,fg-delta-soc: How many percent the monotonic SoC must
+ change before a new delta_soc interrupt
+ is asserted. If this value is raised
+ above 3-4, some period workarounds may
+ not function well, so it's best to
+ leave this at 1 or 2%.
+- qcom,fg-vbatt-low-threshold: Voltage (in mV) which upon set will be
+ used for configuring the low battery
+ voltage threshold. Interrupt will be
+ asserted and handled based upon
+ this. If this property is not specified,
+ low battery voltage threshold will be
+ configured to 4200 mV.
+- qcom,cycle-counter-en: Boolean property which enables the cycle
+ counter feature. If this property is
+ present, then the following properties
+ to specify low and high soc thresholds
+ should be defined.
+- qcom,capacity-learning-on: A boolean property to have the fuel
+ gauge driver attempt to learn the
+ battery capacity when charging. Takes
+ precedence over capacity-estimation-on.
+- qcom,capacity-learning-feedback: A boolean property to have the fuel
+ gauge driver to feedback the learned
+ capacity into the capacity learning
+ algorithm. This has to be used only if
+ the property "qcom,capacity-learning-on"
+ is specified.
+- qcom,cl-max-increment-deciperc: The maximum percent that the capacity
+ can rise as the result of a single
+ charge cycle. This property corresponds
+ to .1% increments.
+- qcom,cl-max-decrement-deciperc: The maximum percent that the capacity
+ can fall as the result of a single
+ charge cycle. This property corresponds
+ to .1% decrements.
+- qcom,cl-max-temp-decidegc: Above this temperature, capacity
+ learning will be canceled.
+- qcom,cl-mix-temp-decidegc: Below this temperature, capacity
+ learning will be canceled.
+- qcom,cl-max-start-soc: The battery soc has to be below this
+ value at the start of a charge cycle
+ for capacity learning to be run.
+- qcom,cl-vbat-est-thr-uv: The maximum difference between the
+ battery voltage shadow and the current
+ predicted voltage in uV to initiate
+ capacity learning.
+- qcom,capacity-estimation-on: A boolean property to have the fuel
+ gauge driver attempt to estimate the
+ battery capacity using battery
+ resistance.
+- qcom,aging-eval-current-ma: Current used to evaluate battery aging.
+ This value should be around the steady
+ state current drawn from the battery
+ when the phone is low on battery.
+- qcom,fg-cc-cv-threshold-mv: Voltage threshold in mV for configuring
+ constant charge (CC) to constant
+ voltage (CV) setpoint in FG upon
+ which the battery EOC status will
+ be determined. This value should be
+ 10 mV less than the float voltage
+ configured in the charger.
+ This property should only be specified
+ if "qcom,autoadjust-vfloat" property is
+ specified in the charger driver to
+ ensure a proper operation.
+- qcom,bad-battery-detection-enable: A boolean property to enable the fuel
+ gauge driver to detect the damaged battery
+ when the safety-timer expires by using the
+ coulomb count.
+- qcom,fg-therm-delay-us: The time in microseconds to delay battery
+ thermistor biasing.
+- qcom,esr-pulse-tuning-en: A boolean property to enable ESR pulse
+ tuning feature. If this is enabled,
+ ESR pulse extraction will be disabled
+ when state of charge (SOC) is less than
+ 2%. It will be enabled back when SOC
+ gets above 2%. In addition, for SOC
+ between 2% and 5%, ESR pulse timing
+ settings will be different from default.
+ Once SOC crosses 5%, ESR pulse timings
+ will be restored back to default.
+
+qcom,fg-soc node required properties:
+- reg : offset and length of the PMIC peripheral register map.
+- interrupts : the interrupt mappings.
+ The format should be
+ <slave-id peripheral-id interrupt-number>.
+- interrupt-names : names for the mapped fg soc interrupts
+ The following interrupts are required:
+ 0: high-soc
+ 1: low-soc
+ 2: full-soc
+ 3: empty-soc
+ 4: delta-soc
+ 5: first-est-done
+ 6: sw-fallbk-ocv
+ 7: sw-fallbk-new-batt
+
+qcom,fg-memif node required properties:
+- reg : offset and length of the PMIC peripheral register map.
+- interrupts : the interrupt mappings.
+ The format should be
+ <slave-id peripheral-id interrupt-number>.
+- interrupt-names : names for the mapped fg adc interrupts
+ The following interrupts are required:
+ 0: mem-avail
+
+Example:
+pmi8994_fg: qcom,fg {
+ compatible = "qcom,qpnp-fg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ qcom,pmic-revid = <&pmi8994_revid>;
+
+ qcom,fg-soc@4000 {
+ reg = <0x4000 0x100>;
+ interrupts = <0x2 0x40 0x0>,
+ <0x2 0x40 0x1>,
+ <0x2 0x40 0x2>,
+ <0x2 0x40 0x3>,
+ <0x2 0x40 0x4>,
+ <0x2 0x40 0x5>,
+ <0x2 0x40 0x6>,
+ <0x2 0x40 0x7>;
+
+ interrupt-names = "high-soc",
+ "low-soc",
+ "full-soc",
+ "empty-soc",
+ "delta-soc",
+ "first-est-done",
+ "sw-fallbk-ocv",
+ "sw-fallbk-new-batt";
+ };
+
+ qcom,fg-batt@4100 {
+ reg = <0x4100 0x100>;
+ interrupts = <0x2 0x41 0x0>,
+ <0x2 0x41 0x1>,
+ <0x2 0x41 0x2>,
+ <0x2 0x41 0x3>,
+ <0x2 0x41 0x4>,
+ <0x2 0x41 0x5>,
+ <0x2 0x41 0x6>,
+ <0x2 0x41 0x7>;
+
+ interrupt-names = "soft-cold",
+ "soft-hot",
+ "vbatt-low",
+ "batt-ided",
+ "batt-id-req",
+ "batt-unknown",
+ "batt-missing",
+ "batt-match";
+ };
+
+ qcom,fg-adc-vbat@4254 {
+ reg = <0x4254 0x1>;
+ };
+
+ qcom,fg-adc-ibat@4255 {
+ reg = <0x4255 0x1>;
+ };
+
+ qcom,fg-memif@4400 {
+ reg = <0x4400 0x100>;
+ interrupts = <0x2 0x44 0x0>,
+ <0x2 0x44 0x1>;
+
+ interrupt-names = "mem-avail",
+ "data-rcvry-sug";
+
+ qcom,cold-hot-jeita-hysteresis = <30 50>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt
index cd2d2ea..866d004 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt
@@ -25,6 +25,10 @@
Documentation/devicetree/bindings/spi/spi-bus.txt
- qcom,wrapper-core: Wrapper QUPv3 core containing this SPI controller.
+Optional properties:
+- qcom,rt: Specifies if the framework worker thread for this
+ controller device should have "real-time" priority.
+
SPI slave nodes must be children of the SPI master node and can contain
properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
diff --git a/Documentation/devicetree/bindings/uio/msm_sharedmem.txt b/Documentation/devicetree/bindings/uio/msm_sharedmem.txt
index 749c6e85..4c89846 100644
--- a/Documentation/devicetree/bindings/uio/msm_sharedmem.txt
+++ b/Documentation/devicetree/bindings/uio/msm_sharedmem.txt
@@ -9,10 +9,18 @@
- reg-names : Indicates various client-names.
- qcom,client-id : The client id for the QMI clients.
+Optional properties:
+- qcom,guard-memory: If this dtsi property is set, then the shared memory
+ region will be guarded by SZ_4K at the start and at the end.
+ This is needed to overcome the XPU limitation on few MSM HW,
+ so as to make this memory not contiguous with other allocations
+ that may possibly happen from other clients.
+
Example:
qcom,msm_sharedmem@0dc80000 {
compatible = "qcom,sharedmem-uio";
reg = <0x0dc80000 0x00180000>,
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
+ qcom,guard-memory;
};
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 21c66eb..63da745 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -55,6 +55,7 @@
select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
+ select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_GCC_PLUGINS
select HAVE_GENERIC_DMA_COHERENT
select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile
index 7eb0c7f..3826bad 100644
--- a/arch/arm/boot/dts/qcom/Makefile
+++ b/arch/arm/boot/dts/qcom/Makefile
@@ -1,5 +1,7 @@
-dtb-$(CONFIG_ARCH_SDXPOORWILLS) += sdxpoorwills-rumi.dtb
+dtb-$(CONFIG_ARCH_SDXPOORWILLS) += sdxpoorwills-rumi.dtb \
+ sdxpoorwills-cdp.dtb \
+ sdxpoorwills-mtp.dtb
ifeq ($(CONFIG_ARM64),y)
diff --git a/arch/arm/boot/dts/qcom/pm8950.dtsi b/arch/arm/boot/dts/qcom/pm8950.dtsi
new file mode 100644
index 0000000..f47872a
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/pm8950.dtsi
@@ -0,0 +1,388 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&spmi_bus {
+ qcom,pm8950@0 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8950_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pm8950_temp_alarm: qcom,temp-alarm@2400 {
+ compatible = "qcom,qpnp-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0>;
+ label = "pm8950_tz";
+ qcom,channel-num = <8>;
+ qcom,threshold-set = <0>;
+ qcom,temp_alarm-vadc = <&pm8950_vadc>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0>,
+ <0x0 0x8 0x1>,
+ <0x0 0x8 0x4>,
+ <0x0 0x8 0x5>;
+ interrupt-names = "kpdpwr", "resin",
+ "resin-bark", "kpdpwr-resin-bark";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,system-reset;
+
+ qcom,pon_1 {
+ qcom,pon-type = <0>;
+ qcom,pull-up = <1>;
+ linux,code = <116>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <1>;
+ qcom,pull-up = <1>;
+ linux,code = <114>;
+ };
+ };
+
+ pm8950_coincell: qcom,coincell@2800 {
+ compatible = "qcom,qpnp-coincell";
+ reg = <0x2800 0x100>;
+ };
+
+ pm8950_mpps: mpps {
+ compatible = "qcom,qpnp-pin";
+ spmi-dev-container;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pm8950-mpp";
+
+ mpp@a000 {
+ reg = <0xa000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ mpp@a100 {
+ /* MPP2 - PA_THERM config */
+ reg = <0xa100 0x100>;
+ qcom,pin-num = <2>;
+ qcom,mode = <4>; /* AIN input */
+ qcom,invert = <1>; /* Enable MPP */
+ qcom,ain-route = <1>; /* AMUX 6 */
+ qcom,master-en = <1>;
+ qcom,src-sel = <0>; /* Function constant */
+ };
+
+ mpp@a200 {
+ reg = <0xa200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ mpp@a300 {
+ /* MPP4 - CASE_THERM config */
+ reg = <0xa300 0x100>;
+ qcom,pin-num = <4>;
+ qcom,mode = <4>; /* AIN input */
+ qcom,invert = <1>; /* Enable MPP */
+ qcom,ain-route = <3>; /* AMUX 8 */
+ qcom,master-en = <1>;
+ qcom,src-sel = <0>; /* Function constant */
+ };
+ };
+
+ pm8950_gpios: gpios {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pm8950-gpio";
+
+ gpio@c000 {
+ reg = <0xc000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ gpio@c100 {
+ reg = <0xc100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+
+ gpio@c200 {
+ reg = <0xc200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ gpio@c300 {
+ reg = <0xc300 0x100>;
+ qcom,pin-num = <4>;
+ status = "disabled";
+ };
+
+ gpio@c400 {
+ reg = <0xc400 0x100>;
+ qcom,pin-num = <5>;
+ status = "disabled";
+ };
+
+ gpio@c500 {
+ reg = <0xc500 0x100>;
+ qcom,pin-num = <6>;
+ status = "disabled";
+ };
+
+ gpio@c600 {
+ reg = <0xc600 0x100>;
+ qcom,pin-num = <7>;
+ status = "disabled";
+ };
+
+ gpio@c700 {
+ reg = <0xc700 0x100>;
+ qcom,pin-num = <8>;
+ status = "disabled";
+ };
+ };
+
+ pm8950_vadc: vadc@3100 {
+ compatible = "qcom,qpnp-vadc";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,vadc-poll-eoc;
+ qcom,pmic-revid = <&pm8950_revid>;
+
+ chan@5 {
+ label = "vcoin";
+ reg = <5>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@7 {
+ label = "vph_pwr";
+ reg = <7>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@8 {
+ label = "die_temp";
+ reg = <8>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <3>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@9 {
+ label = "ref_625mv";
+ reg = <9>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@a {
+ label = "ref_1250v";
+ reg = <0xa>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@c {
+ label = "ref_buf_625mv";
+ reg = <0xc>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@36 {
+ label = "pa_therm0";
+ reg = <0x36>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@11 {
+ label = "pa_therm1";
+ reg = <0x11>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@32 {
+ label = "xo_therm";
+ reg = <0x32>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <4>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@3c {
+ label = "xo_therm_buf";
+ reg = <0x3c>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <4>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@13 {
+ label = "case_therm";
+ reg = <0x13>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+ };
+
+ pm8950_adc_tm: vadc@3400 {
+ compatible = "qcom,qpnp-adc-tm";
+ reg = <0x3400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x34 0x0>,
+ <0x0 0x34 0x3>,
+ <0x0 0x34 0x4>;
+ interrupt-names = "eoc-int-en-set",
+ "high-thr-en-set",
+ "low-thr-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,adc_tm-vadc = <&pm8950_vadc>;
+ qcom,pmic-revid = <&pm8950_revid>;
+
+ chan@36 {
+ label = "pa_therm0";
+ reg = <0x36>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,btm-channel-number = <0x48>;
+ qcom,thermal-node;
+ };
+
+ chan@7 {
+ label = "vph_pwr";
+ reg = <0x7>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ qcom,btm-channel-number = <0x68>;
+ };
+ };
+
+ pm8950_rtc: qcom,pm8950_rtc {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-rtc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,qpnp-rtc-write = <0>;
+ qcom,qpnp-rtc-alarm-pwrup = <0>;
+
+ qcom,pm8950_rtc_rw@6000 {
+ reg = <0x6000 0x100>;
+ };
+
+ qcom,pm8950_rtc_alarm@6100 {
+ reg = <0x6100 0x100>;
+ interrupts = <0x0 0x61 0x1>;
+ };
+ };
+
+ qcom,leds@a300 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xa300 0x100>;
+ label = "mpp";
+ };
+ };
+
+ pm8950_1: qcom,pm8950@1 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8950_pwm: pwm@bc00 {
+ status = "disabled";
+ compatible = "qcom,qpnp-pwm";
+ reg = <0xbc00 0x100>;
+ reg-names = "qpnp-lpg-channel-base";
+ qcom,channel-id = <0>;
+ qcom,supported-sizes = <6>, <9>;
+ #pwm-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/pmi8950.dtsi b/arch/arm/boot/dts/qcom/pmi8950.dtsi
new file mode 100644
index 0000000..0ec1f0b
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/pmi8950.dtsi
@@ -0,0 +1,641 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/msm/power-on.h>
+
+&spmi_bus {
+ qcom,pmi8950@2 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pmi8950_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ qcom,secondary-pon-reset;
+ qcom,hard-reset-poweroff-type =
+ <PON_POWER_OFF_SHUTDOWN>;
+
+ pon_perph_reg: qcom,pon_perph_reg {
+ regulator-name = "pon_spare_reg";
+ qcom,pon-spare-reg-addr = <0x8c>;
+ qcom,pon-spare-reg-bit = <1>;
+ };
+ };
+
+ pmi8950_vadc: vadc@3100 {
+ compatible = "qcom,qpnp-vadc";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x2 0x31 0x0>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,vadc-poll-eoc;
+
+ chan@0 {
+ label = "usbin";
+ reg = <0>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <4>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@1 {
+ label = "dcin";
+ reg = <1>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <4>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@3 {
+ label = "vchg_sns";
+ reg = <3>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@9 {
+ label = "ref_625mv";
+ reg = <9>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@a {
+ label = "ref_1250v";
+ reg = <0xa>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@d {
+ label = "chg_temp";
+ reg = <0xd>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <16>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@43 {
+ label = "usb_dp";
+ reg = <0x43>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@44 {
+ label = "usb_dm";
+ reg = <0x44>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+ };
+
+ pmi8950_gpios: gpios {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pmi8950-gpio";
+
+ gpio@c000 {
+ reg = <0xc000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ gpio@c100 {
+ reg = <0xc100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+ };
+
+ pmi8950_mpps: mpps {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pmi8950-mpp";
+
+ mpp@a000 {
+ reg = <0xa000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ mpp@a100 {
+ reg = <0xa100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+
+ mpp@a200 {
+ reg = <0xa200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ mpp@a300 {
+ reg = <0xa300 0x100>;
+ qcom,pin-num = <4>;
+ status = "disabled";
+ };
+ };
+
+ pmi8950_charger: qcom,qpnp-smbcharger {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-smbcharger";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,iterm-ma = <100>;
+ qcom,float-voltage-mv = <4200>;
+ qcom,resume-delta-mv = <200>;
+ qcom,chg-inhibit-fg;
+ qcom,rparasitic-uohm = <100000>;
+ qcom,bms-psy-name = "bms";
+ qcom,thermal-mitigation = <1500 700 600 0>;
+ qcom,parallel-usb-min-current-ma = <1400>;
+ qcom,parallel-usb-9v-min-current-ma = <900>;
+ qcom,parallel-allowed-lowering-ma = <500>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+ qcom,force-aicl-rerun;
+ qcom,aicl-rerun-period-s = <180>;
+ qcom,autoadjust-vfloat;
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts = <0x2 0x10 0x0>,
+ <0x2 0x10 0x1>,
+ <0x2 0x10 0x2>,
+ <0x2 0x10 0x3>,
+ <0x2 0x10 0x4>,
+ <0x2 0x10 0x5>,
+ <0x2 0x10 0x6>,
+ <0x2 0x10 0x7>;
+
+ interrupt-names = "chg-error",
+ "chg-inhibit",
+ "chg-prechg-sft",
+ "chg-complete-chg-sft",
+ "chg-p2f-thr",
+ "chg-rechg-thr",
+ "chg-taper-thr",
+ "chg-tcc-thr";
+ };
+
+ qcom,otg@1100 {
+ reg = <0x1100 0x100>;
+ interrupts = <0x2 0x11 0x0>,
+ <0x2 0x11 0x1>,
+ <0x2 0x11 0x3>;
+ interrupt-names = "otg-fail",
+ "otg-oc",
+ "usbid-change";
+ };
+
+ qcom,bat-if@1200 {
+ reg = <0x1200 0x100>;
+ interrupts = <0x2 0x12 0x0>,
+ <0x2 0x12 0x1>,
+ <0x2 0x12 0x2>,
+ <0x2 0x12 0x3>,
+ <0x2 0x12 0x4>,
+ <0x2 0x12 0x5>,
+ <0x2 0x12 0x6>,
+ <0x2 0x12 0x7>;
+
+ interrupt-names = "batt-hot",
+ "batt-warm",
+ "batt-cold",
+ "batt-cool",
+ "batt-ov",
+ "batt-low",
+ "batt-missing",
+ "batt-term-missing";
+ };
+
+ qcom,usb-chgpth@1300 {
+ reg = <0x1300 0x100>;
+ interrupts = <0x2 0x13 0x0>,
+ <0x2 0x13 0x1>,
+ <0x2 0x13 0x2>,
+ <0x2 0x13 0x5>;
+
+ interrupt-names = "usbin-uv",
+ "usbin-ov",
+ "usbin-src-det",
+ "aicl-done";
+ };
+
+ qcom,dc-chgpth@1400 {
+ reg = <0x1400 0x100>;
+ interrupts = <0x2 0x14 0x0>,
+ <0x2 0x14 0x1>;
+ interrupt-names = "dcin-uv",
+ "dcin-ov";
+ };
+
+ qcom,chgr-misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts = <0x2 0x16 0x0>,
+ <0x2 0x16 0x1>,
+ <0x2 0x16 0x2>,
+ <0x2 0x16 0x3>,
+ <0x2 0x16 0x4>,
+ <0x2 0x16 0x5>;
+
+ interrupt-names = "power-ok",
+ "temp-shutdown",
+ "wdog-timeout",
+ "flash-fail",
+ "otst2",
+ "otst3";
+ };
+
+ smbcharger_charger_otg: qcom,smbcharger-boost-otg {
+ regulator-name = "smbcharger_charger_otg";
+ };
+ };
+
+ pmi8950_fg: qcom,fg {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-fg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,resume-soc = <95>;
+ status = "okay";
+ qcom,bcl-lm-threshold-ma = <127>;
+ qcom,bcl-mh-threshold-ma = <405>;
+ qcom,fg-iterm-ma = <150>;
+ qcom,fg-chg-iterm-ma = <100>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+ qcom,fg-cutoff-voltage-mv = <3500>;
+ qcom,cycle-counter-en;
+ qcom,capacity-learning-on;
+
+ qcom,fg-soc@4000 {
+ status = "okay";
+ reg = <0x4000 0x100>;
+ interrupts = <0x2 0x40 0x0>,
+ <0x2 0x40 0x1>,
+ <0x2 0x40 0x2>,
+ <0x2 0x40 0x3>,
+ <0x2 0x40 0x4>,
+ <0x2 0x40 0x5>,
+ <0x2 0x40 0x6>;
+
+ interrupt-names = "high-soc",
+ "low-soc",
+ "full-soc",
+ "empty-soc",
+ "delta-soc",
+ "first-est-done",
+ "update-soc";
+ };
+
+ qcom,fg-batt@4100 {
+ reg = <0x4100 0x100>;
+ interrupts = <0x2 0x41 0x0>,
+ <0x2 0x41 0x1>,
+ <0x2 0x41 0x2>,
+ <0x2 0x41 0x3>,
+ <0x2 0x41 0x4>,
+ <0x2 0x41 0x5>,
+ <0x2 0x41 0x6>,
+ <0x2 0x41 0x7>;
+
+ interrupt-names = "soft-cold",
+ "soft-hot",
+ "vbatt-low",
+ "batt-ided",
+ "batt-id-req",
+ "batt-unknown",
+ "batt-missing",
+ "batt-match";
+ };
+
+ qcom,revid-tp-rev@1f1 {
+ reg = <0x1f1 0x1>;
+ };
+
+ qcom,fg-memif@4400 {
+ status = "okay";
+ reg = <0x4400 0x100>;
+ interrupts = <0x2 0x44 0x0>,
+ <0x2 0x44 0x2>;
+
+ interrupt-names = "mem-avail",
+ "data-rcvry-sug";
+ };
+ };
+
+ bcl@4200 {
+ compatible = "qcom,msm-bcl";
+ reg = <0x4200 0xFF 0x88E 0x2>;
+ reg-names = "fg_user_adc", "pon_spare";
+ interrupts = <0x2 0x42 0x0>,
+ <0x2 0x42 0x1>;
+ interrupt-names = "bcl-high-ibat-int",
+ "bcl-low-vbat-int";
+ qcom,vbat-scaling-factor = <39000>;
+ qcom,vbat-gain-numerator = <1>;
+ qcom,vbat-gain-denominator = <128>;
+ qcom,vbat-polling-delay-ms = <100>;
+ qcom,ibat-scaling-factor = <39000>;
+ qcom,ibat-gain-numerator = <1>;
+ qcom,ibat-gain-denominator = <128>;
+ qcom,ibat-offset-numerator = <1200>;
+ qcom,ibat-offset-denominator = <1>;
+ qcom,ibat-polling-delay-ms = <100>;
+ qcom,inhibit-derating-ua = <550000>;
+ };
+
+ qcom,leds@a100 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xa100 0x100>;
+ label = "mpp";
+ };
+ };
+
+ qcom,pmi8950@3 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pmi8950_pwm: pwm@b000 {
+ status = "disabled";
+ compatible = "qcom,qpnp-pwm";
+ reg = <0xb000 0x100>;
+ reg-names = "qpnp-lpg-channel-base";
+ qcom,channel-id = <0>;
+ qcom,supported-sizes = <6>, <9>;
+ #pwm-cells = <2>;
+ };
+
+ labibb: qpnp-labibb-regulator {
+ status = "disabled";
+ spmi-dev-container;
+ compatible = "qcom,qpnp-labibb-regulator";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+
+ ibb_regulator: qcom,ibb@dc00 {
+ reg = <0xdc00 0x100>;
+ reg-names = "ibb_reg";
+ regulator-name = "ibb_reg";
+
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6000000>;
+
+ qcom,qpnp-ibb-min-voltage = <1400000>;
+ qcom,qpnp-ibb-step-size = <100000>;
+ qcom,qpnp-ibb-slew-rate = <2000000>;
+ qcom,qpnp-ibb-use-default-voltage;
+ qcom,qpnp-ibb-init-voltage = <5500000>;
+ qcom,qpnp-ibb-init-amoled-voltage = <4000000>;
+ qcom,qpnp-ibb-init-lcd-voltage = <5500000>;
+
+ qcom,qpnp-ibb-soft-start = <1000>;
+
+ qcom,qpnp-ibb-discharge-resistor = <32>;
+ qcom,qpnp-ibb-lab-pwrup-delay = <8000>;
+ qcom,qpnp-ibb-lab-pwrdn-delay = <8000>;
+ qcom,qpnp-ibb-en-discharge;
+
+ qcom,qpnp-ibb-full-pull-down;
+ qcom,qpnp-ibb-pull-down-enable;
+ qcom,qpnp-ibb-switching-clock-frequency =
+ <1480>;
+ qcom,qpnp-ibb-limit-maximum-current = <1550>;
+ qcom,qpnp-ibb-debounce-cycle = <16>;
+ qcom,qpnp-ibb-limit-max-current-enable;
+ qcom,qpnp-ibb-ps-enable;
+ };
+
+ lab_regulator: qcom,lab@de00 {
+ reg = <0xde00 0x100>;
+ reg-names = "lab";
+ regulator-name = "lab_reg";
+
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6000000>;
+
+ qcom,qpnp-lab-min-voltage = <4600000>;
+ qcom,qpnp-lab-step-size = <100000>;
+ qcom,qpnp-lab-slew-rate = <5000>;
+ qcom,qpnp-lab-use-default-voltage;
+ qcom,qpnp-lab-init-voltage = <5500000>;
+ qcom,qpnp-lab-init-amoled-voltage = <4600000>;
+ qcom,qpnp-lab-init-lcd-voltage = <5500000>;
+
+ qcom,qpnp-lab-soft-start = <800>;
+
+ qcom,qpnp-lab-full-pull-down;
+ qcom,qpnp-lab-pull-down-enable;
+ qcom,qpnp-lab-switching-clock-frequency =
+ <1600>;
+ qcom,qpnp-lab-limit-maximum-current = <800>;
+ qcom,qpnp-lab-limit-max-current-enable;
+ qcom,qpnp-lab-ps-threshold = <40>;
+ qcom,qpnp-lab-ps-enable;
+ qcom,qpnp-lab-nfet-size = <100>;
+ qcom,qpnp-lab-pfet-size = <100>;
+ qcom,qpnp-lab-max-precharge-time = <500>;
+ };
+
+ };
+
+ wled: qcom,leds@d800 {
+ compatible = "qcom,qpnp-wled";
+ reg = <0xd800 0x100>,
+ <0xd900 0x100>,
+ <0xdc00 0x100>,
+ <0xde00 0x100>;
+ reg-names = "qpnp-wled-ctrl-base",
+ "qpnp-wled-sink-base",
+ "qpnp-wled-ibb-base",
+ "qpnp-wled-lab-base";
+ interrupts = <0x3 0xd8 0x2>;
+ interrupt-names = "sc-irq";
+ status = "okay";
+ linux,name = "wled";
+ linux,default-trigger = "bkl-trigger";
+ qcom,fdbk-output = "auto";
+ qcom,vref-mv = <350>;
+ qcom,switch-freq-khz = <800>;
+ qcom,ovp-mv = <29500>;
+ qcom,ilim-ma = <980>;
+ qcom,boost-duty-ns = <26>;
+ qcom,mod-freq-khz = <9600>;
+ qcom,dim-mode = "hybrid";
+ qcom,dim-method = "linear";
+ qcom,hyb-thres = <625>;
+ qcom,sync-dly-us = <800>;
+ qcom,fs-curr-ua = <20000>;
+ qcom,led-strings-list = [00 01];
+ qcom,en-ext-pfet-sc-pro;
+ qcom,cons-sync-write-delay-us = <1000>;
+ };
+
+ flash_led: qcom,leds@d300 {
+ compatible = "qcom,qpnp-flash-led";
+ status = "okay";
+ reg = <0xd300 0x100>;
+ label = "flash";
+ qcom,headroom = <500>;
+ qcom,startup-dly = <128>;
+ qcom,clamp-curr = <200>;
+ qcom,pmic-charger-support;
+ qcom,self-check-enabled;
+ qcom,thermal-derate-enabled;
+ qcom,thermal-derate-threshold = <100>;
+ qcom,thermal-derate-rate = "5_PERCENT";
+ qcom,current-ramp-enabled;
+ qcom,ramp_up_step = "6P7_US";
+ qcom,ramp_dn_step = "6P7_US";
+ qcom,vph-pwr-droop-enabled;
+ qcom,vph-pwr-droop-threshold = <3000>;
+ qcom,vph-pwr-droop-debounce-time = <10>;
+ qcom,headroom-sense-ch0-enabled;
+ qcom,headroom-sense-ch1-enabled;
+ qcom,pmic-revid = <&pmi8950_revid>;
+
+ pmi8950_flash0: qcom,flash_0 {
+ label = "flash";
+ qcom,led-name = "led:flash_0";
+ qcom,default-led-trigger =
+ "flash0_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <0>;
+ qcom,current = <625>;
+ };
+
+ pmi8950_flash1: qcom,flash_1 {
+ label = "flash";
+ qcom,led-name = "led:flash_1";
+ qcom,default-led-trigger =
+ "flash1_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <1>;
+ qcom,current = <625>;
+ };
+
+ pmi8950_torch0: qcom,torch_0 {
+ label = "torch";
+ qcom,led-name = "led:torch_0";
+ qcom,default-led-trigger =
+ "torch0_trigger";
+ qcom,max-current = <200>;
+ qcom,id = <0>;
+ qcom,current = <120>;
+ };
+
+ pmi8950_torch1: qcom,torch_1 {
+ label = "torch";
+ qcom,led-name = "led:torch_1";
+ qcom,default-led-trigger =
+ "torch1_trigger";
+ qcom,max-current = <200>;
+ qcom,id = <1>;
+ qcom,current = <120>;
+ };
+
+ pmi8950_switch: qcom,switch {
+ label = "switch";
+ qcom,led-name = "led:switch";
+ qcom,default-led-trigger =
+ "switch_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <2>;
+ qcom,current = <625>;
+ reg0 {
+ regulator-name = "pon_spare_reg";
+ };
+ };
+ };
+
+ pmi_haptic: qcom,haptic@c000 {
+ compatible = "qcom,qpnp-haptic";
+ reg = <0xc000 0x100>;
+ interrupts = <0x3 0xc0 0x0>,
+ <0x3 0xc0 0x1>;
+ interrupt-names = "sc-irq", "play-irq";
+ qcom,pmic-revid = <&pmi8950_revid>;
+ vcc_pon-supply = <&pon_perph_reg>;
+ qcom,play-mode = "direct";
+ qcom,wave-play-rate-us = <5263>;
+ qcom,actuator-type = "erm";
+ qcom,wave-shape = "square";
+ qcom,vmax-mv = <2000>;
+ qcom,ilim-ma = <800>;
+ qcom,sc-deb-cycles = <8>;
+ qcom,int-pwm-freq-khz = <505>;
+ qcom,en-brake;
+ qcom,brake-pattern = [03 03 00 00];
+ qcom,use-play-irq;
+ qcom,use-sc-irq;
+ qcom,wave-samples = [3e 3e 3e 3e 3e 3e 3e 3e];
+ qcom,wave-rep-cnt = <1>;
+ qcom,wave-samp-rep-cnt = <1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills-bus.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills-bus.dtsi
new file mode 100644
index 0000000..d1d44ec
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills-bus.dtsi
@@ -0,0 +1,804 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ ad_hoc_bus: ad-hoc-bus {
+ compatible = "qcom,msm-bus-device";
+ reg = <0x1100000 0x400000>,
+ <0x1100000 0x400000>,
+ <0x1620000 0x400000>,
+ <0x1620000 0x400000>;
+
+ reg-names = "mc_virt-base", "mem_noc-base",
+ "system_noc-base", "ipa_virt-base";
+
+ /*RSCs*/
+ rsc_apps: rsc-apps {
+ cell-id = <MSM_BUS_RSC_APPS>;
+ label = "apps_rsc";
+ qcom,rsc-dev;
+ qcom,req-state = <2>;
+ };
+
+ /*BCMs*/
+ bcm_alc: bcm-alc {
+ cell-id = <MSM_BUS_BCM_ALC>;
+ label = "ALC";
+ qcom,bcm-name = "ALC";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_ce: bcm-ce {
+ cell-id = <MSM_BUS_BCM_CE>;
+ label = "CE";
+ qcom,bcm-name = "CE";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mc0: bcm-mc0 {
+ cell-id = <MSM_BUS_BCM_MC0>;
+ label = "MC0";
+ qcom,bcm-name = "MC0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_ip0: bcm-ip0 {
+ cell-id = <MSM_BUS_BCM_IP0>;
+ label = "IP0";
+ qcom,bcm-name = "CE";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh0: bcm-sh0 {
+ cell-id = <MSM_BUS_BCM_SH0>;
+ label = "SH0";
+ qcom,bcm-name = "SH0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_pn0: bcm-pn0 {
+ cell-id = <MSM_BUS_BCM_PN0>;
+ label = "PN0";
+ qcom,bcm-name = "PN0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh1: bcm-sh1 {
+ cell-id = <MSM_BUS_BCM_SH1>;
+ label = "SH1";
+ qcom,bcm-name = "SH1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh3: bcm-sh3 {
+ cell-id = <MSM_BUS_BCM_SH3>;
+ label = "SH3";
+ qcom,bcm-name = "SH3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh4: bcm-sh4 {
+ cell-id = <MSM_BUS_BCM_SH4>;
+ label = "SH4";
+ qcom,bcm-name = "SH4";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn0: bcm-sn0 {
+ cell-id = <MSM_BUS_BCM_SN0>;
+ label = "SN0";
+ qcom,bcm-name = "SN0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn1: bcm-sn1 {
+ cell-id = <MSM_BUS_BCM_SN1>;
+ label = "SN1";
+ qcom,bcm-name = "SN1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_pn1: bcm-pn1 {
+ cell-id = <MSM_BUS_BCM_PN1>;
+ label = "PN1";
+ qcom,bcm-name = "PN1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_pn2: bcm-pn2 {
+ cell-id = <MSM_BUS_BCM_PN2>;
+ label = "PN2";
+ qcom,bcm-name = "PN2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn3: bcm-sn3 {
+ cell-id = <MSM_BUS_BCM_SN3>;
+ label = "SN3";
+ qcom,bcm-name = "SN3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_pn3: bcm-pn3 {
+ cell-id = <MSM_BUS_BCM_PN3>;
+ label = "PN3";
+ qcom,bcm-name = "PN3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_pn5: bcm-pn5 {
+ cell-id = <MSM_BUS_BCM_PN5>;
+ label = "PN5";
+ qcom,bcm-name = "PN5";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn6: bcm-sn6 {
+ cell-id = <MSM_BUS_BCM_SN6>;
+ label = "SN6";
+ qcom,bcm-name = "SN6";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn7: bcm-sn7 {
+ cell-id = <MSM_BUS_BCM_SN7>;
+ label = "SN7";
+ qcom,bcm-name = "SN7";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn8: bcm-sn8 {
+ cell-id = <MSM_BUS_BCM_SN8>;
+ label = "SN8";
+ qcom,bcm-name = "SN8";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn9: bcm-sn9 {
+ cell-id = <MSM_BUS_BCM_SN9>;
+ label = "SN9";
+ qcom,bcm-name = "SN9";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn11: bcm-sn11 {
+ cell-id = <MSM_BUS_BCM_SN11>;
+ label = "SN11";
+ qcom,bcm-name = "SN11";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ /*Buses*/
+ fab_ipa_virt: fab-ipa_virt{
+ cell-id = <MSM_BUS_FAB_IPA_VIRT>;
+ label = "fab-ipa_virt";
+ qcom,fab-dev;
+ qcom,base-name = "ipa_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_mc_virt: fab-mc_virt{
+ cell-id = <MSM_BUS_FAB_MC_VIRT>;
+ label = "fab-mc_virt";
+ qcom,fab-dev;
+ qcom,base-name = "mc_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_mem_noc: fab-mem_noc {
+ cell-id = <MSM_BUS_FAB_MEM_NOC>;
+ label = "fab-mem_noc";
+ qcom,fab-dev;
+ qcom,base-name = "mem_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <65536>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_system_noc: fab-system_noc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-system_noc";
+ qcom,fab-dev;
+ qcom,base-name = "system_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ /*Masters*/
+
+ mas_ipa_core_master: mas-ipa-core-master {
+ cell-id = <MSM_BUS_MASTER_IPA_CORE>;
+ label = "mas-ipa-core-master";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_ipa_core_slave>;
+ qcom,bus-dev = <&fab_ipa_virt>;
+ };
+
+ mas_llcc_mc: mas-llcc-mc {
+ cell-id = <MSM_BUS_MASTER_LLCC>;
+ label = "mas-llcc-mc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_mc_virt>;
+ };
+
+ mas_acm_tcu: mas-acm-tcu {
+ cell-id = <MSM_BUS_MASTER_TCU_0>;
+ label = "mas-acm-tcu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_mem_noc>;
+ qcom,bcms = <&bcm_sh1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ };
+
+ mas_qnm_snoc_gc: mas-qnm-snoc-gc {
+ cell-id = <MSM_BUS_MASTER_SNOC_GC_MEM_NOC>;
+ label = "mas-qnm-snoc-gc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_mem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ };
+
+ mas_xm_apps_rdwr: mas-xm-apps-rdwr {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-xm-apps-rdwr";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <3>;
+ qcom,connections = <&slv_qns_llcc &slv_qns_memnoc_snoc>;
+ qcom,bus-dev = <&fab_mem_noc>;
+ qcom,bcms = <&bcm_sh3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ };
+
+ mas_qhm_audio: mas-qhm-audio {
+ cell-id = <MSM_BUS_MASTER_AUDIO>;
+ label = "mas-qhm-audio";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn2>;
+ };
+
+ mas_qhm_blsp1: mas-qhm-blsp1 {
+ cell-id = <MSM_BUS_MASTER_BLSP_1>;
+ label = "mas-qhm-blsp1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn3>;
+ };
+
+ mas_qhm_qdss_bam: mas-qhm-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qhm-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_crypto_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_emac_cfg
+ &slv_qhs_aoss &slv_qhs_spmi_fetcher
+ &slv_qhs_pdm &slv_qns_snoc_memnoc
+ &slv_qhs_tcsr &slv_qhs_qpic
+ &slv_qxs_imem &slv_qhs_ipa
+ &slv_qhs_usb3_phy &slv_qhs_aop
+ &slv_qhs_blsp1 &slv_qhs_sdc1
+ &slv_qhs_pcie_parf &slv_qhs_audio
+ &slv_qhs_tlmm &slv_qhs_prng
+ &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl
+ &slv_qhs_usb3>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn8>;
+ };
+
+ mas_qhm_qpic: mas-qhm-qpic {
+ cell-id = <MSM_BUS_MASTER_QPIC>;
+ label = "mas-qhm-qpic";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_aoss &slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn3>;
+ };
+
+ mas_qhm_snoc_cfg: mas-qhm-snoc-cfg {
+ cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
+ label = "mas-qhm-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_snoc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_qhm_spmi_fetcher1: mas-qhm-spmi-fetcher1 {
+ cell-id = <MSM_BUS_MASTER_SPMI_FETCHER>;
+ label = "mas-qhm-spmi-fetcher1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc &slv_qhs_aop>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn2>;
+ };
+
+ mas_qnm_aggre_noc: mas-qnm-aggre-noc {
+ cell-id = <MSM_BUS_MASTER_ANOC_SNOC>;
+ label = "mas-qnm-aggre-noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_crypto_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_emac_cfg
+ &slv_qhs_aoss &slv_qhs_spmi_fetcher
+ &slv_qhs_pdm &slv_qns_snoc_memnoc
+ &slv_qhs_tcsr &slv_xs_qdss_stm
+ &slv_qhs_qpic &slv_qxs_imem
+ &slv_qhs_ipa &slv_qhs_usb3_phy
+ &slv_qhs_aop &slv_qhs_blsp1
+ &slv_qhs_sdc1 &slv_qhs_pcie_parf
+ &slv_qhs_audio &slv_qxs_pcie
+ &slv_qhs_tlmm &slv_qhs_prng
+ &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl
+ &slv_qhs_usb3>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn7>;
+ };
+
+ mas_qnm_aggre_noc_ipa: mas-qnm-aggre-noc-ipa {
+ cell-id = <MSM_BUS_MASTER_ANOC_IPA>;
+ label = "mas-qnm-aggre-noc-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_crypto_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_emac_cfg
+ &slv_qhs_aoss &slv_qhs_spmi_fetcher
+ &slv_qhs_pdm &slv_qns_snoc_memnoc
+ &slv_qhs_tcsr &slv_xs_qdss_stm
+ &slv_qhs_qpic &slv_qxs_imem
+ &slv_qhs_ipa &slv_qhs_usb3_phy
+ &slv_qhs_aop &slv_qhs_blsp1
+ &slv_qhs_sdc1 &slv_qhs_pcie_parf
+ &slv_qhs_audio &slv_qhs_tlmm
+ &slv_qhs_prng &slv_xs_sys_tcu_cfg
+ &slv_qhs_clk_ctl &slv_qhs_usb3>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_qnm_memnoc: mas-qnm-memnoc {
+ cell-id = <MSM_BUS_MASTER_MEM_NOC_SNOC>;
+ label = "mas-qnm-memnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_crypto_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_emac_cfg
+ &slv_qhs_aoss &slv_qhs_spmi_fetcher
+ &slv_qhs_pdm &slv_qhs_tcsr
+ &slv_xs_qdss_stm &slv_qhs_qpic
+ &slv_qxs_imem &slv_qhs_ipa
+ &slv_qhs_usb3_phy &slv_qhs_aop
+ &slv_qhs_blsp1 &slv_qhs_sdc1
+ &slv_qhs_pcie_parf &slv_qhs_audio
+ &slv_qhs_tlmm &slv_qhs_prng
+ &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl
+ &slv_qhs_usb3>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn9>;
+ };
+
+ mas_qxm_crypto: mas-qxm-crypto {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE_0>;
+ label = "mas-qxm-crypto";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_aoss &slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_ce>;
+ };
+
+ mas_qxm_ipa: mas-qxm-ipa {
+ cell-id = <MSM_BUS_MASTER_IPA>;
+ label = "mas-qxm-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc_ipa>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn11>;
+ };
+
+ mas_xm_emac: mas-xm-emac {
+ cell-id = <MSM_BUS_MASTER_EMAC>;
+ label = "mas-xm-emac";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_xm_pcie: mas-xm-pcie {
+ cell-id = <MSM_BUS_MASTER_PCIE>;
+ label = "mas-xm-pcie";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_xm_qdss_etr: mas-xm-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-xm-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_crypto_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_emac_cfg
+ &slv_qhs_aoss &slv_qhs_spmi_fetcher
+ &slv_qhs_pdm &slv_qns_snoc_memnoc
+ &slv_qhs_tcsr &slv_qhs_qpic
+ &slv_qxs_imem &slv_qhs_ipa
+ &slv_qhs_usb3_phy &slv_qhs_aop
+ &slv_qhs_blsp1 &slv_qhs_sdc1
+ &slv_qhs_pcie_parf &slv_qhs_audio
+ &slv_qhs_tlmm &slv_qhs_prng
+ &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl
+ &slv_qhs_usb3>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn8>;
+ };
+
+ mas_xm_sdc1: mas-xm-sdc1 {
+ cell-id = <MSM_BUS_MASTER_SDCC_1>;
+ label = "mas-xm-sdc1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_aoss &slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn1>;
+ };
+
+ mas_xm_usb3: mas-xm-usb3 {
+ cell-id = <MSM_BUS_MASTER_USB3>;
+ label = "mas-xm-usb3";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_aggre_noc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ /*Internal nodes*/
+
+ /*Slaves*/
+
+ slv_ipa_core_slave:slv-ipa-core-slave {
+ cell-id = <MSM_BUS_SLAVE_IPA_CORE>;
+ label = "slv-ipa-core-slave";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_ipa_virt>;
+ qcom,bcms = <&bcm_ip0>;
+ };
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mc_virt>;
+ qcom,bcms = <&bcm_mc0>;
+ };
+
+ slv_qns_llcc:slv-qns-llcc {
+ cell-id = <MSM_BUS_SLAVE_LLCC>;
+ label = "slv-qns-llcc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mem_noc>;
+ qcom,connections = <&mas_llcc_mc>;
+ qcom,bcms = <&bcm_sh0>;
+ };
+
+ slv_qns_memnoc_snoc:slv-qns-memnoc-snoc {
+ cell-id = <MSM_BUS_SLAVE_MEM_NOC_SNOC>;
+ label = "slv-qns-memnoc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mem_noc>;
+ qcom,connections = <&mas_qnm_memnoc>;
+ qcom,bcms = <&bcm_sh4>;
+ };
+
+ slv_qhs_aop:slv-qhs-aop {
+ cell-id = <MSM_BUS_SLAVE_AOP>;
+ label = "slv-qhs-aop";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_aoss:slv-qhs-aoss {
+ cell-id = <MSM_BUS_SLAVE_AOSS>;
+ label = "slv-qhs-aoss";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_audio:slv-qhs-audio {
+ cell-id = <MSM_BUS_SLAVE_AUDIO>;
+ label = "slv-qhs-audio";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_blsp1:slv-qhs-blsp1 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_1>;
+ label = "slv-qhs-blsp1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_clk_ctl:slv-qhs-clk-ctl {
+ cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+ label = "slv-qhs-clk-ctl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_crypto_cfg:slv-qhs-crypto-cfg {
+ cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
+ label = "slv-qhs-crypto-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_emac_cfg:slv-qhs-emac-cfg {
+ cell-id = <MSM_BUS_SLAVE_EMAC_CFG>;
+ label = "slv-qhs-emac-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_ipa:slv-qhs-ipa {
+ cell-id = <MSM_BUS_SLAVE_IPA_CFG>;
+ label = "slv-qhs-ipa";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_pcie_parf:slv-qhs-pcie-parf {
+ cell-id = <MSM_BUS_SLAVE_PCIE_PARF>;
+ label = "slv-qhs-pcie-parf";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_pdm:slv-qhs-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-qhs-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_prng:slv-qhs-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-qhs-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_qpic:slv-qhs-qpic {
+ cell-id = <MSM_BUS_SLAVE_QPIC>;
+ label = "slv-qhs-qpic";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_sdc1:slv-qhs-sdc1 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_1>;
+ label = "slv-qhs-sdc1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_snoc_cfg:slv-qhs-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-qhs-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qhm_snoc_cfg>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_spmi_fetcher:slv-qhs-spmi-fetcher {
+ cell-id = <MSM_BUS_SLAVE_SPMI_FETCHER>;
+ label = "slv-qhs-spmi-fetcher";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_tcsr:slv-qhs-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-qhs-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_tlmm:slv-qhs-tlmm {
+ cell-id = <MSM_BUS_SLAVE_TLMM>;
+ label = "slv-qhs-tlmm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_usb3:slv-qhs-usb3 {
+ cell-id = <MSM_BUS_SLAVE_USB3>;
+ label = "slv-qhs-usb3";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qhs_usb3_phy:slv-qhs-usb3-phy {
+ cell-id = <MSM_BUS_SLAVE_USB3_PHY_CFG>;
+ label = "slv-qhs-usb3-phy";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_pn0>;
+ };
+
+ slv_qns_aggre_noc:slv-qns-aggre-noc {
+ cell-id = <MSM_BUS_SLAVE_ANOC_SNOC>;
+ label = "slv-qns-aggre-noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_aggre_noc>;
+ };
+
+ slv_qns_aggre_noc_ipa:slv-qns-aggre-noc-ipa {
+ cell-id = <MSM_BUS_SLAVE_ANOC_IPA>;
+ label = "slv-qns-aggre-noc-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_aggre_noc_ipa>;
+ };
+
+ slv_qns_snoc_memnoc:slv-qns-snoc-memnoc {
+ cell-id = <MSM_BUS_SLAVE_SNOC_MEM_NOC_GC>;
+ label = "slv-qns-snoc-memnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc_gc>;
+ qcom,bcms = <&bcm_sn0>;
+ };
+
+ slv_qxs_imem:slv-qxs-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-qxs-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn1>;
+ };
+
+ slv_qxs_pcie:slv-qxs-pcie {
+ cell-id = <MSM_BUS_SLAVE_PCIE_0>;
+ label = "slv-qxs-pcie";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn6>;
+ };
+
+ slv_srvc_snoc:slv-srvc-snoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
+ label = "slv-srvc-snoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_xs_qdss_stm:slv-xs-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-xs-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn3>;
+ };
+
+ slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg {
+ cell-id = <MSM_BUS_SLAVE_TCU>;
+ label = "slv-xs-sys-tcu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills-cdp.dts b/arch/arm/boot/dts/qcom/sdxpoorwills-cdp.dts
new file mode 100644
index 0000000..6be47b4
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills-cdp.dts
@@ -0,0 +1,31 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+
+#include "sdxpoorwills.dtsi"
+#include "sdxpoorwills-pinctrl.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDXPOORWILLS CDP";
+ compatible = "qcom,sdxpoorwills-cdp",
+ "qcom,sdxpoorwills", "qcom,cdp";
+ qcom,board-id = <1 0x0>, <1 0x100>;
+};
+
+&blsp1_uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_console_active>;
+ status = "ok";
+};
+
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills-mtp.dts b/arch/arm/boot/dts/qcom/sdxpoorwills-mtp.dts
new file mode 100644
index 0000000..15ae24c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills-mtp.dts
@@ -0,0 +1,31 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+
+#include "sdxpoorwills.dtsi"
+#include "sdxpoorwills-pinctrl.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDXPOORWILLS MTP";
+ compatible = "qcom,sdxpoorwills-mtp",
+ "qcom,sdxpoorwills", "qcom,mtp";
+ qcom,board-id = <8 0x0>, <8 0x100>;
+};
+
+&blsp1_uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_console_active>;
+ status = "ok";
+};
+
diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
index aa8e31b..146fc9c 100644
--- a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
+++ b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi
@@ -463,3 +463,4 @@
#include "sdxpoorwills-regulator.dtsi"
#include "sdxpoorwills-smp2p.dtsi"
#include "sdxpoorwills-usb.dtsi"
+#include "sdxpoorwills-bus.dtsi"
diff --git a/arch/arm/configs/sdxpoorwills-perf_defconfig b/arch/arm/configs/sdxpoorwills-perf_defconfig
index e3b5dbc..877406f 100644
--- a/arch/arm/configs/sdxpoorwills-perf_defconfig
+++ b/arch/arm/configs/sdxpoorwills-perf_defconfig
@@ -28,6 +28,7 @@
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMA=y
+CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
CONFIG_CPU_IDLE=y
@@ -201,6 +202,7 @@
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MSM_V2=y
CONFIG_SPI=y
CONFIG_SPI_QUP=y
CONFIG_SPI_SPIDEV=m
@@ -276,6 +278,7 @@
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_QPNP=y
CONFIG_DMADEVICES=y
+CONFIG_QCOM_SPS_DMA=y
CONFIG_UIO=y
CONFIG_STAGING=y
CONFIG_GSI=y
diff --git a/arch/arm/configs/sdxpoorwills_defconfig b/arch/arm/configs/sdxpoorwills_defconfig
index b076dcf..d860595 100644
--- a/arch/arm/configs/sdxpoorwills_defconfig
+++ b/arch/arm/configs/sdxpoorwills_defconfig
@@ -30,6 +30,7 @@
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMA=y
+CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
CONFIG_CPU_IDLE=y
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index aefdb52..aec9930 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -17,6 +17,12 @@
sdm845-v2-4k-panel-mtp-overlay.dtbo \
sdm845-v2-4k-panel-cdp-overlay.dtbo \
sdm845-v2-4k-panel-qrd-overlay.dtbo \
+ sdm845-v2.1-cdp-overlay.dtbo \
+ sdm845-v2.1-mtp-overlay.dtbo \
+ sdm845-v2.1-qrd-overlay.dtbo \
+ sdm845-v2.1-4k-panel-mtp-overlay.dtbo \
+ sdm845-v2.1-4k-panel-cdp-overlay.dtbo \
+ sdm845-v2.1-4k-panel-qrd-overlay.dtbo \
sda845-cdp-overlay.dtbo \
sda845-mtp-overlay.dtbo \
sda845-qrd-overlay.dtbo \
@@ -26,6 +32,7 @@
sda845-v2-cdp-overlay.dtbo \
sda845-v2-mtp-overlay.dtbo \
sda845-v2-qrd-overlay.dtbo \
+ sda845-v2-hdk-overlay.dtbo \
sda845-v2-4k-panel-mtp-overlay.dtbo \
sda845-v2-4k-panel-cdp-overlay.dtbo \
sda845-v2-4k-panel-qrd-overlay.dtbo
@@ -44,6 +51,12 @@
sdm845-v2-4k-panel-mtp-overlay.dtbo-base := sdm845-v2.dtb
sdm845-v2-4k-panel-cdp-overlay.dtbo-base := sdm845-v2.dtb
sdm845-v2-4k-panel-qrd-overlay.dtbo-base := sdm845-v2.dtb
+sdm845-v2.1-cdp-overlay.dtbo-base := sdm845-v2.1.dtb
+sdm845-v2.1-mtp-overlay.dtbo-base := sdm845-v2.1.dtb
+sdm845-v2.1-qrd-overlay.dtbo-base := sdm845-v2.1.dtb
+sdm845-v2.1-4k-panel-mtp-overlay.dtbo-base := sdm845-v2.1.dtb
+sdm845-v2.1-4k-panel-cdp-overlay.dtbo-base := sdm845-v2.1.dtb
+sdm845-v2.1-4k-panel-qrd-overlay.dtbo-base := sdm845-v2.1.dtb
sda845-cdp-overlay.dtbo-base := sda845.dtb
sda845-mtp-overlay.dtbo-base := sda845.dtb
sda845-qrd-overlay.dtbo-base := sda845.dtb
@@ -53,6 +66,7 @@
sda845-v2-cdp-overlay.dtbo-base := sda845-v2.dtb
sda845-v2-mtp-overlay.dtbo-base := sda845-v2.dtb
sda845-v2-qrd-overlay.dtbo-base := sda845-v2.dtb
+sda845-v2-hdk-overlay.dtbo-base := sda845-v2.dtb
sda845-v2-4k-panel-mtp-overlay.dtbo-base := sda845-v2.dtb
sda845-v2-4k-panel-cdp-overlay.dtbo-base := sda845-v2.dtb
sda845-v2-4k-panel-qrd-overlay.dtbo-base := sda845-v2.dtb
@@ -79,6 +93,8 @@
sdm670-cdp-overlay.dtbo \
sdm670-mtp-overlay.dtbo \
sdm670-rumi-overlay.dtbo \
+ sdm670-qrd-overlay.dtbo \
+ sdm670-qrd-sku2-overlay.dtbo \
sdm670-pm660a-cdp-overlay.dtbo \
sdm670-pm660a-mtp-overlay.dtbo \
sdm670-external-codec-cdp-overlay.dtbo \
@@ -104,6 +120,8 @@
sdm670-cdp-overlay.dtbo-base := sdm670.dtb
sdm670-mtp-overlay.dtbo-base := sdm670.dtb
sdm670-rumi-overlay.dtbo-base := sdm670.dtb
+sdm670-qrd-overlay.dtbo-base := sdm670.dtb
+sdm670-qrd-sku2-overlay.dtbo-base := sdm670.dtb
sdm670-pm660a-cdp-overlay.dtbo-base := sdm670.dtb
sdm670-pm660a-mtp-overlay.dtbo-base := sdm670.dtb
sdm670-external-codec-cdp-overlay.dtbo-base := sdm670.dtb
@@ -130,6 +148,8 @@
dtb-$(CONFIG_ARCH_SDM670) += sdm670-rumi.dtb \
sdm670-mtp.dtb \
sdm670-cdp.dtb \
+ sdm670-qrd.dtb \
+ sdm670-qrd-sku2.dtb \
sdm670-pm660a-mtp.dtb \
sdm670-pm660a-cdp.dtb \
sdm670-external-codec-cdp.dtb \
diff --git a/arch/arm64/boot/dts/qcom/fg-gen3-batterydata-mlp446579-3800mah.dtsi b/arch/arm64/boot/dts/qcom/fg-gen3-batterydata-mlp446579-3800mah.dtsi
new file mode 100644
index 0000000..ca43a45
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/fg-gen3-batterydata-mlp446579-3800mah.dtsi
@@ -0,0 +1,81 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+qcom,mlp446579_3800mah {
+ /* #MLP446579_3800mAh_averaged_MasterSlave_Oct9th2017*/
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-mv = <4390>;
+ qcom,fastchg-current-ma = <3800>;
+ qcom,batt-id-kohm = <91>;
+ qcom,battery-beta = <4250>;
+ qcom,battery-type = "mlp446579_3800mah_averaged_masterslave_oct9th2017";
+ qcom,checksum = <0x3F0A>;
+ qcom,gui-version = "PMI8998GUI - 2.0.0.58";
+ qcom,fg-profile-data = [
+ 64 1F B8 05
+ 8F 0A 0F 06
+ A0 1D F3 FC
+ 41 13 70 1D
+ 1E 18 1E 23
+ 92 45 88 52
+ 52 00 00 00
+ 12 00 00 00
+ 00 00 04 00
+ FD D4 68 C3
+ 23 00 08 00
+ C3 D2 52 DC
+ 33 05 BB FB
+ 84 05 BE 13
+ 18 07 9E 2B
+ 21 06 09 20
+ 27 00 14 00
+ B7 1F A2 05
+ 8E 0A 1C 06
+ 7F 1D D9 ED
+ 20 12 FE 1D
+ F4 18 0A 23
+ 4C 45 49 53
+ 54 00 00 00
+ 0E 00 00 00
+ 00 00 F8 07
+ 03 00 27 B2
+ 1A 00 00 00
+ FE E2 52 DC
+ FE 05 79 FA
+ 56 05 D5 FA
+ 27 F5 5C 22
+ BC 33 CC FF
+ 07 10 00 00
+ F0 0E 66 46
+ 1A 00 40 00
+ A7 01 0A FA
+ FF 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm670.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm670.dtsi
index 8e5d854..25a332b 100644
--- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm670.dtsi
@@ -36,11 +36,9 @@
<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
clock-names = "gcc_ddrss_gpu_axi_clk",
"gcc_gpu_memnoc_gfx_clk",
- "gpu_cc_ahb_clk",
"gpu_cc_cx_gmu_clk";
clocks = <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
- <&clock_gpucc GPU_CC_AHB_CLK>,
<&clock_gpucc GPU_CC_CX_GMU_CLK>;
attach-impl-defs =
<0x6000 0x2378>,
diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi
index a48fba0..0a8fb4a 100644
--- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi
@@ -35,10 +35,8 @@
<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
- clock-names = "gcc_gpu_memnoc_gfx_clk",
- "gpu_cc_ahb_clk";
- clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
- <&clock_gpucc GPU_CC_AHB_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk";
+ clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;
attach-impl-defs =
<0x6000 0x2378>,
<0x6060 0x1055>,
@@ -316,6 +314,7 @@
};
kgsl_iommu_test_device {
+ status = "disabled";
compatible = "iommu-debug-test";
/*
* 0x7 isn't a valid sid, but should pass the sid sanity check.
diff --git a/arch/arm64/boot/dts/qcom/msm-gdsc-sdm845.dtsi b/arch/arm64/boot/dts/qcom/msm-gdsc-sdm845.dtsi
index dcc646c93b..b43c876 100644
--- a/arch/arm64/boot/dts/qcom/msm-gdsc-sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm-gdsc-sdm845.dtsi
@@ -181,6 +181,8 @@
qcom,poll-cfg-gdscr;
qcom,support-hw-trigger;
status = "disabled";
+ proxy-supply = <&mdss_core_gdsc>;
+ qcom,proxy-consumer-enable;
};
/* GDSCs in Graphics CC */
diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi
index 1fdb3f6..df5a970 100644
--- a/arch/arm64/boot/dts/qcom/pm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm660.dtsi
@@ -371,6 +371,16 @@
"bcl-crit-low-vbat";
#thermal-sensor-cells = <1>;
};
+
+ pm660_div_clk: qcom,clkdiv@5b00 {
+ compatible = "qcom,qpnp-clkdiv";
+ reg = <0x5b00 0x100>;
+ #clock-cells = <1>;
+ qcom,cxo-freq = <19200000>;
+ qcom,clkdiv-id = <1>;
+ qcom,clkdiv-init-freq = <19200000>;
+ status = "disabled";
+ };
};
pm660_1: qcom,pm660@1 {
diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi
new file mode 100644
index 0000000..f47872a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi
@@ -0,0 +1,388 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&spmi_bus {
+ qcom,pm8950@0 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8950_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pm8950_temp_alarm: qcom,temp-alarm@2400 {
+ compatible = "qcom,qpnp-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0>;
+ label = "pm8950_tz";
+ qcom,channel-num = <8>;
+ qcom,threshold-set = <0>;
+ qcom,temp_alarm-vadc = <&pm8950_vadc>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0>,
+ <0x0 0x8 0x1>,
+ <0x0 0x8 0x4>,
+ <0x0 0x8 0x5>;
+ interrupt-names = "kpdpwr", "resin",
+ "resin-bark", "kpdpwr-resin-bark";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,system-reset;
+
+ qcom,pon_1 {
+ qcom,pon-type = <0>;
+ qcom,pull-up = <1>;
+ linux,code = <116>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <1>;
+ qcom,pull-up = <1>;
+ linux,code = <114>;
+ };
+ };
+
+ pm8950_coincell: qcom,coincell@2800 {
+ compatible = "qcom,qpnp-coincell";
+ reg = <0x2800 0x100>;
+ };
+
+ pm8950_mpps: mpps {
+ compatible = "qcom,qpnp-pin";
+ spmi-dev-container;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pm8950-mpp";
+
+ mpp@a000 {
+ reg = <0xa000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ mpp@a100 {
+ /* MPP2 - PA_THERM config */
+ reg = <0xa100 0x100>;
+ qcom,pin-num = <2>;
+ qcom,mode = <4>; /* AIN input */
+ qcom,invert = <1>; /* Enable MPP */
+ qcom,ain-route = <1>; /* AMUX 6 */
+ qcom,master-en = <1>;
+ qcom,src-sel = <0>; /* Function constant */
+ };
+
+ mpp@a200 {
+ reg = <0xa200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ mpp@a300 {
+ /* MPP4 - CASE_THERM config */
+ reg = <0xa300 0x100>;
+ qcom,pin-num = <4>;
+ qcom,mode = <4>; /* AIN input */
+ qcom,invert = <1>; /* Enable MPP */
+ qcom,ain-route = <3>; /* AMUX 8 */
+ qcom,master-en = <1>;
+ qcom,src-sel = <0>; /* Function constant */
+ };
+ };
+
+ pm8950_gpios: gpios {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pm8950-gpio";
+
+ gpio@c000 {
+ reg = <0xc000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ gpio@c100 {
+ reg = <0xc100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+
+ gpio@c200 {
+ reg = <0xc200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ gpio@c300 {
+ reg = <0xc300 0x100>;
+ qcom,pin-num = <4>;
+ status = "disabled";
+ };
+
+ gpio@c400 {
+ reg = <0xc400 0x100>;
+ qcom,pin-num = <5>;
+ status = "disabled";
+ };
+
+ gpio@c500 {
+ reg = <0xc500 0x100>;
+ qcom,pin-num = <6>;
+ status = "disabled";
+ };
+
+ gpio@c600 {
+ reg = <0xc600 0x100>;
+ qcom,pin-num = <7>;
+ status = "disabled";
+ };
+
+ gpio@c700 {
+ reg = <0xc700 0x100>;
+ qcom,pin-num = <8>;
+ status = "disabled";
+ };
+ };
+
+ pm8950_vadc: vadc@3100 {
+ compatible = "qcom,qpnp-vadc";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,vadc-poll-eoc;
+ qcom,pmic-revid = <&pm8950_revid>;
+
+ chan@5 {
+ label = "vcoin";
+ reg = <5>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@7 {
+ label = "vph_pwr";
+ reg = <7>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@8 {
+ label = "die_temp";
+ reg = <8>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <3>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@9 {
+ label = "ref_625mv";
+ reg = <9>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@a {
+ label = "ref_1250v";
+ reg = <0xa>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@c {
+ label = "ref_buf_625mv";
+ reg = <0xc>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@36 {
+ label = "pa_therm0";
+ reg = <0x36>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@11 {
+ label = "pa_therm1";
+ reg = <0x11>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@32 {
+ label = "xo_therm";
+ reg = <0x32>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <4>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@3c {
+ label = "xo_therm_buf";
+ reg = <0x3c>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <4>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@13 {
+ label = "case_therm";
+ reg = <0x13>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+ };
+
+ pm8950_adc_tm: vadc@3400 {
+ compatible = "qcom,qpnp-adc-tm";
+ reg = <0x3400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x34 0x0>,
+ <0x0 0x34 0x3>,
+ <0x0 0x34 0x4>;
+ interrupt-names = "eoc-int-en-set",
+ "high-thr-en-set",
+ "low-thr-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,adc_tm-vadc = <&pm8950_vadc>;
+ qcom,pmic-revid = <&pm8950_revid>;
+
+ chan@36 {
+ label = "pa_therm0";
+ reg = <0x36>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "ratiometric";
+ qcom,scale-function = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,btm-channel-number = <0x48>;
+ qcom,thermal-node;
+ };
+
+ chan@7 {
+ label = "vph_pwr";
+ reg = <0x7>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ qcom,btm-channel-number = <0x68>;
+ };
+ };
+
+ pm8950_rtc: qcom,pm8950_rtc {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-rtc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,qpnp-rtc-write = <0>;
+ qcom,qpnp-rtc-alarm-pwrup = <0>;
+
+ qcom,pm8950_rtc_rw@6000 {
+ reg = <0x6000 0x100>;
+ };
+
+ qcom,pm8950_rtc_alarm@6100 {
+ reg = <0x6100 0x100>;
+ interrupts = <0x0 0x61 0x1>;
+ };
+ };
+
+ qcom,leds@a300 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xa300 0x100>;
+ label = "mpp";
+ };
+ };
+
+ pm8950_1: qcom,pm8950@1 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8950_pwm: pwm@bc00 {
+ status = "disabled";
+ compatible = "qcom,qpnp-pwm";
+ reg = <0xbc00 0x100>;
+ reg-names = "qpnp-lpg-channel-base";
+ qcom,channel-id = <0>;
+ qcom,supported-sizes = <6>, <9>;
+ #pwm-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
new file mode 100644
index 0000000..0ec1f0b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
@@ -0,0 +1,641 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/msm/power-on.h>
+
+&spmi_bus {
+ qcom,pmi8950@2 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pmi8950_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ qcom,secondary-pon-reset;
+ qcom,hard-reset-poweroff-type =
+ <PON_POWER_OFF_SHUTDOWN>;
+
+ pon_perph_reg: qcom,pon_perph_reg {
+ regulator-name = "pon_spare_reg";
+ qcom,pon-spare-reg-addr = <0x8c>;
+ qcom,pon-spare-reg-bit = <1>;
+ };
+ };
+
+ pmi8950_vadc: vadc@3100 {
+ compatible = "qcom,qpnp-vadc";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x2 0x31 0x0>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-bit-resolution = <15>;
+ qcom,adc-vdd-reference = <1800>;
+ qcom,vadc-poll-eoc;
+
+ chan@0 {
+ label = "usbin";
+ reg = <0>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <4>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@1 {
+ label = "dcin";
+ reg = <1>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <4>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@3 {
+ label = "vchg_sns";
+ reg = <3>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@9 {
+ label = "ref_625mv";
+ reg = <9>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@a {
+ label = "ref_1250v";
+ reg = <0xa>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@d {
+ label = "chg_temp";
+ reg = <0xd>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <16>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ qcom,vadc-thermal-node;
+ };
+
+ chan@43 {
+ label = "usb_dp";
+ reg = <0x43>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+
+ chan@44 {
+ label = "usb_dm";
+ reg = <0x44>;
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,calibration-type = "absolute";
+ qcom,scale-function = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ };
+ };
+
+ pmi8950_gpios: gpios {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pmi8950-gpio";
+
+ gpio@c000 {
+ reg = <0xc000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ gpio@c100 {
+ reg = <0xc100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+ };
+
+ pmi8950_mpps: mpps {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-pin";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ label = "pmi8950-mpp";
+
+ mpp@a000 {
+ reg = <0xa000 0x100>;
+ qcom,pin-num = <1>;
+ status = "disabled";
+ };
+
+ mpp@a100 {
+ reg = <0xa100 0x100>;
+ qcom,pin-num = <2>;
+ status = "disabled";
+ };
+
+ mpp@a200 {
+ reg = <0xa200 0x100>;
+ qcom,pin-num = <3>;
+ status = "disabled";
+ };
+
+ mpp@a300 {
+ reg = <0xa300 0x100>;
+ qcom,pin-num = <4>;
+ status = "disabled";
+ };
+ };
+
+ pmi8950_charger: qcom,qpnp-smbcharger {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-smbcharger";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,iterm-ma = <100>;
+ qcom,float-voltage-mv = <4200>;
+ qcom,resume-delta-mv = <200>;
+ qcom,chg-inhibit-fg;
+ qcom,rparasitic-uohm = <100000>;
+ qcom,bms-psy-name = "bms";
+ qcom,thermal-mitigation = <1500 700 600 0>;
+ qcom,parallel-usb-min-current-ma = <1400>;
+ qcom,parallel-usb-9v-min-current-ma = <900>;
+ qcom,parallel-allowed-lowering-ma = <500>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+ qcom,force-aicl-rerun;
+ qcom,aicl-rerun-period-s = <180>;
+ qcom,autoadjust-vfloat;
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts = <0x2 0x10 0x0>,
+ <0x2 0x10 0x1>,
+ <0x2 0x10 0x2>,
+ <0x2 0x10 0x3>,
+ <0x2 0x10 0x4>,
+ <0x2 0x10 0x5>,
+ <0x2 0x10 0x6>,
+ <0x2 0x10 0x7>;
+
+ interrupt-names = "chg-error",
+ "chg-inhibit",
+ "chg-prechg-sft",
+ "chg-complete-chg-sft",
+ "chg-p2f-thr",
+ "chg-rechg-thr",
+ "chg-taper-thr",
+ "chg-tcc-thr";
+ };
+
+ qcom,otg@1100 {
+ reg = <0x1100 0x100>;
+ interrupts = <0x2 0x11 0x0>,
+ <0x2 0x11 0x1>,
+ <0x2 0x11 0x3>;
+ interrupt-names = "otg-fail",
+ "otg-oc",
+ "usbid-change";
+ };
+
+ qcom,bat-if@1200 {
+ reg = <0x1200 0x100>;
+ interrupts = <0x2 0x12 0x0>,
+ <0x2 0x12 0x1>,
+ <0x2 0x12 0x2>,
+ <0x2 0x12 0x3>,
+ <0x2 0x12 0x4>,
+ <0x2 0x12 0x5>,
+ <0x2 0x12 0x6>,
+ <0x2 0x12 0x7>;
+
+ interrupt-names = "batt-hot",
+ "batt-warm",
+ "batt-cold",
+ "batt-cool",
+ "batt-ov",
+ "batt-low",
+ "batt-missing",
+ "batt-term-missing";
+ };
+
+ qcom,usb-chgpth@1300 {
+ reg = <0x1300 0x100>;
+ interrupts = <0x2 0x13 0x0>,
+ <0x2 0x13 0x1>,
+ <0x2 0x13 0x2>,
+ <0x2 0x13 0x5>;
+
+ interrupt-names = "usbin-uv",
+ "usbin-ov",
+ "usbin-src-det",
+ "aicl-done";
+ };
+
+ qcom,dc-chgpth@1400 {
+ reg = <0x1400 0x100>;
+ interrupts = <0x2 0x14 0x0>,
+ <0x2 0x14 0x1>;
+ interrupt-names = "dcin-uv",
+ "dcin-ov";
+ };
+
+ qcom,chgr-misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts = <0x2 0x16 0x0>,
+ <0x2 0x16 0x1>,
+ <0x2 0x16 0x2>,
+ <0x2 0x16 0x3>,
+ <0x2 0x16 0x4>,
+ <0x2 0x16 0x5>;
+
+ interrupt-names = "power-ok",
+ "temp-shutdown",
+ "wdog-timeout",
+ "flash-fail",
+ "otst2",
+ "otst3";
+ };
+
+ smbcharger_charger_otg: qcom,smbcharger-boost-otg {
+ regulator-name = "smbcharger_charger_otg";
+ };
+ };
+
+ pmi8950_fg: qcom,fg {
+ spmi-dev-container;
+ compatible = "qcom,qpnp-fg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,resume-soc = <95>;
+ status = "okay";
+ qcom,bcl-lm-threshold-ma = <127>;
+ qcom,bcl-mh-threshold-ma = <405>;
+ qcom,fg-iterm-ma = <150>;
+ qcom,fg-chg-iterm-ma = <100>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+ qcom,fg-cutoff-voltage-mv = <3500>;
+ qcom,cycle-counter-en;
+ qcom,capacity-learning-on;
+
+ qcom,fg-soc@4000 {
+ status = "okay";
+ reg = <0x4000 0x100>;
+ interrupts = <0x2 0x40 0x0>,
+ <0x2 0x40 0x1>,
+ <0x2 0x40 0x2>,
+ <0x2 0x40 0x3>,
+ <0x2 0x40 0x4>,
+ <0x2 0x40 0x5>,
+ <0x2 0x40 0x6>;
+
+ interrupt-names = "high-soc",
+ "low-soc",
+ "full-soc",
+ "empty-soc",
+ "delta-soc",
+ "first-est-done",
+ "update-soc";
+ };
+
+ qcom,fg-batt@4100 {
+ reg = <0x4100 0x100>;
+ interrupts = <0x2 0x41 0x0>,
+ <0x2 0x41 0x1>,
+ <0x2 0x41 0x2>,
+ <0x2 0x41 0x3>,
+ <0x2 0x41 0x4>,
+ <0x2 0x41 0x5>,
+ <0x2 0x41 0x6>,
+ <0x2 0x41 0x7>;
+
+ interrupt-names = "soft-cold",
+ "soft-hot",
+ "vbatt-low",
+ "batt-ided",
+ "batt-id-req",
+ "batt-unknown",
+ "batt-missing",
+ "batt-match";
+ };
+
+ qcom,revid-tp-rev@1f1 {
+ reg = <0x1f1 0x1>;
+ };
+
+ qcom,fg-memif@4400 {
+ status = "okay";
+ reg = <0x4400 0x100>;
+ interrupts = <0x2 0x44 0x0>,
+ <0x2 0x44 0x2>;
+
+ interrupt-names = "mem-avail",
+ "data-rcvry-sug";
+ };
+ };
+
+ bcl@4200 {
+ compatible = "qcom,msm-bcl";
+ reg = <0x4200 0xFF 0x88E 0x2>;
+ reg-names = "fg_user_adc", "pon_spare";
+ interrupts = <0x2 0x42 0x0>,
+ <0x2 0x42 0x1>;
+ interrupt-names = "bcl-high-ibat-int",
+ "bcl-low-vbat-int";
+ qcom,vbat-scaling-factor = <39000>;
+ qcom,vbat-gain-numerator = <1>;
+ qcom,vbat-gain-denominator = <128>;
+ qcom,vbat-polling-delay-ms = <100>;
+ qcom,ibat-scaling-factor = <39000>;
+ qcom,ibat-gain-numerator = <1>;
+ qcom,ibat-gain-denominator = <128>;
+ qcom,ibat-offset-numerator = <1200>;
+ qcom,ibat-offset-denominator = <1>;
+ qcom,ibat-polling-delay-ms = <100>;
+ qcom,inhibit-derating-ua = <550000>;
+ };
+
+ qcom,leds@a100 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xa100 0x100>;
+ label = "mpp";
+ };
+ };
+
+ qcom,pmi8950@3 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pmi8950_pwm: pwm@b000 {
+ status = "disabled";
+ compatible = "qcom,qpnp-pwm";
+ reg = <0xb000 0x100>;
+ reg-names = "qpnp-lpg-channel-base";
+ qcom,channel-id = <0>;
+ qcom,supported-sizes = <6>, <9>;
+ #pwm-cells = <2>;
+ };
+
+ labibb: qpnp-labibb-regulator {
+ status = "disabled";
+ spmi-dev-container;
+ compatible = "qcom,qpnp-labibb-regulator";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,pmic-revid = <&pmi8950_revid>;
+
+ ibb_regulator: qcom,ibb@dc00 {
+ reg = <0xdc00 0x100>;
+ reg-names = "ibb_reg";
+ regulator-name = "ibb_reg";
+
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6000000>;
+
+ qcom,qpnp-ibb-min-voltage = <1400000>;
+ qcom,qpnp-ibb-step-size = <100000>;
+ qcom,qpnp-ibb-slew-rate = <2000000>;
+ qcom,qpnp-ibb-use-default-voltage;
+ qcom,qpnp-ibb-init-voltage = <5500000>;
+ qcom,qpnp-ibb-init-amoled-voltage = <4000000>;
+ qcom,qpnp-ibb-init-lcd-voltage = <5500000>;
+
+ qcom,qpnp-ibb-soft-start = <1000>;
+
+ qcom,qpnp-ibb-discharge-resistor = <32>;
+ qcom,qpnp-ibb-lab-pwrup-delay = <8000>;
+ qcom,qpnp-ibb-lab-pwrdn-delay = <8000>;
+ qcom,qpnp-ibb-en-discharge;
+
+ qcom,qpnp-ibb-full-pull-down;
+ qcom,qpnp-ibb-pull-down-enable;
+ qcom,qpnp-ibb-switching-clock-frequency =
+ <1480>;
+ qcom,qpnp-ibb-limit-maximum-current = <1550>;
+ qcom,qpnp-ibb-debounce-cycle = <16>;
+ qcom,qpnp-ibb-limit-max-current-enable;
+ qcom,qpnp-ibb-ps-enable;
+ };
+
+ lab_regulator: qcom,lab@de00 {
+ reg = <0xde00 0x100>;
+ reg-names = "lab";
+ regulator-name = "lab_reg";
+
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6000000>;
+
+ qcom,qpnp-lab-min-voltage = <4600000>;
+ qcom,qpnp-lab-step-size = <100000>;
+ qcom,qpnp-lab-slew-rate = <5000>;
+ qcom,qpnp-lab-use-default-voltage;
+ qcom,qpnp-lab-init-voltage = <5500000>;
+ qcom,qpnp-lab-init-amoled-voltage = <4600000>;
+ qcom,qpnp-lab-init-lcd-voltage = <5500000>;
+
+ qcom,qpnp-lab-soft-start = <800>;
+
+ qcom,qpnp-lab-full-pull-down;
+ qcom,qpnp-lab-pull-down-enable;
+ qcom,qpnp-lab-switching-clock-frequency =
+ <1600>;
+ qcom,qpnp-lab-limit-maximum-current = <800>;
+ qcom,qpnp-lab-limit-max-current-enable;
+ qcom,qpnp-lab-ps-threshold = <40>;
+ qcom,qpnp-lab-ps-enable;
+ qcom,qpnp-lab-nfet-size = <100>;
+ qcom,qpnp-lab-pfet-size = <100>;
+ qcom,qpnp-lab-max-precharge-time = <500>;
+ };
+
+ };
+
+ wled: qcom,leds@d800 {
+ compatible = "qcom,qpnp-wled";
+ reg = <0xd800 0x100>,
+ <0xd900 0x100>,
+ <0xdc00 0x100>,
+ <0xde00 0x100>;
+ reg-names = "qpnp-wled-ctrl-base",
+ "qpnp-wled-sink-base",
+ "qpnp-wled-ibb-base",
+ "qpnp-wled-lab-base";
+ interrupts = <0x3 0xd8 0x2>;
+ interrupt-names = "sc-irq";
+ status = "okay";
+ linux,name = "wled";
+ linux,default-trigger = "bkl-trigger";
+ qcom,fdbk-output = "auto";
+ qcom,vref-mv = <350>;
+ qcom,switch-freq-khz = <800>;
+ qcom,ovp-mv = <29500>;
+ qcom,ilim-ma = <980>;
+ qcom,boost-duty-ns = <26>;
+ qcom,mod-freq-khz = <9600>;
+ qcom,dim-mode = "hybrid";
+ qcom,dim-method = "linear";
+ qcom,hyb-thres = <625>;
+ qcom,sync-dly-us = <800>;
+ qcom,fs-curr-ua = <20000>;
+ qcom,led-strings-list = [00 01];
+ qcom,en-ext-pfet-sc-pro;
+ qcom,cons-sync-write-delay-us = <1000>;
+ };
+
+ flash_led: qcom,leds@d300 {
+ compatible = "qcom,qpnp-flash-led";
+ status = "okay";
+ reg = <0xd300 0x100>;
+ label = "flash";
+ qcom,headroom = <500>;
+ qcom,startup-dly = <128>;
+ qcom,clamp-curr = <200>;
+ qcom,pmic-charger-support;
+ qcom,self-check-enabled;
+ qcom,thermal-derate-enabled;
+ qcom,thermal-derate-threshold = <100>;
+ qcom,thermal-derate-rate = "5_PERCENT";
+ qcom,current-ramp-enabled;
+ qcom,ramp_up_step = "6P7_US";
+ qcom,ramp_dn_step = "6P7_US";
+ qcom,vph-pwr-droop-enabled;
+ qcom,vph-pwr-droop-threshold = <3000>;
+ qcom,vph-pwr-droop-debounce-time = <10>;
+ qcom,headroom-sense-ch0-enabled;
+ qcom,headroom-sense-ch1-enabled;
+ qcom,pmic-revid = <&pmi8950_revid>;
+
+ pmi8950_flash0: qcom,flash_0 {
+ label = "flash";
+ qcom,led-name = "led:flash_0";
+ qcom,default-led-trigger =
+ "flash0_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <0>;
+ qcom,current = <625>;
+ };
+
+ pmi8950_flash1: qcom,flash_1 {
+ label = "flash";
+ qcom,led-name = "led:flash_1";
+ qcom,default-led-trigger =
+ "flash1_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <1>;
+ qcom,current = <625>;
+ };
+
+ pmi8950_torch0: qcom,torch_0 {
+ label = "torch";
+ qcom,led-name = "led:torch_0";
+ qcom,default-led-trigger =
+ "torch0_trigger";
+ qcom,max-current = <200>;
+ qcom,id = <0>;
+ qcom,current = <120>;
+ };
+
+ pmi8950_torch1: qcom,torch_1 {
+ label = "torch";
+ qcom,led-name = "led:torch_1";
+ qcom,default-led-trigger =
+ "torch1_trigger";
+ qcom,max-current = <200>;
+ qcom,id = <1>;
+ qcom,current = <120>;
+ };
+
+ pmi8950_switch: qcom,switch {
+ label = "switch";
+ qcom,led-name = "led:switch";
+ qcom,default-led-trigger =
+ "switch_trigger";
+ qcom,max-current = <1000>;
+ qcom,duration = <1280>;
+ qcom,id = <2>;
+ qcom,current = <625>;
+ reg0 {
+ regulator-name = "pon_spare_reg";
+ };
+ };
+ };
+
+ pmi_haptic: qcom,haptic@c000 {
+ compatible = "qcom,qpnp-haptic";
+ reg = <0xc000 0x100>;
+ interrupts = <0x3 0xc0 0x0>,
+ <0x3 0xc0 0x1>;
+ interrupt-names = "sc-irq", "play-irq";
+ qcom,pmic-revid = <&pmi8950_revid>;
+ vcc_pon-supply = <&pon_perph_reg>;
+ qcom,play-mode = "direct";
+ qcom,wave-play-rate-us = <5263>;
+ qcom,actuator-type = "erm";
+ qcom,wave-shape = "square";
+ qcom,vmax-mv = <2000>;
+ qcom,ilim-ma = <800>;
+ qcom,sc-deb-cycles = <8>;
+ qcom,int-pwm-freq-khz = <505>;
+ qcom,en-brake;
+ qcom,brake-pattern = [03 03 00 00];
+ qcom,use-play-irq;
+ qcom,use-sc-irq;
+ qcom,wave-samples = [3e 3e 3e 3e 3e 3e 3e 3e];
+ qcom,wave-rep-cnt = <1>;
+ qcom,wave-samp-rep-cnt = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sda845-v2-hdk-overlay.dts b/arch/arm64/boot/dts/qcom/sda845-v2-hdk-overlay.dts
new file mode 100644
index 0000000..f836f50
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sda845-v2-hdk-overlay.dts
@@ -0,0 +1,29 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sda845-v2-hdk.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA845 v2 HDK";
+ compatible = "qcom,sda845-hdk", "qcom,sda845", "qcom,hdk";
+ qcom,msm-id = <341 0x20000>;
+ qcom,board-id = <0x01001F 0x00>;
+};
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h b/arch/arm64/boot/dts/qcom/sda845-v2-hdk.dts
similarity index 61%
copy from drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
copy to arch/arm64/boot/dts/qcom/sda845-v2-hdk.dts
index 71b21b9..17f8324 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
+++ b/arch/arm64/boot/dts/qcom/sda845-v2-hdk.dts
@@ -10,19 +10,14 @@
* GNU General Public License for more details.
*/
-#ifndef CAM_JPEG_DMA_HW_INTF_H
-#define CAM_JPEG_DMA_HW_INTF_H
-#include <uapi/media/cam_defs.h>
-#include <media/cam_jpeg.h>
+/dts-v1/;
-#include "cam_hw_mgr_intf.h"
-#include "cam_jpeg_hw_intf.h"
+#include "sda845-v2.dtsi"
+#include "sda845-v2-hdk.dtsi"
-enum cam_jpeg_dma_cmd_type {
- CAM_JPEG_DMA_CMD_CDM_CFG,
- CAM_JPEG_DMA_CMD_SET_IRQ_CB,
- CAM_JPEG_DMA_CMD_MAX,
+/ {
+ model = "Qualcomm Technologies, Inc. SDA845 HDK";
+ compatible = "qcom,sda845-hdk", "qcom,sda845", "qcom,hdk";
+ qcom,board-id = <0x01001F 0x00>;
};
-
-#endif /* CAM_JPEG_DMA_HW_INTF_H */
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h b/arch/arm64/boot/dts/qcom/sda845-v2-hdk.dtsi
similarity index 61%
copy from drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
copy to arch/arm64/boot/dts/qcom/sda845-v2-hdk.dtsi
index 71b21b9..a8ff041 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
+++ b/arch/arm64/boot/dts/qcom/sda845-v2-hdk.dtsi
@@ -10,19 +10,10 @@
* GNU General Public License for more details.
*/
-#ifndef CAM_JPEG_DMA_HW_INTF_H
-#define CAM_JPEG_DMA_HW_INTF_H
+#include "sdm845-qvr.dtsi"
-#include <uapi/media/cam_defs.h>
-#include <media/cam_jpeg.h>
-
-#include "cam_hw_mgr_intf.h"
-#include "cam_jpeg_hw_intf.h"
-
-enum cam_jpeg_dma_cmd_type {
- CAM_JPEG_DMA_CMD_CDM_CFG,
- CAM_JPEG_DMA_CMD_SET_IRQ_CB,
- CAM_JPEG_DMA_CMD_MAX,
+&vendor {
+ qcom,battery-data {
+ #include "fg-gen3-batterydata-mlp356477-2800mah.dtsi"
+ };
};
-
-#endif /* CAM_JPEG_DMA_HW_INTF_H */
diff --git a/arch/arm64/boot/dts/qcom/sdm670-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdm670-cdp.dtsi
index 60a81ff..8e152b0 100644
--- a/arch/arm64/boot/dts/qcom/sdm670-cdp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670-cdp.dtsi
@@ -95,15 +95,6 @@
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
- #address-cells = <0>;
- interrupt-parent = <&sdhc_2>;
- interrupts = <0 1 2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0xffffffff>;
- interrupt-map = <0 &intc 0 0 204 0
- 1 &intc 0 0 222 0
- 2 &tlmm 96 0>;
- interrupt-names = "hc_irq", "pwr_irq", "status_irq";
cd-gpios = <&tlmm 96 0x1>;
status = "ok";
diff --git a/arch/arm64/boot/dts/qcom/sdm670-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdm670-mtp.dtsi
index 5e88b0a..c5eefea 100644
--- a/arch/arm64/boot/dts/qcom/sdm670-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670-mtp.dtsi
@@ -95,15 +95,6 @@
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
- #address-cells = <0>;
- interrupt-parent = <&sdhc_2>;
- interrupts = <0 1 2>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0xffffffff>;
- interrupt-map = <0 &intc 0 0 204 0
- 1 &intc 0 0 222 0
- 2 &tlmm 96 0>;
- interrupt-names = "hc_irq", "pwr_irq", "status_irq";
cd-gpios = <&tlmm 96 0x1>;
status = "ok";
diff --git a/arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi
index 177813f..2bf00fb 100644
--- a/arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670-pinctrl.dtsi
@@ -1625,6 +1625,20 @@
};
&pm660l_gpios {
+ camera0_dvdd_en_default: camera0_dvdd_en_default {
+ pins = "gpio3";
+ function = "normal";
+ power-source = <0>;
+ output-low;
+ };
+
+ camera1_dvdd_en_default: camera1_dvdd_en_default {
+ pins = "gpio4";
+ function = "normal";
+ power-source = <0>;
+ output-low;
+ };
+
key_vol_up {
key_vol_up_default: key_vol_up_default {
pins = "gpio7";
@@ -1635,3 +1649,13 @@
};
};
};
+
+&pm660_gpios {
+ smb_shutdown_default: smb_shutdown_default {
+ pins = "gpio11";
+ function = "normal";
+ power-source = <0>;
+ qcom,drive-strength = <3>;
+ output-high;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm670-qrd-overlay.dts b/arch/arm64/boot/dts/qcom/sdm670-qrd-overlay.dts
new file mode 100644
index 0000000..36d485e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm670-qrd-overlay.dts
@@ -0,0 +1,32 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm670-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM670 PM660 + PM660L QRD";
+ compatible = "qcom,sdm670-qrd", "qcom,sdm670", "qcom,qrd";
+ qcom,msm-id = <336 0x0>;
+ qcom,board-id = <0x0002000b 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm670-qrd-sku2-overlay.dts b/arch/arm64/boot/dts/qcom/sdm670-qrd-sku2-overlay.dts
new file mode 100644
index 0000000..37eb4cd
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm670-qrd-sku2-overlay.dts
@@ -0,0 +1,32 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm670-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM670 PM660 + PM660L QRD SKU2";
+ compatible = "qcom,sdm670-qrd", "qcom,sdm670", "qcom,qrd";
+ qcom,msm-id = <336 0x0>;
+ qcom,board-id = <0x0012000b 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm670-qrd-sku2.dts b/arch/arm64/boot/dts/qcom/sdm670-qrd-sku2.dts
new file mode 100644
index 0000000..dada4c6
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm670-qrd-sku2.dts
@@ -0,0 +1,26 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+
+#include "sdm670.dtsi"
+#include "sdm670-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM670 PM660 + PM660L QRD SKU2";
+ compatible = "qcom,sdm670-qrd", "qcom,sdm670", "qcom,qrd";
+ qcom,board-id = <0x0012000b 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm670-qrd.dts b/arch/arm64/boot/dts/qcom/sdm670-qrd.dts
new file mode 100644
index 0000000..c22afa4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm670-qrd.dts
@@ -0,0 +1,26 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+
+#include "sdm670.dtsi"
+#include "sdm670-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM670 PM660 + PM660L QRD";
+ compatible = "qcom,sdm670-qrd", "qcom,sdm670", "qcom,qrd";
+ qcom,board-id = <0x0002000b 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm670-qrd.dtsi b/arch/arm64/boot/dts/qcom/sdm670-qrd.dtsi
new file mode 100644
index 0000000..55f3b93
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm670-qrd.dtsi
@@ -0,0 +1,147 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "sdm670-pmic-overlay.dtsi"
+#include "sdm670-audio-overlay.dtsi"
+#include "smb1355.dtsi"
+
+&qupv3_se9_2uart {
+ status = "disabled";
+};
+
+&qupv3_se12_2uart {
+ status = "ok";
+};
+
+&qupv3_se8_spi {
+ status = "disabled";
+};
+
+&qupv3_se3_i2c {
+ status = "disabled";
+};
+
+&qupv3_se10_i2c {
+ status = "ok";
+};
+
+&qupv3_se6_4uart {
+ status = "disabled";
+};
+
+&vendor {
+ qrd_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "fg-gen3-batterydata-mlp356477-2800mah.dtsi"
+ };
+};
+
+&pm660_fg {
+ qcom,battery-data = <&qrd_batterydata>;
+ qcom,fg-bmd-en-delay-ms = <300>;
+};
+
+&tlmm {
+ smb_int_default: smb_int_default {
+ mux {
+ pins = "gpio54";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+};
+
+&smb1355_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default
+ &smb_shutdown_default>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <54 IRQ_TYPE_LEVEL_LOW>;
+ smb1355_charger_0: qcom,smb1355-charger@1000 {
+ io-channels = <&pm660_rradc 2>,
+ <&pm660_rradc 12>;
+ io-channel-names = "charger_temp",
+ "charger_temp_max";
+ status = "ok";
+ };
+};
+
+&smb1355_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default
+ &smb_shutdown_default>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <54 IRQ_TYPE_LEVEL_LOW>;
+ smb1355_charger_1: qcom,smb1355-charger@1000 {
+ io-channels = <&pm660_rradc 2>,
+ <&pm660_rradc 12>;
+ io-channel-names = "charger_temp",
+ "charger_temp_max";
+ status = "ok";
+ };
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <115>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+};
+
+&pm660_haptics {
+ qcom,vmax-mv = <1800>;
+ qcom,wave-play-rate-us = <4255>;
+ qcom,lra-auto-mode;
+ status = "okay";
+};
+
+&int_codec {
+ qcom,model = "sdm660-skuw-snd-card";
+ qcom,audio-routing =
+ "RX_BIAS", "INT_MCLK0",
+ "SPK_RX_BIAS", "INT_MCLK0",
+ "INT_LDO_H", "INT_MCLK0",
+ "MIC BIAS External2", "Headset Mic",
+ "AMIC2", "MIC BIAS External2",
+ "MIC BIAS External", "Handset Mic",
+ "AMIC1", "MIC BIAS External",
+ "MIC BIAS External", "Secondary Mic",
+ "AMIC3", "MIC BIAS External",
+ "SpkrLeft IN", "SPK1 OUT",
+ "PDM_IN_RX1", "PDM_OUT_RX1",
+ "PDM_IN_RX2", "PDM_OUT_RX2",
+ "PDM_IN_RX3", "PDM_OUT_RX3",
+ "ADC1_IN", "ADC1_OUT",
+ "ADC2_IN", "ADC2_OUT",
+ "ADC3_IN", "ADC3_OUT";
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_211_en>, <&wsa881x_213_en>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft";
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi b/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi
index 00829f0..2878184 100644
--- a/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670-sde.dtsi
@@ -190,6 +190,9 @@
qcom,sde-dspp-blocks {
qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
qcom,sde-dspp-gamut = <0x1000 0x00040000>;
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index b2d802e..e52fb62 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -56,7 +56,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_0>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -75,11 +75,11 @@
};
L1_I_0: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_0: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_0: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -92,7 +92,7 @@
reg = <0x0 0x100>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_100>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -106,11 +106,11 @@
};
L1_I_100: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_100: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_100: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -123,7 +123,7 @@
reg = <0x0 0x200>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_200>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -137,11 +137,11 @@
};
L1_I_200: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_200: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_200: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -154,7 +154,7 @@
reg = <0x0 0x300>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_300>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -168,11 +168,11 @@
};
L1_I_300: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_300: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_300: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -185,7 +185,7 @@
reg = <0x0 0x400>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_400>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -199,11 +199,11 @@
};
L1_I_400: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_400: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_400: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -216,7 +216,7 @@
reg = <0x0 0x500>;
enable-method = "psci";
efficiency = <1024>;
- cache-size = <0x8000>;
+ cache-size = <0x10000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_500>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
@@ -230,11 +230,11 @@
};
L1_I_500: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0x12000>;
};
L1_D_500: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x9000>;
+ qcom,dump-size = <0xa000>;
};
L1_TLB_500: l1-tlb {
qcom,dump-size = <0x3000>;
@@ -247,7 +247,7 @@
reg = <0x0 0x600>;
enable-method = "psci";
efficiency = <1740>;
- cache-size = <0x10000>;
+ cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_600>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
@@ -261,11 +261,11 @@
};
L1_I_600: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x12000>;
+ qcom,dump-size = <0x24000>;
};
L1_D_600: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x12000>;
+ qcom,dump-size = <0x14000>;
};
L1_TLB_600: l1-tlb {
qcom,dump-size = <0x3c000>;
@@ -278,7 +278,7 @@
reg = <0x0 0x700>;
enable-method = "psci";
efficiency = <1740>;
- cache-size = <0x10000>;
+ cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
next-level-cache = <&L2_700>;
sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
@@ -292,11 +292,11 @@
};
L1_I_700: l1-icache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x12000>;
+ qcom,dump-size = <0x24000>;
};
L1_D_700: l1-dcache {
compatible = "arm,arch-cache";
- qcom,dump-size = <0x12000>;
+ qcom,dump-size = <0x14000>;
};
L1_TLB_700: l1-tlb {
qcom,dump-size = <0x3c000>;
@@ -726,6 +726,73 @@
qcom,pipe-attr-ee;
};
+ qcom_cedev: qcedev@1de0000 {
+ compatible = "qcom,qcedev";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <0 272 0>;
+ qcom,bam-pipe-pair = <3>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,bam-ee = <0>;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <125 512 0 0>,
+ <125 512 393600 393600>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks = <&clock_gcc GCC_CE1_CLK>,
+ <&clock_gcc GCC_CE1_CLK>,
+ <&clock_gcc GCC_CE1_AHB_CLK>,
+ <&clock_gcc GCC_CE1_AXI_CLK>;
+ qcom,ce-opp-freq = <171430000>;
+ qcom,request-bw-before-clk;
+ qcom,smmu-s1-bypass;
+ iommus = <&apps_smmu 0x706 0x3>,
+ <&apps_smmu 0x716 0x3>;
+ };
+
+ qcom_crypto: qcrypto@1de0000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <0 272 0>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,bam-ee = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <125 512 0 0>,
+ <125 512 393600 393600>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks = <&clock_gcc GCC_CE1_CLK>,
+ <&clock_gcc GCC_CE1_CLK>,
+ <&clock_gcc GCC_CE1_AHB_CLK>,
+ <&clock_gcc GCC_CE1_AXI_CLK>;
+ qcom,ce-opp-freq = <171430000>;
+ qcom,request-bw-before-clk;
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-aead-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-hmac-algo;
+ qcom,smmu-s1-bypass;
+ iommus = <&apps_smmu 0x704 0x3>,
+ <&apps_smmu 0x714 0x3>;
+ };
+
qcom,qbt1000 {
compatible = "qcom,qbt1000";
clock-names = "core", "iface";
@@ -734,6 +801,58 @@
qcom,finger-detect-gpio = <&tlmm 122 0>;
};
+ qcom_seecom: qseecom@86d00000 {
+ compatible = "qcom,qseecom";
+ reg = <0x86d00000 0x2200000>;
+ reg-names = "secapp-region";
+ qcom,hlos-num-ce-hw-instances = <1>;
+ qcom,hlos-ce-hw-instance = <0>;
+ qcom,qsee-ce-hw-instance = <0>;
+ qcom,disk-encrypt-pipe-pair = <2>;
+ qcom,support-fde;
+ qcom,no-clock-support;
+ qcom,appsbl-qseecom-support;
+ qcom,msm-bus,name = "qseecom-noc";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <125 512 0 0>,
+ <125 512 200000 400000>,
+ <125 512 300000 800000>,
+ <125 512 400000 1000000>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks = <&clock_gcc GCC_CE1_CLK>,
+ <&clock_gcc GCC_CE1_CLK>,
+ <&clock_gcc GCC_CE1_AHB_CLK>,
+ <&clock_gcc GCC_CE1_AXI_CLK>;
+ qcom,ce-opp-freq = <171430000>;
+ qcom,qsee-reentrancy-support = <2>;
+ };
+
+ qcom_tzlog: tz-log@146bf720 {
+ compatible = "qcom,tz-log";
+ reg = <0x146bf720 0x3000>;
+ qcom,hyplog-enabled;
+ hyplog-address-offset = <0x410>;
+ hyplog-size-offset = <0x414>;
+ };
+
+ qcom_rng: qrng@793000{
+ compatible = "qcom,msm-rng";
+ reg = <0x793000 0x1000>;
+ qcom,msm-rng-iface-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 618 0 0>, /* No vote */
+ <1 618 0 800>; /* 100 KHz */
+ clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "iface_clk";
+ };
+
thermal_zones: thermal-zones {};
tsens0: tsens@c222000 {
@@ -960,7 +1079,7 @@
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <0 291 0>, <0 292 0>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
- status = "disabled";
+ status = "ok";
qcom,iommu-s1-bypass;
iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb {
@@ -968,6 +1087,13 @@
iommus = <&apps_smmu 0x1833 0x0>;
};
+ /* Slimbus Slave DT for WCN3990 */
+ btfmslim_codec: wcn3990 {
+ compatible = "qcom,btfmslim_slave";
+ elemental-addr = [00 01 20 02 17 02];
+ qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+ qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+ };
};
wdog: qcom,wdt@17980000{
@@ -1642,6 +1768,7 @@
<0 0>,
<0 0>;
+ non-removable;
qcom,msm-bus,name = "ufshc_mem";
qcom,msm-bus,num-cases = <12>;
qcom,msm-bus,num-paths = <2>;
@@ -1725,6 +1852,10 @@
qcom,client-id = <0x00000001>;
};
+ qcom,msm_gsi {
+ compatible = "qcom,msm_gsi";
+ };
+
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa3";
qcom,rmnet-ipa-ssr;
@@ -1930,7 +2061,7 @@
qcom,ssctl-instance-id = <0x12>;
qcom,override-acc;
qcom,qdsp6v65-1-0;
- qcom,mss_pdc_offset = <8>;
+ qcom,mss_pdc_offset = <9>;
status = "ok";
memory-region = <&pil_modem_mem>;
qcom,mem-protect-id = <0xF>;
@@ -2030,30 +2161,30 @@
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No vote */
- <78 512 0 0>, <1 606 0 0>,
+ <150 512 0 0>, <1 606 0 0>,
/* 400 KB/s*/
- <78 512 1046 1600>,
+ <150 512 1046 1600>,
<1 606 1600 1600>,
/* 20 MB/s */
- <78 512 52286 80000>,
+ <150 512 52286 80000>,
<1 606 80000 80000>,
/* 25 MB/s */
- <78 512 65360 100000>,
+ <150 512 65360 100000>,
<1 606 100000 100000>,
/* 50 MB/s */
- <78 512 130718 200000>,
+ <150 512 130718 200000>,
<1 606 133320 133320>,
/* 100 MB/s */
- <78 512 130718 200000>,
+ <150 512 130718 200000>,
<1 606 150000 150000>,
/* 200 MB/s */
- <78 512 261438 400000>,
+ <150 512 261438 400000>,
<1 606 300000 300000>,
/* 400 MB/s */
- <78 512 261438 400000>,
+ <150 512 261438 400000>,
<1 606 300000 300000>,
/* Max. bandwidth */
- <78 512 1338562 4096000>,
+ <150 512 1338562 4096000>,
<1 606 1338562 4096000>;
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100000000 200000000 400000000 4294967295>;
@@ -2067,8 +2198,10 @@
clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
<&clock_gcc GCC_SDCC1_APPS_CLK>,
- <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>;
- clock-names = "iface_clk", "core_clk", "ice_core_clk";
+ <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
+ <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
+ clock-names = "iface_clk", "core_clk", "ice_core_clk",
+ "bus_aggr_clk";
qcom,ice-clk-rates = <300000000 75000000>;
@@ -2220,12 +2353,36 @@
iommus = <&apps_smmu 0x1805 0x0>;
dma-coherent;
};
+ qcom,msm_fastrpc_compute_cb12 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1806 0x0>;
+ dma-coherent;
+ };
+ };
+
+ bluetooth: bt_wcn3990 {
+ compatible = "qca,wcn3990";
+ qca,bt-vdd-core-supply = <&pm660_l9>;
+ qca,bt-vdd-pa-supply = <&pm660_l6>;
+ qca,bt-vdd-ldo-supply = <&pm660_l19>;
+
+ qca,bt-vdd-core-voltage-level = <1800000 1900000>;
+ qca,bt-vdd-pa-voltage-level = <1304000 1370000>;
+ qca,bt-vdd-ldo-voltage-level = <3312000 3400000>;
+
+ qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */
};
qcom,icnss@18800000 {
- status = "disabled";
compatible = "qcom,icnss";
- reg = <0x18800000 0x800000>;
+ reg = <0x18800000 0x800000>,
+ <0xa0000000 0x10000000>,
+ <0xb0000000 0x10000>;
+ reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
+ iommus = <&apps_smmu 0x0040 0x1>;
interrupts = <0 414 0 /* CE0 */ >,
<0 415 0 /* CE1 */ >,
<0 416 0 /* CE2 */ >,
@@ -2238,6 +2395,10 @@
<0 423 0 /* CE9 */ >,
<0 424 0 /* CE10 */ >,
<0 425 0 /* CE11 */ >;
+ vdd-0.8-cx-mx-supply = <&pm660_l5>;
+ vdd-1.8-xo-supply = <&pm660_l9>;
+ vdd-1.3-rfa-supply = <&pm660_l6>;
+ vdd-3.3-ch0-supply = <&pm660_l19>;
qcom,wlan-msa-memory = <0x100000>;
qcom,smmu-s1-bypass;
};
@@ -2268,6 +2429,7 @@
reg-names = "base", "global_base";
interrupts = <0 581 4>;
qcom,mport = <0>;
+ qcom,count-unit = <0x10000>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&cpubw>;
};
@@ -2291,7 +2453,7 @@
< MHZ_TO_MBPS(1804, 4) >; /* 6881 MB/s */
};
- memlat_cpu4: qcom,memlat-cpu4 {
+ memlat_cpu6: qcom,memlat-cpu6 {
compatible = "qcom,devbw";
governor = "powersave";
qcom,src-dst-ports = <1 512>;
@@ -2313,9 +2475,9 @@
devfreq_memlat_0: qcom,cpu0-memlat-mon {
compatible = "qcom,arm-memlat-mon";
- qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
qcom,target-dev = <&memlat_cpu0>;
- qcom,cachemiss-ev = <0x24>;
+ qcom,cachemiss-ev = <0x2a>;
qcom,core-dev-table =
< 748800 MHZ_TO_MBPS( 300, 4) >,
< 998400 MHZ_TO_MBPS( 451, 4) >,
@@ -2324,11 +2486,11 @@
< 1728000 MHZ_TO_MBPS(1017, 4) >;
};
- devfreq_memlat_4: qcom,cpu4-memlat-mon {
+ devfreq_memlat_6: qcom,cpu6-memlat-mon {
compatible = "qcom,arm-memlat-mon";
- qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
- qcom,target-dev = <&memlat_cpu4>;
- qcom,cachemiss-ev = <0x24>;
+ qcom,cpulist = <&CPU6 &CPU7>;
+ qcom,target-dev = <&memlat_cpu6>;
+ qcom,cachemiss-ev = <0x2a>;
qcom,core-dev-table =
< 787200 MHZ_TO_MBPS( 300, 4) >,
< 1113600 MHZ_TO_MBPS( 547, 4) >,
@@ -2344,7 +2506,7 @@
governor = "performance";
};
- l3_cpu4: qcom,l3-cpu4 {
+ l3_cpu6: qcom,l3-cpu6 {
compatible = "devfreq-simple-dev";
clock-names = "devfreq_clk";
clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>;
@@ -2353,7 +2515,7 @@
devfreq_l3lat_0: qcom,cpu0-l3lat-mon {
compatible = "qcom,arm-memlat-mon";
- qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
qcom,target-dev = <&l3_cpu0>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table =
@@ -2365,10 +2527,10 @@
< 1728000 1440000000 >;
};
- devfreq_l3lat_4: qcom,cpu4-l3lat-mon {
+ devfreq_l3lat_6: qcom,cpu6-l3lat-mon {
compatible = "qcom,arm-memlat-mon";
- qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
- qcom,target-dev = <&l3_cpu4>;
+ qcom,cpulist = <&CPU6 &CPU7>;
+ qcom,target-dev = <&l3_cpu6>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table =
< 1113600 566400000 >,
@@ -2405,7 +2567,7 @@
< 1209600 MHZ_TO_MBPS( 451, 4) >,
< 1612000 MHZ_TO_MBPS( 547, 4) >,
< 1728000 MHZ_TO_MBPS( 768, 4) >;
- cpu-to-dev-map-4 =
+ cpu-to-dev-map-6 =
< 1113600 MHZ_TO_MBPS( 300, 4) >,
< 1344000 MHZ_TO_MBPS( 547, 4) >,
< 1728000 MHZ_TO_MBPS( 768, 4) >,
@@ -2559,3 +2721,7 @@
#include "sdm670-gpu.dtsi"
#include "sdm670-thermal.dtsi"
#include "sdm670-bus.dtsi"
+
+&pm660_div_clk {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi
index 04418d4..dc520a9 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi
@@ -122,8 +122,9 @@
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_rear_ldo>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vio", "cam_vana", "cam_vdig",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <0 3312000 1050000 0>;
rgltr-max-voltage = <0 3600000 1050000 0>;
@@ -165,8 +166,9 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vdig", "cam_vio", "cam_vana",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <1050000 0 3312000 0>;
rgltr-max-voltage = <1050000 0 3600000 0>;
@@ -179,14 +181,17 @@
&cam_sensor_rear2_suspend>;
gpios = <&tlmm 15 0>,
<&tlmm 9 0>,
- <&tlmm 8 0>;
+ <&tlmm 8 0>,
+ <&tlmm 27 0>;
gpio-reset = <1>;
gpio-vana = <2>;
- gpio-req-tbl-num = <0 1 2>;
- gpio-req-tbl-flags = <1 0 0>;
+ gpio-vaf = <3>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 0 0 0>;
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1",
- "CAM_VANA1";
+ "CAM_VANA1",
+ "CAM_VAF";
sensor-position = <0>;
sensor-mode = <0>;
cci-master = <1>;
@@ -205,8 +210,9 @@
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_ldo>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vio", "cam_vana", "cam_vdig",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <0 3312000 1050000 0>;
rgltr-max-voltage = <0 3600000 1050000 0>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi
index 9088fac..b723802 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi
@@ -122,8 +122,9 @@
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_rear_ldo>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vio", "cam_vana", "cam_vdig",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <0 3312000 1050000 0>;
rgltr-max-voltage = <0 3600000 1050000 0>;
@@ -165,8 +166,9 @@
cam_vio-supply = <&pm8998_lvs1>;
cam_vana-supply = <&pmi8998_bob>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vdig", "cam_vio", "cam_vana",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <1050000 0 3312000 0>;
rgltr-max-voltage = <1050000 0 3600000 0>;
@@ -179,14 +181,17 @@
&cam_sensor_rear2_suspend>;
gpios = <&tlmm 15 0>,
<&tlmm 9 0>,
- <&tlmm 8 0>;
+ <&tlmm 8 0>,
+ <&tlmm 27 0>;
gpio-reset = <1>;
gpio-vana = <2>;
- gpio-req-tbl-num = <0 1 2>;
- gpio-req-tbl-flags = <1 0 0>;
+ gpio-vaf = <3>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 0 0 0>;
gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1",
- "CAM_VANA1";
+ "CAM_VANA1",
+ "CAM_VAF";
sensor-position = <0>;
sensor-mode = <0>;
cci-master = <1>;
@@ -205,8 +210,9 @@
cam_vana-supply = <&pmi8998_bob>;
cam_vdig-supply = <&camera_ldo>;
cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&actuator_regulator>;
regulator-names = "cam_vio", "cam_vana", "cam_vdig",
- "cam_clk";
+ "cam_clk", "cam_vaf";
rgltr-cntrl-support;
rgltr-min-voltage = <0 3312000 1050000 0>;
rgltr-max-voltage = <0 3600000 1050000 0>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
index 7c9482c..744d021 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
@@ -28,7 +28,7 @@
gdscr-supply = <&titan_top_gdsc>;
regulator-names = "gdscr";
csi-vdd-voltage = <1200000>;
- mipi-csi-vdd-supply = <&pm8998_l26>;
+ mipi-csi-vdd-supply = <&pm8998_l1>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
@@ -62,7 +62,7 @@
gdscr-supply = <&titan_top_gdsc>;
regulator-names = "gdscr";
csi-vdd-voltage = <1200000>;
- mipi-csi-vdd-supply = <&pm8998_l26>;
+ mipi-csi-vdd-supply = <&pm8998_l1>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
@@ -97,7 +97,7 @@
gdscr-supply = <&titan_top_gdsc>;
regulator-names = "gdscr";
csi-vdd-voltage = <1200000>;
- mipi-csi-vdd-supply = <&pm8998_l26>;
+ mipi-csi-vdd-supply = <&pm8998_l1>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi
index 81ce1e5..dffb5e0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi
@@ -269,6 +269,27 @@
qcom,platform-reset-gpio = <&tlmm 6 0>;
};
+&dsi_dual_nt35597_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_dual_nt35597_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+};
+
&dsi_nt35597_truly_dsc_cmd_display {
qcom,dsi-display-active;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-gpu.dtsi b/arch/arm64/boot/dts/qcom/sdm845-gpu.dtsi
index 11b6a4d..0eee34a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-gpu.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-gpu.dtsi
@@ -58,6 +58,7 @@
qcom,initial-pwrlevel = <5>;
qcom,gpu-quirk-hfi-use-reg;
+ qcom,gpu-quirk-secvid-set-once;
qcom,idle-timeout = <80>; //msecs
qcom,no-nap;
@@ -267,7 +268,8 @@
compatible = "qcom,kgsl-smmu-v2";
reg = <0x05040000 0x10000>;
- qcom,protect = <0x40000 0x10000>;
+ /* CB5(ATOS) & CB5/6/7 are protected by HYP */
+ qcom,protect = <0x40000 0xc000>;
qcom,micro-mmu-control = <0x6000>;
clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
@@ -288,7 +290,7 @@
gfx3d_secure: gfx3d_secure {
compatible = "qcom,smmu-kgsl-cb";
- iommus = <&kgsl_smmu 2>;
+ iommus = <&kgsl_smmu 2>, <&kgsl_smmu 1>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi b/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi
index cc609aa..1a8de22 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi
@@ -54,6 +54,18 @@
ibb-supply = <&lcdb_ncp_vreg>;
};
+&dsi_dual_nt35597_video_display {
+ vddio-supply = <&pm660_l11>;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+};
+
+&dsi_dual_nt35597_cmd_display {
+ vddio-supply = <&pm660_l11>;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+};
+
&sde_dp {
status = "disabled";
/delete-property/ vdda-1p2-supply;
@@ -230,12 +242,17 @@
&soc {
/delete-node/ gpio_keys;
+ qcom,mss@4080000 {
+ /delete-property/ vdd_mss-supply;
+ };
+
qcom,lpass@17300000 {
/delete-property/ vdd_cx-supply;
};
qcom,ssc@5c00000 {
/delete-property/ vdd_cx-supply;
+ /delete-property/ vdd_mx-supply;
};
qcom,spss@1880000 {
@@ -325,8 +342,6 @@
&soc {
/* Delete all regulators */
- /delete-node/ cprh-ctrl@17dc0000;
- /delete-node/ cprh-ctrl@17db0000;
/delete-node/ rpmh-regulator-ebilvl;
/delete-node/ rpmh-regulator-smpa2;
/delete-node/ rpmh-regulator-smpa3;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
index f0d16ec..48a4a8b 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi
@@ -164,6 +164,27 @@
qcom,platform-reset-gpio = <&tlmm 6 0>;
};
+&dsi_dual_nt35597_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_dual_nt35597_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+};
+
&dsi_nt35597_truly_dsc_cmd_display {
qcom,dsi-display-active;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi
index 322c5f5..daf5687 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi
@@ -214,7 +214,8 @@
qcom,smmu-sid-base = <0x1c10>;
- iommu-map = <0x100 &apps_smmu 0x1c11 0x1>,
+ iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
+ <0x100 &apps_smmu 0x1c11 0x1>,
<0x200 &apps_smmu 0x1c12 0x1>,
<0x300 &apps_smmu 0x1c13 0x1>,
<0x400 &apps_smmu 0x1c14 0x1>,
@@ -547,7 +548,8 @@
qcom,smmu-sid-base = <0x1c00>;
- iommu-map = <0x100 &apps_smmu 0x1c01 0x1>,
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>,
<0x200 &apps_smmu 0x1c02 0x1>,
<0x300 &apps_smmu 0x1c03 0x1>,
<0x400 &apps_smmu 0x1c04 0x1>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi b/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi
index 77495bf..810afde 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi
@@ -629,7 +629,7 @@
<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_spi_active>;
- pinctrl-1 = <&qupv3_se8_spi_sleep>;
+ pinctrl-1 = <&qupv3_se8_spi_active>;
interrupts = <GIC_SPI 353 0>;
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_1>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-qvr-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-qvr-overlay.dts
index 2fac9e8..fb99157 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-qvr-overlay.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-qvr-overlay.dts
@@ -19,6 +19,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "sdm845-sde-display.dtsi"
#include "sdm845-qvr.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/qcom/sdm845-qvr.dtsi b/arch/arm64/boot/dts/qcom/sdm845-qvr.dtsi
index d89722f..ae49fec 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-qvr.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-qvr.dtsi
@@ -14,11 +14,19 @@
#include "sdm845-pinctrl-overlay.dtsi"
#include "smb1355.dtsi"
+&vendor {
+ qvr_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "fg-gen3-batterydata-mlp446579-3800mah.dtsi"
+ };
+};
+
&pmi8998_pdphy {
vbus-supply = <&smb2_vbus>;
};
&pmi8998_fg {
+ qcom,battery-data = <&qvr_batterydata>;
qcom,fg-bmd-en-delay-ms = <300>;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi b/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi
index d22c28a..da4d41c 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi
@@ -29,690 +29,7 @@
};
};
-&spmi_bus {
- qcom,pm8998@1 {
- /* PM8998 S12 + S11 + S10 = VDD_APC1 supply */
- pm8998_s12: regulator@3500 {
- compatible = "qcom,qpnp-regulator";
- reg = <0x3500 0x100>;
- regulator-name = "pm8998_s12";
- regulator-min-microvolt = <568000>;
- regulator-max-microvolt = <1136000>;
- qcom,enable-time = <500>;
- regulator-always-on;
- };
-
- /* PM8998 S13 = VDD_APC0 supply */
- pm8998_s13: regulator@3800 {
- compatible = "qcom,qpnp-regulator";
- reg = <0x3800 0x100>;
- regulator-name = "pm8998_s13";
- regulator-min-microvolt = <568000>;
- regulator-max-microvolt = <996000>;
- qcom,enable-time = <500>;
- regulator-always-on;
- };
- };
-};
-
&soc {
- /* CPR controller regulators */
- apc0_cpr: cprh-ctrl@17dc0000 {
- compatible = "qcom,cprh-sdm845-v1-kbss-regulator";
- reg = <0x17dc0000 0x4000>,
- <0x00784000 0x1000>,
- <0x17840000 0x1000>;
- reg-names = "cpr_ctrl", "fuse_base", "saw";
- clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
- clock-names = "core_clk";
- qcom,cpr-ctrl-name = "apc0";
- qcom,cpr-controller-id = <0>;
-
- qcom,cpr-sensor-time = <1000>;
- qcom,cpr-loop-time = <5000000>;
- qcom,cpr-idle-cycles = <15>;
- qcom,cpr-up-down-delay-time = <3000>;
- qcom,cpr-step-quot-init-min = <11>;
- qcom,cpr-step-quot-init-max = <12>;
- qcom,cpr-count-mode = <0>; /* All at once */
- qcom,cpr-count-repeat = <20>;
- qcom,cpr-down-error-step-limit = <1>;
- qcom,cpr-up-error-step-limit = <1>;
- qcom,cpr-corner-switch-delay-time = <1042>;
- qcom,cpr-voltage-settling-time = <1760>;
- qcom,cpr-reset-step-quot-loop-en;
-
- qcom,voltage-step = <4000>;
- qcom,voltage-base = <352000>;
- qcom,cpr-saw-use-unit-mV;
-
- qcom,saw-avs-ctrl = <0x101C031>;
- qcom,saw-avs-limit = <0x3A003A0>;
-
- qcom,cpr-enable;
- qcom,cpr-hw-closed-loop;
-
- qcom,cpr-panic-reg-addr-list =
- <0x17dc3a84 0x17dc3a88 0x17840c18>;
- qcom,cpr-panic-reg-name-list =
- "APSS_SILVER_CPRH_STATUS_0",
- "APSS_SILVER_CPRH_STATUS_1",
- "SILVER_SAW4_PMIC_STS";
-
- qcom,cpr-aging-ref-voltage = <996000>;
- vdd-supply = <&pm8998_s13>;
-
- thread@1 {
- qcom,cpr-thread-id = <1>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc0_pwrcl_vreg: regulator {
- regulator-name = "apc0_pwrcl_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <19>;
-
- qcom,cpr-fuse-corners = <4>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <19 19 19>;
- qcom,cpr-corners = <19>;
-
- qcom,cpr-corner-fmax-map = <6 12 17 19>;
-
- qcom,cpr-voltage-ceiling =
- <872000 872000 872000 872000 872000
- 872000 872000 872000 872000 872000
- 872000 872000 872000 872000 872000
- 872000 928000 996000 996000>;
-
- qcom,cpr-voltage-floor =
- /* Speed bin 0 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 996000 996000>,
- /* Speed bin 1 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000>,
- /* Speed bin 2 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000>;
-
- qcom,corner-frequencies =
- /* Speed bin 0 */
- <300000000 422400000 499200000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1440000000
- 1516800000 1593600000 1651200000
- 1708800000>,
- /* Speed bin 1 */
- <300000000 422400000 499200000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1440000000
- 1516800000 1593600000 1651200000
- 1708800000>,
- /* Speed bin 2 */
- <300000000 422400000 499200000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1440000000
- 1516800000 1593600000 1670400000
- 1747200000>;
-
- qcom,cpr-ro-scaling-factor =
- <2594 2795 2576 2761 2469 2673 2198
- 2553 3188 3255 3191 2962 3055 2984
- 2043 2947>,
- <2594 2795 2576 2761 2469 2673 2198
- 2553 3188 3255 3191 2962 3055 2984
- 2043 2947>,
- <2259 2389 2387 2531 2294 2464 2218
- 2476 2525 2855 2817 2836 2740 2490
- 1950 2632>,
- <2259 2389 2387 2531 2294 2464 2218
- 2476 2525 2855 2817 2836 2740 2490
- 1950 2632>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- /* Speed bin 1 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- /* Speed bin 2 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- /* Speed bin 1 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- /* Speed bin 2 */
- <100000 100000 100000 100000>,
- < 0 0 0 100000>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>,
- < 0 0 0 0>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <19>;
- qcom,cpr-aging-ro-scaling-factor = <1620>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
-
- thread@0 {
- qcom,cpr-thread-id = <0>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc0_l3_vreg: regulator {
- regulator-name = "apc0_l3_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <13>;
-
- qcom,cpr-fuse-corners = <4>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <11 11 13>;
- qcom,cpr-corners =
- /* Speed bin 0 */
- <11 11 11 11 11 11 11 11>,
- /* Speed bin 1 */
- <11 11 11 11 11 11 11 11>,
- /* Speed bin 2 */
- <13 13 13 13 13 13 13 13>;
-
- qcom,cpr-corner-fmax-map =
- /* Speed bin 0 */
- <4 7 9 11>,
- /* Speed bin 1 */
- <4 7 9 11>,
- /* Speed bin 2 */
- <4 7 9 13>;
-
- qcom,cpr-voltage-ceiling =
- /* Speed bin 0 */
- <872000 872000 872000 872000 872000
- 872000 872000 872000 928000 996000
- 996000>,
- /* Speed bin 1 */
- <872000 872000 872000 872000 872000
- 872000 872000 872000 928000 996000
- 996000>,
- /* Speed bin 2 */
- <872000 872000 872000 872000 872000
- 872000 872000 872000 928000 996000
- 996000 996000 996000>;
-
- qcom,cpr-voltage-floor =
- /* Speed bin 0 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 996000
- 996000>,
- /* Speed bin 1 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000>,
- /* Speed bin 2 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- /* Speed bin 0 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 40000
- 40000>,
- /* Speed bin 1 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 40000
- 40000>,
- /* Speed bin 2 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 40000
- 40000 40000 40000>;
-
- qcom,corner-frequencies =
- /* Speed bin 0 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1094400000>,
- /* Speed bin 1 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1094400000>,
- /* Speed bin 2 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1113600000 1209600000
- 1305600000>;
-
- qcom,cpr-ro-scaling-factor =
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2439 2577 2552 2667 2461 2577 2394
- 2536 2132 2307 2191 2903 2838 2912
- 2501 2095>,
- <2439 2577 2552 2667 2461 2577 2394
- 2536 2132 2307 2191 2903 2838 2912
- 2501 2095>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000 100000>,
- < 0 24000 4000 100000>,
- < 0 24000 4000 0>,
- < 0 24000 4000 0>,
- < 0 24000 4000 0>,
- < 0 24000 4000 0>,
- < 0 24000 4000 0>,
- < 0 24000 4000 0>,
- /* Speed bin 1 */
- <100000 100000 100000 100000>,
- < 0 24000 4000 100000>,
- < 0 24000 4000 20000>,
- < 0 24000 4000 20000>,
- < 0 24000 4000 20000>,
- < 0 24000 4000 20000>,
- < 0 24000 4000 20000>,
- < 0 24000 4000 20000>,
- /* Speed bin 2 */
- <100000 100000 100000 100000>,
- < 0 24000 4000 100000>,
- < 0 24000 4000 40000>,
- < 0 24000 4000 40000>,
- < 0 24000 4000 40000>,
- < 0 24000 4000 40000>,
- < 0 24000 4000 40000>,
- < 0 24000 4000 40000>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000 100000>,
- < 0 29000 6000 100000>,
- < 0 29000 6000 0>,
- < 0 29000 6000 0>,
- < 0 29000 6000 0>,
- < 0 29000 6000 0>,
- < 0 29000 6000 0>,
- < 0 29000 6000 0>,
- /* Speed bin 1 */
- <100000 100000 100000 100000>,
- < 0 29000 6000 100000>,
- < 0 29000 6000 20000>,
- < 0 29000 6000 20000>,
- < 0 29000 6000 20000>,
- < 0 29000 6000 20000>,
- < 0 29000 6000 20000>,
- < 0 29000 6000 20000>,
- /* Speed bin 2 */
- <100000 100000 100000 100000>,
- < 0 29000 6000 100000>,
- < 0 29000 6000 40000>,
- < 0 29000 6000 40000>,
- < 0 29000 6000 40000>,
- < 0 29000 6000 40000>,
- < 0 29000 6000 40000>,
- < 0 29000 6000 40000>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <11 11 13>;
- qcom,cpr-aging-ro-scaling-factor = <1620>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
- };
-
- apc1_cpr: cprh-ctrl@17db0000 {
- compatible = "qcom,cprh-sdm845-v1-kbss-regulator";
- reg = <0x17db0000 0x4000>,
- <0x00784000 0x1000>,
- <0x17830000 0x1000>;
- reg-names = "cpr_ctrl", "fuse_base", "saw";
- clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
- clock-names = "core_clk";
- qcom,cpr-ctrl-name = "apc1";
- qcom,cpr-controller-id = <1>;
-
- qcom,cpr-sensor-time = <1000>;
- qcom,cpr-loop-time = <5000000>;
- qcom,cpr-idle-cycles = <15>;
- qcom,cpr-up-down-delay-time = <3000>;
- qcom,cpr-step-quot-init-min = <9>;
- qcom,cpr-step-quot-init-max = <14>;
- qcom,cpr-count-mode = <0>; /* All at once */
- qcom,cpr-count-repeat = <20>;
- qcom,cpr-down-error-step-limit = <1>;
- qcom,cpr-up-error-step-limit = <1>;
- qcom,cpr-corner-switch-delay-time = <1042>;
- qcom,cpr-voltage-settling-time = <1760>;
- qcom,cpr-reset-step-quot-loop-en;
-
- qcom,apm-threshold-voltage = <800000>;
- qcom,apm-crossover-voltage = <880000>;
- qcom,mem-acc-threshold-voltage = <852000>;
- qcom,mem-acc-crossover-voltage = <852000>;
-
- qcom,voltage-step = <4000>;
- qcom,voltage-base = <352000>;
- qcom,cpr-saw-use-unit-mV;
-
- qcom,saw-avs-ctrl = <0x101C031>;
- qcom,saw-avs-limit = <0x4200420>;
-
- qcom,cpr-enable;
- qcom,cpr-hw-closed-loop;
-
- qcom,cpr-panic-reg-addr-list =
- <0x17db3a84 0x17830c18>;
- qcom,cpr-panic-reg-name-list =
- "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS";
-
- qcom,cpr-aging-ref-voltage = <1136000>;
- vdd-supply = <&pm8998_s12>;
-
- thread@0 {
- qcom,cpr-thread-id = <0>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc1_perfcl_vreg: regulator {
- regulator-name = "apc1_perfcl_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <27>;
-
- qcom,cpr-fuse-corners = <3>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <22 24 25>;
- qcom,cpr-corners =
- /* Speed bin 0 */
- <22 22 22 22 22 22 22 22>,
- /* Speed bin 1 */
- <24 24 24 24 24 24 24 24>,
- /* Speed bin 2 */
- <25 25 25 25 25 25 25 25>;
-
- qcom,cpr-corner-fmax-map =
- /* Speed bin 0 */
- <10 17 22>,
- /* Speed bin 1 */
- <10 17 24>,
- /* Speed bin 2 */
- <10 17 25>;
-
- qcom,cpr-voltage-ceiling =
- /* Speed bin 0 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 884000 952000 952000
- 1136000 1136000>,
- /* Speed bin 1 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 884000 952000 952000
- 1136000 1136000 1136000 1136000>,
- /* Speed bin 2 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 884000 952000 952000
- 1136000 1136000 1136000 1136000
- 1136000>;
-
- qcom,cpr-voltage-floor =
- /* Speed bin 0 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000>,
- /* Speed bin 1 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000>,
- /* Speed bin 2 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000
- 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- /* Speed bin 0 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000 40000
- 40000 40000>,
- /* Speed bin 1 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000 40000
- 40000 40000 40000 40000>,
- /* Speed bin 2 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000 40000
- 40000 40000 40000 40000 40000>;
-
- qcom,corner-frequencies =
- /* Speed bin 0 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1113600000 1190400000
- 1267200000 1344000000 1420800000
- 1497600000 1574400000 1651200000
- 1728000000 1804800000 1881600000
- 1958400000>,
- /* Speed bin 1 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1113600000 1190400000
- 1267200000 1344000000 1420800000
- 1497600000 1574400000 1651200000
- 1728000000 1804800000 1881600000
- 1958400000 2035200000 2092800000>,
- /* Speed bin 2 */
- <300000000 422400000 499200000
- 576000000 652800000 729600000
- 806400000 883200000 960000000
- 1036800000 1113600000 1190400000
- 1267200000 1344000000 1420800000
- 1497600000 1574400000 1651200000
- 1728000000 1804800000 1881600000
- 1958400000 2035200000 2112000000
- 2208000000>;
-
- qcom,cpr-ro-scaling-factor =
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2086 2208 2273 2408 2203 2327 2213
- 2340 1755 2039 2049 2474 2437 2618
- 2003 1675>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- /* Speed bin 1 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- /* Speed bin 2 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- /* Speed bin 1 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- /* Speed bin 2 */
- <100000 100000 100000>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>,
- < 0 0 0>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <22 24 25>;
- qcom,cpr-aging-ro-scaling-factor = <1700>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
- };
-
/* RPMh regulators: */
/* PM8998 S1 = VDD_EBI supply */
@@ -854,11 +171,14 @@
<RPMH_REGULATOR_MODE_LDO_LPM
RPMH_REGULATOR_MODE_LDO_HPM>;
qcom,mode-threshold-currents = <0 1>;
+ proxy-supply = <&pm8998_l1>;
pm8998_l1: regulator-l1 {
regulator-name = "pm8998_l1";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <72000>;
qcom,init-voltage = <880000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_LDO_LPM>;
};
@@ -1103,9 +423,12 @@
<RPMH_REGULATOR_MODE_LDO_LPM
RPMH_REGULATOR_MODE_LDO_HPM>;
qcom,mode-threshold-currents = <0 10000>;
+ proxy-supply = <&pm8998_l14>;
pm8998_l14: regulator-l14 {
regulator-name = "pm8998_l14";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <115000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1880000>;
qcom,init-voltage = <1800000>;
@@ -1320,11 +643,14 @@
<RPMH_REGULATOR_MODE_LDO_LPM
RPMH_REGULATOR_MODE_LDO_HPM>;
qcom,mode-threshold-currents = <0 1>;
+ proxy-supply = <&pm8998_l26>;
pm8998_l26: regulator-l26 {
regulator-name = "pm8998_l26";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <43600>;
qcom,init-voltage = <1200000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_LDO_LPM>;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-rumi.dtsi b/arch/arm64/boot/dts/qcom/sdm845-rumi.dtsi
index d607f75..34de0a0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-rumi.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-rumi.dtsi
@@ -132,14 +132,6 @@
};
};
-&apc0_cpr {
- qcom,cpr-ignore-invalid-fuses;
-};
-
-&apc1_cpr {
- qcom,cpr-ignore-invalid-fuses;
-};
-
&pmi8998_charger {
qcom,suspend-input;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
index 4337da7..8c8d5d4 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi
@@ -25,6 +25,8 @@
#include "dsi-panel-sharp-1080p-cmd.dtsi"
#include "dsi-panel-sharp-dualmipi-1080p-120hz.dtsi"
#include "dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi"
+#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
+#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
&soc {
@@ -401,6 +403,54 @@
qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>;
};
+ dsi_dual_nt35597_video_display: qcom,dsi-display@14 {
+ compatible = "qcom,dsi-display";
+ label = "dsi_dual_nt35597_video_display";
+ qcom,display-type = "primary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
+ clock-names = "src_byte_clk", "src_pixel_clk";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+
+ qcom,dsi-panel = <&dsi_dual_nt35597_video>;
+ vddio-supply = <&pm8998_l14>;
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+ };
+
+
+ dsi_dual_nt35597_cmd_display: qcom,dsi-display@15 {
+ compatible = "qcom,dsi-display";
+ label = "dsi_dual_nt35597_cmd_display";
+ qcom,display-type = "primary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
+ clock-names = "src_byte_clk", "src_pixel_clk";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+
+ qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
+ vddio-supply = <&pm8998_l14>;
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+ };
+
sde_wb: qcom,wb-display@0 {
compatible = "qcom,wb-display";
cell-index = <0>;
@@ -660,3 +710,31 @@
};
};
};
+
+&dsi_dual_nt35597_video {
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
+ 05 03 04 00];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_nt35597_cmd {
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
+ 05 03 04 00];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
index e7a946c..4a7b634 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
@@ -55,10 +55,13 @@
qcom,sde-ctl-off = <0x2000 0x2200 0x2400
0x2600 0x2800>;
qcom,sde-ctl-size = <0xE4>;
+ qcom,sde-ctl-display-pref = "primary", "primary", "none",
+ "none", "none";
- qcom,sde-mixer-off = <0x45000 0x46000 0x47000
- 0x48000 0x49000 0x4a000>;
+ qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0 0 0x4a000>;
qcom,sde-mixer-size = <0x320>;
+ qcom,sde-mixer-display-pref = "primary", "primary", "none",
+ "none", "none", "none";
qcom,sde-dspp-top-off = <0x1300>;
qcom,sde-dspp-top-size = <0xc>;
@@ -207,6 +210,9 @@
qcom,sde-dspp-blocks {
qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
qcom,sde-dspp-gamut = <0x1000 0x00040000>;
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-usb.dtsi b/arch/arm64/boot/dts/qcom/sdm845-usb.dtsi
index 09f4efa..ba397e5 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-usb.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-usb.dtsi
@@ -78,6 +78,7 @@
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
usb-core-id = <0>;
};
@@ -387,6 +388,7 @@
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
usb-core-id = <1>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-cdp-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-cdp-overlay.dts
new file mode 100644
index 0000000..b7bc3dc
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-cdp-overlay.dts
@@ -0,0 +1,66 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-cdp.dtsi"
+#include "sdm845-cdp-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. sdm845 v2.1 4K Display Panel CDP";
+ compatible = "qcom,sdm845-cdp", "qcom,sdm845", "qcom,cdp";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <1 1>;
+};
+
+&dsi_nt35597_truly_dsc_cmd_display {
+ /delete-property/ qcom,dsi-display-active;
+};
+
+&mdss_mdp {
+ connectors = <&sde_rscc &sde_wb>;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_sharp_4k_dsc_video_display {
+ qcom,dsi-display-active;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-mtp-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-mtp-overlay.dts
new file mode 100644
index 0000000..95bd94b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-mtp-overlay.dts
@@ -0,0 +1,66 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-mtp.dtsi"
+#include "sdm845-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. sdm845 v2.1 4K Display Panel MTP";
+ compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <8 1>;
+};
+
+&dsi_nt35597_truly_dsc_cmd_display {
+ /delete-property/ qcom,dsi-display-active;
+};
+
+&mdss_mdp {
+ connectors = <&sde_rscc &sde_wb &sde_dp>;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+};
+
+&dsi_sharp_4k_dsc_video_display {
+ qcom,dsi-display-active;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-qrd-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-qrd-overlay.dts
new file mode 100644
index 0000000..42ccbf5
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-4k-panel-qrd-overlay.dts
@@ -0,0 +1,64 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-qrd.dtsi"
+#include "sdm845-qrd-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. sdm845 v2.1 4K Display Panel QRD";
+ compatible = "qcom,sdm845-qrd", "qcom,sdm845", "qcom,qrd";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <11 1>;
+};
+
+&dsi_nt35597_truly_dsc_cmd_display {
+ /delete-property/ qcom,dsi-display-active;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,mdss-dsi-panel-orientation = "180";
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-mode-gpio = <&tlmm 52 0>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&tlmm 6 0>;
+ qcom,mdss-dsi-panel-orientation = "180";
+};
+
+&dsi_sharp_4k_dsc_video_display {
+ qcom,dsi-display-active;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-cdp-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-cdp-overlay.dts
new file mode 100644
index 0000000..0825f4b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-cdp-overlay.dts
@@ -0,0 +1,31 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-cdp.dtsi"
+#include "sdm845-cdp-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 v2.1 CDP";
+ compatible = "qcom,sdm845-cdp", "qcom,sdm845", "qcom,cdp";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <1 0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-mtp-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-mtp-overlay.dts
new file mode 100644
index 0000000..7b3573a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-mtp-overlay.dts
@@ -0,0 +1,31 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-mtp.dtsi"
+#include "sdm845-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 v2.1 MTP";
+ compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <8 0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.1-qrd-overlay.dts b/arch/arm64/boot/dts/qcom/sdm845-v2.1-qrd-overlay.dts
new file mode 100644
index 0000000..15d79c2
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1-qrd-overlay.dts
@@ -0,0 +1,31 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm845-sde-display.dtsi"
+#include "sdm845-qrd.dtsi"
+#include "sdm845-qrd-audio-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 v2.1 QRD";
+ compatible = "qcom,sdm845-qrd", "qcom,sdm845", "qcom,qrd";
+ qcom,msm-id = <321 0x20001>;
+ qcom,board-id = <11 0>;
+};
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h b/arch/arm64/boot/dts/qcom/sdm845-v2.1.dts
similarity index 61%
rename from drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
rename to arch/arm64/boot/dts/qcom/sdm845-v2.1.dts
index 71b21b9..2902a60 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1.dts
@@ -10,19 +10,13 @@
* GNU General Public License for more details.
*/
-#ifndef CAM_JPEG_DMA_HW_INTF_H
-#define CAM_JPEG_DMA_HW_INTF_H
+/dts-v1/;
-#include <uapi/media/cam_defs.h>
-#include <media/cam_jpeg.h>
+#include "sdm845-v2.1.dtsi"
-#include "cam_hw_mgr_intf.h"
-#include "cam_jpeg_hw_intf.h"
-
-enum cam_jpeg_dma_cmd_type {
- CAM_JPEG_DMA_CMD_CDM_CFG,
- CAM_JPEG_DMA_CMD_SET_IRQ_CB,
- CAM_JPEG_DMA_CMD_MAX,
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 v2.1 SoC";
+ compatible = "qcom,sdm845";
+ qcom,board-id = <0 0>;
};
-#endif /* CAM_JPEG_DMA_HW_INTF_H */
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h b/arch/arm64/boot/dts/qcom/sdm845-v2.1.dtsi
similarity index 61%
copy from drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
copy to arch/arm64/boot/dts/qcom/sdm845-v2.1.dtsi
index 71b21b9..43c9f12 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_dma_hw_intf.h
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.1.dtsi
@@ -10,19 +10,14 @@
* GNU General Public License for more details.
*/
-#ifndef CAM_JPEG_DMA_HW_INTF_H
-#define CAM_JPEG_DMA_HW_INTF_H
+#include "sdm845-v2.dtsi"
+#include "sdm845-v2-camera.dtsi"
-#include <uapi/media/cam_defs.h>
-#include <media/cam_jpeg.h>
-
-#include "cam_hw_mgr_intf.h"
-#include "cam_jpeg_hw_intf.h"
-
-enum cam_jpeg_dma_cmd_type {
- CAM_JPEG_DMA_CMD_CDM_CFG,
- CAM_JPEG_DMA_CMD_SET_IRQ_CB,
- CAM_JPEG_DMA_CMD_MAX,
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 V2.1";
+ qcom,msm-id = <321 0x20001>;
};
-#endif /* CAM_JPEG_DMA_HW_INTF_H */
+&spmi_bus {
+ /delete-property/ qcom,enable-ahb-bus-workaround;
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi b/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi
index b3cb8f5..9343e2a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi
@@ -22,674 +22,11 @@
/delete-property/ qcom,sdr104-wa;
};
-/delete-node/ &apc0_cpr;
-/delete-node/ &apc1_cpr;
-
&tlmm {
compatible = "qcom,sdm845-pinctrl-v2";
};
&soc {
- /* CPR controller regulators */
- apc0_cpr: cprh-ctrl@17dc0000 {
- compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
- reg = <0x17dc0000 0x4000>,
- <0x00784000 0x1000>,
- <0x17840000 0x1000>;
- reg-names = "cpr_ctrl", "fuse_base", "saw";
- clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
- clock-names = "core_clk";
- qcom,cpr-ctrl-name = "apc0";
- qcom,cpr-controller-id = <0>;
-
- qcom,cpr-sensor-time = <1000>;
- qcom,cpr-loop-time = <5000000>;
- qcom,cpr-idle-cycles = <15>;
- qcom,cpr-up-down-delay-time = <3000>;
- qcom,cpr-step-quot-init-min = <11>;
- qcom,cpr-step-quot-init-max = <12>;
- qcom,cpr-count-mode = <0>; /* All at once */
- qcom,cpr-count-repeat = <20>;
- qcom,cpr-down-error-step-limit = <1>;
- qcom,cpr-up-error-step-limit = <1>;
- qcom,cpr-corner-switch-delay-time = <1042>;
- qcom,cpr-voltage-settling-time = <1760>;
- qcom,cpr-reset-step-quot-loop-en;
-
- qcom,voltage-step = <4000>;
- qcom,voltage-base = <352000>;
- qcom,cpr-saw-use-unit-mV;
-
- qcom,saw-avs-ctrl = <0x101C031>;
- qcom,saw-avs-limit = <0x3E803E8>;
-
- qcom,cpr-enable;
- qcom,cpr-hw-closed-loop;
-
- qcom,cpr-panic-reg-addr-list =
- <0x17dc3a84 0x17dc3a88 0x17840c18>;
- qcom,cpr-panic-reg-name-list =
- "APSS_SILVER_CPRH_STATUS_0",
- "APSS_SILVER_CPRH_STATUS_1",
- "SILVER_SAW4_PMIC_STS";
-
- qcom,cpr-aging-ref-voltage = <1000000>;
- vdd-supply = <&pm8998_s13>;
-
- thread@0 {
- qcom,cpr-thread-id = <0>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc0_pwrcl_vreg: regulator {
- regulator-name = "apc0_pwrcl_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <18>;
-
- qcom,cpr-fuse-corners = <4>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <18 18 18>;
- qcom,cpr-corners = <18>;
-
- qcom,cpr-corner-fmax-map = <6 12 15 18>;
-
- qcom,cpr-voltage-ceiling =
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 932000 1000000 1000000>;
-
- qcom,cpr-voltage-floor =
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 40000 40000>;
-
- qcom,corner-frequencies =
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1228800000
- 1324800000 1420800000 1516800000
- 1612800000 1689600000 1766400000>;
-
- qcom,cpr-ro-scaling-factor =
- <2594 2795 2576 2761 2469 2673 2198
- 2553 3188 3255 3191 2962 3055 2984
- 2043 2947>,
- <2594 2795 2576 2761 2469 2673 2198
- 2553 3188 3255 3191 2962 3055 2984
- 2043 2947>,
- <2259 2389 2387 2531 2294 2464 2218
- 2476 2525 2855 2817 2836 2740 2490
- 1950 2632>,
- <2259 2389 2387 2531 2294 2464 2218
- 2476 2525 2855 2817 2836 2740 2490
- 1950 2632>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 0 0 12000 12000>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- /* Speed bin 1 */
- < 0 0 12000 12000>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- /* Speed bin 2 */
- < 0 0 12000 12000>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>,
- <(-15000) (-15000) (-3000) (-3000)>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 0 0 12000 10000>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- /* Speed bin 1 */
- < 0 0 12000 10000>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- /* Speed bin 2 */
- < 0 0 12000 10000>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>,
- <(-15000) (-15000) (-3000) (-5000)>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <18>;
- qcom,cpr-aging-ro-scaling-factor = <1620>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
-
- thread@1 {
- qcom,cpr-thread-id = <1>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc0_l3_vreg: regulator {
- regulator-name = "apc0_l3_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <15>;
-
- qcom,cpr-fuse-corners = <4>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <14 15 15>;
- qcom,cpr-corners =
- /* Speed bin 0 */
- <14 14 14 14 14 14 14 14>,
- /* Speed bin 1 */
- <15 15 15 15 15 15 15 15>,
- /* Speed bin 2 */
- <15 15 15 15 15 15 15 15>;
-
- qcom,cpr-corner-fmax-map =
- /* Speed bin 0 */
- <4 8 11 14>,
- /* Speed bin 1 */
- <4 8 11 15>,
- /* Speed bin 2 */
- <4 8 11 15>;
-
- qcom,cpr-voltage-ceiling =
- /* Speed bin 0 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 932000 932000 1000000>,
- /* Speed bin 1 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 932000 932000 1000000
- 1000000>,
- /* Speed bin 2 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 932000 932000 1000000
- 1000000>;
-
- qcom,cpr-voltage-floor =
- /* Speed bin 0 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000>,
- /* Speed bin 1 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000
- 568000>,
- /* Speed bin 2 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000
- 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- /* Speed bin 0 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 40000>,
- /* Speed bin 1 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 40000 40000>,
- /* Speed bin 2 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 40000 40000>;
-
- qcom,corner-frequencies =
- /* Speed bin 0 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 844800000 940800000 1036800000
- 1132800000 1209600000 1305600000
- 1401600000 1478400000>,
- /* Speed bin 1 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 844800000 940800000 1036800000
- 1132800000 1209600000 1305600000
- 1401600000 1497600000 1593600000>,
- /* Speed bin 2 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 844800000 940800000 1036800000
- 1132800000 1209600000 1305600000
- 1401600000 1497600000 1593600000>;
-
- qcom,cpr-ro-scaling-factor =
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2439 2577 2552 2667 2461 2577 2394
- 2536 2132 2307 2191 2903 2838 2912
- 2501 2095>,
- <2439 2577 2552 2667 2461 2577 2394
- 2536 2132 2307 2191 2903 2838 2912
- 2501 2095>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 8000 16000 16000 12000>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- /* Speed bin 1 */
- < 8000 16000 16000 12000>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- /* Speed bin 2 */
- < 8000 16000 16000 12000>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>,
- < (-7000) 1000 1000 (-3000)>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 6000 14000 16000 12000>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- /* Speed bin 1 */
- < 6000 14000 16000 12000>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- /* Speed bin 2 */
- < 6000 14000 16000 12000>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>,
- < (-9000) (-1000) 1000 (-3000)>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <14 15 15>;
- qcom,cpr-aging-ro-scaling-factor = <1620>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
- };
-
- apc1_cpr: cprh-ctrl@17db0000 {
- compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
- reg = <0x17db0000 0x4000>,
- <0x00784000 0x1000>,
- <0x17830000 0x1000>;
- reg-names = "cpr_ctrl", "fuse_base", "saw";
- clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
- clock-names = "core_clk";
- qcom,cpr-ctrl-name = "apc1";
- qcom,cpr-controller-id = <1>;
-
- qcom,cpr-sensor-time = <1000>;
- qcom,cpr-loop-time = <5000000>;
- qcom,cpr-idle-cycles = <15>;
- qcom,cpr-up-down-delay-time = <3000>;
- qcom,cpr-step-quot-init-min = <9>;
- qcom,cpr-step-quot-init-max = <14>;
- qcom,cpr-count-mode = <0>; /* All at once */
- qcom,cpr-count-repeat = <20>;
- qcom,cpr-down-error-step-limit = <1>;
- qcom,cpr-up-error-step-limit = <1>;
- qcom,cpr-corner-switch-delay-time = <1042>;
- qcom,cpr-voltage-settling-time = <1760>;
- qcom,cpr-reset-step-quot-loop-en;
-
- qcom,apm-threshold-voltage = <800000>;
- qcom,apm-crossover-voltage = <880000>;
- qcom,mem-acc-threshold-voltage = <852000>;
- qcom,mem-acc-crossover-voltage = <852000>;
-
- qcom,voltage-step = <4000>;
- qcom,voltage-base = <352000>;
- qcom,cpr-saw-use-unit-mV;
-
- qcom,saw-avs-ctrl = <0x101C031>;
- qcom,saw-avs-limit = <0x4880488>;
-
- qcom,cpr-enable;
- qcom,cpr-hw-closed-loop;
-
- qcom,cpr-panic-reg-addr-list =
- <0x17db3a84 0x17830c18>;
- qcom,cpr-panic-reg-name-list =
- "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS";
-
- qcom,cpr-aging-ref-voltage = <1160000>;
- vdd-supply = <&pm8998_s12>;
-
- thread@0 {
- qcom,cpr-thread-id = <0>;
- qcom,cpr-consecutive-up = <0>;
- qcom,cpr-consecutive-down = <0>;
- qcom,cpr-up-threshold = <2>;
- qcom,cpr-down-threshold = <2>;
-
- apc1_perfcl_vreg: regulator {
- regulator-name = "apc1_perfcl_corner";
- regulator-min-microvolt = <1>;
- regulator-max-microvolt = <35>;
-
- qcom,cpr-fuse-corners = <5>;
- qcom,cpr-fuse-combos = <24>;
- qcom,cpr-speed-bins = <3>;
- qcom,cpr-speed-bin-corners = <28 31 33>;
- qcom,cpr-corners =
- /* Speed bin 0 */
- <28 28 28 28 28 28 28 28>,
- /* Speed bin 1 */
- <31 31 31 31 31 31 31 31>,
- /* Speed bin 2 */
- <33 33 33 33 33 33 33 33>;
-
- qcom,cpr-corner-fmax-map =
- /* Speed bin 0 */
- <7 14 22 27 28>,
- /* Speed bin 1 */
- <7 14 22 27 31>,
- /* Speed bin 2 */
- <7 14 22 30 33>;
-
- qcom,cpr-voltage-ceiling =
- /* Speed bin 0 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 932000 932000
- 932000 932000 1104000 1104000 1104000
- 1104000 1160000 1160000>,
- /* Speed bin 1 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 932000 932000
- 932000 932000 1104000 1104000 1104000
- 1104000 1160000 1160000 1160000 1160000
- 1160000>,
- /* Speed bin 2 */
- <828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 828000 828000
- 828000 828000 828000 932000 932000
- 932000 932000 1104000 1104000 1104000
- 1104000 1160000 1160000 1160000 1160000
- 1160000 1160000 1160000>;
-
- qcom,cpr-voltage-floor =
- /* Speed bin 0 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000>,
- /* Speed bin 1 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000>,
- /* Speed bin 2 */
- <568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000 568000 568000
- 568000 568000 568000>;
-
- qcom,cpr-floor-to-ceiling-max-range =
- /* Speed bin 0 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000>,
- /* Speed bin 1 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000 40000
- 40000>,
- /* Speed bin 2 */
- <32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 32000 32000 32000
- 32000 32000 40000 40000 40000
- 40000 40000 40000>;
-
- qcom,corner-frequencies =
- /* Speed bin 0 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1459200000
- 1536000000 1612800000 1689600000
- 1766400000 1843200000 1920000000
- 1996800000 2092800000 2169600000
- 2246400000 2323200000 2400000000
- 2400000000>,
- /* Speed bin 1 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1459200000
- 1536000000 1612800000 1689600000
- 1766400000 1843200000 1920000000
- 1996800000 2092800000 2169600000
- 2246400000 2323200000 2400000000
- 2476800000 2553600000 2649600000
- 2707200000>,
- /* Speed bin 2 */
- <300000000 403200000 480000000
- 576000000 652800000 748800000
- 825600000 902400000 979200000
- 1056000000 1132800000 1209600000
- 1286400000 1363200000 1459200000
- 1536000000 1612800000 1689600000
- 1766400000 1843200000 1920000000
- 1996800000 2092800000 2169600000
- 2246400000 2323200000 2400000000
- 2476800000 2553600000 2649600000
- 2707200000 2726400000 2745600000>;
-
- qcom,cpr-ro-scaling-factor =
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2857 3056 2828 2952 2699 2796 2447
- 2631 2630 2579 2244 3343 3287 3137
- 3164 2656>,
- <2086 2208 2273 2408 2203 2327 2213
- 2340 1755 2039 2049 2474 2437 2618
- 2003 1675>,
- <2086 2208 2273 2408 2203 2327 2213
- 2340 1755 2039 2049 2474 2437 2618
- 2003 1675>,
- <2086 2208 2273 2408 2203 2327 2213
- 2340 1755 2039 2049 2474 2437 2618
- 2003 1675>;
-
- qcom,cpr-open-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 8000 8000 8000 0 0>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- < (-7000) (-7000) (-7000) (-15000) (-15000)>,
- /* Speed bin 1 */
- < 8000 8000 8000 0 16000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- /* Speed bin 2 */
- < 8000 8000 8000 0 16000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>,
- < (-7000) (-7000) (-7000) (-15000) 1000>;
-
- qcom,cpr-closed-loop-voltage-fuse-adjustment =
- /* Speed bin 0 */
- < 6000 6000 8000 0 0>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- < (-9000) (-9000) (-7000) (-15000) (-15000)>,
- /* Speed bin 1 */
- < 6000 6000 8000 0 16000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- /* Speed bin 2 */
- < 6000 6000 8000 0 16000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>,
- < (-9000) (-9000) (-7000) (-15000) 1000>;
-
- qcom,allow-voltage-interpolation;
- qcom,allow-quotient-interpolation;
- qcom,cpr-scaled-open-loop-voltage-as-ceiling;
-
- qcom,cpr-aging-max-voltage-adjustment = <15000>;
- qcom,cpr-aging-ref-corner = <27 31 33>;
- qcom,cpr-aging-ro-scaling-factor = <1700>;
- qcom,allow-aging-voltage-adjustment =
- /* Speed bin 0 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 1 */
- <0 1 1 1 1 1 1 1>,
- /* Speed bin 2 */
- <0 1 1 1 1 1 1 1>;
- qcom,allow-aging-open-loop-voltage-adjustment =
- <1>;
- };
- };
- };
-
gpu_gx_domain_addr: syscon@0x5091508 {
compatible = "syscon";
reg = <0x5091508 0x4>;
@@ -705,244 +42,8 @@
qcom,mss_pdc_offset = <9>;
};
-/* VDD_APC0 */
-&pm8998_s13 {
- regulator-min-microvolt = <568000>;
- regulator-max-microvolt = <1000000>;
-};
-
-/* VDD_APC1 */
-&pm8998_s12 {
- regulator-min-microvolt = <568000>;
- regulator-max-microvolt = <1160000>;
-};
-
&clock_cpucc {
compatible = "qcom,clk-cpu-osm-v2";
-
- vdd-l3-supply = <&apc0_l3_vreg>;
- vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
- vdd-perfcl-supply = <&apc1_perfcl_vreg>;
-
- qcom,l3-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 844800000 0x4024062c 0x00002323 0x2 7 >,
- < 940800000 0x40240731 0x00002727 0x2 8 >,
- < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
- < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
- < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
- < 1305600000 0x40340b44 0x00003636 0x2 12 >,
- < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
- < 1478400000 0x403c0d4d 0x00003e3e 0x2 14 >;
-
- qcom,l3-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 844800000 0x4024062c 0x00002323 0x2 7 >,
- < 940800000 0x40240731 0x00002727 0x2 8 >,
- < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
- < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
- < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
- < 1305600000 0x40340b44 0x00003636 0x2 12 >,
- < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
- < 1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,
- < 1593600000 0x403c0e53 0x00004242 0x2 15 >;
-
- qcom,l3-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 844800000 0x4024062c 0x00002323 0x2 7 >,
- < 940800000 0x40240731 0x00002727 0x2 8 >,
- < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
- < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
- < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
- < 1305600000 0x40340b44 0x00003636 0x2 12 >,
- < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
- < 1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,
- < 1593600000 0x403c0e53 0x00004242 0x2 15 >;
-
- qcom,pwrcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
- < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
- < 1324800000 0x40340c45 0x00003737 0x2 13 >,
- < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
- < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
- < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
- < 1689600000 0x40441058 0x00004646 0x2 17 >,
- < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
-
- qcom,pwrcl-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
- < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
- < 1324800000 0x40340c45 0x00003737 0x2 13 >,
- < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
- < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
- < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
- < 1689600000 0x40441058 0x00004646 0x2 17 >,
- < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
-
- qcom,pwrcl-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
- < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
- < 1324800000 0x40340c45 0x00003737 0x2 13 >,
- < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
- < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
- < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
- < 1689600000 0x40441058 0x00004646 0x2 17 >,
- < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
-
- qcom,perfcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
- < 1286400000 0x40340c43 0x00003636 0x2 13 >,
- < 1363200000 0x40340d47 0x00003939 0x2 14 >,
- < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
- < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
- < 1612800000 0x403c1054 0x00004343 0x2 17 >,
- < 1689600000 0x40441158 0x00004646 0x2 18 >,
- < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
- < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
- < 1920000000 0x404c1464 0x00005050 0x2 21 >,
- < 1996800000 0x404c1568 0x00005353 0x2 22 >,
- < 2092800000 0x4054166d 0x00005757 0x2 23 >,
- < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
- < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
- < 2323200000 0x40541979 0x00006161 0x2 26 >,
- < 2400000000 0x40541a7d 0x00006464 0x2 27 >;
-
- qcom,perfcl-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
- < 1286400000 0x40340c43 0x00003636 0x2 13 >,
- < 1363200000 0x40340d47 0x00003939 0x2 14 >,
- < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
- < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
- < 1612800000 0x403c1054 0x00004343 0x2 17 >,
- < 1689600000 0x40441158 0x00004646 0x2 18 >,
- < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
- < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
- < 1920000000 0x404c1464 0x00005050 0x2 21 >,
- < 1996800000 0x404c1568 0x00005353 0x2 22 >,
- < 2092800000 0x4054166d 0x00005757 0x2 23 >,
- < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
- < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
- < 2323200000 0x40541979 0x00006161 0x2 26 >,
- < 2400000000 0x40541a7d 0x00006464 0x2 27 >,
- < 2476800000 0x40541b81 0x00006767 0x2 28 >,
- < 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
- < 2649600000 0x40541d8a 0x00006e6e 0x2 30 >,
- < 2745600000 0x40511e8f 0x00007272 0x2 31 >;
-
- qcom,perfcl-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 403200000 0x500c0115 0x00002020 0x1 2 >,
- < 480000000 0x50140219 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
- < 1286400000 0x40340c43 0x00003636 0x2 13 >,
- < 1363200000 0x40340d47 0x00003939 0x2 14 >,
- < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
- < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
- < 1612800000 0x403c1054 0x00004343 0x2 17 >,
- < 1689600000 0x40441158 0x00004646 0x2 18 >,
- < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
- < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
- < 1920000000 0x404c1464 0x00005050 0x2 21 >,
- < 1996800000 0x404c1568 0x00005353 0x2 22 >,
- < 2092800000 0x4054166d 0x00005757 0x2 23 >,
- < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
- < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
- < 2323200000 0x40541979 0x00006161 0x2 26 >,
- < 2400000000 0x40541a7d 0x00006464 0x2 27 >,
- < 2476800000 0x40541b81 0x00006767 0x2 28 >,
- < 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
- < 2649600000 0x40541d8a 0x00006e6e 0x2 30 >,
- < 2707200000 0x40511e8d 0x00007171 0x2 30 >,
- < 2764800000 0x40511f90 0x00007373 0x2 31 >,
- < 2784000000 0x40512091 0x00007474 0x2 32 >,
- < 2803200000 0x40512192 0x00007575 0x2 33 >;
-
- qcom,l3-memacc-level-vc-bin0 = <8 13>;
- qcom,l3-memacc-level-vc-bin1 = <8 13>;
- qcom,l3-memacc-level-vc-bin2 = <8 13>;
-
- qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;
- qcom,pwrcl-memacc-level-vc-bin1 = <12 16>;
- qcom,pwrcl-memacc-level-vc-bin2 = <12 16>;
-
- qcom,perfcl-memacc-level-vc-bin0 = <14 22>;
- qcom,perfcl-memacc-level-vc-bin1 = <14 22>;
- qcom,perfcl-memacc-level-vc-bin2 = <14 22>;
};
&pcie1 {
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 359c53a..a2b5248 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -610,6 +610,11 @@
size = <0 0x800000>;
};
+ cont_splash_memory: cont_splash_region@9d400000 {
+ reg = <0x0 0x9d400000 0x0 0x02400000>;
+ label = "cont_splash_region";
+ };
+
secure_display_memory: secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
@@ -1207,267 +1212,14 @@
compatible = "qcom,clk-cpu-osm";
reg = <0x17d41000 0x1400>,
<0x17d43000 0x1400>,
- <0x17d45800 0x1400>,
- <0x178d0000 0x1000>,
- <0x178c0000 0x1000>,
- <0x178b0000 0x1000>,
- <0x17d42400 0x0c00>,
- <0x17d44400 0x0c00>,
- <0x17d46c00 0x0c00>,
- <0x00784130 0x4>,
- <0x00784130 0x4>,
- <0x00784130 0x4>;
- reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base",
- "l3_pll", "pwrcl_pll", "perfcl_pll", "l3_sequencer",
- "pwrcl_sequencer", "perfcl_sequencer", "l3_efuse",
- "pwrcl_efuse", "perfcl_efuse";
+ <0x17d45800 0x1400>;
+ reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
- vdd-l3-supply = <&apc0_l3_vreg>;
- vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
- vdd-perfcl-supply = <&apc1_perfcl_vreg>;
-
- l3-dev0 = <&l3_cpu0>;
- l3-dev4 = <&l3_cpu4>;
-
- qcom,l3-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >;
-
- qcom,l3-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1094400000 0x402c0a39 0x00002e2e 0x1 11 >;
-
- qcom,l3-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x1 12 >,
- < 1305600000 0x40340c44 0x00003636 0x1 13 >;
-
- qcom,pwrcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x1 12 >,
- < 1286400000 0x40340c43 0x00003636 0x1 13 >,
- < 1363200000 0x40340d47 0x00003939 0x1 14 >,
- < 1440000000 0x40340e4b 0x00003c3c 0x1 15 >,
- < 1516800000 0x403c0f4f 0x00003f3f 0x1 16 >,
- < 1593600000 0x403c1053 0x00004242 0x1 17 >;
-
- qcom,pwrcl-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x1 12 >,
- < 1286400000 0x40340c43 0x00003636 0x1 13 >,
- < 1363200000 0x40340d47 0x00003939 0x1 14 >,
- < 1440000000 0x40340e4b 0x00003c3c 0x1 15 >,
- < 1516800000 0x403c0f4f 0x00003f3f 0x1 16 >,
- < 1593600000 0x403c1053 0x00004242 0x1 17 >,
- < 1651200000 0x403c1156 0x00004545 0x1 18 >,
- < 1708800000 0x40441259 0x00004747 0x1 19 >;
-
- qcom,pwrcl-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 748800000 0x401c0527 0x00002020 0x1 6 >,
- < 825600000 0x401c062b 0x00002222 0x1 7 >,
- < 902400000 0x4024072f 0x00002626 0x1 8 >,
- < 979200000 0x40240833 0x00002929 0x1 9 >,
- < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
- < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
- < 1209600000 0x402c0b3f 0x00003232 0x1 12 >,
- < 1286400000 0x40340c43 0x00003636 0x1 13 >,
- < 1363200000 0x40340d47 0x00003939 0x1 14 >,
- < 1440000000 0x40340e4b 0x00003c3c 0x1 15 >,
- < 1516800000 0x403c0f4f 0x00003f3f 0x1 16 >,
- < 1593600000 0x403c1053 0x00004242 0x1 17 >,
- < 1670400000 0x40441157 0x00004646 0x1 18 >,
- < 1747200000 0x4044125b 0x00004949 0x1 19 >;
-
- qcom,perfcl-speedbin0-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
- < 1190400000 0x402c0b3e 0x00003232 0x1 12 >,
- < 1267200000 0x40340c42 0x00003535 0x1 13 >,
- < 1344000000 0x40340d46 0x00003838 0x1 14 >,
- < 1420800000 0x40340e4a 0x00003b3b 0x1 15 >,
- < 1497600000 0x403c0f4e 0x00003e3e 0x1 16 >,
- < 1574400000 0x403c1052 0x00004242 0x1 17 >,
- < 1651200000 0x403c1156 0x00004545 0x1 18 >,
- < 1728000000 0x4044125a 0x00004848 0x1 19 >,
- < 1804800000 0x4044135e 0x00004b4b 0x1 20 >,
- < 1881600000 0x404c1462 0x00004e4e 0x1 21 >,
- < 1958400000 0x404c1566 0x00005252 0x1 22 >;
-
- qcom,perfcl-speedbin1-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
- < 1190400000 0x402c0b3e 0x00003232 0x1 12 >,
- < 1267200000 0x40340c42 0x00003535 0x1 13 >,
- < 1344000000 0x40340d46 0x00003838 0x1 14 >,
- < 1420800000 0x40340e4a 0x00003b3b 0x1 15 >,
- < 1497600000 0x403c0f4e 0x00003e3e 0x1 16 >,
- < 1574400000 0x403c1052 0x00004242 0x1 17 >,
- < 1651200000 0x403c1156 0x00004545 0x1 18 >,
- < 1728000000 0x4044125a 0x00004848 0x1 19 >,
- < 1804800000 0x4044135e 0x00004b4b 0x1 20 >,
- < 1881600000 0x404c1462 0x00004e4e 0x1 21 >,
- < 1958400000 0x404c1566 0x00005252 0x1 22 >,
- < 2035200000 0x404c166a 0x00005555 0x1 23 >,
- < 2092800000 0x4054176d 0x00005757 0x1 24 >;
-
- qcom,perfcl-speedbin2-v0 =
- < 300000000 0x000c000f 0x00002020 0x1 1 >,
- < 422400000 0x50140116 0x00002020 0x1 2 >,
- < 499200000 0x5014021a 0x00002020 0x1 3 >,
- < 576000000 0x5014031e 0x00002020 0x1 4 >,
- < 652800000 0x401c0422 0x00002020 0x1 5 >,
- < 729600000 0x401c0526 0x00002020 0x1 6 >,
- < 806400000 0x401c062a 0x00002222 0x1 7 >,
- < 883200000 0x4024072e 0x00002525 0x1 8 >,
- < 960000000 0x40240832 0x00002828 0x1 9 >,
- < 1036800000 0x40240936 0x00002b2b 0x1 10 >,
- < 1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
- < 1190400000 0x402c0b3e 0x00003232 0x1 12 >,
- < 1267200000 0x40340c42 0x00003535 0x1 13 >,
- < 1344000000 0x40340d46 0x00003838 0x1 14 >,
- < 1420800000 0x40340e4a 0x00003b3b 0x1 15 >,
- < 1497600000 0x403c0f4e 0x00003e3e 0x1 16 >,
- < 1574400000 0x403c1052 0x00004242 0x1 17 >,
- < 1651200000 0x403c1156 0x00004545 0x1 18 >,
- < 1728000000 0x4044125a 0x00004848 0x1 19 >,
- < 1804800000 0x4044135e 0x00004b4b 0x1 20 >,
- < 1881600000 0x404c1462 0x00004e4e 0x1 21 >,
- < 1958400000 0x404c1566 0x00005252 0x1 22 >,
- < 2035200000 0x404c166a 0x00005555 0x1 23 >,
- < 2112000000 0x4054176e 0x00005858 0x1 24 >,
- < 2208000000 0x40541873 0x00005c5c 0x1 25 >;
-
- qcom,l3-memacc-level-vc-bin0 = <7 63>;
- qcom,l3-memacc-level-vc-bin1 = <7 9>;
- qcom,l3-memacc-level-vc-bin2 = <7 9>;
-
- qcom,pwrcl-memacc-level-vc-bin0 = <12 63>;
- qcom,pwrcl-memacc-level-vc-bin1 = <12 17>;
- qcom,pwrcl-memacc-level-vc-bin2 = <12 17>;
-
- qcom,perfcl-memacc-level-vc-bin0 = <12 18>;
- qcom,perfcl-memacc-level-vc-bin1 = <12 18>;
- qcom,perfcl-memacc-level-vc-bin2 = <12 18>;
-
- qcom,up-timer =
- <1000 1000 1000>;
- qcom,down-timer =
- <100000 100000 100000>;
- qcom,set-ret-inactive;
- qcom,enable-llm-freq-vote;
- qcom,llm-freq-up-timer =
- <1000 1000 1000>;
- qcom,llm-freq-down-timer =
- <327675 327675 327675>;
- qcom,enable-llm-volt-vote;
- qcom,llm-volt-up-timer =
- <1000 1000 1000>;
- qcom,llm-volt-down-timer =
- <327675 327675 327675>;
- qcom,cc-reads = <10>;
- qcom,cc-delay = <5>;
- qcom,cc-factor = <100>;
- qcom,osm-clk-rate = <100000000>;
- qcom,xo-clk-rate = <19200000>;
-
- qcom,l-val-base =
- <0x178d0004 0x178c0004 0x178b0004>;
- qcom,apcs-pll-user-ctl =
- <0x178d000c 0x178c000c 0x178b000c>;
- qcom,apcs-pll-min-freq =
- <0x17d41094 0x17d43094 0x17d45894>;
- qcom,apm-mode-ctl =
- <0x0 0x0 0x17d20010>;
- qcom,apm-status-ctrl =
- <0x0 0x0 0x17d20000>;
- qcom,perfcl-isense-addr = <0x17871480>;
- qcom,l3-mem-acc-addr = <0x17990170 0x17990170 0x17990170>;
- qcom,pwrcl-mem-acc-addr = <0x17990160 0x17990164 0x17990164>;
- qcom,perfcl-mem-acc-addr = <0x17990168 0x1799016c 0x1799016c>;
- qcom,cfg-gfmux-addr =<0x178d0084 0x178c0084 0x178b0084>;
- qcom,apcs-cbc-addr = <0x178d008c 0x178c008c 0x178b008c>;
- qcom,apcs-ramp-ctl-addr = <0x17840904 0x17840904 0x17830904>;
-
- qcom,perfcl-apcs-apm-threshold-voltage = <800000>;
- qcom,perfcl-apcs-mem-acc-threshold-voltage = <852000>;
- qcom,boost-fsm-en;
- qcom,safe-fsm-en;
- qcom,ps-fsm-en;
- qcom,droop-fsm-en;
+ l3-devs = <&l3_cpu0 &l3_cpu4>;
clock-names = "xo_ao";
clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
#clock-cells = <1>;
- #reset-cells = <1>;
};
clock_debug: qcom,cc-debug@100000 {
@@ -1573,6 +1325,7 @@
<0 0>,
<0 0>;
+ non-removable;
qcom,msm-bus,name = "ufshc_mem";
qcom,msm-bus,num-cases = <22>;
qcom,msm-bus,num-paths = <2>;
@@ -1727,6 +1480,8 @@
vdd_cx-voltage = <RPMH_REGULATOR_LEVEL_TURBO>;
vdd_mx-supply = <&pm8998_s6_level>;
vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
+ vdd_mss-supply = <&pm8005_s2_level>;
+ vdd_mss-uV = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,firmware-name = "modem";
qcom,pil-self-auth;
qcom,sysmon-id = <0>;
@@ -1800,7 +1555,9 @@
vdd_cx-supply = <&pm8998_l27_level>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
- qcom,proxy-reg-names = "vdd_cx";
+ vdd_mx-supply = <&pm8998_l4_level>;
+ qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ qcom,proxy-reg-names = "vdd_cx", "vdd_mx";
qcom,keep-proxy-regs-on;
clocks = <&clock_rpmh RPMH_CXO_CLK>;
@@ -2797,6 +2554,7 @@
reg = <0x0 0x200000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
+ qcom,guard-memory;
};
qcom,rmnet-ipa {
@@ -2824,7 +2582,6 @@
qcom,ipa-wdi2;
qcom,use-64-bit-dma-mask;
qcom,arm-smmu;
- qcom,smmu-s1-bypass;
qcom,bandwidth-vote-for-ipa;
qcom,msm-bus,name = "ipa";
qcom,msm-bus,num-cases = <5>;
@@ -2949,15 +2706,23 @@
compatible = "qcom,ipa-smmu-ap-cb";
iommus = <&apps_smmu 0x720 0x0>;
qcom,iova-mapping = <0x20000000 0x40000000>;
+ qcom,additional-mapping =
+ /* modem tables in IMEM */
+ <0x146BD000 0x146BD000 0x2000>;
};
ipa_smmu_wlan: ipa_smmu_wlan {
compatible = "qcom,ipa-smmu-wlan-cb";
+ qcom,smmu-s1-bypass;
iommus = <&apps_smmu 0x721 0x0>;
+ qcom,additional-mapping =
+ /* ipa-uc ram */
+ <0x1E60000 0x1E60000 0x80000>;
};
ipa_smmu_uc: ipa_smmu_uc {
compatible = "qcom,ipa-smmu-uc-cb";
+ qcom,smmu-s1-bypass;
iommus = <&apps_smmu 0x722 0x0>;
qcom,iova-mapping = <0x40000000 0x20000000>;
};
diff --git a/arch/arm64/configs/sdm670-perf_defconfig b/arch/arm64/configs/sdm670-perf_defconfig
index 901143b..fa397c8 100644
--- a/arch/arm64/configs/sdm670-perf_defconfig
+++ b/arch/arm64/configs/sdm670-perf_defconfig
@@ -282,6 +282,7 @@
# CONFIG_WIL6210_TRACING is not set
CONFIG_WCNSS_MEM_PRE_ALLOC=y
CONFIG_CLD_LL_CORE=y
+CONFIG_CNSS_GENL=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
@@ -529,7 +530,6 @@
CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_PM=y
CONFIG_MSM_QBT1000=y
-CONFIG_APSS_CORE_EA=y
CONFIG_QTI_RPM_STATS_LOG=y
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
CONFIG_QMP_DEBUGFS_CLIENT=y
diff --git a/arch/arm64/configs/sdm670_defconfig b/arch/arm64/configs/sdm670_defconfig
index 1e9c191..c4295db 100644
--- a/arch/arm64/configs/sdm670_defconfig
+++ b/arch/arm64/configs/sdm670_defconfig
@@ -287,6 +287,7 @@
CONFIG_WIL6210=m
CONFIG_WCNSS_MEM_PRE_ALLOC=y
CONFIG_CLD_LL_CORE=y
+CONFIG_CNSS_GENL=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
@@ -446,8 +447,6 @@
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_KRYO3XX_ARM64=y
CONFIG_EDAC_KRYO3XX_ARM64_PANIC_ON_UE=y
-CONFIG_EDAC_QCOM_LLCC=y
-CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_QPNP=y
CONFIG_DMADEVICES=y
@@ -536,7 +535,6 @@
CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_PM=y
CONFIG_MSM_QBT1000=y
-CONFIG_APSS_CORE_EA=y
CONFIG_QCOM_DCC_V2=y
CONFIG_QTI_RPM_STATS_LOG=y
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
diff --git a/arch/arm64/configs/sdm845-perf_defconfig b/arch/arm64/configs/sdm845-perf_defconfig
index 3c5b65c..efdbfb4 100644
--- a/arch/arm64/configs/sdm845-perf_defconfig
+++ b/arch/arm64/configs/sdm845-perf_defconfig
@@ -344,7 +344,6 @@
CONFIG_MFD_SPMI_PMIC=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_PROXY_CONSUMER=y
-CONFIG_REGULATOR_CPRH_KBSS=y
CONFIG_REGULATOR_QPNP_LABIBB=y
CONFIG_REGULATOR_QPNP=y
CONFIG_REGULATOR_REFGEN=y
@@ -527,7 +526,6 @@
CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_PM=y
CONFIG_MSM_QBT1000=y
-CONFIG_APSS_CORE_EA=y
CONFIG_QTI_RPM_STATS_LOG=y
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
CONFIG_QMP_DEBUGFS_CLIENT=y
diff --git a/arch/arm64/configs/sdm845_defconfig b/arch/arm64/configs/sdm845_defconfig
index 09f81c0..5acd093 100644
--- a/arch/arm64/configs/sdm845_defconfig
+++ b/arch/arm64/configs/sdm845_defconfig
@@ -301,6 +301,8 @@
# CONFIG_SERIO_SERPORT is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVMEM is not set
+# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_MSM_GENI=y
CONFIG_SERIAL_MSM_GENI_CONSOLE=y
CONFIG_DIAG_CHAR=y
@@ -352,7 +354,6 @@
CONFIG_MFD_SPMI_PMIC=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_PROXY_CONSUMER=y
-CONFIG_REGULATOR_CPRH_KBSS=y
CONFIG_REGULATOR_QPNP_LABIBB=y
CONFIG_REGULATOR_QPNP=y
CONFIG_REGULATOR_REFGEN=y
@@ -545,7 +546,6 @@
CONFIG_MSM_EVENT_TIMER=y
CONFIG_MSM_PM=y
CONFIG_MSM_QBT1000=y
-CONFIG_APSS_CORE_EA=y
CONFIG_QCOM_DCC_V2=y
CONFIG_QTI_RPM_STATS_LOG=y
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index b325f74..c1e932d 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1161,8 +1161,8 @@
{
int ret;
- ret = cpuhp_setup_state_nocalls(CPUHP_AP_NOTIFY_ONLINE,
- "PERF_EVENT/CPUHP_AP_NOTIFY_ONLINE",
+ ret = cpuhp_setup_state_nocalls(CPUHP_AP_NOTIFY_PERF_ONLINE,
+ "PERF_EVENT/CPUHP_AP_NOTIFY_PERF_ONLINE",
perf_event_hotplug_coming_up,
perf_event_hotplug_going_down);
if (ret)
diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c
index 3868665..9701cc2 100644
--- a/drivers/block/zram/zram_drv.c
+++ b/drivers/block/zram/zram_drv.c
@@ -41,6 +41,12 @@
static int zram_major;
static const char *default_compressor = "lzo";
+/*
+ * We don't need to see memory allocation errors more than once every 1
+ * second to know that a problem is occurring.
+ */
+#define ALLOC_ERROR_LOG_RATE_MS 1000
+
/* Module params (documentation at end) */
static unsigned int num_devices = 1;
@@ -668,6 +674,7 @@
struct zram_meta *meta = zram->meta;
struct zcomp_strm *zstrm = NULL;
unsigned long alloced_pages;
+ static unsigned long zram_rs_time;
page = bvec->bv_page;
if (is_partial_io(bvec)) {
@@ -761,8 +768,10 @@
if (handle)
goto compress_again;
- pr_err("Error allocating memory for compressed page: %u, size=%u\n",
- index, clen);
+ if (printk_timed_ratelimit(&zram_rs_time,
+ ALLOC_ERROR_LOG_RATE_MS))
+ pr_err("Error allocating memory for compressed page: %u, size=%u\n",
+ index, clen);
ret = -ENOMEM;
goto out;
}
diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c
index 876ed90..9e762d9 100644
--- a/drivers/char/adsprpc.c
+++ b/drivers/char/adsprpc.c
@@ -61,6 +61,7 @@
#define M_FDLIST (16)
#define M_CRCLIST (64)
#define SESSION_ID_INDEX (30)
+#define FASTRPC_CTX_MAGIC (0xbeeddeed)
#define IS_CACHE_ALIGNED(x) (((x) & ((L1_CACHE_BYTES)-1)) == 0)
@@ -76,6 +77,9 @@
#define FASTRPC_STATIC_HANDLE_MAX (20)
#define FASTRPC_LATENCY_CTRL_ENB (1)
+#define INIT_FILELEN_MAX (2*1024*1024)
+#define INIT_MEMLEN_MAX (8*1024*1024)
+
#define PERF_END (void)0
#define PERF(enb, cnt, ff) \
@@ -176,6 +180,7 @@
struct overlap **overps;
struct smq_msg msg;
uint32_t *crc;
+ unsigned int magic;
};
struct fastrpc_ctx_lst {
@@ -864,6 +869,7 @@
ctx->pid = current->pid;
ctx->tgid = fl->tgid;
init_completion(&ctx->work);
+ ctx->magic = FASTRPC_CTX_MAGIC;
spin_lock(&fl->hlock);
hlist_add_head(&ctx->hn, &clst->pending);
@@ -899,6 +905,7 @@
for (i = 0; i < nbufs; ++i)
fastrpc_mmap_free(ctx->maps[i]);
fastrpc_buf_free(ctx->buf, 1);
+ ctx->magic = 0;
kfree(ctx);
}
@@ -1089,9 +1096,10 @@
list[i].pgidx = ipage - pages;
ipage++;
}
+
/* map ion buffers */
PERF(ctx->fl->profile, ctx->fl->perf.map,
- for (i = 0; i < inbufs + outbufs; ++i) {
+ for (i = 0; rpra && i < inbufs + outbufs; ++i) {
struct fastrpc_mmap *map = ctx->maps[i];
uint64_t buf = ptr_to_uint64(lpra[i].buf.pv);
ssize_t len = lpra[i].buf.len;
@@ -1199,7 +1207,7 @@
uint64_to_ptr(rpra[i].buf.pv + rpra[i].buf.len));
}
PERF_END);
- for (i = bufs; i < bufs + handles; i++) {
+ for (i = bufs; rpra && i < bufs + handles; i++) {
rpra[i].dma.fd = ctx->fds[i];
rpra[i].dma.len = (uint32_t)lpra[i].buf.len;
rpra[i].dma.offset = (uint32_t)(uintptr_t)lpra[i].buf.pv;
@@ -1487,8 +1495,7 @@
if (fl->profile && !interrupted) {
if (invoke->handle != FASTRPC_STATIC_HANDLE_LISTENER)
fl->perf.invoke += getnstimediff(&invoket);
- if (!(invoke->handle >= 0 &&
- invoke->handle <= FASTRPC_STATIC_HANDLE_MAX))
+ if (invoke->handle > FASTRPC_STATIC_HANDLE_MAX)
fl->perf.count++;
}
return err;
@@ -1547,6 +1554,7 @@
if (err)
goto bail;
}
+
inbuf.pageslen = 1;
VERIFY(err, !fastrpc_mmap_create(fl, init->memfd, 0,
init->mem, init->memlen, mflags, &mem));
@@ -1822,64 +1830,26 @@
{
}
-static int fastrpc_search_ctx(uint64_t rctx)
-{
- struct fastrpc_apps *me = &gfa;
- struct fastrpc_file *fl;
- struct hlist_node *n, *m;
- struct smq_invoke_ctx *ictx = NULL;
- struct smq_invoke_ctx *ctx;
- int bfound = 0;
- unsigned long flags;
- unsigned long flags1;
-
- ctx = (struct smq_invoke_ctx *)(uint64_to_ptr(rctx));
- if (!ctx)
- return bfound;
-
- spin_lock_irqsave(&me->hlock, flags);
- hlist_for_each_entry_safe(fl, n, &me->drivers, hn) {
- if (ctx->fl != fl)
- continue;
- spin_lock_irqsave(&fl->hlock, flags1);
- hlist_for_each_entry_safe(ictx, m, &fl->clst.pending, hn) {
- if (ptr_to_uint64(ictx) == rctx) {
- bfound = 1;
- break;
- }
- }
- hlist_for_each_entry_safe(ictx, m, &fl->clst.interrupted, hn) {
- if (ptr_to_uint64(ictx) == rctx) {
- bfound = 1;
- break;
- }
- }
- spin_unlock_irqrestore(&fl->hlock, flags1);
- if (bfound)
- break;
- }
- spin_unlock_irqrestore(&me->hlock, flags);
- return bfound;
-}
-
void fastrpc_glink_notify_rx(void *handle, const void *priv,
const void *pkt_priv, const void *ptr, size_t size)
{
struct smq_invoke_rsp *rsp = (struct smq_invoke_rsp *)ptr;
- int bfound = 0;
+ struct smq_invoke_ctx *ctx;
+ int err = 0;
- if (!rsp || (size < sizeof(*rsp)))
+ VERIFY(err, (rsp && size >= sizeof(*rsp)));
+ if (err)
goto bail;
- bfound = fastrpc_search_ctx((uint64_t)(rsp->ctx & ~1));
- if (!bfound) {
- pr_err("adsprpc: invalid context %pK\n", (void *)rsp->ctx);
+ ctx = (struct smq_invoke_ctx *)(uint64_to_ptr(rsp->ctx & ~1));
+ VERIFY(err, (ctx && ctx->magic == FASTRPC_CTX_MAGIC));
+ if (err)
goto bail;
- }
- rsp->ctx = rsp->ctx & ~1;
- context_notify_user(uint64_to_ptr(rsp->ctx), rsp->retval);
+ context_notify_user(ctx, rsp->retval);
bail:
+ if (err)
+ pr_err("adsprpc: invalid response or context\n");
glink_rx_done(handle, ptr, true);
}
@@ -2416,6 +2386,13 @@
sizeof(p.mmap)));
if (err)
goto bail;
+
+ VERIFY(err, !IS_ERR_OR_NULL(p.mmap.vaddrin));
+ if (err)
+ goto bail;
+ VERIFY(err, p.mmap.size > 0);
+ if (err)
+ goto bail;
VERIFY(err, 0 == (err = fastrpc_internal_mmap(fl, &p.mmap)));
if (err)
goto bail;
@@ -2428,6 +2405,13 @@
sizeof(p.munmap)));
if (err)
goto bail;
+ VERIFY(err, !IS_ERR_OR_NULL(
+ uint64_to_ptr((uint64_t)p.munmap.vaddrout)));
+ if (err)
+ goto bail;
+ VERIFY(err, p.munmap.size > 0);
+ if (err)
+ goto bail;
VERIFY(err, 0 == (err = fastrpc_internal_munmap(fl,
&p.munmap)));
if (err)
@@ -2505,7 +2489,11 @@
if (err)
goto bail;
VERIFY(err, p.init.init.filelen >= 0 &&
- p.init.init.memlen >= 0);
+ p.init.init.filelen < INIT_FILELEN_MAX);
+ if (err)
+ goto bail;
+ VERIFY(err, p.init.init.memlen >= 0 &&
+ p.init.init.memlen < INIT_MEMLEN_MAX);
if (err)
goto bail;
VERIFY(err, 0 == fastrpc_init_process(fl, &p.init));
diff --git a/drivers/char/diag/diag_dci.c b/drivers/char/diag/diag_dci.c
index e2d39e7..0aad08a 100644
--- a/drivers/char/diag/diag_dci.c
+++ b/drivers/char/diag/diag_dci.c
@@ -134,6 +134,35 @@
void diag_dci_record_traffic(int read_bytes, uint8_t ch_type,
uint8_t peripheral, uint8_t proc) { }
#endif
+
+static int check_peripheral_dci_support(int peripheral_id, int dci_proc_id)
+{
+ int dci_peripheral_list = 0;
+
+ if (dci_proc_id < 0 || dci_proc_id >= NUM_DCI_PROC) {
+ pr_err("diag:In %s,not a supported DCI proc id\n", __func__);
+ return 0;
+ }
+ if (peripheral_id < 0 || peripheral_id >= NUM_PERIPHERALS) {
+ pr_err("diag:In %s,not a valid peripheral id\n", __func__);
+ return 0;
+ }
+ dci_peripheral_list = dci_ops_tbl[dci_proc_id].peripheral_status;
+
+ if (dci_peripheral_list <= 0 || dci_peripheral_list > DIAG_CON_ALL) {
+ pr_err("diag:In %s,not a valid dci peripheral mask\n",
+ __func__);
+ return 0;
+ }
+ /* Remove APSS bit mask information */
+ dci_peripheral_list = dci_peripheral_list >> 1;
+
+ if ((1 << peripheral_id) & (dci_peripheral_list))
+ return 1;
+ else
+ return 0;
+}
+
static void create_dci_log_mask_tbl(unsigned char *mask, uint8_t dirty)
{
unsigned char *temp = mask;
@@ -1440,6 +1469,8 @@
struct siginfo info;
struct list_head *start, *temp;
struct diag_dci_client_tbl *entry = NULL;
+ struct pid *pid_struct = NULL;
+ struct task_struct *dci_task = NULL;
memset(&info, 0, sizeof(struct siginfo));
info.si_code = SI_QUEUE;
@@ -1457,20 +1488,32 @@
continue;
if (entry->client_info.notification_list & peripheral_mask) {
info.si_signo = entry->client_info.signal_type;
- if (entry->client &&
- entry->tgid == entry->client->tgid) {
- DIAG_LOG(DIAG_DEBUG_DCI,
- "entry tgid = %d, dci client tgid = %d\n",
- entry->tgid, entry->client->tgid);
- stat = send_sig_info(
- entry->client_info.signal_type,
- &info, entry->client);
- if (stat)
- pr_err("diag: Err sending dci signal to client, signal data: 0x%x, stat: %d\n",
+ pid_struct = find_get_pid(entry->tgid);
+ if (pid_struct) {
+ dci_task = get_pid_task(pid_struct,
+ PIDTYPE_PID);
+ if (!dci_task) {
+ DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
+ "diag: dci client with pid = %d Exited..\n",
+ entry->tgid);
+ mutex_unlock(&driver->dci_mutex);
+ return;
+ }
+ if (entry->client &&
+ entry->tgid == dci_task->tgid) {
+ DIAG_LOG(DIAG_DEBUG_DCI,
+ "entry tgid = %d, dci client tgid = %d\n",
+ entry->tgid, dci_task->tgid);
+ stat = send_sig_info(
+ entry->client_info.signal_type,
+ &info, dci_task);
+ if (stat)
+ pr_err("diag: Err sending dci signal to client, signal data: 0x%x, stat: %d\n",
info.si_int, stat);
- } else
- pr_err("diag: client data is corrupted, signal data: 0x%x, stat: %d\n",
+ } else
+ pr_err("diag: client data is corrupted, signal data: 0x%x, stat: %d\n",
info.si_int, stat);
+ }
}
}
mutex_unlock(&driver->dci_mutex);
@@ -2396,10 +2439,12 @@
* is down. It may also mean that the peripheral doesn't
* support DCI.
*/
- err = diag_dci_write_proc(i, DIAG_CNTL_TYPE, buf,
- header_size + DCI_EVENT_MASK_SIZE);
- if (err != DIAG_DCI_NO_ERROR)
- ret = DIAG_DCI_SEND_DATA_FAIL;
+ if (check_peripheral_dci_support(i, DCI_LOCAL_PROC)) {
+ err = diag_dci_write_proc(i, DIAG_CNTL_TYPE, buf,
+ header_size + DCI_EVENT_MASK_SIZE);
+ if (err != DIAG_DCI_NO_ERROR)
+ ret = DIAG_DCI_SEND_DATA_FAIL;
+ }
}
mutex_unlock(&event_mask.lock);
@@ -2581,11 +2626,13 @@
}
write_len = dci_fill_log_mask(buf, log_mask_ptr);
for (j = 0; j < NUM_PERIPHERALS && write_len; j++) {
- err = diag_dci_write_proc(j, DIAG_CNTL_TYPE, buf,
- write_len);
- if (err != DIAG_DCI_NO_ERROR) {
- updated = 0;
- ret = DIAG_DCI_SEND_DATA_FAIL;
+ if (check_peripheral_dci_support(j, DCI_LOCAL_PROC)) {
+ err = diag_dci_write_proc(j, DIAG_CNTL_TYPE,
+ buf, write_len);
+ if (err != DIAG_DCI_NO_ERROR) {
+ updated = 0;
+ ret = DIAG_DCI_SEND_DATA_FAIL;
+ }
}
}
if (updated)
diff --git a/drivers/char/diag/diag_masks.c b/drivers/char/diag/diag_masks.c
index ee76d39..2df62e4 100644
--- a/drivers/char/diag/diag_masks.c
+++ b/drivers/char/diag/diag_masks.c
@@ -1662,6 +1662,7 @@
struct diag_msg_mask_t *src_mask = NULL;
struct diag_msg_mask_t *dest_mask = NULL;
struct diag_ssid_range_t range;
+ int mask_size = 0;
if (!src || !dest)
return -EINVAL;
@@ -1682,8 +1683,11 @@
err = diag_create_msg_mask_table_entry(dest_mask, &range);
if (err)
break;
- memcpy(dest_mask->ptr, src_mask->ptr,
- dest_mask->range * sizeof(uint32_t));
+ if (src_mask->range_tools < dest_mask->range)
+ mask_size = src_mask->range_tools * sizeof(uint32_t);
+ else
+ mask_size = dest_mask->range * sizeof(uint32_t);
+ memcpy(dest_mask->ptr, src_mask->ptr, mask_size);
src_mask++;
dest_mask++;
}
diff --git a/drivers/char/diag/diag_memorydevice.c b/drivers/char/diag/diag_memorydevice.c
index 7e3fe90..dabb1f4 100644
--- a/drivers/char/diag/diag_memorydevice.c
+++ b/drivers/char/diag/diag_memorydevice.c
@@ -218,6 +218,7 @@
uint8_t drain_again = 0;
int peripheral = 0;
struct diag_md_session_t *session_info = NULL;
+ struct pid *pid_struct = NULL;
for (i = 0; i < NUM_DIAG_MD_DEV && !err; i++) {
ch = &diag_md[i];
@@ -240,6 +241,14 @@
if ((info && (info->peripheral_mask &
MD_PERIPHERAL_MASK(peripheral)) == 0))
goto drop_data;
+ pid_struct = find_get_pid(session_info->pid);
+ if (!pid_struct) {
+ err = -ESRCH;
+ DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
+ "diag: No such md_session_map[%d] with pid = %d err=%d exists..\n",
+ peripheral, session_info->pid, err);
+ goto drop_data;
+ }
/*
* If the data is from remote processor, copy the remote
* token first
@@ -259,27 +268,35 @@
}
if (i > 0) {
remote_token = diag_get_remote(i);
- err = copy_to_user(buf + ret, &remote_token,
- sizeof(int));
+ if (get_pid_task(pid_struct, PIDTYPE_PID)) {
+ err = copy_to_user(buf + ret,
+ &remote_token,
+ sizeof(int));
+ if (err)
+ goto drop_data;
+ ret += sizeof(int);
+ }
+ }
+
+ /* Copy the length of data being passed */
+ if (get_pid_task(pid_struct, PIDTYPE_PID)) {
+ err = copy_to_user(buf + ret,
+ (void *)&(entry->len),
+ sizeof(int));
if (err)
goto drop_data;
ret += sizeof(int);
}
- /* Copy the length of data being passed */
- err = copy_to_user(buf + ret, (void *)&(entry->len),
- sizeof(int));
- if (err)
- goto drop_data;
- ret += sizeof(int);
-
/* Copy the actual data being passed */
- err = copy_to_user(buf + ret, (void *)entry->buf,
- entry->len);
- if (err)
- goto drop_data;
- ret += entry->len;
-
+ if (get_pid_task(pid_struct, PIDTYPE_PID)) {
+ err = copy_to_user(buf + ret,
+ (void *)entry->buf,
+ entry->len);
+ if (err)
+ goto drop_data;
+ ret += entry->len;
+ }
/*
* The data is now copied to the user space client,
* Notify that the write is complete and delete its
@@ -301,7 +318,11 @@
}
*pret = ret;
- err = copy_to_user(buf + sizeof(int), (void *)&num_data, sizeof(int));
+ if (pid_struct && get_pid_task(pid_struct, PIDTYPE_PID)) {
+ err = copy_to_user(buf + sizeof(int),
+ (void *)&num_data,
+ sizeof(int));
+ }
diag_ws_on_copy_complete(DIAG_WS_MUX);
if (drain_again)
chk_logging_wakeup();
diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c
index 543f0a2..54e6486 100644
--- a/drivers/char/diag/diagchar_core.c
+++ b/drivers/char/diag/diagchar_core.c
@@ -1304,11 +1304,9 @@
mutex_unlock(&driver->md_session_lock);
return -ENOMEM;
}
-
new_session->peripheral_mask = 0;
new_session->pid = current->tgid;
new_session->task = current;
-
new_session->log_mask = kzalloc(sizeof(struct diag_mask_info),
GFP_KERNEL);
if (!new_session->log_mask) {
@@ -1426,7 +1424,6 @@
struct diag_md_session_t *diag_md_session_get_pid(int pid)
{
int i;
-
for (i = 0; i < NUM_MD_SESSIONS; i++) {
if (driver->md_session_map[i] &&
driver->md_session_map[i]->pid == pid)
@@ -1542,7 +1539,10 @@
* If this session owns all the requested peripherals, then
* call function to switch the modes/masks for the md_session
*/
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
+
if (!session_info) {
*change_mode = 1;
return 0;
@@ -1571,7 +1571,9 @@
* owned by this md session
*/
change_mask = driver->md_session_mask & param->peripheral_mask;
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
if (session_info) {
if ((session_info->peripheral_mask & change_mask)
@@ -1999,8 +2001,9 @@
{
uint8_t hdlc_support;
struct diag_md_session_t *session_info = NULL;
-
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
if (copy_from_user(&hdlc_support, (void __user *)ioarg,
sizeof(uint8_t)))
return -EFAULT;
@@ -2768,10 +2771,13 @@
} else {
wait_event_interruptible(driver->wait_q,
(driver->in_busy_pktdata == 0));
+ mutex_lock(&driver->md_session_lock);
info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
ret = diag_process_apps_pkt(user_space_data, len, info);
if (ret == 1)
- diag_send_error_rsp((void *)(user_space_data), len);
+ diag_send_error_rsp((void *)(user_space_data), len,
+ info);
}
fail:
diagmem_free(driver, user_space_data, mempool);
@@ -2835,7 +2841,9 @@
/* send masks to local processor now */
if (!remote_proc) {
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
if (!session_info) {
pr_err("diag:In %s request came from invalid md session pid:%d",
__func__, current->tgid);
@@ -3010,7 +3018,9 @@
goto exit;
/* place holder for number of data field */
ret += sizeof(int);
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
exit_stat = diag_md_copy_to_user(buf, &ret, count,
session_info);
goto exit;
@@ -3028,7 +3038,9 @@
if (ret == -EFAULT)
goto exit;
+ mutex_lock(&driver->md_session_lock);
session_info = diag_md_session_get_pid(current->tgid);
+ mutex_unlock(&driver->md_session_lock);
if (session_info) {
COPY_USER_SPACE_OR_ERR(buf+4,
session_info->hdlc_disabled,
diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c
index b59f245..fc67c1a 100644
--- a/drivers/char/diag/diagfwd.c
+++ b/drivers/char/diag/diagfwd.c
@@ -240,10 +240,11 @@
}
}
-static void pack_rsp_and_send(unsigned char *buf, int len)
+static void pack_rsp_and_send(unsigned char *buf, int len,
+ struct diag_md_session_t *info)
{
int err;
- int retry_count = 0;
+ int retry_count = 0, i, rsp_ctxt;
uint32_t write_len = 0;
unsigned long flags;
unsigned char *rsp_ptr = driver->encoded_rsp_buf;
@@ -259,6 +260,26 @@
}
/*
+ * Explicitly check for the Peripheral Modem here
+ * is necessary till a way to identify a peripheral
+ * if its supporting qshrink4 feature.
+ */
+ if (info && info->peripheral_mask) {
+ if (info->peripheral_mask == DIAG_CON_ALL ||
+ (info->peripheral_mask & (1 << APPS_DATA)) ||
+ (info->peripheral_mask & (1 << PERIPHERAL_MODEM))) {
+ rsp_ctxt = SET_BUF_CTXT(APPS_DATA, TYPE_CMD, 1);
+ } else {
+ for (i = 0; i < NUM_MD_SESSIONS; i++) {
+ if (info->peripheral_mask & (1 << i))
+ break;
+ }
+ rsp_ctxt = SET_BUF_CTXT(i, TYPE_CMD, 1);
+ }
+ } else
+ rsp_ctxt = driver->rsp_buf_ctxt;
+
+ /*
* Keep trying till we get the buffer back. It should probably
* take one or two iterations. When this loops till UINT_MAX, it
* means we did not get a write complete for the previous
@@ -299,8 +320,7 @@
*(uint8_t *)(rsp_ptr + write_len) = CONTROL_CHAR;
write_len += sizeof(uint8_t);
- err = diag_mux_write(DIAG_LOCAL_PROC, rsp_ptr, write_len,
- driver->rsp_buf_ctxt);
+ err = diag_mux_write(DIAG_LOCAL_PROC, rsp_ptr, write_len, rsp_ctxt);
if (err) {
pr_err("diag: In %s, unable to write to mux, err: %d\n",
__func__, err);
@@ -310,12 +330,13 @@
}
}
-static void encode_rsp_and_send(unsigned char *buf, int len)
+static void encode_rsp_and_send(unsigned char *buf, int len,
+ struct diag_md_session_t *info)
{
struct diag_send_desc_type send = { NULL, NULL, DIAG_STATE_START, 0 };
struct diag_hdlc_dest_type enc = { NULL, NULL, 0 };
unsigned char *rsp_ptr = driver->encoded_rsp_buf;
- int err, retry_count = 0;
+ int err, i, rsp_ctxt, retry_count = 0;
unsigned long flags;
if (!rsp_ptr || !buf)
@@ -328,6 +349,26 @@
}
/*
+ * Explicitly check for the Peripheral Modem here
+ * is necessary till a way to identify a peripheral
+ * if its supporting qshrink4 feature.
+ */
+ if (info && info->peripheral_mask) {
+ if (info->peripheral_mask == DIAG_CON_ALL ||
+ (info->peripheral_mask & (1 << APPS_DATA)) ||
+ (info->peripheral_mask & (1 << PERIPHERAL_MODEM))) {
+ rsp_ctxt = SET_BUF_CTXT(APPS_DATA, TYPE_CMD, 1);
+ } else {
+ for (i = 0; i < NUM_MD_SESSIONS; i++) {
+ if (info->peripheral_mask & (1 << i))
+ break;
+ }
+ rsp_ctxt = SET_BUF_CTXT(i, TYPE_CMD, 1);
+ }
+ } else
+ rsp_ctxt = driver->rsp_buf_ctxt;
+
+ /*
* Keep trying till we get the buffer back. It should probably
* take one or two iterations. When this loops till UINT_MAX, it
* means we did not get a write complete for the previous
@@ -370,7 +411,7 @@
diag_hdlc_encode(&send, &enc);
driver->encoded_rsp_len = (int)(enc.dest - (void *)rsp_ptr);
err = diag_mux_write(DIAG_LOCAL_PROC, rsp_ptr, driver->encoded_rsp_len,
- driver->rsp_buf_ctxt);
+ rsp_ctxt);
if (err) {
pr_err("diag: In %s, Unable to write to device, err: %d\n",
__func__, err);
@@ -381,21 +422,23 @@
memset(buf, '\0', DIAG_MAX_RSP_SIZE);
}
-void diag_send_rsp(unsigned char *buf, int len)
+static void diag_send_rsp(unsigned char *buf, int len,
+ struct diag_md_session_t *info)
{
struct diag_md_session_t *session_info = NULL;
uint8_t hdlc_disabled;
- session_info = diag_md_session_get_peripheral(APPS_DATA);
+ session_info = (info) ? info :
+ diag_md_session_get_peripheral(APPS_DATA);
if (session_info)
hdlc_disabled = session_info->hdlc_disabled;
else
hdlc_disabled = driver->hdlc_disabled;
if (hdlc_disabled)
- pack_rsp_and_send(buf, len);
+ pack_rsp_and_send(buf, len, session_info);
else
- encode_rsp_and_send(buf, len);
+ encode_rsp_and_send(buf, len, session_info);
}
void diag_update_pkt_buffer(unsigned char *buf, uint32_t len, int type)
@@ -926,7 +969,8 @@
return write_len;
}
-void diag_send_error_rsp(unsigned char *buf, int len)
+void diag_send_error_rsp(unsigned char *buf, int len,
+ struct diag_md_session_t *info)
{
/* -1 to accommodate the first byte 0x13 */
if (len > (DIAG_MAX_RSP_SIZE - 1)) {
@@ -936,7 +980,7 @@
*(uint8_t *)driver->apps_rsp_buf = DIAG_CMD_ERROR;
memcpy((driver->apps_rsp_buf + sizeof(uint8_t)), buf, len);
- diag_send_rsp(driver->apps_rsp_buf, len + 1);
+ diag_send_rsp(driver->apps_rsp_buf, len + 1, info);
}
int diag_process_apps_pkt(unsigned char *buf, int len,
@@ -956,7 +1000,7 @@
/* Check if the command is a supported mask command */
mask_ret = diag_process_apps_masks(buf, len, info);
if (mask_ret > 0) {
- diag_send_rsp(driver->apps_rsp_buf, mask_ret);
+ diag_send_rsp(driver->apps_rsp_buf, mask_ret, info);
return 0;
}
@@ -978,7 +1022,7 @@
driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0)
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
@@ -988,13 +1032,15 @@
reg_item = container_of(temp_entry, struct diag_cmd_reg_t,
entry);
if (info) {
- if (MD_PERIPHERAL_MASK(reg_item->proc) &
- info->peripheral_mask)
+ if ((MD_PERIPHERAL_MASK(reg_item->proc) &
+ info->peripheral_mask) ||
+ (MD_PERIPHERAL_PD_MASK(reg_item->proc) &
+ info->peripheral_mask))
write_len = diag_send_data(reg_item, buf, len);
} else {
if (MD_PERIPHERAL_MASK(reg_item->proc) &
driver->logging_mask)
- diag_send_error_rsp(buf, len);
+ diag_send_error_rsp(buf, len, info);
else
write_len = diag_send_data(reg_item, buf, len);
}
@@ -1010,13 +1056,13 @@
for (i = 0; i < 4; i++)
*(driver->apps_rsp_buf+i) = *(buf+i);
*(uint32_t *)(driver->apps_rsp_buf+4) = DIAG_MAX_REQ_SIZE;
- diag_send_rsp(driver->apps_rsp_buf, 8);
+ diag_send_rsp(driver->apps_rsp_buf, 8, info);
return 0;
} else if ((*buf == 0x4b) && (*(buf+1) == 0x12) &&
(*(uint16_t *)(buf+2) == DIAG_DIAG_STM)) {
len = diag_process_stm_cmd(buf, driver->apps_rsp_buf);
if (len > 0) {
- diag_send_rsp(driver->apps_rsp_buf, len);
+ diag_send_rsp(driver->apps_rsp_buf, len, info);
return 0;
}
return len;
@@ -1029,7 +1075,7 @@
driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0)
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
/* Check for time sync switch command */
@@ -1040,7 +1086,7 @@
driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0)
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
/* Check for diag id command */
@@ -1051,14 +1097,14 @@
driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0)
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
/* Check for download command */
else if ((chk_apps_master()) && (*buf == 0x3A)) {
/* send response back */
driver->apps_rsp_buf[0] = *buf;
- diag_send_rsp(driver->apps_rsp_buf, 1);
+ diag_send_rsp(driver->apps_rsp_buf, 1, info);
msleep(5000);
/* call download API */
msm_set_restart_mode(RESTART_DLOAD);
@@ -1078,7 +1124,7 @@
for (i = 0; i < 13; i++)
driver->apps_rsp_buf[i+3] = 0;
- diag_send_rsp(driver->apps_rsp_buf, 16);
+ diag_send_rsp(driver->apps_rsp_buf, 16, info);
return 0;
}
}
@@ -1087,7 +1133,7 @@
(*(buf+2) == 0x04) && (*(buf+3) == 0x0)) {
memcpy(driver->apps_rsp_buf, buf, 4);
driver->apps_rsp_buf[4] = wrap_enabled;
- diag_send_rsp(driver->apps_rsp_buf, 5);
+ diag_send_rsp(driver->apps_rsp_buf, 5, info);
return 0;
}
/* Wrap the Delayed Rsp ID */
@@ -1096,7 +1142,7 @@
wrap_enabled = true;
memcpy(driver->apps_rsp_buf, buf, 4);
driver->apps_rsp_buf[4] = wrap_count;
- diag_send_rsp(driver->apps_rsp_buf, 6);
+ diag_send_rsp(driver->apps_rsp_buf, 6, info);
return 0;
}
/* Mobile ID Rsp */
@@ -1107,7 +1153,7 @@
driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0) {
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
}
@@ -1127,7 +1173,7 @@
for (i = 0; i < 55; i++)
driver->apps_rsp_buf[i] = 0;
- diag_send_rsp(driver->apps_rsp_buf, 55);
+ diag_send_rsp(driver->apps_rsp_buf, 55, info);
return 0;
}
/* respond to 0x7c command */
@@ -1140,14 +1186,14 @@
chk_config_get_id();
*(unsigned char *)(driver->apps_rsp_buf + 12) = '\0';
*(unsigned char *)(driver->apps_rsp_buf + 13) = '\0';
- diag_send_rsp(driver->apps_rsp_buf, 14);
+ diag_send_rsp(driver->apps_rsp_buf, 14, info);
return 0;
}
}
write_len = diag_cmd_chk_stats(buf, len, driver->apps_rsp_buf,
DIAG_MAX_RSP_SIZE);
if (write_len > 0) {
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
return 0;
}
write_len = diag_cmd_disable_hdlc(buf, len, driver->apps_rsp_buf,
@@ -1159,7 +1205,7 @@
* before disabling HDLC encoding on Apps processor.
*/
mutex_lock(&driver->hdlc_disable_mutex);
- diag_send_rsp(driver->apps_rsp_buf, write_len);
+ diag_send_rsp(driver->apps_rsp_buf, write_len, info);
/*
* Set the value of hdlc_disabled after sending the response to
* the tools. This is required since the tools is expecting a
@@ -1179,7 +1225,7 @@
/* We have now come to the end of the function. */
if (chk_apps_only())
- diag_send_error_rsp(buf, len);
+ diag_send_error_rsp(buf, len, info);
return 0;
}
@@ -1262,7 +1308,7 @@
* recovery algorithm. Send an error response if the
* packet is not in expected format.
*/
- diag_send_error_rsp(driver->hdlc_buf, driver->hdlc_buf_len);
+ diag_send_error_rsp(driver->hdlc_buf, driver->hdlc_buf_len, info);
driver->hdlc_buf_len = 0;
end:
mutex_unlock(&driver->diag_hdlc_mutex);
@@ -1535,7 +1581,7 @@
if (actual_pkt->start != CONTROL_CHAR) {
diag_hdlc_start_recovery(buf, len, info);
- diag_send_error_rsp(buf, len);
+ diag_send_error_rsp(buf, len, info);
goto end;
}
mutex_lock(&driver->hdlc_recovery_mutex);
@@ -1625,15 +1671,14 @@
case TYPE_CMD:
if (peripheral >= 0 && peripheral < NUM_PERIPHERALS) {
diagfwd_write_done(peripheral, type, num);
- } else if (peripheral == APPS_DATA) {
+ }
+ if (peripheral == APPS_DATA ||
+ ctxt == DIAG_MEMORY_DEVICE_MODE) {
spin_lock_irqsave(&driver->rsp_buf_busy_lock, flags);
driver->rsp_buf_busy = 0;
driver->encoded_rsp_len = 0;
spin_unlock_irqrestore(&driver->rsp_buf_busy_lock,
flags);
- } else {
- pr_err_ratelimited("diag: Invalid peripheral %d in %s, type: %d\n",
- peripheral, __func__, type);
}
break;
default:
diff --git a/drivers/char/diag/diagfwd.h b/drivers/char/diag/diagfwd.h
index 677099f..0e0bf2d 100644
--- a/drivers/char/diag/diagfwd.h
+++ b/drivers/char/diag/diagfwd.h
@@ -47,7 +47,8 @@
void diag_update_sleeping_process(int process_id, int data_type);
int diag_process_apps_pkt(unsigned char *buf, int len,
struct diag_md_session_t *info);
-void diag_send_error_rsp(unsigned char *buf, int len);
+void diag_send_error_rsp(unsigned char *buf, int len,
+ struct diag_md_session_t *info);
void diag_update_pkt_buffer(unsigned char *buf, uint32_t len, int type);
int diag_process_stm_cmd(unsigned char *buf, unsigned char *dest_buf);
void diag_md_hdlc_reset_timer_func(unsigned long pid);
diff --git a/drivers/char/diag/diagfwd_cntl.c b/drivers/char/diag/diagfwd_cntl.c
index 710271e..d8c107e 100644
--- a/drivers/char/diag/diagfwd_cntl.c
+++ b/drivers/char/diag/diagfwd_cntl.c
@@ -111,6 +111,8 @@
{
int stat = 0;
struct siginfo info;
+ struct pid *pid_struct;
+ struct task_struct *result;
if (peripheral > NUM_PERIPHERALS)
return;
@@ -123,18 +125,38 @@
info.si_code = SI_QUEUE;
info.si_int = (PERIPHERAL_MASK(peripheral) | data);
info.si_signo = SIGCONT;
- if (driver->md_session_map[peripheral] &&
- driver->md_session_map[peripheral]->task) {
- if (driver->md_session_map[peripheral]->pid ==
- driver->md_session_map[peripheral]->task->tgid) {
+
+ if (!driver->md_session_map[peripheral] ||
+ driver->md_session_map[peripheral]->pid <= 0) {
+ pr_err("diag: md_session_map[%d] is invalid\n", peripheral);
+ mutex_unlock(&driver->md_session_lock);
+ return;
+ }
+
+ pid_struct = find_get_pid(
+ driver->md_session_map[peripheral]->pid);
+ DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
+ "md_session_map[%d] pid = %d task = %pK\n",
+ peripheral,
+ driver->md_session_map[peripheral]->pid,
+ driver->md_session_map[peripheral]->task);
+
+ if (pid_struct) {
+ result = get_pid_task(pid_struct, PIDTYPE_PID);
+
+ if (!result) {
DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
- "md_session %d pid = %d, md_session %d task tgid = %d\n",
+ "diag: md_session_map[%d] with pid = %d Exited..\n",
peripheral,
- driver->md_session_map[peripheral]->pid,
- peripheral,
- driver->md_session_map[peripheral]->task->tgid);
- stat = send_sig_info(info.si_signo, &info,
- driver->md_session_map[peripheral]->task);
+ driver->md_session_map[peripheral]->pid);
+ mutex_unlock(&driver->md_session_lock);
+ return;
+ }
+
+ if (driver->md_session_map[peripheral] &&
+ driver->md_session_map[peripheral]->task == result) {
+ stat = send_sig_info(info.si_signo,
+ &info, result);
if (stat)
pr_err("diag: Err sending signal to memory device client, signal data: 0x%x, stat: %d\n",
info.si_int, stat);
diff --git a/drivers/char/diag/diagfwd_peripheral.c b/drivers/char/diag/diagfwd_peripheral.c
index 0703c38..4d4b660 100644
--- a/drivers/char/diag/diagfwd_peripheral.c
+++ b/drivers/char/diag/diagfwd_peripheral.c
@@ -222,12 +222,22 @@
struct diagfwd_info *fwd_info = NULL;
peripheral = GET_BUF_PERIPHERAL(ctxt);
- if (peripheral < 0 || peripheral > NUM_PERIPHERALS)
+
+ /* Check for peripheral value within bounds
+ * of peripherals and UPD combined.
+ */
+ if (peripheral < 0 || peripheral > NUM_MD_SESSIONS)
return -EINVAL;
if (peripheral == APPS_DATA)
return peripheral;
+ /* With peripheral value bound checked
+ * return user pd value.
+ */
+ if (peripheral > NUM_PERIPHERALS)
+ return peripheral;
+
type = GET_BUF_TYPE(ctxt);
if (type < 0 || type >= NUM_TYPES)
return -EINVAL;
diff --git a/drivers/clk/qcom/clk-cpu-osm.c b/drivers/clk/qcom/clk-cpu-osm.c
index 93a08db..cabf0c2 100644
--- a/drivers/clk/qcom/clk-cpu-osm.c
+++ b/drivers/clk/qcom/clk-cpu-osm.c
@@ -18,7 +18,6 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/clk.h>
@@ -27,20 +26,15 @@
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/pm_opp.h>
-#include <linux/pm_qos.h>
#include <linux/interrupt.h>
-#include <linux/regulator/driver.h>
-#include <linux/regmap.h>
#include <linux/uaccess.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
-#include <soc/qcom/scm.h>
#include <dt-bindings/clock/qcom,cpucc-sdm845.h>
#include "common.h"
#include "clk-regmap.h"
-#include "clk-rcg.h"
#include "clk-voter.h"
#include "clk-debug.h"
@@ -53,105 +47,12 @@
#define MAX_CORE_COUNT 4
#define CORE_COUNT_VAL(val) ((val & GENMASK(18, 16)) >> 16)
-#define OSM_CYCLE_COUNTER_CTRL_REG 0x760
-#define OSM_CYCLE_COUNTER_USE_XO_EDGE_EN BIT(8)
-
#define OSM_REG_SIZE 32
-#define L3_EFUSE_SHIFT 29
-#define L3_EFUSE_MASK 0x7
-#define PWRCL_EFUSE_SHIFT 29
-#define PWRCL_EFUSE_MASK 0x7
-#define PERFCL_EFUSE_SHIFT 29
-#define PERFCL_EFUSE_MASK 0x7
-
#define ENABLE_REG 0x0
-#define ENABLE_OSM BIT(0)
#define FREQ_REG 0x110
#define VOLT_REG 0x114
-#define OVERRIDE_REG 0x118
-#define SPM_CC_INC_HYSTERESIS 0x1c
-#define SPM_CC_DEC_HYSTERESIS 0x20
-#define SPM_CORE_INACTIVE_MAPPING 0x28
-#define CC_ZERO_BEHAV_CTRL 0xc
-#define ENABLE_OVERRIDE BIT(0)
-#define SPM_CC_DCVS_DISABLE 0x24
-#define LLM_FREQ_VOTE_INC_HYSTERESIS 0x30
-#define LLM_FREQ_VOTE_DEC_HYSTERESIS 0x34
-#define LLM_INTF_DCVS_DISABLE 0x40
-#define LLM_VOLTAGE_VOTE_INC_HYSTERESIS 0x38
-#define LLM_VOLTAGE_VOTE_DEC_HYSTERESIS 0x3c
-#define VMIN_REDUCTION_ENABLE_REG 0x48
-#define VMIN_REDUCTION_TIMER_REG 0x4c
-#define PDN_FSM_CTRL_REG 0x54
-#define DELTA_DEX_VAL BVAL(31, 23, 0xa)
-#define IGNORE_PLL_LOCK BIT(15)
-#define CC_BOOST_FSM_EN BIT(0)
-#define CC_BOOST_FSM_TIMERS_REG0 0x58
-#define CC_BOOST_FSM_TIMERS_REG1 0x5c
-#define CC_BOOST_FSM_TIMERS_REG2 0x60
-#define DCVS_BOOST_FSM_EN_MASK BIT(2)
-#define DCVS_BOOST_FSM_TIMERS_REG0 0x64
-#define DCVS_BOOST_FSM_TIMERS_REG1 0x68
-#define DCVS_BOOST_FSM_TIMERS_REG2 0x6c
-#define PS_BOOST_FSM_EN_MASK BIT(1)
-#define PS_BOOST_FSM_TIMERS_REG0 0x74
-#define PS_BOOST_FSM_TIMERS_REG1 0x78
-#define PS_BOOST_FSM_TIMERS_REG2 0x7c
-#define BOOST_PROG_SYNC_DELAY_REG 0x80
-#define DCVS_DROOP_FSM_EN_MASK BIT(5)
-#define DROOP_PROG_SYNC_DELAY_REG 0x9c
-#define DROOP_RELEASE_TIMER_CTRL 0x88
-#define DROOP_CTRL_REG 0x84
-#define DCVS_DROOP_TIMER_CTRL 0x98
-#define PLL_SW_OVERRIDE_ENABLE 0xa0
-#define PLL_SW_OVERRIDE_DROOP_EN BIT(0)
-#define SPM_CORE_COUNT_CTRL 0x2c
#define CORE_DCVS_CTRL 0xbc
-#define OVERRIDE_CLUSTER_IDLE_ACK 0x800
-#define REQ_GEN_FSM_STATUS 0x70c
-
-#define PLL_MIN_LVAL 0x21
-#define PLL_MIN_FREQ_REG 0x94
-#define PLL_POST_DIV1 0x09
-#define PLL_POST_DIV2 0x109
-#define PLL_MODE 0x0
-#define PLL_L_VAL 0x4
-#define PLL_USER_CTRL 0xc
-#define PLL_CONFIG_CTL_LO 0x10
-#define PLL_CONFIG_CTL_HI 0x14
-#define MIN_VCO_VAL 0x2b
-
-#define MAX_VC 63
-#define MEM_ACC_LEVELS_LUT 2
-#define MAX_MEM_ACC_LEVELS 3
-#define MAX_MEM_ACC_VAL_PER_LEVEL 3
-#define MAX_MEM_ACC_VALUES (MAX_MEM_ACC_LEVELS * \
- MAX_MEM_ACC_VAL_PER_LEVEL)
-#define MEM_ACC_ADDRS 3
-
-#define ISENSE_ON_DATA 0xf
-#define ISENSE_OFF_DATA 0x0
-#define CONSTANT_32 0x20
-
-#define APM_MX_MODE 0x4100000
-#define APM_APC_MODE 0x4100002
-#define APM_READ_DATA_MASK 0xc
-#define APM_MX_MODE_VAL 0x4
-#define APM_APC_READ_VAL 0x8
-#define APM_MX_READ_VAL 0x4
-#define APM_CROSSOVER_VC 0xb0
-
-#define MEM_ACC_SEQ_CONST(n) (n)
-#define MEM_ACC_APM_READ_MASK 0xff
-#define MEMACC_CROSSOVER_VC 0xb8
-
-#define PLL_WAIT_LOCK_TIME_US 10
-#define PLL_WAIT_LOCK_TIME_NS (PLL_WAIT_LOCK_TIME_US * 1000)
-#define SAFE_FREQ_WAIT_NS 5000
-#define DEXT_DECREMENT_WAIT_NS 1000
-
-#define DATA_MEM(n) (0x400 + (n) * 4)
#define DCVS_PERF_STATE_DESIRED_REG_0_V1 0x780
#define DCVS_PERF_STATE_DESIRED_REG_0_V2 0x920
@@ -165,339 +66,52 @@
(((v2) ? OSM_CYCLE_COUNTER_STATUS_REG_0_V2 \
: OSM_CYCLE_COUNTER_STATUS_REG_0_V1) + 4 * (n))
-/* ACD registers */
-#define ACD_HW_VERSION 0x0
-#define ACDCR 0x4
-#define ACDTD 0x8
-#define ACDSSCR 0x28
-#define ACD_EXTINT_CFG 0x30
-#define ACD_DCVS_SW 0x34
-#define ACD_GFMUX_CFG 0x3c
-#define ACD_READOUT_CFG 0x48
-#define ACD_AVG_CFG_0 0x4c
-#define ACD_AVG_CFG_1 0x50
-#define ACD_AVG_CFG_2 0x54
-#define ACD_AUTOXFER_CFG 0x80
-#define ACD_AUTOXFER 0x84
-#define ACD_AUTOXFER_CTL 0x88
-#define ACD_AUTOXFER_STATUS 0x8c
-#define ACD_WRITE_CTL 0x90
-#define ACD_WRITE_STATUS 0x94
-#define ACD_READOUT 0x98
-
-#define ACD_MASTER_ONLY_REG_ADDR 0x80
-#define ACD_1P1_MAX_REG_OFFSET 0x100
-#define ACD_WRITE_CTL_UPDATE_EN BIT(0)
-#define ACD_WRITE_CTL_SELECT_SHIFT 1
-#define ACD_GFMUX_CFG_SELECT BIT(0)
-#define ACD_AUTOXFER_START_CLEAR 0
-#define ACD_AUTOXFER_START_SET 1
-#define AUTO_XFER_DONE_MASK BIT(0)
-#define ACD_DCVS_SW_DCVS_IN_PRGR_SET BIT(0)
-#define ACD_DCVS_SW_DCVS_IN_PRGR_CLEAR 0
-#define ACD_LOCAL_TRANSFER_TIMEOUT_NS 500
-
-#define ACD_REG_RELATIVE_ADDR(addr) (addr / 4)
-#define ACD_REG_RELATIVE_ADDR_BITMASK(addr) \
- (1 << (ACD_REG_RELATIVE_ADDR(addr)))
-
-static const struct regmap_config osm_qcom_regmap_config = {
- .reg_bits = 32,
- .reg_stride = 4,
- .val_bits = 32,
- .fast_io = true,
-};
-
-enum clk_osm_bases {
- OSM_BASE,
- PLL_BASE,
- EFUSE_BASE,
- SEQ_BASE,
- ACD_BASE,
- NUM_BASES,
-};
-
-enum clk_osm_lut_data {
- FREQ,
- FREQ_DATA,
- PLL_OVERRIDES,
- MEM_ACC_LEVEL,
- VIRTUAL_CORNER,
- NUM_FIELDS,
-};
-
struct osm_entry {
u16 virtual_corner;
u16 open_loop_volt;
- u32 freq_data;
- u32 override_data;
- u32 mem_acc_level;
long frequency;
};
-static struct dentry *osm_debugfs_base;
-
struct clk_osm {
struct clk_hw hw;
struct osm_entry osm_table[OSM_TABLE_SIZE];
struct dentry *debugfs;
- struct regulator *vdd_reg;
- struct platform_device *vdd_dev;
- void *vbases[NUM_BASES];
- unsigned long pbases[NUM_BASES];
+ void __iomem *vbase;
+ phys_addr_t pbase;
spinlock_t lock;
-
+ bool per_core_dcvs;
u32 num_entries;
u32 cluster_num;
u32 core_num;
- u32 apm_crossover_vc;
- u32 apm_threshold_vc;
- u32 mem_acc_crossover_vc;
- u32 mem_acc_threshold_vc;
- u32 min_cpr_vc;
- u32 cycle_counter_reads;
- u32 cycle_counter_delay;
- u32 cycle_counter_factor;
u64 total_cycle_counter;
u32 prev_cycle_counter;
- u32 l_val_base;
- u32 apcs_pll_user_ctl;
- u32 apcs_pll_min_freq;
- u32 cfg_gfmux_addr;
- u32 apcs_cbc_addr;
- u32 speedbin;
- u32 mem_acc_crossover_vc_addr;
- u32 mem_acc_addr[MEM_ACC_ADDRS];
- u32 mem_acc_level_vc[MEM_ACC_LEVELS_LUT];
- u32 ramp_ctl_addr;
- u32 apm_mode_ctl;
- u32 apm_status_ctl;
- u32 osm_clk_rate;
- u32 xo_clk_rate;
- bool secure_init;
- bool per_core_dcvs;
- bool red_fsm_en;
- bool boost_fsm_en;
- bool safe_fsm_en;
- bool ps_fsm_en;
- bool droop_fsm_en;
-
- struct notifier_block panic_notifier;
- u32 trace_periodic_timer;
- bool trace_en;
- bool wdog_trace_en;
-
- bool acd_init;
- u32 acd_td;
- u32 acd_cr;
- u32 acd_sscr;
- u32 acd_extint0_cfg;
- u32 acd_extint1_cfg;
- u32 acd_autoxfer_ctl;
- u32 acd_debugfs_addr;
- bool acd_avg_init;
- u32 acd_avg_cfg0;
- u32 acd_avg_cfg1;
- u32 acd_avg_cfg2;
};
-static struct regulator *vdd_l3;
-static struct regulator *vdd_pwrcl;
-static struct regulator *vdd_perfcl;
-
-static inline int clk_osm_acd_mb(struct clk_osm *c)
-{
- return readl_relaxed_no_log((char *)c->vbases[ACD_BASE] +
- ACD_HW_VERSION);
-}
-
-static int clk_osm_acd_local_read_reg(struct clk_osm *c, u32 offset)
-{
- u32 reg = 0;
- int timeout;
-
- if (offset >= ACD_MASTER_ONLY_REG_ADDR) {
- pr_err("ACD register at offset=0x%x not locally readable\n",
- offset);
- return -EINVAL;
- }
-
- /* Set select field in read control register */
- writel_relaxed(ACD_REG_RELATIVE_ADDR(offset),
- (char *)c->vbases[ACD_BASE] + ACD_READOUT_CFG);
-
- /* Clear write control register */
- writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
-
- /* Set select and update_en fields in write control register */
- reg = (ACD_REG_RELATIVE_ADDR(ACD_READOUT_CFG)
- << ACD_WRITE_CTL_SELECT_SHIFT)
- | ACD_WRITE_CTL_UPDATE_EN;
- writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
-
- /* Ensure writes complete before polling */
- clk_osm_acd_mb(c);
-
- /* Poll write status register */
- for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS; timeout > 0;
- timeout -= 100) {
- reg = readl_relaxed((char *)c->vbases[ACD_BASE]
- + ACD_WRITE_STATUS);
- if ((reg & (ACD_REG_RELATIVE_ADDR_BITMASK(ACD_READOUT_CFG))))
- break;
- ndelay(100);
- }
-
- if (!timeout) {
- pr_err("local read timed out, offset=0x%x status=0x%x\n",
- offset, reg);
- return -ETIMEDOUT;
- }
-
- reg = readl_relaxed((char *)c->vbases[ACD_BASE] + ACD_READOUT);
- return reg;
-}
-
-static int clk_osm_acd_local_write_reg(struct clk_osm *c, u32 val, u32 offset)
-{
- u32 reg = 0;
- int timeout;
-
- if (offset >= ACD_MASTER_ONLY_REG_ADDR) {
- pr_err("ACD register at offset=0x%x not transferrable\n",
- offset);
- return -EINVAL;
- }
-
- /* Clear write control register */
- writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
-
- /* Set select and update_en fields in write control register */
- reg = (ACD_REG_RELATIVE_ADDR(offset) << ACD_WRITE_CTL_SELECT_SHIFT)
- | ACD_WRITE_CTL_UPDATE_EN;
- writel_relaxed(reg, (char *)c->vbases[ACD_BASE] + ACD_WRITE_CTL);
-
- /* Ensure writes complete before polling */
- clk_osm_acd_mb(c);
-
- /* Poll write status register */
- for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS; timeout > 0;
- timeout -= 100) {
- reg = readl_relaxed((char *)c->vbases[ACD_BASE]
- + ACD_WRITE_STATUS);
- if ((reg & (ACD_REG_RELATIVE_ADDR_BITMASK(offset))))
- break;
- ndelay(100);
- }
-
- if (!timeout) {
- pr_err("local write timed out, offset=0x%x val=0x%x status=0x%x\n",
- offset, val, reg);
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
-static int clk_osm_acd_master_write_through_reg(struct clk_osm *c,
- u32 val, u32 offset)
-{
- writel_relaxed(val, (char *)c->vbases[ACD_BASE] + offset);
-
- /* Ensure writes complete before transfer to local copy */
- clk_osm_acd_mb(c);
-
- return clk_osm_acd_local_write_reg(c, val, offset);
-}
-
-static int clk_osm_acd_auto_local_write_reg(struct clk_osm *c, u32 mask)
-{
- u32 numregs, bitmask = mask;
- u32 reg = 0;
- int timeout;
-
- /* count number of bits set in register mask */
- for (numregs = 0; bitmask; numregs++)
- bitmask &= bitmask - 1;
-
- /* Program auto-transfer mask */
- writel_relaxed(mask, (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER_CFG);
-
- /* Clear start field in auto-transfer register */
- writel_relaxed(ACD_AUTOXFER_START_CLEAR,
- (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER);
-
- /* Set start field in auto-transfer register */
- writel_relaxed(ACD_AUTOXFER_START_SET,
- (char *)c->vbases[ACD_BASE] + ACD_AUTOXFER);
-
- /* Ensure writes complete before polling */
- clk_osm_acd_mb(c);
-
- /* Poll auto-transfer status register */
- for (timeout = ACD_LOCAL_TRANSFER_TIMEOUT_NS * numregs;
- timeout > 0; timeout -= 100) {
- reg = readl_relaxed((char *)c->vbases[ACD_BASE]
- + ACD_AUTOXFER_STATUS);
- if (reg & AUTO_XFER_DONE_MASK)
- break;
- ndelay(100);
- }
-
- if (!timeout) {
- pr_err("local register auto-transfer timed out, mask=0x%x registers=%d status=0x%x\n",
- mask, numregs, reg);
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
static bool is_v2;
-static bool osm_tz_enabled;
static inline struct clk_osm *to_clk_osm(struct clk_hw *_hw)
{
return container_of(_hw, struct clk_osm, hw);
}
-static inline void clk_osm_masked_write_reg(struct clk_osm *c, u32 val,
- u32 offset, u32 mask)
+static inline void clk_osm_write_reg(struct clk_osm *c, u32 val, u32 offset)
{
- u32 val2, orig_val;
-
- val2 = orig_val = readl_relaxed((char *)c->vbases[OSM_BASE] + offset);
- val2 &= ~mask;
- val2 |= val & mask;
-
- if (val2 != orig_val)
- writel_relaxed(val2, (char *)c->vbases[OSM_BASE] + offset);
-}
-
-static inline void clk_osm_write_seq_reg(struct clk_osm *c, u32 val, u32 offset)
-{
- writel_relaxed(val, (char *)c->vbases[SEQ_BASE] + offset);
-}
-
-static inline void clk_osm_write_reg(struct clk_osm *c, u32 val, u32 offset,
- int base)
-{
- writel_relaxed(val, (char *)c->vbases[base] + offset);
+ writel_relaxed(val, c->vbase + offset);
}
static inline int clk_osm_read_reg(struct clk_osm *c, u32 offset)
{
- return readl_relaxed((char *)c->vbases[OSM_BASE] + offset);
+ return readl_relaxed(c->vbase + offset);
}
static inline int clk_osm_read_reg_no_log(struct clk_osm *c, u32 offset)
{
- return readl_relaxed_no_log((char *)c->vbases[OSM_BASE] + offset);
+ return readl_relaxed_no_log(c->vbase + offset);
}
-static inline int clk_osm_mb(struct clk_osm *c, int base)
+static inline int clk_osm_mb(struct clk_osm *c)
{
- return readl_relaxed_no_log((char *)c->vbases[base] + ENABLE_REG);
+ return readl_relaxed_no_log(c->vbase + ENABLE_REG);
}
static long clk_osm_list_rate(struct clk_hw *hw, unsigned int n,
@@ -559,23 +173,6 @@
return -EINVAL;
}
-static int clk_osm_enable(struct clk_hw *hw)
-{
- struct clk_osm *cpuclk = to_clk_osm(hw);
-
- clk_osm_masked_write_reg(cpuclk, ENABLE_OSM, ENABLE_REG, ENABLE_OSM);
-
- /* Make sure the write goes through before proceeding */
- clk_osm_mb(cpuclk, OSM_BASE);
-
- /* Wait for 5us for OSM hardware to enable */
- udelay(5);
-
- pr_debug("OSM clk enabled for cluster=%d\n", cpuclk->cluster_num);
-
- return 0;
-}
-
const struct clk_ops clk_ops_cpu_osm = {
.round_rate = clk_osm_round_rate,
.list_rate = clk_osm_list_rate,
@@ -608,11 +205,10 @@
}
pr_debug("rate: %lu --> index %d\n", rate, index);
- clk_osm_write_reg(cpuclk, index, DCVS_PERF_STATE_DESIRED_REG(0, is_v2),
- OSM_BASE);
+ clk_osm_write_reg(cpuclk, index, DCVS_PERF_STATE_DESIRED_REG(0, is_v2));
/* Make sure the write goes through before proceeding */
- clk_osm_mb(cpuclk, OSM_BASE);
+ clk_osm_mb(cpuclk);
return 0;
}
@@ -637,7 +233,6 @@
static struct clk_ops clk_ops_l3_osm = {
- .enable = clk_osm_enable,
.round_rate = clk_osm_round_rate,
.list_rate = clk_osm_list_rate,
.recalc_rate = l3_clk_recalc_rate,
@@ -673,6 +268,7 @@
static DEFINE_CLK_VOTER(l3_cluster0_vote_clk, l3_clk, 0);
static DEFINE_CLK_VOTER(l3_cluster1_vote_clk, l3_clk, 0);
+static DEFINE_CLK_VOTER(l3_misc_vote_clk, l3_clk, 0);
static struct clk_osm pwrcl_clk = {
.cluster_num = 1,
@@ -781,16 +377,11 @@
},
};
-/*
- * Use the cpu* clocks only for writing to the PERF_STATE_DESIRED registers.
- * Note that we are currently NOT programming the APSS_LMH_GFMUX_CFG &
- * APSS_OSM_GFMUX_CFG registers.
- */
-
static struct clk_hw *osm_qcom_clk_hws[] = {
[L3_CLK] = &l3_clk.hw,
[L3_CLUSTER0_VOTE_CLK] = &l3_cluster0_vote_clk.hw,
[L3_CLUSTER1_VOTE_CLK] = &l3_cluster1_vote_clk.hw,
+ [L3_MISC_VOTE_CLK] = &l3_misc_vote_clk.hw,
[PWRCL_CLK] = &pwrcl_clk.hw,
[CPU0_PWRCL_CLK] = &cpu0_pwrcl_clk.hw,
[CPU1_PWRCL_CLK] = &cpu1_pwrcl_clk.hw,
@@ -894,11 +485,10 @@
static void
osm_set_index(struct clk_osm *c, unsigned int index, unsigned int num)
{
- clk_osm_write_reg(c, index, DCVS_PERF_STATE_DESIRED_REG(num, is_v2),
- OSM_BASE);
+ clk_osm_write_reg(c, index, DCVS_PERF_STATE_DESIRED_REG(num, is_v2));
/* Make sure the write goes through before proceeding */
- clk_osm_mb(c, OSM_BASE);
+ clk_osm_mb(c);
}
static int
@@ -947,7 +537,7 @@
}
parent = to_clk_osm(p_hw);
- c->vbases[OSM_BASE] = parent->vbases[OSM_BASE];
+ c->vbase = parent->vbase;
p_hw = clk_hw_get_parent(p_hw);
if (!p_hw) {
@@ -999,10 +589,6 @@
}
policy->driver_data = c;
-
- clk_osm_enable(&parent->hw);
- udelay(300);
-
return 0;
err:
@@ -1036,704 +622,6 @@
.boost_enabled = true,
};
-static inline int clk_osm_count_ns(struct clk_osm *c, u64 nsec)
-{
- u64 temp;
-
- temp = (u64)c->osm_clk_rate * nsec;
- do_div(temp, 1000000000);
-
- return temp;
-}
-
-static void clk_osm_program_mem_acc_regs(struct clk_osm *c)
-{
- if (c->secure_init) {
- clk_osm_write_seq_reg(c,
- c->pbases[OSM_BASE] + MEMACC_CROSSOVER_VC,
- DATA_MEM(57));
- clk_osm_write_seq_reg(c, c->mem_acc_addr[0], DATA_MEM(48));
- clk_osm_write_seq_reg(c, c->mem_acc_addr[1], DATA_MEM(49));
- clk_osm_write_seq_reg(c, c->mem_acc_addr[2], DATA_MEM(50));
- clk_osm_write_seq_reg(c, c->mem_acc_crossover_vc,
- DATA_MEM(78));
- clk_osm_write_seq_reg(c, c->mem_acc_level_vc[0], DATA_MEM(79));
- clk_osm_write_seq_reg(c, c->mem_acc_level_vc[1], DATA_MEM(80));
- /*
- * Note that DATA_MEM[81] -> DATA_MEM[89] values will be
- * confirmed post-si. Use a value of 1 for DATA_MEM[89] and
- * leave the rest of them as 0.
- */
- clk_osm_write_seq_reg(c, 1, DATA_MEM(89));
- } else {
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(78),
- c->mem_acc_crossover_vc);
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(79),
- c->mem_acc_level_vc[0]);
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(80),
- c->mem_acc_level_vc[1]);
- }
-}
-
-static void clk_osm_program_apm_regs(struct clk_osm *c)
-{
- if (c == &l3_clk || c == &pwrcl_clk)
- return;
-
- /*
- * Program address of the control register used to configure
- * the Array Power Mux controller
- */
- clk_osm_write_seq_reg(c, c->apm_mode_ctl, DATA_MEM(41));
-
- /* Program address of controller status register */
- clk_osm_write_seq_reg(c, c->apm_status_ctl, DATA_MEM(43));
-
- /* Program address of crossover register */
- clk_osm_write_seq_reg(c, c->pbases[OSM_BASE] + APM_CROSSOVER_VC,
- DATA_MEM(44));
-
- /* Program mode value to switch APM to VDD_APC */
- clk_osm_write_seq_reg(c, APM_APC_MODE, DATA_MEM(72));
-
- /* Program mode value to switch APM to VDD_MX */
- clk_osm_write_seq_reg(c, APM_MX_MODE, DATA_MEM(73));
-
- /* Program mask used to move into read_mask port */
- clk_osm_write_seq_reg(c, APM_READ_DATA_MASK, DATA_MEM(74));
-
- /* Value used to move into read_exp port */
- clk_osm_write_seq_reg(c, APM_APC_READ_VAL, DATA_MEM(75));
- clk_osm_write_seq_reg(c, APM_MX_READ_VAL, DATA_MEM(76));
-}
-
-static void clk_osm_do_additional_setup(struct clk_osm *c,
- struct platform_device *pdev)
-{
- if (!c->secure_init)
- return;
-
- dev_info(&pdev->dev, "Performing additional OSM setup due to lack of TZ for cluster=%d\n",
- c->cluster_num);
-
- /* PLL L_VAL & post-div programming */
- clk_osm_write_seq_reg(c, c->apcs_pll_min_freq, DATA_MEM(32));
- clk_osm_write_seq_reg(c, c->l_val_base, DATA_MEM(33));
- clk_osm_write_seq_reg(c, c->apcs_pll_user_ctl, DATA_MEM(34));
- clk_osm_write_seq_reg(c, PLL_POST_DIV1, DATA_MEM(35));
- clk_osm_write_seq_reg(c, PLL_POST_DIV2, DATA_MEM(36));
-
- /* APM Programming */
- clk_osm_program_apm_regs(c);
-
- /* GFMUX Programming */
- clk_osm_write_seq_reg(c, c->cfg_gfmux_addr, DATA_MEM(37));
- clk_osm_write_seq_reg(c, 0x1, DATA_MEM(65));
- clk_osm_write_seq_reg(c, 0x2, DATA_MEM(66));
- clk_osm_write_seq_reg(c, 0x3, DATA_MEM(67));
- clk_osm_write_seq_reg(c, 0x40000000, DATA_MEM(68));
- clk_osm_write_seq_reg(c, 0x20000000, DATA_MEM(69));
- clk_osm_write_seq_reg(c, 0x10000000, DATA_MEM(70));
- clk_osm_write_seq_reg(c, 0x70000000, DATA_MEM(71));
-
- /* Override programming */
- clk_osm_write_seq_reg(c, c->pbases[OSM_BASE] +
- OVERRIDE_CLUSTER_IDLE_ACK, DATA_MEM(54));
- clk_osm_write_seq_reg(c, 0x3, DATA_MEM(55));
- clk_osm_write_seq_reg(c, c->pbases[OSM_BASE] + PDN_FSM_CTRL_REG,
- DATA_MEM(40));
- clk_osm_write_seq_reg(c, c->pbases[OSM_BASE] + REQ_GEN_FSM_STATUS,
- DATA_MEM(60));
- clk_osm_write_seq_reg(c, 0x10, DATA_MEM(61));
- clk_osm_write_seq_reg(c, 0x70, DATA_MEM(62));
- clk_osm_write_seq_reg(c, c->apcs_cbc_addr, DATA_MEM(112));
- clk_osm_write_seq_reg(c, 0x2, DATA_MEM(113));
-
- if (c == &perfcl_clk) {
- int rc;
- u32 isense_addr;
-
- /* Performance cluster isense programming */
- rc = of_property_read_u32(pdev->dev.of_node,
- "qcom,perfcl-isense-addr", &isense_addr);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,perfcl-isense-addr property, rc=%d\n",
- rc);
- return;
- }
- clk_osm_write_seq_reg(c, isense_addr, DATA_MEM(45));
- clk_osm_write_seq_reg(c, ISENSE_ON_DATA, DATA_MEM(46));
- clk_osm_write_seq_reg(c, ISENSE_OFF_DATA, DATA_MEM(47));
- }
-
- clk_osm_write_seq_reg(c, c->ramp_ctl_addr, DATA_MEM(105));
- clk_osm_write_seq_reg(c, CONSTANT_32, DATA_MEM(92));
-
- /* Enable/disable CPR ramp settings */
- clk_osm_write_seq_reg(c, 0x101C031, DATA_MEM(106));
- clk_osm_write_seq_reg(c, 0x1010031, DATA_MEM(107));
-}
-
-static void clk_osm_setup_fsms(struct clk_osm *c)
-{
- u32 val;
-
- /* Voltage Reduction FSM */
- if (c->red_fsm_en) {
- val = clk_osm_read_reg(c, VMIN_REDUCTION_ENABLE_REG) | BIT(0);
- val |= BVAL(6, 1, c->min_cpr_vc);
- clk_osm_write_reg(c, val, VMIN_REDUCTION_ENABLE_REG,
- OSM_BASE);
-
- clk_osm_write_reg(c, clk_osm_count_ns(c, 10000),
- VMIN_REDUCTION_TIMER_REG, OSM_BASE);
- }
-
- /* Boost FSM */
- if (c->boost_fsm_en) {
- val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
- val |= DELTA_DEX_VAL | CC_BOOST_FSM_EN | IGNORE_PLL_LOCK;
- clk_osm_write_reg(c, val, PDN_FSM_CTRL_REG, OSM_BASE);
-
- val = clk_osm_read_reg(c, CC_BOOST_FSM_TIMERS_REG0);
- val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS));
- val |= BVAL(31, 16, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
- clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG0, OSM_BASE);
-
- val = clk_osm_read_reg(c, CC_BOOST_FSM_TIMERS_REG1);
- val |= BVAL(15, 0, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS));
- val |= BVAL(31, 16, clk_osm_count_ns(c, PLL_WAIT_LOCK_TIME_NS));
- clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG1, OSM_BASE);
-
- val = clk_osm_read_reg(c, CC_BOOST_FSM_TIMERS_REG2);
- val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS));
- clk_osm_write_reg(c, val, CC_BOOST_FSM_TIMERS_REG2, OSM_BASE);
- }
-
- /* Safe Freq FSM */
- if (c->safe_fsm_en) {
- val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
- clk_osm_write_reg(c, val | DCVS_BOOST_FSM_EN_MASK,
- PDN_FSM_CTRL_REG, OSM_BASE);
-
- val = clk_osm_read_reg(c, DCVS_BOOST_FSM_TIMERS_REG0);
- val |= BVAL(31, 16, clk_osm_count_ns(c, 1000));
- clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG0, OSM_BASE);
-
- val = clk_osm_read_reg(c, DCVS_BOOST_FSM_TIMERS_REG1);
- val |= BVAL(15, 0, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
- clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG1, OSM_BASE);
-
- val = clk_osm_read_reg(c, DCVS_BOOST_FSM_TIMERS_REG2);
- val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS));
- clk_osm_write_reg(c, val, DCVS_BOOST_FSM_TIMERS_REG2, OSM_BASE);
-
- }
-
- /* Pulse Swallowing FSM */
- if (c->ps_fsm_en) {
- val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
- clk_osm_write_reg(c, val | PS_BOOST_FSM_EN_MASK,
- PDN_FSM_CTRL_REG, OSM_BASE);
-
- val = clk_osm_read_reg(c, PS_BOOST_FSM_TIMERS_REG0);
- val |= BVAL(15, 0, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
- val |= BVAL(31, 16, clk_osm_count_ns(c, 1000));
- clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG0, OSM_BASE);
-
- val = clk_osm_read_reg(c, PS_BOOST_FSM_TIMERS_REG1);
- val |= BVAL(15, 0, clk_osm_count_ns(c, SAFE_FREQ_WAIT_NS));
- val |= BVAL(31, 16, clk_osm_count_ns(c, 1000));
- clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG1, OSM_BASE);
-
- val = clk_osm_read_reg(c, PS_BOOST_FSM_TIMERS_REG2);
- val |= BVAL(15, 0, clk_osm_count_ns(c, DEXT_DECREMENT_WAIT_NS));
- clk_osm_write_reg(c, val, PS_BOOST_FSM_TIMERS_REG2, OSM_BASE);
- }
-
- /* PLL signal timing control */
- if (c->boost_fsm_en || c->safe_fsm_en || c->ps_fsm_en)
- clk_osm_write_reg(c, 0x2, BOOST_PROG_SYNC_DELAY_REG, OSM_BASE);
-
- /* DCVS droop FSM - only if RCGwRC is not used for di/dt control */
- if (c->droop_fsm_en) {
- val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
- clk_osm_write_reg(c, val | DCVS_DROOP_FSM_EN_MASK,
- PDN_FSM_CTRL_REG, OSM_BASE);
- }
-
- if (c->ps_fsm_en || c->droop_fsm_en) {
- clk_osm_write_reg(c, 0x1, DROOP_PROG_SYNC_DELAY_REG, OSM_BASE);
- clk_osm_write_reg(c, clk_osm_count_ns(c, 100),
- DROOP_RELEASE_TIMER_CTRL, OSM_BASE);
- clk_osm_write_reg(c, clk_osm_count_ns(c, 150),
- DCVS_DROOP_TIMER_CTRL, OSM_BASE);
- /*
- * TODO: Check if DCVS_DROOP_CODE used is correct. Also check
- * if RESYNC_CTRL should be set for L3.
- */
- val = BIT(31) | BVAL(22, 16, 0x2) | BVAL(6, 0, 0x8);
- clk_osm_write_reg(c, val, DROOP_CTRL_REG, OSM_BASE);
- }
-}
-
-static int clk_osm_set_llm_volt_policy(struct platform_device *pdev)
-{
- struct device_node *of = pdev->dev.of_node;
- u32 *array;
- int rc = 0, val, regval;
-
- array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
- GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- /*
- * Setup Timer to control how long OSM should wait before performing
- * DCVS when a LLM up voltage request is received.
- * Time is specified in us.
- */
- rc = of_property_read_u32_array(of, "qcom,llm-volt-up-timer",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No LLM voltage up timer value, rc=%d\n",
- rc);
- } else {
- val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val,
- LLM_VOLTAGE_VOTE_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val,
- LLM_VOLTAGE_VOTE_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val,
- LLM_VOLTAGE_VOTE_INC_HYSTERESIS,
- OSM_BASE);
- }
-
- /*
- * Setup Timer to control how long OSM should wait before performing
- * DCVS when a LLM down voltage request is received.
- * Time is specified in us.
- */
- rc = of_property_read_u32_array(of, "qcom,llm-volt-down-timer",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No LLM Voltage down timer value: %d\n",
- rc);
- } else {
- val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val,
- LLM_VOLTAGE_VOTE_DEC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val,
- LLM_VOLTAGE_VOTE_DEC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val,
- LLM_VOLTAGE_VOTE_DEC_HYSTERESIS,
- OSM_BASE);
- }
-
- /* Enable or disable honoring of LLM Voltage requests */
- rc = of_property_read_bool(pdev->dev.of_node,
- "qcom,enable-llm-volt-vote");
- if (rc) {
- dev_dbg(&pdev->dev, "Honoring LLM Voltage requests\n");
- val = 0;
- } else
- val = 1;
-
- /* Enable or disable LLM VOLT DVCS */
- regval = val | clk_osm_read_reg(&l3_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&l3_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
- regval = val | clk_osm_read_reg(&pwrcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&pwrcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
- regval = val | clk_osm_read_reg(&perfcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&perfcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
-
- /* Wait for the writes to complete */
- clk_osm_mb(&perfcl_clk, OSM_BASE);
-
- devm_kfree(&pdev->dev, array);
- return 0;
-}
-
-static int clk_osm_set_llm_freq_policy(struct platform_device *pdev)
-{
- struct device_node *of = pdev->dev.of_node;
- u32 *array;
- int rc = 0, val, regval;
-
- array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
- GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- /*
- * Setup Timer to control how long OSM should wait before performing
- * DCVS when a LLM up frequency request is received.
- * Time is specified in us.
- */
- rc = of_property_read_u32_array(of, "qcom,llm-freq-up-timer", array,
- MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "Unable to get CC up timer value: %d\n",
- rc);
- } else {
- val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, LLM_FREQ_VOTE_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val,
- LLM_FREQ_VOTE_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val,
- LLM_FREQ_VOTE_INC_HYSTERESIS,
- OSM_BASE);
- }
-
- /*
- * Setup Timer to control how long OSM should wait before performing
- * DCVS when a LLM down frequency request is received.
- * Time is specified in us.
- */
- rc = of_property_read_u32_array(of, "qcom,llm-freq-down-timer",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No LLM Frequency down timer value: %d\n",
- rc);
- } else {
- val = clk_osm_count_ns(&l3_clk, array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, LLM_FREQ_VOTE_DEC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val,
- LLM_FREQ_VOTE_DEC_HYSTERESIS, OSM_BASE);
-
- val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val,
- LLM_FREQ_VOTE_DEC_HYSTERESIS, OSM_BASE);
- }
-
- /* Enable or disable honoring of LLM frequency requests */
- rc = of_property_read_bool(pdev->dev.of_node,
- "qcom,enable-llm-freq-vote");
- if (rc) {
- dev_dbg(&pdev->dev, "Honoring LLM Frequency requests\n");
- val = 0;
- } else
- val = BIT(1);
-
- /* Enable or disable LLM FREQ DVCS */
- regval = val | clk_osm_read_reg(&l3_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&l3_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
- regval = val | clk_osm_read_reg(&pwrcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&pwrcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
- regval = val | clk_osm_read_reg(&perfcl_clk, LLM_INTF_DCVS_DISABLE);
- clk_osm_write_reg(&perfcl_clk, regval, LLM_INTF_DCVS_DISABLE, OSM_BASE);
-
- /* Wait for the write to complete */
- clk_osm_mb(&perfcl_clk, OSM_BASE);
-
- devm_kfree(&pdev->dev, array);
- return 0;
-}
-
-static int clk_osm_set_cc_policy(struct platform_device *pdev)
-{
- int rc = 0, val;
- u32 *array;
- struct device_node *of = pdev->dev.of_node;
-
- array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
- GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- rc = of_property_read_u32_array(of, "qcom,up-timer", array,
- MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No up timer value, rc=%d\n",
- rc);
- } else {
- val = clk_osm_count_ns(&l3_clk,
- array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, SPM_CC_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_INC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CC_INC_HYSTERESIS,
- OSM_BASE);
- }
-
- rc = of_property_read_u32_array(of, "qcom,down-timer",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No down timer value, rc=%d\n", rc);
- } else {
- val = clk_osm_count_ns(&l3_clk,
- array[l3_clk.cluster_num]);
- clk_osm_write_reg(&l3_clk, val, SPM_CC_DEC_HYSTERESIS,
- OSM_BASE);
-
- val = clk_osm_count_ns(&pwrcl_clk,
- array[pwrcl_clk.cluster_num]);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_DEC_HYSTERESIS,
- OSM_BASE);
-
- clk_osm_count_ns(&perfcl_clk,
- array[perfcl_clk.cluster_num]);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CC_DEC_HYSTERESIS,
- OSM_BASE);
- }
-
- /* OSM index override for cluster PC */
- rc = of_property_read_u32_array(of, "qcom,pc-override-index",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_dbg(&pdev->dev, "No PC override index value, rc=%d\n",
- rc);
- clk_osm_write_reg(&pwrcl_clk, 0, CC_ZERO_BEHAV_CTRL, OSM_BASE);
- clk_osm_write_reg(&perfcl_clk, 0, CC_ZERO_BEHAV_CTRL,
- OSM_BASE);
- } else {
- val = BVAL(6, 1, array[pwrcl_clk.cluster_num])
- | ENABLE_OVERRIDE;
- clk_osm_write_reg(&pwrcl_clk, val, CC_ZERO_BEHAV_CTRL,
- OSM_BASE);
- val = BVAL(6, 1, array[perfcl_clk.cluster_num])
- | ENABLE_OVERRIDE;
- clk_osm_write_reg(&perfcl_clk, val, CC_ZERO_BEHAV_CTRL,
- OSM_BASE);
- }
-
- /* Wait for the writes to complete */
- clk_osm_mb(&perfcl_clk, OSM_BASE);
-
- rc = of_property_read_bool(pdev->dev.of_node, "qcom,set-c3-active");
- if (rc) {
- dev_dbg(&pdev->dev, "Treat cores in C3 as active\n");
-
- val = clk_osm_read_reg(&l3_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(2);
- clk_osm_write_reg(&l3_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
-
- val = clk_osm_read_reg(&pwrcl_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(2);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
-
- val = clk_osm_read_reg(&perfcl_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(2);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
- }
-
- rc = of_property_read_bool(pdev->dev.of_node, "qcom,set-c2-active");
- if (rc) {
- dev_dbg(&pdev->dev, "Treat cores in C2 as active\n");
-
- val = clk_osm_read_reg(&l3_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(1);
- clk_osm_write_reg(&l3_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
-
- val = clk_osm_read_reg(&pwrcl_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(1);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
-
- val = clk_osm_read_reg(&perfcl_clk, SPM_CORE_INACTIVE_MAPPING);
- val &= ~BIT(1);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CORE_INACTIVE_MAPPING,
- OSM_BASE);
- }
-
- rc = of_property_read_bool(pdev->dev.of_node, "qcom,disable-cc-dvcs");
- if (rc) {
- dev_dbg(&pdev->dev, "Disabling CC based DCVS\n");
- val = 1;
- } else
- val = 0;
-
- clk_osm_write_reg(&l3_clk, val, SPM_CC_DCVS_DISABLE, OSM_BASE);
- clk_osm_write_reg(&pwrcl_clk, val, SPM_CC_DCVS_DISABLE, OSM_BASE);
- clk_osm_write_reg(&perfcl_clk, val, SPM_CC_DCVS_DISABLE, OSM_BASE);
-
- /* Wait for the writes to complete */
- clk_osm_mb(&perfcl_clk, OSM_BASE);
-
- devm_kfree(&pdev->dev, array);
- return 0;
-}
-
-static void clk_osm_setup_cluster_pll(struct clk_osm *c)
-{
- writel_relaxed(0x0, c->vbases[PLL_BASE] + PLL_MODE);
- writel_relaxed(0x26, c->vbases[PLL_BASE] + PLL_L_VAL);
- writel_relaxed(0x8, c->vbases[PLL_BASE] +
- PLL_USER_CTRL);
- writel_relaxed(0x20000AA8, c->vbases[PLL_BASE] +
- PLL_CONFIG_CTL_LO);
- writel_relaxed(0x000003D2, c->vbases[PLL_BASE] +
- PLL_CONFIG_CTL_HI);
- writel_relaxed(0x2, c->vbases[PLL_BASE] +
- PLL_MODE);
-
- /* Ensure writes complete before delaying */
- clk_osm_mb(c, PLL_BASE);
-
- udelay(PLL_WAIT_LOCK_TIME_US);
-
- writel_relaxed(0x6, c->vbases[PLL_BASE] + PLL_MODE);
-
- /* Ensure write completes before delaying */
- clk_osm_mb(c, PLL_BASE);
-
- usleep_range(50, 75);
-
- writel_relaxed(0x7, c->vbases[PLL_BASE] + PLL_MODE);
-}
-
-static void clk_osm_misc_programming(struct clk_osm *c)
-{
- u32 lval = 0xFF, val;
- int i;
-
- clk_osm_write_reg(c, BVAL(23, 16, 0xF), SPM_CORE_COUNT_CTRL,
- OSM_BASE);
- clk_osm_write_reg(c, PLL_MIN_LVAL, PLL_MIN_FREQ_REG, OSM_BASE);
-
- /* Pattern to set/clear PLL lock in PDN_FSM_CTRL_REG */
- val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG);
- if (c->secure_init) {
- val |= IGNORE_PLL_LOCK;
- clk_osm_write_seq_reg(c, val, DATA_MEM(108));
- val &= ~IGNORE_PLL_LOCK;
- clk_osm_write_seq_reg(c, val, DATA_MEM(109));
- clk_osm_write_seq_reg(c, MIN_VCO_VAL, DATA_MEM(110));
- } else {
- val |= IGNORE_PLL_LOCK;
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(108), val);
- val &= ~IGNORE_PLL_LOCK;
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(109), val);
- }
-
- /* Program LVAL corresponding to first turbo VC */
- for (i = 0; i < c->num_entries; i++) {
- if (c->osm_table[i].virtual_corner ==
- c->mem_acc_level_vc[1]) {
- lval = c->osm_table[i].freq_data & GENMASK(7, 0);
- break;
- }
- }
-
- if (c->secure_init)
- clk_osm_write_seq_reg(c, lval, DATA_MEM(114));
- else
- scm_io_write(c->pbases[SEQ_BASE] + DATA_MEM(114), lval);
-
-}
-
-static int clk_osm_setup_hw_table(struct clk_osm *c)
-{
- struct osm_entry *entry = c->osm_table;
- int i;
- u32 freq_val = 0, volt_val = 0, override_val = 0;
- u32 table_entry_offset, last_mem_acc_level, last_virtual_corner = 0;
-
- for (i = 0; i < OSM_TABLE_SIZE; i++) {
- if (i < c->num_entries) {
- freq_val = entry[i].freq_data;
- volt_val = BVAL(27, 24, entry[i].mem_acc_level)
- | BVAL(21, 16, entry[i].virtual_corner)
- | BVAL(11, 0, entry[i].open_loop_volt);
- override_val = entry[i].override_data;
-
- if (last_virtual_corner && last_virtual_corner ==
- entry[i].virtual_corner && last_mem_acc_level !=
- entry[i].mem_acc_level) {
- pr_err("invalid LUT entry at row=%d virtual_corner=%d, mem_acc_level=%d\n",
- i, entry[i].virtual_corner,
- entry[i].mem_acc_level);
- return -EINVAL;
- }
- last_virtual_corner = entry[i].virtual_corner;
- last_mem_acc_level = entry[i].mem_acc_level;
- }
-
- table_entry_offset = i * OSM_REG_SIZE;
- clk_osm_write_reg(c, freq_val, FREQ_REG + table_entry_offset,
- OSM_BASE);
- clk_osm_write_reg(c, volt_val, VOLT_REG + table_entry_offset,
- OSM_BASE);
- clk_osm_write_reg(c, override_val, OVERRIDE_REG +
- table_entry_offset, OSM_BASE);
- }
-
- /* Make sure all writes go through */
- clk_osm_mb(c, OSM_BASE);
-
- return 0;
-}
-
-static void clk_osm_print_osm_table(struct clk_osm *c)
-{
- int i;
- struct osm_entry *table = c->osm_table;
- u32 pll_src, pll_div, lval, core_count;
-
- pr_debug("Index, Frequency, VC, OLV (mv), Core Count, PLL Src, PLL Div, L-Val, ACC Level\n");
- for (i = 0; i < c->num_entries; i++) {
- pll_src = (table[i].freq_data & GENMASK(31, 30)) >> 30;
- pll_div = (table[i].freq_data & GENMASK(29, 28)) >> 28;
- lval = table[i].freq_data & GENMASK(7, 0);
- core_count = (table[i].freq_data & GENMASK(18, 16)) >> 16;
-
- pr_debug("%3d, %11lu, %2u, %5u, %2u, %6u, %8u, %7u, %5u\n",
- i,
- table[i].frequency,
- table[i].virtual_corner,
- table[i].open_loop_volt,
- core_count,
- pll_src,
- pll_div,
- lval,
- table[i].mem_acc_level);
- }
- pr_debug("APM threshold corner=%d, crossover corner=%d\n",
- c->apm_threshold_vc, c->apm_crossover_vc);
- pr_debug("MEM-ACC threshold corner=%d, crossover corner=%d\n",
- c->mem_acc_threshold_vc, c->mem_acc_crossover_vc);
-}
-
static u32 find_voltage(struct clk_osm *c, unsigned long rate)
{
struct osm_entry *table = c->osm_table;
@@ -1749,12 +637,12 @@
return -EINVAL;
}
-static int add_opp(struct clk_osm *c, struct device *dev)
+static int add_opp(struct clk_osm *c, struct device **device_list, int count)
{
unsigned long rate = 0;
u32 uv;
long rc;
- int j = 0;
+ int i, j = 0;
unsigned long min_rate = c->hw.init->rate_max[0];
unsigned long max_rate =
c->hw.init->rate_max[c->hw.init->num_rate_max - 1];
@@ -1767,10 +655,12 @@
return -EINVAL;
}
- rc = dev_pm_opp_add(dev, rate, uv);
- if (rc) {
- pr_warn("failed to add OPP for %lu\n", rate);
- return rc;
+ for (i = 0; i < count; i++) {
+ rc = dev_pm_opp_add(device_list[i], rate, uv);
+ if (rc) {
+ pr_warn("failed to add OPP for %lu\n", rate);
+ return rc;
+ }
}
/*
@@ -1779,13 +669,18 @@
* this information will be used by thermal mitigation and the
* scheduler.
*/
- if (rate == min_rate)
- pr_info("Set OPP pair (%lu Hz, %d uv) on %s\n",
- rate, uv, dev_name(dev));
+ if (rate == min_rate) {
+ for (i = 0; i < count; i++) {
+ pr_info("Set OPP pair (%lu Hz, %d uv) on %s\n",
+ rate, uv, dev_name(device_list[i]));
+ }
+ }
if (rate == max_rate && max_rate != min_rate) {
- pr_info("Set OPP pair (%lu Hz, %d uv) on %s\n",
- rate, uv, dev_name(dev));
+ for (i = 0; i < count; i++) {
+ pr_info("Set OPP pair (%lu Hz, %d uv) on %s\n",
+ rate, uv, dev_name(device_list[i]));
+ }
break;
}
@@ -1795,14 +690,70 @@
return 0;
}
+static int derive_device_list(struct device **device_list,
+ struct device_node *np,
+ char *phandle_name, int count)
+{
+ int i;
+ struct platform_device *pdev;
+ struct device_node *dev_node;
+
+ for (i = 0; i < count; i++) {
+ dev_node = of_parse_phandle(np, phandle_name, i);
+ if (!dev_node) {
+ pr_err("Unable to get device_node pointer for opp-handle (%s)\n",
+ phandle_name);
+ return -ENODEV;
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+ if (!pdev) {
+ pr_err("Unable to find platform_device node for opp-handle (%s)\n",
+ phandle_name);
+ return -ENODEV;
+ }
+ device_list[i] = &pdev->dev;
+ }
+ return 0;
+}
+
+static void populate_l3_opp_table(struct device_node *np, char *phandle_name)
+{
+ struct device **device_list;
+ int len, count, ret = 0;
+
+ if (of_find_property(np, phandle_name, &len)) {
+ count = len / sizeof(u32);
+
+ device_list = kcalloc(count, sizeof(struct device *),
+ GFP_KERNEL);
+ if (!device_list)
+ return;
+
+ ret = derive_device_list(device_list, np, phandle_name, count);
+ if (ret < 0) {
+ pr_err("Failed to fill device_list for %s\n",
+ phandle_name);
+ return;
+ }
+ } else {
+ pr_debug("Unable to find %s\n", phandle_name);
+ return;
+ }
+
+ if (add_opp(&l3_clk, device_list, count))
+ pr_err("Failed to add OPP levels for %s\n", phandle_name);
+
+ kfree(device_list);
+}
+
static void populate_opp_table(struct platform_device *pdev)
{
int cpu;
struct device *cpu_dev;
struct clk_osm *c, *parent;
struct clk_hw *hw_parent;
- struct device_node *l3_node_0, *l3_node_4;
- struct platform_device *l3_dev_0, *l3_dev_4;
+ struct device_node *np = pdev->dev.of_node;
for_each_possible_cpu(cpu) {
c = logical_cpu_to_clk(cpu);
@@ -1815,40 +766,12 @@
parent = to_clk_osm(hw_parent);
cpu_dev = get_cpu_device(cpu);
if (cpu_dev)
- if (add_opp(parent, cpu_dev))
+ if (add_opp(parent, &cpu_dev, 1))
pr_err("Failed to add OPP levels for %s\n",
dev_name(cpu_dev));
}
- l3_node_0 = of_parse_phandle(pdev->dev.of_node, "l3-dev0", 0);
- if (!l3_node_0) {
- pr_err("can't find the L3 cluster 0 dt node\n");
- return;
- }
-
- l3_dev_0 = of_find_device_by_node(l3_node_0);
- if (!l3_dev_0) {
- pr_err("can't find the L3 cluster 0 dt device\n");
- return;
- }
-
- if (add_opp(&l3_clk, &l3_dev_0->dev))
- pr_err("Failed to add OPP levels for L3 cluster 0\n");
-
- l3_node_4 = of_parse_phandle(pdev->dev.of_node, "l3-dev4", 0);
- if (!l3_node_4) {
- pr_err("can't find the L3 cluster 1 dt node\n");
- return;
- }
-
- l3_dev_4 = of_find_device_by_node(l3_node_4);
- if (!l3_dev_4) {
- pr_err("can't find the L3 cluster 1 dt device\n");
- return;
- }
-
- if (add_opp(&l3_clk, &l3_dev_4->dev))
- pr_err("Failed to add OPP levels for L3 cluster 1\n");
+ populate_l3_opp_table(np, "l3-devs");
}
static u64 clk_osm_get_cpu_cycle_counter(int cpu)
@@ -1890,196 +813,6 @@
return cycle_counter_ret;
}
-static void clk_osm_setup_cycle_counters(struct clk_osm *c)
-{
- u32 ratio = c->osm_clk_rate;
- u32 val = 0;
-
- /* Enable cycle counter */
- val = BIT(0);
- /* Setup OSM clock to XO ratio */
- do_div(ratio, c->xo_clk_rate);
- val |= BVAL(5, 1, ratio - 1) | OSM_CYCLE_COUNTER_USE_XO_EDGE_EN;
-
- clk_osm_write_reg(c, val, OSM_CYCLE_COUNTER_CTRL_REG, OSM_BASE);
- pr_debug("OSM to XO clock ratio: %d\n", ratio);
-}
-
-static int clk_osm_resolve_crossover_corners(struct clk_osm *c,
- struct platform_device *pdev)
-{
- struct regulator *regulator = c->vdd_reg;
- int count, vc, i, memacc_threshold, apm_threshold;
- int rc = 0;
- u32 corner_volt;
-
- if (c == &l3_clk || c == &pwrcl_clk)
- return rc;
-
- rc = of_property_read_u32(pdev->dev.of_node,
- "qcom,perfcl-apcs-apm-threshold-voltage",
- &apm_threshold);
- if (rc) {
- pr_err("qcom,perfcl-apcs-apm-threshold-voltage property not specified\n");
- return rc;
- }
-
- rc = of_property_read_u32(pdev->dev.of_node,
- "qcom,perfcl-apcs-mem-acc-threshold-voltage",
- &memacc_threshold);
- if (rc) {
- pr_err("qcom,perfcl-apcs-mem-acc-threshold-voltage property not specified\n");
- return rc;
- }
-
- /*
- * Initialize VC settings in case none of them go above the voltage
- * limits
- */
- c->apm_threshold_vc = c->apm_crossover_vc = c->mem_acc_crossover_vc =
- c->mem_acc_threshold_vc = MAX_VC;
-
- count = regulator_count_voltages(regulator);
- if (count < 0) {
- pr_err("Failed to get the number of virtual corners supported\n");
- return count;
- }
-
- c->apm_crossover_vc = count - 2;
- c->mem_acc_crossover_vc = count - 1;
-
- for (i = 0; i < OSM_TABLE_SIZE; i++) {
- vc = c->osm_table[i].virtual_corner + 1;
- corner_volt = regulator_list_corner_voltage(regulator, vc);
-
- if (c->apm_threshold_vc == MAX_VC &&
- corner_volt >= apm_threshold)
- c->apm_threshold_vc = c->osm_table[i].virtual_corner;
-
- if (c->mem_acc_threshold_vc == MAX_VC &&
- corner_volt >= memacc_threshold)
- c->mem_acc_threshold_vc =
- c->osm_table[i].virtual_corner;
- }
-
- return rc;
-}
-
-static int clk_osm_resolve_open_loop_voltages(struct clk_osm *c)
-{
- struct regulator *regulator = c->vdd_reg;
- u32 vc, mv;
- int i;
-
- for (i = 0; i < OSM_TABLE_SIZE; i++) {
- vc = c->osm_table[i].virtual_corner + 1;
- /* Voltage is in uv. Convert to mv */
- mv = regulator_list_corner_voltage(regulator, vc) / 1000;
- c->osm_table[i].open_loop_volt = mv;
- }
-
- return 0;
-}
-
-static int clk_osm_get_lut(struct platform_device *pdev,
- struct clk_osm *c, char *prop_name)
-{
- struct device_node *of = pdev->dev.of_node;
- int prop_len, total_elems, num_rows, i, j, k;
- int rc = 0;
- u32 *array;
- u32 *fmax_temp;
- u32 data;
- unsigned long abs_fmax = 0;
- bool last_entry = false;
-
- if (!of_find_property(of, prop_name, &prop_len)) {
- dev_err(&pdev->dev, "missing %s\n", prop_name);
- return -EINVAL;
- }
-
- total_elems = prop_len / sizeof(u32);
- if (total_elems % NUM_FIELDS) {
- dev_err(&pdev->dev, "bad length %d\n", prop_len);
- return -EINVAL;
- }
-
- num_rows = total_elems / NUM_FIELDS;
-
- fmax_temp = devm_kzalloc(&pdev->dev, num_rows * sizeof(unsigned long),
- GFP_KERNEL);
- if (!fmax_temp)
- return -ENOMEM;
-
- array = devm_kzalloc(&pdev->dev, prop_len, GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- rc = of_property_read_u32_array(of, prop_name, array, total_elems);
- if (rc) {
- dev_err(&pdev->dev, "Unable to parse OSM table, rc=%d\n", rc);
- goto exit;
- }
-
- pr_debug("%s: Entries in Table: %d\n", __func__, num_rows);
- c->num_entries = num_rows;
- if (c->num_entries > OSM_TABLE_SIZE) {
- pr_err("LUT entries %d exceed maximum size %d\n",
- c->num_entries, OSM_TABLE_SIZE);
- return -EINVAL;
- }
-
- for (i = 0, j = 0, k = 0; j < OSM_TABLE_SIZE; j++) {
- c->osm_table[j].frequency = array[i + FREQ];
- c->osm_table[j].freq_data = array[i + FREQ_DATA];
- c->osm_table[j].override_data = array[i + PLL_OVERRIDES];
- c->osm_table[j].mem_acc_level = array[i + MEM_ACC_LEVEL];
- /* Voltage corners are 0 based in the OSM LUT */
- c->osm_table[j].virtual_corner = array[i + VIRTUAL_CORNER] - 1;
- pr_debug("index=%d freq=%ld virtual_corner=%d freq_data=0x%x override_data=0x%x mem_acc_level=0x%x\n",
- j, c->osm_table[j].frequency,
- c->osm_table[j].virtual_corner,
- c->osm_table[j].freq_data,
- c->osm_table[j].override_data,
- c->osm_table[j].mem_acc_level);
-
- data = (array[i + FREQ_DATA] & GENMASK(29, 28)) >> 28;
- if (j && !c->min_cpr_vc && !data)
- c->min_cpr_vc = c->osm_table[j].virtual_corner;
-
- data = (array[i + FREQ_DATA] & GENMASK(18, 16)) >> 16;
- if (!last_entry && data == MAX_CORE_COUNT) {
- fmax_temp[k] = array[i];
- k++;
- }
-
- if (i < total_elems - NUM_FIELDS)
- i += NUM_FIELDS;
- else {
- abs_fmax = array[i];
- last_entry = true;
- }
- }
- fmax_temp[k++] = abs_fmax;
-
- osm_clks_init[c->cluster_num].rate_max = devm_kzalloc(&pdev->dev,
- k * sizeof(unsigned long),
- GFP_KERNEL);
- if (!osm_clks_init[c->cluster_num].rate_max) {
- rc = -ENOMEM;
- goto exit;
- }
-
- for (i = 0; i < k; i++)
- osm_clks_init[c->cluster_num].rate_max[i] = fmax_temp[i];
-
- osm_clks_init[c->cluster_num].num_rate_max = k;
-exit:
- devm_kfree(&pdev->dev, fmax_temp);
- devm_kfree(&pdev->dev, array);
- return rc;
-}
-
static int clk_osm_read_lut(struct platform_device *pdev, struct clk_osm *c)
{
u32 data, src, lval, i, j = OSM_TABLE_SIZE;
@@ -2123,494 +856,9 @@
return 0;
}
-static int clk_osm_parse_acd_dt_configs(struct platform_device *pdev)
-{
- struct device_node *of = pdev->dev.of_node;
- u32 *array;
- int rc = 0;
-
- array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
- GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- l3_clk.acd_init = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "l3_acd") != NULL ? true : false;
- pwrcl_clk.acd_init = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "pwrcl_acd") != NULL ? true : false;
- perfcl_clk.acd_init = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "perfcl_acd") != NULL ? true : false;
-
- if (pwrcl_clk.acd_init || perfcl_clk.acd_init || l3_clk.acd_init) {
- rc = of_property_read_u32_array(of, "qcom,acdtd-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdtd-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_td = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_td = array[perfcl_clk.cluster_num];
- l3_clk.acd_td = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdcr-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdcr-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_cr = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_cr = array[perfcl_clk.cluster_num];
- l3_clk.acd_cr = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdsscr-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdsscr-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_sscr = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_sscr = array[perfcl_clk.cluster_num];
- l3_clk.acd_sscr = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdextint0-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdextint0-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_extint0_cfg = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_extint0_cfg = array[perfcl_clk.cluster_num];
- l3_clk.acd_extint0_cfg = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdextint1-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdextint1-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_extint1_cfg = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_extint1_cfg = array[perfcl_clk.cluster_num];
- l3_clk.acd_extint1_cfg = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdautoxfer-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdautoxfer-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- pwrcl_clk.acd_autoxfer_ctl = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_autoxfer_ctl = array[perfcl_clk.cluster_num];
- l3_clk.acd_autoxfer_ctl = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdavg-init",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdavg-init property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- pwrcl_clk.acd_avg_init = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_avg_init = array[perfcl_clk.cluster_num];
- l3_clk.acd_avg_init = array[l3_clk.cluster_num];
- }
-
- if (pwrcl_clk.acd_avg_init || perfcl_clk.acd_avg_init ||
- l3_clk.acd_avg_init) {
- rc = of_property_read_u32_array(of, "qcom,acdavgcfg0-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdavgcfg0-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- pwrcl_clk.acd_avg_cfg0 = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_avg_cfg0 = array[perfcl_clk.cluster_num];
- l3_clk.acd_avg_cfg0 = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdavgcfg1-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdavgcfg1-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- pwrcl_clk.acd_avg_cfg1 = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_avg_cfg1 = array[perfcl_clk.cluster_num];
- l3_clk.acd_avg_cfg1 = array[l3_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,acdavgcfg2-val",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,acdavgcfg2-val property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- pwrcl_clk.acd_avg_cfg2 = array[pwrcl_clk.cluster_num];
- perfcl_clk.acd_avg_cfg2 = array[perfcl_clk.cluster_num];
- l3_clk.acd_avg_cfg2 = array[l3_clk.cluster_num];
- }
-
- devm_kfree(&pdev->dev, array);
- return rc;
-}
-
-static int clk_osm_parse_dt_configs(struct platform_device *pdev)
-{
- struct device_node *of = pdev->dev.of_node;
- u32 *array;
- char memacc_str[40];
- int rc = 0;
- struct resource *res;
-
- array = devm_kzalloc(&pdev->dev, MAX_CLUSTER_CNT * sizeof(u32),
- GFP_KERNEL);
- if (!array)
- return -ENOMEM;
-
- rc = of_property_read_u32_array(of, "qcom,l-val-base",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,l-val-base property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.l_val_base = array[l3_clk.cluster_num];
- pwrcl_clk.l_val_base = array[pwrcl_clk.cluster_num];
- perfcl_clk.l_val_base = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apcs-pll-user-ctl",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apcs-pll-user-ctl property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.apcs_pll_user_ctl = array[l3_clk.cluster_num];
- pwrcl_clk.apcs_pll_user_ctl = array[pwrcl_clk.cluster_num];
- perfcl_clk.apcs_pll_user_ctl = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apcs-pll-min-freq",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apcs-pll-min-freq property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.apcs_pll_min_freq = array[l3_clk.cluster_num];
- pwrcl_clk.apcs_pll_min_freq = array[pwrcl_clk.cluster_num];
- perfcl_clk.apcs_pll_min_freq = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apm-mode-ctl",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apm-mode-ctl property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.apm_mode_ctl = array[l3_clk.cluster_num];
- pwrcl_clk.apm_mode_ctl = array[pwrcl_clk.cluster_num];
- perfcl_clk.apm_mode_ctl = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apm-status-ctrl",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apm-status-ctrl property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.apm_status_ctl = array[l3_clk.cluster_num];
- pwrcl_clk.apm_status_ctl = array[pwrcl_clk.cluster_num];
- perfcl_clk.apm_status_ctl = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,cfg-gfmux-addr",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,cfg-gfmux-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.cfg_gfmux_addr = array[l3_clk.cluster_num];
- pwrcl_clk.cfg_gfmux_addr = array[pwrcl_clk.cluster_num];
- perfcl_clk.cfg_gfmux_addr = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apcs-cbc-addr",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apcs-cbc-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.apcs_cbc_addr = array[l3_clk.cluster_num];
- pwrcl_clk.apcs_cbc_addr = array[pwrcl_clk.cluster_num];
- perfcl_clk.apcs_cbc_addr = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32_array(of, "qcom,apcs-ramp-ctl-addr",
- array, MAX_CLUSTER_CNT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,apcs-ramp-ctl-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.ramp_ctl_addr = array[l3_clk.cluster_num];
- pwrcl_clk.ramp_ctl_addr = array[pwrcl_clk.cluster_num];
- perfcl_clk.ramp_ctl_addr = array[perfcl_clk.cluster_num];
-
- rc = of_property_read_u32(of, "qcom,xo-clk-rate",
- &pwrcl_clk.xo_clk_rate);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,xo-clk-rate property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- l3_clk.xo_clk_rate = perfcl_clk.xo_clk_rate = pwrcl_clk.xo_clk_rate;
-
- rc = of_property_read_u32(of, "qcom,osm-clk-rate",
- &pwrcl_clk.osm_clk_rate);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,osm-clk-rate property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- l3_clk.osm_clk_rate = perfcl_clk.osm_clk_rate = pwrcl_clk.osm_clk_rate;
-
- rc = of_property_read_u32(of, "qcom,cc-reads",
- &pwrcl_clk.cycle_counter_reads);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,cc-reads property, rc=%d\n",
- rc);
- return -EINVAL;
- }
- l3_clk.cycle_counter_reads = perfcl_clk.cycle_counter_reads =
- pwrcl_clk.cycle_counter_reads;
-
- rc = of_property_read_u32(of, "qcom,cc-delay",
- &pwrcl_clk.cycle_counter_delay);
- if (rc)
- dev_dbg(&pdev->dev, "no delays between cycle counter reads\n");
- else
- l3_clk.cycle_counter_delay = perfcl_clk.cycle_counter_delay =
- pwrcl_clk.cycle_counter_delay;
-
- rc = of_property_read_u32(of, "qcom,cc-factor",
- &pwrcl_clk.cycle_counter_factor);
- if (rc)
- dev_dbg(&pdev->dev, "no factor specified for cycle counter estimation\n");
- else
- l3_clk.cycle_counter_factor = perfcl_clk.cycle_counter_factor =
- pwrcl_clk.cycle_counter_factor;
-
- l3_clk.red_fsm_en = perfcl_clk.red_fsm_en = pwrcl_clk.red_fsm_en =
- of_property_read_bool(of, "qcom,red-fsm-en");
-
- l3_clk.boost_fsm_en = perfcl_clk.boost_fsm_en =
- pwrcl_clk.boost_fsm_en =
- of_property_read_bool(of, "qcom,boost-fsm-en");
-
- l3_clk.safe_fsm_en = perfcl_clk.safe_fsm_en = pwrcl_clk.safe_fsm_en =
- of_property_read_bool(of, "qcom,safe-fsm-en");
-
- l3_clk.ps_fsm_en = perfcl_clk.ps_fsm_en = pwrcl_clk.ps_fsm_en =
- of_property_read_bool(of, "qcom,ps-fsm-en");
-
- l3_clk.droop_fsm_en = perfcl_clk.droop_fsm_en =
- pwrcl_clk.droop_fsm_en =
- of_property_read_bool(of, "qcom,droop-fsm-en");
-
- devm_kfree(&pdev->dev, array);
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "l3_sequencer");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for l3_sequencer\n");
- return -ENOMEM;
- }
-
- l3_clk.pbases[SEQ_BASE] = (unsigned long)res->start;
- l3_clk.vbases[SEQ_BASE] = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
-
- if (!l3_clk.vbases[SEQ_BASE]) {
- dev_err(&pdev->dev, "Unable to map l3_sequencer base\n");
- return -ENOMEM;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "pwrcl_sequencer");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for pwrcl_sequencer\n");
- return -ENOMEM;
- }
-
- pwrcl_clk.pbases[SEQ_BASE] = (unsigned long)res->start;
- pwrcl_clk.vbases[SEQ_BASE] = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
-
- if (!pwrcl_clk.vbases[SEQ_BASE]) {
- dev_err(&pdev->dev, "Unable to map pwrcl_sequencer base\n");
- return -ENOMEM;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "perfcl_sequencer");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for perfcl_sequencer\n");
- return -ENOMEM;
- }
-
- perfcl_clk.pbases[SEQ_BASE] = (unsigned long)res->start;
- perfcl_clk.vbases[SEQ_BASE] = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
-
- if (!perfcl_clk.vbases[SEQ_BASE]) {
- dev_err(&pdev->dev, "Unable to map perfcl_sequencer base\n");
- return -ENOMEM;
- }
-
- snprintf(memacc_str, ARRAY_SIZE(memacc_str),
- "qcom,l3-memacc-level-vc-bin%d", l3_clk.speedbin);
- rc = of_property_read_u32_array(of, memacc_str, l3_clk.mem_acc_level_vc,
- MEM_ACC_LEVELS_LUT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find %s property, rc=%d\n",
- memacc_str, rc);
- return rc;
- }
-
- snprintf(memacc_str, ARRAY_SIZE(memacc_str),
- "qcom,pwrcl-memacc-level-vc-bin%d", pwrcl_clk.speedbin);
- rc = of_property_read_u32_array(of, memacc_str,
- pwrcl_clk.mem_acc_level_vc, MEM_ACC_LEVELS_LUT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find %s property, rc=%d\n",
- memacc_str, rc);
- return rc;
- }
-
- snprintf(memacc_str, ARRAY_SIZE(memacc_str),
- "qcom,perfcl-memacc-level-vc-bin%d", pwrcl_clk.speedbin);
- rc = of_property_read_u32_array(of, memacc_str,
- perfcl_clk.mem_acc_level_vc, MEM_ACC_LEVELS_LUT);
- if (rc) {
- dev_err(&pdev->dev, "unable to find %s property, rc=%d\n",
- memacc_str, rc);
- return rc;
- }
-
- l3_clk.secure_init = perfcl_clk.secure_init = pwrcl_clk.secure_init =
- of_property_read_bool(pdev->dev.of_node, "qcom,osm-no-tz");
-
- if (!pwrcl_clk.secure_init)
- return rc;
-
- rc = of_property_read_u32_array(of, "qcom,l3-mem-acc-addr",
- l3_clk.mem_acc_addr, MEM_ACC_ADDRS);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,l3-mem-acc-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- rc = of_property_read_u32_array(of, "qcom,pwrcl-mem-acc-addr",
- pwrcl_clk.mem_acc_addr, MEM_ACC_ADDRS);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,pwrcl-mem-acc-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- rc = of_property_read_u32_array(of, "qcom,perfcl-mem-acc-addr",
- perfcl_clk.mem_acc_addr, MEM_ACC_ADDRS);
- if (rc) {
- dev_err(&pdev->dev, "unable to find qcom,perfcl-mem-acc-addr property, rc=%d\n",
- rc);
- return -EINVAL;
- }
-
- return rc;
-}
-
-static int clk_osm_acd_resources_init(struct platform_device *pdev)
-{
- struct resource *res;
- unsigned long pbase;
- void *vbase;
- int rc = 0;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "pwrcl_acd");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map pwrcl_acd base\n");
- return -ENOMEM;
- }
- pwrcl_clk.pbases[ACD_BASE] = pbase;
- pwrcl_clk.vbases[ACD_BASE] = vbase;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "perfcl_acd");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map perfcl_acd base\n");
- return -ENOMEM;
- }
- perfcl_clk.pbases[ACD_BASE] = pbase;
- perfcl_clk.vbases[ACD_BASE] = vbase;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "l3_acd");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map l3_acd base\n");
- return -ENOMEM;
- }
- l3_clk.pbases[ACD_BASE] = pbase;
- l3_clk.vbases[ACD_BASE] = vbase;
- }
- return rc;
-}
-
static int clk_osm_resources_init(struct platform_device *pdev)
{
- struct device_node *node;
struct resource *res;
- unsigned long pbase;
- int rc = 0;
- void *vbase;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"osm_l3_base");
@@ -2620,21 +868,14 @@
return -ENOMEM;
}
- l3_clk.pbases[OSM_BASE] = (unsigned long)res->start;
- l3_clk.vbases[OSM_BASE] = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ l3_clk.pbase = (unsigned long)res->start;
+ l3_clk.vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
- if (!l3_clk.vbases[OSM_BASE]) {
+ if (!l3_clk.vbase) {
dev_err(&pdev->dev, "Unable to map osm_l3_base base\n");
return -ENOMEM;
}
- /* Check if OSM has been enabled already by trustzone. */
- if (readl_relaxed(l3_clk.vbases[OSM_BASE] + ENABLE_REG) & ENABLE_OSM) {
- dev_info(&pdev->dev, "OSM has been initialized and enabled by TZ software\n");
- osm_tz_enabled = true;
- }
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"osm_pwrcl_base");
if (!res) {
@@ -2643,10 +884,10 @@
return -ENOMEM;
}
- pwrcl_clk.pbases[OSM_BASE] = (unsigned long)res->start;
- pwrcl_clk.vbases[OSM_BASE] = devm_ioremap(&pdev->dev, res->start,
+ pwrcl_clk.pbase = (unsigned long)res->start;
+ pwrcl_clk.vbase = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (!pwrcl_clk.vbases[OSM_BASE]) {
+ if (!pwrcl_clk.vbase) {
dev_err(&pdev->dev, "Unable to map osm_pwrcl_base base\n");
return -ENOMEM;
}
@@ -2659,394 +900,26 @@
return -ENOMEM;
}
- perfcl_clk.pbases[OSM_BASE] = (unsigned long)res->start;
- perfcl_clk.vbases[OSM_BASE] = devm_ioremap(&pdev->dev, res->start,
+ perfcl_clk.pbase = (unsigned long)res->start;
+ perfcl_clk.vbase = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (!perfcl_clk.vbases[OSM_BASE]) {
+ if (!perfcl_clk.vbase) {
dev_err(&pdev->dev, "Unable to map osm_perfcl_base base\n");
return -ENOMEM;
}
- if (osm_tz_enabled)
- return rc;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "l3_pll");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for l3_pll\n");
- return -ENOMEM;
- }
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
-
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map l3_pll base\n");
- return -ENOMEM;
- }
-
- l3_clk.pbases[PLL_BASE] = pbase;
- l3_clk.vbases[PLL_BASE] = vbase;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrcl_pll");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for pwrcl_pll\n");
- return -ENOMEM;
- }
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
-
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map pwrcl_pll base\n");
- return -ENOMEM;
- }
-
- pwrcl_clk.pbases[PLL_BASE] = pbase;
- pwrcl_clk.vbases[PLL_BASE] = vbase;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "perfcl_pll");
- if (!res) {
- dev_err(&pdev->dev,
- "Unable to get platform resource for perfcl_pll\n");
- return -ENOMEM;
- }
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
-
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map perfcl_pll base\n");
- return -ENOMEM;
- }
-
- perfcl_clk.pbases[PLL_BASE] = pbase;
- perfcl_clk.vbases[PLL_BASE] = vbase;
-
- /* efuse speed bin fuses are optional */
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "l3_efuse");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map in l3_efuse base\n");
- return -ENOMEM;
- }
- l3_clk.pbases[EFUSE_BASE] = pbase;
- l3_clk.vbases[EFUSE_BASE] = vbase;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "pwrcl_efuse");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map pwrcl_efuse base\n");
- return -ENOMEM;
- }
- pwrcl_clk.pbases[EFUSE_BASE] = pbase;
- pwrcl_clk.vbases[EFUSE_BASE] = vbase;
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "perfcl_efuse");
- if (res) {
- pbase = (unsigned long)res->start;
- vbase = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!vbase) {
- dev_err(&pdev->dev, "Unable to map perfcl_efuse base\n");
- return -ENOMEM;
- }
- perfcl_clk.pbases[EFUSE_BASE] = pbase;
- perfcl_clk.vbases[EFUSE_BASE] = vbase;
- }
-
- vdd_l3 = devm_regulator_get(&pdev->dev, "vdd-l3");
- if (IS_ERR(vdd_l3)) {
- rc = PTR_ERR(vdd_l3);
- if (rc != -EPROBE_DEFER)
- dev_err(&pdev->dev, "Unable to get the l3 vreg, rc=%d\n",
- rc);
- return rc;
- }
- l3_clk.vdd_reg = vdd_l3;
-
- vdd_pwrcl = devm_regulator_get(&pdev->dev, "vdd-pwrcl");
- if (IS_ERR(vdd_pwrcl)) {
- rc = PTR_ERR(vdd_pwrcl);
- if (rc != -EPROBE_DEFER)
- dev_err(&pdev->dev, "Unable to get the pwrcl vreg, rc=%d\n",
- rc);
- return rc;
- }
- pwrcl_clk.vdd_reg = vdd_pwrcl;
-
- vdd_perfcl = devm_regulator_get(&pdev->dev, "vdd-perfcl");
- if (IS_ERR(vdd_perfcl)) {
- rc = PTR_ERR(vdd_perfcl);
- if (rc != -EPROBE_DEFER)
- dev_err(&pdev->dev, "Unable to get the perfcl vreg, rc=%d\n",
- rc);
- return rc;
- }
- perfcl_clk.vdd_reg = vdd_perfcl;
-
- node = of_parse_phandle(pdev->dev.of_node, "vdd-l3-supply", 0);
- if (!node) {
- pr_err("Unable to find vdd-l3-supply\n");
- return -EINVAL;
- }
-
- l3_clk.vdd_dev = of_find_device_by_node(node->parent->parent);
- if (!l3_clk.vdd_dev) {
- pr_err("Unable to find device for vdd-l3-supply node\n");
- return -EINVAL;
- }
-
- node = of_parse_phandle(pdev->dev.of_node, "vdd-pwrcl-supply", 0);
- if (!node) {
- pr_err("Unable to find vdd-pwrcl-supply\n");
- return -EINVAL;
- }
-
- pwrcl_clk.vdd_dev = of_find_device_by_node(node->parent->parent);
- if (!pwrcl_clk.vdd_dev) {
- pr_err("Unable to find device for vdd-pwrcl-supply node\n");
- return -EINVAL;
- }
-
- node = of_parse_phandle(pdev->dev.of_node, "vdd-perfcl-supply", 0);
- if (!node) {
- pr_err("Unable to find vdd-perfcl-supply\n");
- return -EINVAL;
- }
-
- perfcl_clk.vdd_dev = of_find_device_by_node(node->parent->parent);
- if (!perfcl_clk.vdd_dev) {
- pr_err("Unable to find device for vdd-perfcl-supply\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int debugfs_get_debug_reg(void *data, u64 *val)
-{
- struct clk_osm *c = data;
-
- if (c->acd_debugfs_addr >= ACD_MASTER_ONLY_REG_ADDR)
- *val = readl_relaxed((char *)c->vbases[ACD_BASE] +
- c->acd_debugfs_addr);
- else
- *val = clk_osm_acd_local_read_reg(c, c->acd_debugfs_addr);
- return 0;
-}
-
-static int debugfs_set_debug_reg(void *data, u64 val)
-{
- struct clk_osm *c = data;
-
- if (c->acd_debugfs_addr >= ACD_MASTER_ONLY_REG_ADDR)
- clk_osm_write_reg(c, val, c->acd_debugfs_addr, ACD_BASE);
- else
- clk_osm_acd_master_write_through_reg(c, val,
- c->acd_debugfs_addr);
-
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(debugfs_acd_debug_reg_fops,
- debugfs_get_debug_reg,
- debugfs_set_debug_reg,
- "0x%llx\n");
-
-static int debugfs_get_debug_reg_addr(void *data, u64 *val)
-{
- struct clk_osm *c = data;
-
- *val = c->acd_debugfs_addr;
- return 0;
-}
-
-static int debugfs_set_debug_reg_addr(void *data, u64 val)
-{
- struct clk_osm *c = data;
-
- if (val > ACD_1P1_MAX_REG_OFFSET) {
- pr_err("invalid ACD register address offset, must be between 0-0x%x\n",
- ACD_1P1_MAX_REG_OFFSET);
- return 0;
- }
-
- c->acd_debugfs_addr = val;
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(debugfs_acd_debug_reg_addr_fops,
- debugfs_get_debug_reg_addr,
- debugfs_set_debug_reg_addr,
- "%llu\n");
-
-static void populate_debugfs_dir(struct clk_osm *c)
-{
- struct dentry *temp;
-
- if (osm_debugfs_base == NULL) {
- osm_debugfs_base = debugfs_create_dir("osm", NULL);
- if (IS_ERR_OR_NULL(osm_debugfs_base)) {
- pr_err("osm debugfs base directory creation failed\n");
- osm_debugfs_base = NULL;
- return;
- }
- }
-
- c->debugfs = debugfs_create_dir(clk_hw_get_name(&c->hw),
- osm_debugfs_base);
- if (IS_ERR_OR_NULL(c->debugfs)) {
- pr_err("osm debugfs directory creation failed\n");
- return;
- }
-
- temp = debugfs_create_file("acd_debug_reg",
- 0644,
- c->debugfs, c,
- &debugfs_acd_debug_reg_fops);
- if (IS_ERR_OR_NULL(temp)) {
- pr_err("debugfs_acd_debug_reg_fops debugfs file creation failed\n");
- goto exit;
- }
-
- temp = debugfs_create_file("acd_debug_reg_addr",
- 0644,
- c->debugfs, c,
- &debugfs_acd_debug_reg_addr_fops);
- if (IS_ERR_OR_NULL(temp)) {
- pr_err("debugfs_acd_debug_reg_addr_fops debugfs file creation failed\n");
- goto exit;
- }
-
-exit:
- if (IS_ERR_OR_NULL(temp))
- debugfs_remove_recursive(c->debugfs);
-}
-
-static int clk_osm_acd_init(struct clk_osm *c)
-{
-
- int rc = 0;
- u32 auto_xfer_mask = 0;
-
- if (c->secure_init) {
- clk_osm_write_reg(c, c->pbases[ACD_BASE] + ACDCR,
- DATA_MEM(115), OSM_BASE);
- clk_osm_write_reg(c, c->pbases[ACD_BASE] + ACD_WRITE_CTL,
- DATA_MEM(116), OSM_BASE);
- }
-
- if (!c->acd_init)
- return 0;
-
- c->acd_debugfs_addr = ACD_HW_VERSION;
-
- /* Program ACD tunable-length delay register */
- clk_osm_write_reg(c, c->acd_td, ACDTD, ACD_BASE);
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDTD);
-
- /* Program ACD control register */
- clk_osm_write_reg(c, c->acd_cr, ACDCR, ACD_BASE);
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDCR);
-
- /* Program ACD soft start control register */
- clk_osm_write_reg(c, c->acd_sscr, ACDSSCR, ACD_BASE);
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACDSSCR);
-
- /* Program initial ACD external interface configuration register */
- clk_osm_write_reg(c, c->acd_extint0_cfg, ACD_EXTINT_CFG, ACD_BASE);
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_EXTINT_CFG);
-
- /* Program ACD auto-register transfer control register */
- clk_osm_write_reg(c, c->acd_autoxfer_ctl, ACD_AUTOXFER_CTL, ACD_BASE);
-
- /* Ensure writes complete before transfers to local copy */
- clk_osm_acd_mb(c);
-
- /* Transfer master copies */
- rc = clk_osm_acd_auto_local_write_reg(c, auto_xfer_mask);
- if (rc)
- return rc;
-
- /* Switch CPUSS clock source to ACD clock */
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_GFMUX_CFG);
- rc = clk_osm_acd_master_write_through_reg(c, ACD_GFMUX_CFG_SELECT,
- ACD_GFMUX_CFG);
- if (rc)
- return rc;
-
- /* Program ACD_DCVS_SW */
- rc = clk_osm_acd_master_write_through_reg(c,
- ACD_DCVS_SW_DCVS_IN_PRGR_SET,
- ACD_DCVS_SW);
- if (rc)
- return rc;
-
- rc = clk_osm_acd_master_write_through_reg(c,
- ACD_DCVS_SW_DCVS_IN_PRGR_CLEAR,
- ACD_DCVS_SW);
- if (rc)
- return rc;
-
- udelay(1);
-
- /* Program final ACD external interface configuration register */
- rc = clk_osm_acd_master_write_through_reg(c, c->acd_extint1_cfg,
- ACD_EXTINT_CFG);
- if (rc)
- return rc;
-
- if (c->acd_avg_init) {
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_AVG_CFG_2);
- rc = clk_osm_acd_master_write_through_reg(c, c->acd_avg_cfg2,
- ACD_AVG_CFG_2);
- if (rc)
- return rc;
-
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_AVG_CFG_1);
- rc = clk_osm_acd_master_write_through_reg(c, c->acd_avg_cfg1,
- ACD_AVG_CFG_1);
- if (rc)
- return rc;
-
- auto_xfer_mask |= ACD_REG_RELATIVE_ADDR_BITMASK(ACD_AVG_CFG_0);
- rc = clk_osm_acd_master_write_through_reg(c, c->acd_avg_cfg0,
- ACD_AVG_CFG_0);
- if (rc)
- return rc;
- }
-
- /*
- * ACDCR, ACDTD, ACDSSCR, ACD_EXTINT_CFG, ACD_GFMUX_CFG
- * must be copied from master to local copy on PC exit.
- * Also, ACD_AVG_CFG0, ACF_AVG_CFG1, and ACD_AVG_CFG2 when
- * AVG is enabled.
- */
- clk_osm_write_reg(c, auto_xfer_mask, ACD_AUTOXFER_CFG, ACD_BASE);
return 0;
}
static int clk_cpu_osm_driver_probe(struct platform_device *pdev)
{
int rc = 0, i;
- int pvs_ver = 0;
- u32 pte_efuse, val;
+ u32 val;
int num_clks = ARRAY_SIZE(osm_qcom_clk_hws);
struct clk *ext_xo_clk, *clk;
struct device *dev = &pdev->dev;
struct clk_onecell_data *clk_data;
- char l3speedbinstr[] = "qcom,l3-speedbin0-v0";
- char perfclspeedbinstr[] = "qcom,perfcl-speedbin0-v0";
- char pwrclspeedbinstr[] = "qcom,pwrcl-speedbin0-v0";
struct cpu_cycle_counter_cb cb = {
.get_cpu_cycle_counter = clk_osm_get_cpu_cycle_counter,
};
@@ -3085,282 +958,34 @@
return rc;
}
- if (!osm_tz_enabled) {
- if (l3_clk.vbases[EFUSE_BASE]) {
- /* Multiple speed-bins are supported */
- pte_efuse = readl_relaxed(l3_clk.vbases[EFUSE_BASE]);
- l3_clk.speedbin = ((pte_efuse >> L3_EFUSE_SHIFT) &
- L3_EFUSE_MASK);
- snprintf(l3speedbinstr, ARRAY_SIZE(l3speedbinstr),
- "qcom,l3-speedbin%d-v%d", l3_clk.speedbin, pvs_ver);
- }
+ /* Check if per-core DCVS is enabled/not */
+ val = clk_osm_read_reg(&pwrcl_clk, CORE_DCVS_CTRL);
+ if (val && BIT(0))
+ pwrcl_clk.per_core_dcvs = true;
- dev_info(&pdev->dev, "using L3 speed bin %u and pvs_ver %d\n",
- l3_clk.speedbin, pvs_ver);
+ val = clk_osm_read_reg(&perfcl_clk, CORE_DCVS_CTRL);
+ if (val && BIT(0))
+ perfcl_clk.per_core_dcvs = true;
- rc = clk_osm_get_lut(pdev, &l3_clk, l3speedbinstr);
- if (rc) {
- dev_err(&pdev->dev, "Unable to get OSM LUT for L3, rc=%d\n",
- rc);
- return rc;
- }
+ rc = clk_osm_read_lut(pdev, &l3_clk);
+ if (rc) {
+ dev_err(&pdev->dev, "Unable to read OSM LUT for L3, rc=%d\n",
+ rc);
+ return rc;
+ }
- if (pwrcl_clk.vbases[EFUSE_BASE]) {
- /* Multiple speed-bins are supported */
- pte_efuse = readl_relaxed(pwrcl_clk.vbases[EFUSE_BASE]);
- pwrcl_clk.speedbin = ((pte_efuse >> PWRCL_EFUSE_SHIFT) &
- PWRCL_EFUSE_MASK);
- snprintf(pwrclspeedbinstr, ARRAY_SIZE(pwrclspeedbinstr),
- "qcom,pwrcl-speedbin%d-v%d", pwrcl_clk.speedbin,
- pvs_ver);
- }
+ rc = clk_osm_read_lut(pdev, &pwrcl_clk);
+ if (rc) {
+ dev_err(&pdev->dev, "Unable to read OSM LUT for power cluster, rc=%d\n",
+ rc);
+ return rc;
+ }
- dev_info(&pdev->dev, "using pwrcl speed bin %u and pvs_ver %d\n",
- pwrcl_clk.speedbin, pvs_ver);
-
- rc = clk_osm_get_lut(pdev, &pwrcl_clk, pwrclspeedbinstr);
- if (rc) {
- dev_err(&pdev->dev, "Unable to get OSM LUT for power cluster, rc=%d\n",
- rc);
- return rc;
- }
-
- if (perfcl_clk.vbases[EFUSE_BASE]) {
- /* Multiple speed-bins are supported */
- pte_efuse =
- readl_relaxed(perfcl_clk.vbases[EFUSE_BASE]);
- perfcl_clk.speedbin = ((pte_efuse >> PERFCL_EFUSE_SHIFT)
- & PERFCL_EFUSE_MASK);
- snprintf(perfclspeedbinstr,
- ARRAY_SIZE(perfclspeedbinstr),
- "qcom,perfcl-speedbin%d-v%d",
- perfcl_clk.speedbin, pvs_ver);
- }
-
- dev_info(&pdev->dev, "using perfcl speed bin %u and pvs_ver %d\n",
- perfcl_clk.speedbin, pvs_ver);
-
- rc = clk_osm_get_lut(pdev, &perfcl_clk, perfclspeedbinstr);
- if (rc) {
- dev_err(&pdev->dev, "Unable to get OSM LUT for perf cluster, rc=%d\n",
- rc);
- return rc;
- }
-
- rc = clk_osm_parse_dt_configs(pdev);
- if (rc) {
- dev_err(&pdev->dev, "Unable to parse OSM device tree configurations\n");
- return rc;
- }
-
- rc = clk_osm_parse_acd_dt_configs(pdev);
- if (rc) {
- dev_err(&pdev->dev, "Unable to parse ACD device tree configurations\n");
- return rc;
- }
-
- rc = clk_osm_acd_resources_init(pdev);
- if (rc) {
- dev_err(&pdev->dev, "ACD resources init failed, rc=%d\n",
- rc);
- return rc;
- }
-
- rc = clk_osm_resolve_open_loop_voltages(&l3_clk);
- if (rc) {
- if (rc == -EPROBE_DEFER)
- return rc;
- dev_err(&pdev->dev, "Unable to determine open-loop voltages for L3, rc=%d\n",
- rc);
- return rc;
- }
- rc = clk_osm_resolve_open_loop_voltages(&pwrcl_clk);
- if (rc) {
- if (rc == -EPROBE_DEFER)
- return rc;
- dev_err(&pdev->dev, "Unable to determine open-loop voltages for power cluster, rc=%d\n",
- rc);
- return rc;
- }
- rc = clk_osm_resolve_open_loop_voltages(&perfcl_clk);
- if (rc) {
- if (rc == -EPROBE_DEFER)
- return rc;
- dev_err(&pdev->dev, "Unable to determine open-loop voltages for perf cluster, rc=%d\n",
- rc);
- return rc;
- }
-
- rc = clk_osm_resolve_crossover_corners(&l3_clk, pdev);
- if (rc)
- dev_info(&pdev->dev,
- "No APM crossover corner programmed for L3\n");
- rc = clk_osm_resolve_crossover_corners(&pwrcl_clk, pdev);
- if (rc)
- dev_info(&pdev->dev,
- "No APM crossover corner programmed for pwrcl_clk\n");
- rc = clk_osm_resolve_crossover_corners(&perfcl_clk, pdev);
- if (rc)
- dev_info(&pdev->dev, "No MEM-ACC crossover corner programmed\n");
-
- clk_osm_setup_cycle_counters(&l3_clk);
- clk_osm_setup_cycle_counters(&pwrcl_clk);
- clk_osm_setup_cycle_counters(&perfcl_clk);
-
- clk_osm_print_osm_table(&l3_clk);
- clk_osm_print_osm_table(&pwrcl_clk);
- clk_osm_print_osm_table(&perfcl_clk);
-
- rc = clk_osm_setup_hw_table(&l3_clk);
- if (rc) {
- dev_err(&pdev->dev, "failed to setup l3 hardware table\n");
- goto exit;
- }
- rc = clk_osm_setup_hw_table(&pwrcl_clk);
- if (rc) {
- dev_err(&pdev->dev, "failed to setup power cluster hardware table\n");
- goto exit;
- }
- rc = clk_osm_setup_hw_table(&perfcl_clk);
- if (rc) {
- dev_err(&pdev->dev, "failed to setup perf cluster hardware table\n");
- goto exit;
- }
-
- /* Policy tuning */
- rc = clk_osm_set_cc_policy(pdev);
- if (rc < 0) {
- dev_err(&pdev->dev, "cc policy setup failed");
- goto exit;
- }
-
- /* LLM Freq Policy Tuning */
- rc = clk_osm_set_llm_freq_policy(pdev);
- if (rc < 0) {
- dev_err(&pdev->dev, "LLM Frequency Policy setup failed");
- goto exit;
- }
-
- /* LLM Voltage Policy Tuning */
- rc = clk_osm_set_llm_volt_policy(pdev);
- if (rc < 0) {
- dev_err(&pdev->dev, "Failed to set LLM voltage Policy");
- goto exit;
- }
-
- clk_osm_setup_fsms(&l3_clk);
- clk_osm_setup_fsms(&pwrcl_clk);
- clk_osm_setup_fsms(&perfcl_clk);
-
- /*
- * Program the VC at which the array power supply
- * needs to be switched.
- */
- clk_osm_write_reg(&perfcl_clk, perfcl_clk.apm_threshold_vc,
- APM_CROSSOVER_VC, OSM_BASE);
- if (perfcl_clk.secure_init) {
- clk_osm_write_seq_reg(&perfcl_clk,
- perfcl_clk.apm_crossover_vc, DATA_MEM(77));
- clk_osm_write_seq_reg(&perfcl_clk,
- (0x39 | (perfcl_clk.apm_threshold_vc << 6)),
- DATA_MEM(111));
- } else {
- scm_io_write(perfcl_clk.pbases[SEQ_BASE] + DATA_MEM(77),
- perfcl_clk.apm_crossover_vc);
- scm_io_write(perfcl_clk.pbases[SEQ_BASE] +
- DATA_MEM(111),
- (0x39 | (perfcl_clk.apm_threshold_vc << 6)));
- }
-
- /*
- * Perform typical secure-world HW initialization
- * as necessary.
- */
- clk_osm_do_additional_setup(&l3_clk, pdev);
- clk_osm_do_additional_setup(&pwrcl_clk, pdev);
- clk_osm_do_additional_setup(&perfcl_clk, pdev);
-
- /* MEM-ACC Programming */
- clk_osm_program_mem_acc_regs(&l3_clk);
- clk_osm_program_mem_acc_regs(&pwrcl_clk);
- clk_osm_program_mem_acc_regs(&perfcl_clk);
-
- if (of_property_read_bool(pdev->dev.of_node,
- "qcom,osm-pll-setup")) {
- clk_osm_setup_cluster_pll(&l3_clk);
- clk_osm_setup_cluster_pll(&pwrcl_clk);
- clk_osm_setup_cluster_pll(&perfcl_clk);
- }
-
- /* Misc programming */
- clk_osm_misc_programming(&l3_clk);
- clk_osm_misc_programming(&pwrcl_clk);
- clk_osm_misc_programming(&perfcl_clk);
-
- rc = clk_osm_acd_init(&l3_clk);
- if (rc) {
- pr_err("failed to initialize ACD for L3, rc=%d\n", rc);
- goto exit;
- }
- rc = clk_osm_acd_init(&pwrcl_clk);
- if (rc) {
- pr_err("failed to initialize ACD for pwrcl, rc=%d\n",
- rc);
- goto exit;
- }
- rc = clk_osm_acd_init(&perfcl_clk);
- if (rc) {
- pr_err("failed to initialize ACD for perfcl, rc=%d\n",
- rc);
- goto exit;
- }
-
- pwrcl_clk.per_core_dcvs = perfcl_clk.per_core_dcvs =
- of_property_read_bool(pdev->dev.of_node,
- "qcom,enable-per-core-dcvs");
- if (pwrcl_clk.per_core_dcvs) {
- val = clk_osm_read_reg(&pwrcl_clk, CORE_DCVS_CTRL);
- val |= BIT(0);
- clk_osm_write_reg(&pwrcl_clk, val, CORE_DCVS_CTRL,
- OSM_BASE);
- val = clk_osm_read_reg(&perfcl_clk, CORE_DCVS_CTRL);
- val |= BIT(0);
- clk_osm_write_reg(&perfcl_clk, val, CORE_DCVS_CTRL,
- OSM_BASE);
- }
- } else {
- /* OSM has been enabled already by trustzone */
- rc = clk_osm_read_lut(pdev, &l3_clk);
- if (rc) {
- dev_err(&pdev->dev, "Unable to read OSM LUT for L3, rc=%d\n",
- rc);
- return rc;
- }
-
- rc = clk_osm_read_lut(pdev, &pwrcl_clk);
- if (rc) {
- dev_err(&pdev->dev, "Unable to read OSM LUT for power cluster, rc=%d\n",
- rc);
- return rc;
- }
-
- rc = clk_osm_read_lut(pdev, &perfcl_clk);
- if (rc) {
- dev_err(&pdev->dev, "Unable to read OSM LUT for perf cluster, rc=%d\n",
- rc);
- return rc;
- }
-
- /* Check if per-core DCVS is enabled/not */
- val = clk_osm_read_reg(&pwrcl_clk, CORE_DCVS_CTRL);
- if (val && BIT(0))
- pwrcl_clk.per_core_dcvs = true;
-
- val = clk_osm_read_reg(&perfcl_clk, CORE_DCVS_CTRL);
- if (val && BIT(0))
- perfcl_clk.per_core_dcvs = true;
-
- clk_ops_l3_osm.enable = NULL;
+ rc = clk_osm_read_lut(pdev, &perfcl_clk);
+ if (rc) {
+ dev_err(&pdev->dev, "Unable to read OSM LUT for perf cluster, rc=%d\n",
+ rc);
+ return rc;
}
spin_lock_init(&l3_clk.lock);
@@ -3387,34 +1012,12 @@
get_online_cpus();
- if (!osm_tz_enabled) {
- populate_debugfs_dir(&l3_clk);
- populate_debugfs_dir(&pwrcl_clk);
- populate_debugfs_dir(&perfcl_clk);
-
- /* Configure default rate to lowest frequency */
- for (i = 0; i < MAX_CORE_COUNT; i++) {
- osm_set_index(&pwrcl_clk, 0, i);
- osm_set_index(&perfcl_clk, 0, i);
- }
- }
- /*
- * Set the L3 clock to run off GPLL0 and enable OSM for the domain.
- * In the case that trustzone has already enabled OSM, bring the L3
- * clock rate to a safe level until the devfreq driver comes up and
- * votes for its desired frequency.
- */
- rc = clk_set_rate(l3_clk.hw.clk, OSM_INIT_RATE);
- if (rc) {
- dev_err(&pdev->dev, "Unable to set init rate on L3 cluster, rc=%d\n",
- rc);
- goto provider_err;
- }
WARN(clk_prepare_enable(l3_cluster0_vote_clk.hw.clk),
"clk: Failed to enable cluster0 clock for L3\n");
WARN(clk_prepare_enable(l3_cluster1_vote_clk.hw.clk),
"clk: Failed to enable cluster1 clock for L3\n");
- udelay(300);
+ WARN(clk_prepare_enable(l3_misc_vote_clk.hw.clk),
+ "clk: Failed to enable misc clock for L3\n");
populate_opp_table(pdev);
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 4142dd5..53f0778 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -36,9 +36,6 @@
#include "clk-alpha-pll.h"
#include "vdd-level-sdm845.h"
-#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OFFSET 0x52008
-#define CPUSS_AHB_CLK_SLEEP_ENA BIT(21)
-#define SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA BIT(0)
#define GCC_MMSS_MISC 0x09FFC
#define GCC_GPU_MISC 0x71028
@@ -4288,14 +4285,6 @@
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- /*
- * Set the *_SLEEP_ENA bits to allow certain cpuss* clocks to be
- * turned off by hardware during certain apps low power modes.
- */
- regmap_update_bits(regmap, GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OFFSET,
- CPUSS_AHB_CLK_SLEEP_ENA | SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA,
- CPUSS_AHB_CLK_SLEEP_ENA | SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA);
-
vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
if (IS_ERR(vdd_cx.regulator[0])) {
if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))
diff --git a/drivers/cpuidle/lpm-levels.c b/drivers/cpuidle/lpm-levels.c
index 67f2d0c..dc5ec96 100644
--- a/drivers/cpuidle/lpm-levels.c
+++ b/drivers/cpuidle/lpm-levels.c
@@ -1464,7 +1464,8 @@
struct lpm_cpu_level *cpu_level = &lpm_cpu->levels[i];
snprintf(st->name, CPUIDLE_NAME_LEN, "C%u\n", i);
- snprintf(st->desc, CPUIDLE_DESC_LEN, cpu_level->name);
+ snprintf(st->desc, CPUIDLE_DESC_LEN, "%s",
+ cpu_level->name);
st->flags = 0;
st->exit_latency = cpu_level->pwr.latency_us;
st->power_usage = cpu_level->pwr.ss_power;
diff --git a/drivers/devfreq/arm-memlat-mon.c b/drivers/devfreq/arm-memlat-mon.c
index f4f503e..9943c8c 100644
--- a/drivers/devfreq/arm-memlat-mon.c
+++ b/drivers/devfreq/arm-memlat-mon.c
@@ -36,6 +36,7 @@
INST_IDX,
CM_IDX,
CYC_IDX,
+ STALL_CYC_IDX,
NUM_EVENTS
};
#define INST_EV 0x08
@@ -105,12 +106,19 @@
{
struct cpu_pmu_stats *cpustats = to_cpustats(cpu_grp, cpu);
struct dev_stats *devstats = to_devstats(cpu_grp, cpu);
- unsigned long cyc_cnt;
+ unsigned long cyc_cnt, stall_cnt;
devstats->inst_count = read_event(&cpustats->events[INST_IDX]);
devstats->mem_count = read_event(&cpustats->events[CM_IDX]);
cyc_cnt = read_event(&cpustats->events[CYC_IDX]);
devstats->freq = compute_freq(cpustats, cyc_cnt);
+ if (cpustats->events[STALL_CYC_IDX].pevent) {
+ stall_cnt = read_event(&cpustats->events[STALL_CYC_IDX]);
+ stall_cnt = min(stall_cnt, cyc_cnt);
+ devstats->stall_pct = mult_frac(100, stall_cnt, cyc_cnt);
+ } else {
+ devstats->stall_pct = 100;
+ }
}
static unsigned long get_cnt(struct memlat_hwmon *hw)
@@ -130,7 +138,10 @@
for (i = 0; i < ARRAY_SIZE(cpustats->events); i++) {
cpustats->events[i].prev_count = 0;
- perf_event_release_kernel(cpustats->events[i].pevent);
+ if (cpustats->events[i].pevent) {
+ perf_event_release_kernel(cpustats->events[i].pevent);
+ cpustats->events[i].pevent = NULL;
+ }
}
}
@@ -149,6 +160,7 @@
devstats->inst_count = 0;
devstats->mem_count = 0;
devstats->freq = 0;
+ devstats->stall_pct = 0;
}
mutex_lock(&list_lock);
if (!cpumask_equal(&cpu_grp->cpus, &cpu_grp->inited_cpus))
@@ -182,6 +194,7 @@
struct perf_event *pevent;
struct perf_event_attr *attr;
int err, i;
+ unsigned int event_id;
struct cpu_pmu_stats *cpustats = to_cpustats(cpu_grp, cpu);
/* Allocate an attribute for event initialization */
@@ -190,7 +203,11 @@
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(cpustats->events); i++) {
- attr->config = cpu_grp->event_ids[i];
+ event_id = cpu_grp->event_ids[i];
+ if (!event_id)
+ continue;
+
+ attr->config = event_id;
pevent = perf_event_create_kernel_counter(attr, cpu, NULL,
NULL, NULL);
if (IS_ERR(pevent))
@@ -348,6 +365,13 @@
}
cpu_grp->event_ids[INST_IDX] = event_id;
+ ret = of_property_read_u32(dev->of_node, "qcom,stall-cycle-ev",
+ &event_id);
+ if (ret)
+ dev_dbg(dev, "Stall cycle event not specified. Event ignored.\n");
+ else
+ cpu_grp->event_ids[STALL_CYC_IDX] = event_id;
+
for_each_cpu(cpu, &cpu_grp->cpus)
to_devstats(cpu_grp, cpu)->id = cpu;
diff --git a/drivers/devfreq/governor_bw_hwmon.c b/drivers/devfreq/governor_bw_hwmon.c
index 53c0f8a..a1d9b50 100644
--- a/drivers/devfreq/governor_bw_hwmon.c
+++ b/drivers/devfreq/governor_bw_hwmon.c
@@ -820,11 +820,13 @@
static int devfreq_bw_hwmon_ev_handler(struct devfreq *df,
unsigned int event, void *data)
{
- int ret;
+ int ret = 0;
unsigned int sample_ms;
struct hwmon_node *node;
struct bw_hwmon *hw;
+ mutex_lock(&state_lock);
+
switch (event) {
case DEVFREQ_GOV_START:
sample_ms = df->profile->polling_ms;
@@ -834,7 +836,7 @@
ret = gov_start(df);
if (ret)
- return ret;
+ goto out;
dev_dbg(df->dev.parent,
"Enabled dev BW HW monitor governor\n");
@@ -864,7 +866,7 @@
if (ret) {
dev_err(df->dev.parent,
"Unable to resume HW monitor (%d)\n", ret);
- return ret;
+ goto out;
}
break;
@@ -874,7 +876,7 @@
dev_err(df->dev.parent,
"Unable to suspend BW HW mon governor (%d)\n",
ret);
- return ret;
+ goto out;
}
dev_dbg(df->dev.parent, "Suspended BW HW mon governor\n");
@@ -886,14 +888,17 @@
dev_err(df->dev.parent,
"Unable to resume BW HW mon governor (%d)\n",
ret);
- return ret;
+ goto out;
}
dev_dbg(df->dev.parent, "Resumed BW HW mon governor\n");
break;
}
- return 0;
+out:
+ mutex_unlock(&state_lock);
+
+ return ret;
}
static struct devfreq_governor devfreq_gov_bw_hwmon = {
diff --git a/drivers/devfreq/governor_memlat.c b/drivers/devfreq/governor_memlat.c
index 1a8ef1f..9688502 100644
--- a/drivers/devfreq/governor_memlat.c
+++ b/drivers/devfreq/governor_memlat.c
@@ -35,6 +35,7 @@
struct memlat_node {
unsigned int ratio_ceil;
+ unsigned int stall_floor;
bool mon_started;
bool already_zero;
struct list_head list;
@@ -247,9 +248,11 @@
hw->core_stats[i].id,
hw->core_stats[i].inst_count,
hw->core_stats[i].mem_count,
- hw->core_stats[i].freq, ratio);
+ hw->core_stats[i].freq,
+ hw->core_stats[i].stall_pct, ratio);
if (ratio <= node->ratio_ceil
+ && hw->core_stats[i].stall_pct >= node->stall_floor
&& hw->core_stats[i].freq > max_freq) {
lat_dev = i;
max_freq = hw->core_stats[i].freq;
@@ -275,9 +278,11 @@
}
gov_attr(ratio_ceil, 1U, 10000U);
+gov_attr(stall_floor, 0U, 100U);
static struct attribute *dev_attr[] = {
&dev_attr_ratio_ceil.attr,
+ &dev_attr_stall_floor.attr,
&dev_attr_freq_map.attr,
NULL,
};
diff --git a/drivers/devfreq/governor_memlat.h b/drivers/devfreq/governor_memlat.h
index 8c533ee..f2ba534 100644
--- a/drivers/devfreq/governor_memlat.h
+++ b/drivers/devfreq/governor_memlat.h
@@ -29,6 +29,7 @@
unsigned long inst_count;
unsigned long mem_count;
unsigned long freq;
+ unsigned long stall_pct;
};
struct core_dev_map {
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index ea07d15..7fbc63a 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -88,6 +88,7 @@
struct workqueue_struct *hdcp_workqueue;
struct delayed_work hdcp_cb_work;
struct mutex hdcp_mutex;
+ struct mutex session_lock;
int hdcp_status;
};
@@ -500,6 +501,8 @@
if (!wait_for_completion_timeout(&dp->notification_comp, HZ * 5)) {
pr_warn("%s timeout\n", hpd ? "connect" : "disconnect");
+ /* cancel any pending request */
+ dp->ctrl->abort(dp->ctrl);
return -EINVAL;
}
@@ -634,6 +637,7 @@
dp->ctrl->push_idle(dp->ctrl);
dp->ctrl->off(dp->ctrl);
+ dp->power_on = false;
}
static int dp_display_usbpd_disconnect_cb(struct device *dev)
@@ -662,6 +666,8 @@
rc = dp_display_send_hpd_notification(dp, false);
+ mutex_lock(&dp->session_lock);
+
/* if cable is disconnected, reset psm_enabled flag */
if (!dp->usbpd->alt_mode_cfg_done)
dp->link->psm_enabled = false;
@@ -670,6 +676,8 @@
dp_display_clean(dp);
dp_display_host_deinit(dp);
+
+ mutex_unlock(&dp->session_lock);
end:
return rc;
}
@@ -760,6 +768,7 @@
dp_catalog_put(dp->catalog);
dp_parser_put(dp->parser);
dp_usbpd_put(dp->usbpd);
+ mutex_destroy(&dp->session_lock);
dp_debug_put(dp->debug);
}
@@ -787,6 +796,8 @@
goto error;
}
+ mutex_init(&dp->session_lock);
+
dp->parser = dp_parser_get(dp->pdev);
if (IS_ERR(dp->parser)) {
rc = PTR_ERR(dp->parser);
@@ -890,6 +901,7 @@
dp_parser_put(dp->parser);
error_parser:
dp_usbpd_put(dp->usbpd);
+ mutex_destroy(&dp->session_lock);
error:
return rc;
}
@@ -897,20 +909,20 @@
static int dp_display_set_mode(struct dp_display *dp_display,
struct dp_display_mode *mode)
{
- int rc = 0;
struct dp_display_private *dp;
if (!dp_display) {
pr_err("invalid input\n");
- rc = -EINVAL;
- goto error;
+ return -EINVAL;
}
dp = container_of(dp_display, struct dp_display_private, dp_display);
+ mutex_lock(&dp->session_lock);
dp->panel->pinfo = mode->timing;
dp->panel->init_info(dp->panel);
-error:
- return rc;
+ mutex_unlock(&dp->session_lock);
+
+ return 0;
}
static int dp_display_prepare(struct dp_display *dp)
@@ -925,37 +937,44 @@
if (!dp_display) {
pr_err("invalid input\n");
- rc = -EINVAL;
- goto error;
+ return -EINVAL;
}
dp = container_of(dp_display, struct dp_display_private, dp_display);
+ mutex_lock(&dp->session_lock);
+
if (dp->power_on) {
pr_debug("Link already setup, return\n");
- return 0;
+ goto end;
}
rc = dp->ctrl->on(dp->ctrl);
if (!rc)
dp->power_on = true;
-error:
+end:
+ mutex_unlock(&dp->session_lock);
return rc;
}
static int dp_display_post_enable(struct dp_display *dp_display)
{
- int rc = 0;
struct dp_display_private *dp;
if (!dp_display) {
pr_err("invalid input\n");
- rc = -EINVAL;
- goto end;
+ return -EINVAL;
}
dp = container_of(dp_display, struct dp_display_private, dp_display);
+ mutex_lock(&dp->session_lock);
+
+ if (!dp->power_on) {
+ pr_debug("Link not setup, return\n");
+ goto end;
+ }
+
if (dp->audio_supported) {
dp->audio->bw_code = dp->link->link_params.bw_code;
dp->audio->lane_count = dp->link->link_params.lane_count;
@@ -973,23 +992,30 @@
queue_delayed_work(dp->hdcp_workqueue,
&dp->hdcp_cb_work, HZ / 2);
}
+
end:
- return rc;
+ mutex_unlock(&dp->session_lock);
+ return 0;
}
static int dp_display_pre_disable(struct dp_display *dp_display)
{
- int rc = 0;
struct dp_display_private *dp;
if (!dp_display) {
pr_err("invalid input\n");
- rc = -EINVAL;
- goto error;
+ return -EINVAL;
}
dp = container_of(dp_display, struct dp_display_private, dp_display);
+ mutex_lock(&dp->session_lock);
+
+ if (!dp->power_on) {
+ pr_debug("Link already powered off, return\n");
+ goto end;
+ }
+
if (dp_display_is_hdcp_enabled(dp)) {
dp->hdcp_status = HDCP_STATE_INACTIVE;
@@ -1003,33 +1029,38 @@
dp->link->psm_config(dp->link, &dp->panel->link_info, true);
dp->ctrl->push_idle(dp->ctrl);
-error:
- return rc;
+
+end:
+ mutex_unlock(&dp->session_lock);
+ return 0;
}
static int dp_display_disable(struct dp_display *dp_display)
{
- int rc = 0;
struct dp_display_private *dp;
if (!dp_display) {
pr_err("invalid input\n");
- rc = -EINVAL;
- goto error;
+ return -EINVAL;
}
dp = container_of(dp_display, struct dp_display_private, dp_display);
- if (!dp->power_on || !dp->core_initialized)
- goto error;
+ mutex_lock(&dp->session_lock);
+
+ if (!dp->power_on || !dp->core_initialized) {
+ pr_debug("Link already powered off, return\n");
+ goto end;
+ }
dp->ctrl->off(dp->ctrl);
dp->power_on = false;
+end:
complete_all(&dp->notification_comp);
-error:
- return rc;
+ mutex_unlock(&dp->session_lock);
+ return 0;
}
static int dp_request_irq(struct dp_display *dp_display)
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c
index eb787fa..d793365 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -562,6 +562,15 @@
power = container_of(dp_power, struct dp_power_private, dp_power);
dp_power_clk_enable(dp_power, DP_CORE_PM, false);
+ /*
+ * If the display power on event was not successful, for example if
+ * there was a link training failure, then the link clocks could
+ * possibly still be on. In this scenario, we need to turn off the
+ * link clocks as soon as the cable is disconnected so that the clock
+ * state is cleaned up before subsequent connection events.
+ */
+ if (power->link_clks_on)
+ dp_power_clk_enable(dp_power, DP_CTRL_PM, false);
rc = sde_power_resource_enable(power->phandle,
power->dp_core_client, false);
if (rc) {
diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.c b/drivers/gpu/drm/msm/sde/sde_color_processing.c
index e9ffb96..2c5b7ea 100644
--- a/drivers/gpu/drm/msm/sde/sde_color_processing.c
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.c
@@ -52,6 +52,10 @@
static void dspp_hsic_install_property(struct drm_crtc *crtc);
+static void dspp_memcolor_install_property(struct drm_crtc *crtc);
+
+static void dspp_sixzone_install_property(struct drm_crtc *crtc);
+
static void dspp_ad_install_property(struct drm_crtc *crtc);
static void dspp_vlut_install_property(struct drm_crtc *crtc);
@@ -85,6 +89,8 @@
do { \
func[SDE_DSPP_PCC] = dspp_pcc_install_property; \
func[SDE_DSPP_HSIC] = dspp_hsic_install_property; \
+ func[SDE_DSPP_MEMCOLOR] = dspp_memcolor_install_property; \
+ func[SDE_DSPP_SIXZONE] = dspp_sixzone_install_property; \
func[SDE_DSPP_AD] = dspp_ad_install_property; \
func[SDE_DSPP_VLUT] = dspp_vlut_install_property; \
func[SDE_DSPP_GAMUT] = dspp_gamut_install_property; \
@@ -108,11 +114,11 @@
SDE_CP_CRTC_DSPP_IGC,
SDE_CP_CRTC_DSPP_PCC,
SDE_CP_CRTC_DSPP_GC,
- SDE_CP_CRTC_DSPP_HUE,
- SDE_CP_CRTC_DSPP_SAT,
- SDE_CP_CRTC_DSPP_VAL,
- SDE_CP_CRTC_DSPP_CONT,
- SDE_CP_CRTC_DSPP_MEMCOLOR,
+ SDE_CP_CRTC_DSPP_HSIC,
+ SDE_CP_CRTC_DSPP_MEMCOL_SKIN,
+ SDE_CP_CRTC_DSPP_MEMCOL_SKY,
+ SDE_CP_CRTC_DSPP_MEMCOL_FOLIAGE,
+ SDE_CP_CRTC_DSPP_MEMCOL_PROT,
SDE_CP_CRTC_DSPP_SIXZONE,
SDE_CP_CRTC_DSPP_GAMUT,
SDE_CP_CRTC_DSPP_DITHER,
@@ -667,40 +673,40 @@
}
hw_dspp->ops.setup_gc(hw_dspp, &hw_cfg);
break;
- case SDE_CP_CRTC_DSPP_HUE:
- if (!hw_dspp || !hw_dspp->ops.setup_hue) {
+ case SDE_CP_CRTC_DSPP_HSIC:
+ if (!hw_dspp || !hw_dspp->ops.setup_pa_hsic) {
ret = -EINVAL;
continue;
}
- hw_dspp->ops.setup_hue(hw_dspp, &hw_cfg);
+ hw_dspp->ops.setup_pa_hsic(hw_dspp, &hw_cfg);
break;
- case SDE_CP_CRTC_DSPP_SAT:
- if (!hw_dspp || !hw_dspp->ops.setup_sat) {
+ case SDE_CP_CRTC_DSPP_MEMCOL_SKIN:
+ if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_skin) {
ret = -EINVAL;
continue;
}
- hw_dspp->ops.setup_sat(hw_dspp, &hw_cfg);
+ hw_dspp->ops.setup_pa_memcol_skin(hw_dspp, &hw_cfg);
break;
- case SDE_CP_CRTC_DSPP_VAL:
- if (!hw_dspp || !hw_dspp->ops.setup_val) {
+ case SDE_CP_CRTC_DSPP_MEMCOL_SKY:
+ if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_sky) {
ret = -EINVAL;
continue;
}
- hw_dspp->ops.setup_val(hw_dspp, &hw_cfg);
+ hw_dspp->ops.setup_pa_memcol_sky(hw_dspp, &hw_cfg);
break;
- case SDE_CP_CRTC_DSPP_CONT:
- if (!hw_dspp || !hw_dspp->ops.setup_cont) {
+ case SDE_CP_CRTC_DSPP_MEMCOL_FOLIAGE:
+ if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_foliage) {
ret = -EINVAL;
continue;
}
- hw_dspp->ops.setup_cont(hw_dspp, &hw_cfg);
+ hw_dspp->ops.setup_pa_memcol_foliage(hw_dspp, &hw_cfg);
break;
- case SDE_CP_CRTC_DSPP_MEMCOLOR:
- if (!hw_dspp || !hw_dspp->ops.setup_pa_memcolor) {
+ case SDE_CP_CRTC_DSPP_MEMCOL_PROT:
+ if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_prot) {
ret = -EINVAL;
continue;
}
- hw_dspp->ops.setup_pa_memcolor(hw_dspp, &hw_cfg);
+ hw_dspp->ops.setup_pa_memcol_prot(hw_dspp, &hw_cfg);
break;
case SDE_CP_CRTC_DSPP_SIXZONE:
if (!hw_dspp || !hw_dspp->ops.setup_sixzone) {
@@ -1214,9 +1220,72 @@
switch (version) {
case 1:
snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
- "SDE_DSPP_HUE_V", version);
- sde_cp_crtc_install_range_property(crtc, feature_name,
- SDE_CP_CRTC_DSPP_HUE, 0, U32_MAX, 0);
+ "SDE_DSPP_PA_HSIC_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_HSIC, sizeof(struct drm_msm_pa_hsic));
+ break;
+ default:
+ DRM_ERROR("version %d not supported\n", version);
+ break;
+ }
+}
+
+static void dspp_memcolor_install_property(struct drm_crtc *crtc)
+{
+ char feature_name[256];
+ struct sde_kms *kms = NULL;
+ struct sde_mdss_cfg *catalog = NULL;
+ u32 version;
+
+ kms = get_kms(crtc);
+ catalog = kms->catalog;
+ version = catalog->dspp[0].sblk->memcolor.version >> 16;
+ switch (version) {
+ case 1:
+ snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+ "SDE_DSPP_PA_MEMCOL_SKIN_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_MEMCOL_SKIN,
+ sizeof(struct drm_msm_memcol));
+ snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+ "SDE_DSPP_PA_MEMCOL_SKY_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_MEMCOL_SKY,
+ sizeof(struct drm_msm_memcol));
+ snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+ "SDE_DSPP_PA_MEMCOL_FOLIAGE_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_MEMCOL_FOLIAGE,
+ sizeof(struct drm_msm_memcol));
+ snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+ "SDE_DSPP_PA_MEMCOL_PROT_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_MEMCOL_PROT,
+ sizeof(struct drm_msm_memcol));
+ break;
+ default:
+ DRM_ERROR("version %d not supported\n", version);
+ break;
+ }
+}
+
+static void dspp_sixzone_install_property(struct drm_crtc *crtc)
+{
+ char feature_name[256];
+ struct sde_kms *kms = NULL;
+ struct sde_mdss_cfg *catalog = NULL;
+ u32 version;
+
+ kms = get_kms(crtc);
+ catalog = kms->catalog;
+ version = catalog->dspp[0].sblk->sixzone.version >> 16;
+ switch (version) {
+ case 1:
+ snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",
+ "SDE_DSPP_PA_SIXZONE_V", version);
+ sde_cp_crtc_install_blob_property(crtc, feature_name,
+ SDE_CP_CRTC_DSPP_SIXZONE,
+ sizeof(struct drm_msm_sixzone));
break;
default:
DRM_ERROR("version %d not supported\n", version);
diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.h b/drivers/gpu/drm/msm/sde/sde_color_processing.h
index aff07ef..7eb1738 100644
--- a/drivers/gpu/drm/msm/sde/sde_color_processing.h
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.h
@@ -26,7 +26,8 @@
enum sde_memcolor_type {
MEMCOLOR_SKIN = 0,
MEMCOLOR_SKY,
- MEMCOLOR_FOLIAGE
+ MEMCOLOR_FOLIAGE,
+ MEMCOLOR_MAX
};
/*
diff --git a/drivers/gpu/drm/msm/sde/sde_connector.h b/drivers/gpu/drm/msm/sde/sde_connector.h
index 4018441..beeeb4c 100644
--- a/drivers/gpu/drm/msm/sde/sde_connector.h
+++ b/drivers/gpu/drm/msm/sde/sde_connector.h
@@ -319,7 +319,7 @@
* Returns: Pointer to associated private display structure
*/
#define sde_connector_get_display(C) \
- ((C) ? to_sde_connector((C))->display : 0)
+ ((C) ? to_sde_connector((C))->display : NULL)
/**
* sde_connector_get_panel - get sde connector's private panel pointer
@@ -335,7 +335,7 @@
* Returns: Pointer to associated private encoder structure
*/
#define sde_connector_get_encoder(C) \
- ((C) ? to_sde_connector((C))->encoder : 0)
+ ((C) ? to_sde_connector((C))->encoder : NULL)
/**
* sde_connector_get_propinfo - get sde connector's property info pointer
@@ -343,7 +343,7 @@
* Returns: Pointer to associated private property info structure
*/
#define sde_connector_get_propinfo(C) \
- ((C) ? &to_sde_connector((C))->property_info : 0)
+ ((C) ? &to_sde_connector((C))->property_info : NULL)
/**
* struct sde_connector_state - private connector status structure
diff --git a/drivers/gpu/drm/msm/sde/sde_core_perf.c b/drivers/gpu/drm/msm/sde/sde_core_perf.c
index 9ddca8c..6b36745 100644
--- a/drivers/gpu/drm/msm/sde/sde_core_perf.c
+++ b/drivers/gpu/drm/msm/sde/sde_core_perf.c
@@ -169,6 +169,7 @@
perf->core_clk_rate = kms->perf.fix_core_clk_rate;
}
+ SDE_EVT32(crtc->base.id, perf->core_clk_rate);
SDE_DEBUG(
"crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu llcc_ib=%llu llcc_ab=%llu mem_ib=%llu mem_ab=%llu\n",
crtc->base.id, perf->core_clk_rate,
@@ -293,7 +294,8 @@
}
static void _sde_core_perf_crtc_update_bus(struct sde_kms *kms,
- struct drm_crtc *crtc, u32 bus_id)
+ struct drm_crtc *crtc, u32 bus_id,
+ struct sde_core_perf_params *crtc_perf)
{
u64 bw_sum_of_intfs = 0, bus_ab_quota, bus_ib_quota;
struct sde_core_perf_params perf = { { 0 } };
@@ -303,21 +305,36 @@
struct sde_crtc_state *sde_cstate;
struct msm_drm_private *priv = kms->dev->dev_private;
+ u64 tmp_max_per_pipe_ib;
+ u64 tmp_bw_ctl;
+
drm_for_each_crtc(tmp_crtc, crtc->dev) {
if (_sde_core_perf_crtc_is_power_on(tmp_crtc) &&
_is_crtc_client_type_matches(tmp_crtc, curr_client_type,
&kms->perf)) {
- sde_cstate = to_sde_crtc_state(tmp_crtc->state);
+
+ if (crtc->base.id == tmp_crtc->base.id) {
+ /* for current crtc use the cached values */
+ tmp_max_per_pipe_ib =
+ crtc_perf->max_per_pipe_ib[bus_id];
+ tmp_bw_ctl = crtc_perf->bw_ctl[bus_id];
+ } else {
+ sde_cstate = to_sde_crtc_state(tmp_crtc->state);
+ tmp_max_per_pipe_ib =
+ sde_cstate->new_perf.max_per_pipe_ib[bus_id];
+ tmp_bw_ctl =
+ sde_cstate->new_perf.bw_ctl[bus_id];
+ }
perf.max_per_pipe_ib[bus_id] =
max(perf.max_per_pipe_ib[bus_id],
- sde_cstate->new_perf.max_per_pipe_ib[bus_id]);
+ tmp_max_per_pipe_ib);
- bw_sum_of_intfs += sde_cstate->new_perf.bw_ctl[bus_id];
+ bw_sum_of_intfs += tmp_bw_ctl;
- SDE_DEBUG("crtc=%d bus_id=%d bw=%llu\n",
+ SDE_DEBUG("crtc=%d bus_id=%d bw=%llu perf_pipe:%llu\n",
tmp_crtc->base.id, bus_id,
- sde_cstate->new_perf.bw_ctl[bus_id]);
+ tmp_bw_ctl, tmp_max_per_pipe_ib);
}
}
@@ -442,22 +459,32 @@
SDE_DEBUG("Release BW crtc=%d\n", crtc->base.id);
for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
sde_crtc->cur_perf.bw_ctl[i] = 0;
- _sde_core_perf_crtc_update_bus(kms, crtc, i);
+ _sde_core_perf_crtc_update_bus(kms, crtc, i,
+ &sde_crtc->cur_perf);
}
}
}
-static u64 _sde_core_perf_get_core_clk_rate(struct sde_kms *kms)
+static u64 _sde_core_perf_get_core_clk_rate(struct sde_kms *kms,
+ struct sde_core_perf_params *crct_perf, struct drm_crtc *crtc)
{
u64 clk_rate = kms->perf.perf_tune.min_core_clk;
- struct drm_crtc *crtc;
+ struct drm_crtc *tmp_crtc;
struct sde_crtc_state *sde_cstate;
+ u64 tmp_rate;
- drm_for_each_crtc(crtc, kms->dev) {
- if (_sde_core_perf_crtc_is_power_on(crtc)) {
- sde_cstate = to_sde_crtc_state(crtc->state);
- clk_rate = max(sde_cstate->new_perf.core_clk_rate,
- clk_rate);
+ drm_for_each_crtc(tmp_crtc, kms->dev) {
+ if (_sde_core_perf_crtc_is_power_on(tmp_crtc)) {
+
+ if (crtc->base.id == tmp_crtc->base.id) {
+ /* for current CRTC, use the cached value */
+ tmp_rate = crct_perf->core_clk_rate;
+ } else {
+ sde_cstate = to_sde_crtc_state(tmp_crtc->state);
+ tmp_rate = sde_cstate->new_perf.core_clk_rate;
+ }
+ clk_rate = max(tmp_rate, clk_rate);
+
clk_rate = clk_round_rate(kms->perf.core_clk, clk_rate);
}
}
@@ -504,8 +531,17 @@
SDE_DEBUG("crtc:%d stop_req:%d core_clk:%llu\n",
crtc->base.id, stop_req, kms->perf.core_clk_rate);
+ /*
+ * cache the performance numbers in the crtc prior to the
+ * crtc kickoff, so the same numbers are used during the
+ * perf update that happens post kickoff.
+ */
+ if (params_changed)
+ memcpy(&sde_crtc->new_perf, &sde_cstate->new_perf,
+ sizeof(struct sde_core_perf_params));
+
old = &sde_crtc->cur_perf;
- new = &sde_cstate->new_perf;
+ new = &sde_crtc->new_perf;
if (_sde_core_perf_crtc_is_power_on(crtc) && !stop_req) {
for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
@@ -580,7 +616,7 @@
for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
if (update_bus & BIT(i))
- _sde_core_perf_crtc_update_bus(kms, crtc, i);
+ _sde_core_perf_crtc_update_bus(kms, crtc, i, old);
}
/*
@@ -588,9 +624,10 @@
* bandwidth is available before clock rate is increased.
*/
if (update_clk) {
- clk_rate = _sde_core_perf_get_core_clk_rate(kms);
+ clk_rate = _sde_core_perf_get_core_clk_rate(kms, old, crtc);
- SDE_EVT32(kms->dev, stop_req, clk_rate);
+ SDE_EVT32(kms->dev, stop_req, clk_rate, params_changed,
+ old->core_clk_rate, new->core_clk_rate);
ret = sde_power_clk_set_rate(&priv->phandle,
kms->perf.clk_name, clk_rate);
if (ret) {
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 23ca2e9..4c75ee6 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -2530,6 +2530,11 @@
}
count = ds_data.num_dest_scaler;
+ if (!count) {
+ SDE_DEBUG("no ds data available\n");
+ return 0;
+ }
+
if (!sde_crtc->num_mixers || count > sde_crtc->num_mixers ||
(count && (count != sde_crtc->num_mixers) &&
!(ds_data.ds_cfg[0].flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h
index 59bfc47..a4c0501 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.h
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.h
@@ -280,6 +280,7 @@
struct sde_power_event *power_event;
struct sde_core_perf_params cur_perf;
+ struct sde_core_perf_params new_perf;
struct mutex rp_lock;
struct list_head rp_head;
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.c b/drivers/gpu/drm/msm/sde/sde_encoder.c
index 7c600ca..55173e3 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.c
@@ -194,7 +194,6 @@
* clks and resources after IDLE_TIMEOUT time.
* @vsync_event_work: worker to handle vsync event for autorefresh
* @topology: topology of the display
- * @mode_set_complete: flag to indicate modeset completion
* @rsc_config: rsc configuration for display vtotal, fps, etc.
* @cur_conn_roi: current connector roi
* @prv_conn_roi: previous connector roi to optimize if unchanged
@@ -241,7 +240,6 @@
struct kthread_delayed_work delayed_off_work;
struct kthread_work vsync_event_work;
struct msm_display_topology topology;
- bool mode_set_complete;
struct sde_rsc_cmd_config rsc_config;
struct sde_rect cur_conn_roi;
@@ -559,6 +557,7 @@
}
hw_res->topology = sde_enc->mode_info.topology;
+ hw_res->is_primary = sde_enc->disp_info.is_primary;
}
void sde_encoder_destroy(struct drm_encoder *drm_enc)
@@ -697,6 +696,7 @@
struct sde_kms *sde_kms;
const struct drm_display_mode *mode;
struct drm_display_mode *adj_mode;
+ struct sde_connector *sde_conn = NULL;
int i = 0;
int ret = 0;
@@ -713,6 +713,7 @@
sde_kms = to_sde_kms(priv->kms);
mode = &crtc_state->mode;
adj_mode = &crtc_state->adjusted_mode;
+ sde_conn = to_sde_connector(conn_state->connector);
SDE_EVT32(DRMID(drm_enc));
/*
@@ -742,17 +743,42 @@
}
}
- /* Reserve dynamic resources now. Indicating AtomicTest phase */
- if (!ret) {
- /*
- * Avoid reserving resources when mode set is pending. Topology
- * info may not be available to complete reservation.
+
+ if (!ret && sde_conn && drm_atomic_crtc_needs_modeset(crtc_state)) {
+ struct msm_display_topology *topology = NULL;
+
+ ret = sde_conn->ops.get_mode_info(adj_mode,
+ &sde_enc->mode_info,
+ sde_kms->catalog->max_mixer_width);
+ if (ret) {
+ SDE_ERROR_ENC(sde_enc,
+ "failed to get mode info, rc = %d\n", ret);
+ return ret;
+ }
+
+ /* Reserve dynamic resources, indicating atomic_check phase */
+ ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
+ conn_state, true);
+ if (ret) {
+ SDE_ERROR_ENC(sde_enc,
+ "RM failed to reserve resources, rc = %d\n",
+ ret);
+ return ret;
+ }
+
+ /**
+ * Update connector state with the topology selected for the
+ * resource set validated. Reset the topology if we are
+ * de-activating crtc.
*/
- if (drm_atomic_crtc_needs_modeset(crtc_state)
- && sde_enc->mode_set_complete) {
- ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
- conn_state, true);
- sde_enc->mode_set_complete = false;
+ if (crtc_state->active)
+ topology = &sde_enc->mode_info.topology;
+
+ ret = sde_rm_update_topology(conn_state, topology);
+ if (ret) {
+ SDE_ERROR_ENC(sde_enc,
+ "RM failed to update topology, rc: %d\n", ret);
+ return ret;
}
}
@@ -1243,13 +1269,9 @@
static int _sde_encoder_dsc_disable(struct sde_encoder_virt *sde_enc)
{
- enum sde_rm_topology_name topology;
- struct drm_connector *drm_conn;
int i, ret = 0;
- struct sde_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
- struct sde_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC] = {NULL};
- int pp_count = 0;
- int dsc_count = 0;
+ struct sde_hw_pingpong *hw_pp = NULL;
+ struct sde_hw_dsc *hw_dsc = NULL;
if (!sde_enc || !sde_enc->phys_encs[0] ||
!sde_enc->phys_encs[0]->connector) {
@@ -1258,80 +1280,16 @@
return -EINVAL;
}
- drm_conn = sde_enc->phys_encs[0]->connector;
-
- topology = sde_connector_get_topology_name(drm_conn);
- if (topology == SDE_RM_TOPOLOGY_NONE) {
- SDE_ERROR_ENC(sde_enc, "topology not set yet\n");
- return -EINVAL;
- }
-
- switch (topology) {
- case SDE_RM_TOPOLOGY_SINGLEPIPE:
- case SDE_RM_TOPOLOGY_SINGLEPIPE_DSC:
- /* single PP */
- hw_pp[0] = sde_enc->hw_pp[0];
- hw_dsc[0] = sde_enc->hw_dsc[0];
- pp_count = 1;
- dsc_count = 1;
- break;
- case SDE_RM_TOPOLOGY_DUALPIPE_DSC:
- case SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC:
- case SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE:
- /* dual dsc */
- for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
- hw_dsc[i] = sde_enc->hw_dsc[i];
- if (hw_dsc[i])
- dsc_count++;
- }
- /* fall through */
- case SDE_RM_TOPOLOGY_DUALPIPE:
- case SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE:
- /* dual pp */
- for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
- hw_pp[i] = sde_enc->hw_pp[i];
- if (hw_pp[i])
- pp_count++;
- }
- break;
- default:
- SDE_DEBUG_ENC(sde_enc, "Unexpected topology:%d\n", topology);
- return -EINVAL;
- };
-
- SDE_EVT32(DRMID(&sde_enc->base), topology, pp_count, dsc_count);
-
- if (pp_count > MAX_CHANNELS_PER_ENC ||
- dsc_count > MAX_CHANNELS_PER_ENC) {
- SDE_ERROR_ENC(sde_enc, "Wrong count pp:%d dsc:%d top:%d\n",
- pp_count, dsc_count, topology);
- return -EINVAL;
- }
-
/* Disable DSC for all the pp's present in this topology */
- for (i = 0; i < pp_count; i++) {
+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+ hw_pp = sde_enc->hw_pp[i];
+ hw_dsc = sde_enc->hw_dsc[i];
- if (!hw_pp[i]) {
- SDE_ERROR_ENC(sde_enc, "null pp:%d top:%d cnt:%d\n",
- i, topology, pp_count);
- return -EINVAL;
- }
+ if (hw_pp && hw_pp->ops.disable_dsc)
+ hw_pp->ops.disable_dsc(hw_pp);
- if (hw_pp[i]->ops.disable_dsc)
- hw_pp[i]->ops.disable_dsc(hw_pp[i]);
- }
-
- /* Disable DSC HW */
- for (i = 0; i < dsc_count; i++) {
-
- if (!hw_dsc[i]) {
- SDE_ERROR_ENC(sde_enc, "null dsc:%d top:%d cnt:%d\n",
- i, topology, dsc_count);
- return -EINVAL;
- }
-
- if (hw_dsc[i]->ops.dsc_disable)
- hw_dsc[i]->ops.dsc_disable(hw_dsc[i]);
+ if (hw_dsc && hw_dsc->ops.dsc_disable)
+ hw_dsc->ops.dsc_disable(hw_dsc);
}
return ret;
@@ -2031,8 +1989,6 @@
if (msm_is_mode_seamless_dms(adj_mode))
sde_encoder_resource_control(&sde_enc->base,
SDE_ENC_RC_EVENT_POST_MODESET);
-
- sde_enc->mode_set_complete = true;
}
static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder.h b/drivers/gpu/drm/msm/sde/sde_encoder.h
index baf59b4..9a9ff86 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder.h
+++ b/drivers/gpu/drm/msm/sde/sde_encoder.h
@@ -40,6 +40,7 @@
* @needs_cdm: Encoder requests a CDM based on pixel format conversion needs
* @display_num_of_h_tiles: Number of horizontal tiles in case of split
* interface
+ * @is_primary: set to true if the display is primary display
* @topology: Topology of the display
*/
struct sde_encoder_hw_resources {
@@ -47,6 +48,7 @@
enum sde_intf_mode wbs[WB_MAX];
bool needs_cdm;
u32 display_num_of_h_tiles;
+ bool is_primary;
struct msm_display_topology topology;
};
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
index 4291098..647bba4 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c
@@ -177,6 +177,13 @@
return;
SDE_ATRACE_BEGIN("pp_done_irq");
+
+ /* handle rare cases where the ctl_start_irq is not received */
+ if (sde_encoder_phys_cmd_is_master(phys_enc)
+ && atomic_add_unless(&phys_enc->pending_retire_fence_cnt, -1, 0))
+ phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
+ phys_enc, SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE);
+
/* notify all synchronous clients first, then asynchronous clients */
if (phys_enc->parent_ops.handle_frame_done)
phys_enc->parent_ops.handle_frame_done(phys_enc->parent,
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index aea2c6b..0b5f37d 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -122,6 +122,7 @@
enum {
HW_OFF,
HW_LEN,
+ HW_DISP,
HW_PROP_MAX,
};
@@ -288,6 +289,7 @@
MIXER_LEN,
MIXER_PAIR_MASK,
MIXER_BLOCKS,
+ MIXER_DISP,
MIXER_PROP_MAX,
};
@@ -475,6 +477,7 @@
static struct sde_prop_type ctl_prop[] = {
{HW_OFF, "qcom,sde-ctl-off", true, PROP_TYPE_U32_ARRAY},
{HW_LEN, "qcom,sde-ctl-size", false, PROP_TYPE_U32},
+ {HW_DISP, "qcom,sde-ctl-display-pref", false, PROP_TYPE_STRING_ARRAY},
};
struct sde_prop_type mixer_blend_prop[] = {
@@ -488,6 +491,8 @@
{MIXER_PAIR_MASK, "qcom,sde-mixer-pair-mask", true,
PROP_TYPE_U32_ARRAY},
{MIXER_BLOCKS, "qcom,sde-mixer-blocks", false, PROP_TYPE_NODE},
+ {MIXER_DISP, "qcom,sde-mixer-display-pref", false,
+ PROP_TYPE_STRING_ARRAY},
};
static struct sde_prop_type mixer_blocks_prop[] = {
@@ -1292,6 +1297,8 @@
goto end;
for (i = 0; i < off_count; i++) {
+ const char *disp_pref = NULL;
+
ctl = sde_cfg->ctl + i;
ctl->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);
ctl->len = PROP_VALUE_ACCESS(prop_value, HW_LEN, 0);
@@ -1299,6 +1306,10 @@
snprintf(ctl->name, SDE_HW_BLK_NAME_LEN, "ctl_%u",
ctl->id - CTL_0);
+ of_property_read_string_index(np,
+ ctl_prop[HW_DISP].prop_name, i, &disp_pref);
+ if (disp_pref && !strcmp(disp_pref, "primary"))
+ set_bit(SDE_CTL_PRIMARY_PREF, &ctl->features);
if (i < MAX_SPLIT_DISPLAY_CTL)
set_bit(SDE_CTL_SPLIT_DISPLAY, &ctl->features);
if (i < MAX_PP_SPLIT_DISPLAY_CTL)
@@ -1306,7 +1317,6 @@
if (sde_cfg->has_sbuf)
set_bit(SDE_CTL_SBUF, &ctl->features);
}
-
end:
kfree(prop_value);
return rc;
@@ -1326,8 +1336,9 @@
u32 off_count, blend_off_count, max_blendstages, lm_pair_mask;
struct sde_lm_cfg *mixer;
struct sde_lm_sub_blks *sblk;
- int pp_count, dspp_count, ds_count;
+ int pp_count, dspp_count, ds_count, mixer_count;
u32 pp_idx, dspp_idx, ds_idx;
+ u32 mixer_base;
struct device_node *snp = NULL;
if (!sde_cfg) {
@@ -1349,8 +1360,6 @@
if (rc)
goto end;
- sde_cfg->mixer_count = off_count;
-
rc = _read_dt_entry(np, mixer_prop, ARRAY_SIZE(mixer_prop), prop_count,
prop_exists, prop_value);
if (rc)
@@ -1398,8 +1407,16 @@
if (rc)
goto end;
- for (i = 0, pp_idx = 0, dspp_idx = 0, ds_idx = 0; i < off_count; i++) {
- mixer = sde_cfg->mixer + i;
+ for (i = 0, mixer_count = 0, pp_idx = 0, dspp_idx = 0,
+ ds_idx = 0; i < off_count; i++) {
+ const char *disp_pref = NULL;
+
+ mixer_base = PROP_VALUE_ACCESS(prop_value, MIXER_OFF, i);
+ if (!mixer_base)
+ continue;
+
+ mixer = sde_cfg->mixer + mixer_count;
+
sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
if (!sblk) {
rc = -ENOMEM;
@@ -1408,7 +1425,7 @@
}
mixer->sblk = sblk;
- mixer->base = PROP_VALUE_ACCESS(prop_value, MIXER_OFF, i);
+ mixer->base = mixer_base;
mixer->len = PROP_VALUE_ACCESS(prop_value, MIXER_LEN, 0);
mixer->id = LM_0 + i;
snprintf(mixer->name, SDE_HW_BLK_NAME_LEN, "lm_%u",
@@ -1435,23 +1452,24 @@
if (sde_cfg->has_dim_layer)
set_bit(SDE_DIM_LAYER, &mixer->features);
- if ((i < ROT_LM_OFFSET) || (i >= LINE_LM_OFFSET)) {
- mixer->pingpong = pp_count > 0 ? pp_idx + PINGPONG_0
- : PINGPONG_MAX;
- mixer->dspp = dspp_count > 0 ? dspp_idx + DSPP_0
- : DSPP_MAX;
- mixer->ds = ds_count > 0 ? ds_idx + DS_0 : DS_MAX;
- pp_count--;
- dspp_count--;
- ds_count--;
- pp_idx++;
- dspp_idx++;
- ds_idx++;
- } else {
- mixer->pingpong = PINGPONG_MAX;
- mixer->dspp = DSPP_MAX;
- mixer->ds = DS_MAX;
- }
+ of_property_read_string_index(np,
+ mixer_prop[MIXER_DISP].prop_name, i, &disp_pref);
+ if (disp_pref && !strcmp(disp_pref, "primary"))
+ set_bit(SDE_DISP_PRIMARY_PREF, &mixer->features);
+
+ mixer->pingpong = pp_count > 0 ? pp_idx + PINGPONG_0
+ : PINGPONG_MAX;
+ mixer->dspp = dspp_count > 0 ? dspp_idx + DSPP_0
+ : DSPP_MAX;
+ mixer->ds = ds_count > 0 ? ds_idx + DS_0 : DS_MAX;
+ pp_count--;
+ dspp_count--;
+ ds_count--;
+ pp_idx++;
+ dspp_idx++;
+ ds_idx++;
+
+ mixer_count++;
sblk->gc.id = SDE_MIXER_GC;
if (blocks_prop_value && blocks_prop_exists[MIXER_GC_PROP]) {
@@ -1463,6 +1481,7 @@
set_bit(SDE_MIXER_GC, &mixer->features);
}
}
+ sde_cfg->mixer_count = mixer_count;
end:
kfree(prop_value);
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index e60b5ca..2656e82 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -152,6 +152,7 @@
* @SDE_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
* @SDE_MIXER_GC Gamma correction block
* @SDE_DIM_LAYER Layer mixer supports dim layer
+ * @SDE_DISP_PRIMARY_PREF Layer mixer preferred for primary display
* @SDE_MIXER_MAX maximum value
*/
enum {
@@ -159,6 +160,7 @@
SDE_MIXER_SOURCESPLIT,
SDE_MIXER_GC,
SDE_DIM_LAYER,
+ SDE_DISP_PRIMARY_PREF,
SDE_MIXER_MAX
};
@@ -217,12 +219,14 @@
* @SDE_CTL_SPLIT_DISPLAY CTL supports video mode split display
* @SDE_CTL_PINGPONG_SPLIT CTL supports pingpong split
* @SDE_CTL_SBUF CTL supports inline stream buffer
+ * @SDE_CTL_PRIMARY_PREF CTL preferred for primary display
* @SDE_CTL_MAX
*/
enum {
SDE_CTL_SPLIT_DISPLAY = 0x1,
SDE_CTL_PINGPONG_SPLIT,
SDE_CTL_SBUF,
+ SDE_CTL_PRIMARY_PREF,
SDE_CTL_MAX
};
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h b/drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h
index 6896ba7..3d2c0a5 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h
@@ -66,4 +66,42 @@
#define PCC_GG_OFF 0x70
#define PCC_BB_OFF 0x7c
+#define PA_EN BIT(20)
+#define PA_HUE_EN BIT(25)
+#define PA_SAT_EN BIT(26)
+#define PA_VAL_EN BIT(27)
+#define PA_CONT_EN BIT(28)
+
+#define PA_SIXZONE_HUE_EN BIT(29)
+#define PA_SIXZONE_SAT_EN BIT(30)
+#define PA_SIXZONE_VAL_EN BIT(31)
+
+#define PA_HIST_EN BIT(16)
+
+#define PA_SKIN_EN BIT(7)
+#define PA_FOL_EN BIT(6)
+#define PA_SKY_EN BIT(5)
+
+#define PA_HUE_MASK (BIT(12) - 1)
+#define PA_SAT_MASK (BIT(16) - 1)
+#define PA_VAL_MASK (BIT(8) - 1)
+#define PA_CONT_MASK (BIT(8) - 1)
+
+#define PA_HUE_OFF 0x1c
+#define PA_SAT_OFF 0x20
+#define PA_VAL_OFF 0x24
+#define PA_CONT_OFF 0x28
+#define PA_PWL_HOLD_OFF 0x40
+
+#define PA_DISABLE_REQUIRED(x) \
+ !((x) & (PA_SKIN_EN | PA_SKY_EN | \
+ PA_FOL_EN | PA_HUE_EN | \
+ PA_SAT_EN | PA_VAL_EN | \
+ PA_CONT_EN | PA_HIST_EN | \
+ PA_SIXZONE_HUE_EN | PA_SIXZONE_SAT_EN | \
+ PA_SIXZONE_VAL_EN))
+
+#define SIXZONE_ADJ_CURVE_P1_OFF 0x4
+#define SIXZONE_THRESHOLDS_OFF 0x8
+
#endif /* _SDE_HW_COLOR_PROC_COMMON_V4_H_ */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
index 8e54a2a..d32459a 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c
@@ -14,15 +14,17 @@
#include "sde_hw_color_processing_v1_7.h"
#include "sde_hw_ctl.h"
+#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
+
#define PA_HUE_VIG_OFF 0x110
#define PA_SAT_VIG_OFF 0x114
#define PA_VAL_VIG_OFF 0x118
#define PA_CONT_VIG_OFF 0x11C
-#define PA_HUE_DSPP_OFF 0x238
-#define PA_SAT_DSPP_OFF 0x23C
-#define PA_VAL_DSPP_OFF 0x240
-#define PA_CONT_DSPP_OFF 0x244
+#define PA_HUE_DSPP_OFF 0x1c
+#define PA_SAT_DSPP_OFF 0x20
+#define PA_VAL_DSPP_OFF 0x24
+#define PA_CONT_DSPP_OFF 0x28
#define PA_HIST_CTRL_DSPP_OFF 0x4
#define PA_HIST_DATA_DSPP_OFF 0x400
@@ -78,18 +80,44 @@
#define DSPP_OP_PA_FOL_EN BIT(6)
#define DSPP_OP_PA_SKY_EN BIT(7)
+#define DSPP_SZ_ADJ_CURVE_P1_OFF 0x4
+#define DSPP_SZ_THRESHOLDS_OFF 0x8
+#define DSPP_PA_PWL_HOLD_OFF 0x40
+
+#define DSPP_MEMCOL_SIZE0 0x14
+#define DSPP_MEMCOL_SIZE1 0x8
+#define DSPP_MEMCOL_PWL0_OFF 0x0
+#define DSPP_MEMCOL_PWL2_OFF 0x3C
+#define DSPP_MEMCOL_HOLD_SIZE 0x4
+
+#define DSPP_MEMCOL_PROT_VAL_EN BIT(24)
+#define DSPP_MEMCOL_PROT_SAT_EN BIT(23)
+#define DSPP_MEMCOL_PROT_HUE_EN BIT(22)
+#define DSPP_MEMCOL_PROT_CONT_EN BIT(18)
+#define DSPP_MEMCOL_PROT_SIXZONE_EN BIT(17)
+#define DSPP_MEMCOL_PROT_BLEND_EN BIT(3)
+
+#define DSPP_MEMCOL_MASK \
+ (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | DSPP_OP_PA_FOL_EN)
+
+#define DSPP_MEMCOL_PROT_MASK \
+ (DSPP_MEMCOL_PROT_HUE_EN | DSPP_MEMCOL_PROT_SAT_EN | \
+ DSPP_MEMCOL_PROT_VAL_EN | DSPP_MEMCOL_PROT_CONT_EN | \
+ DSPP_MEMCOL_PROT_SIXZONE_EN | DSPP_MEMCOL_PROT_BLEND_EN)
+
#define PA_VIG_DISABLE_REQUIRED(x) \
!((x) & (VIG_OP_PA_SKIN_EN | VIG_OP_PA_SKY_EN | \
VIG_OP_PA_FOL_EN | VIG_OP_PA_HUE_EN | \
VIG_OP_PA_SAT_EN | VIG_OP_PA_VAL_EN | \
VIG_OP_PA_CONT_EN))
-
#define PA_DSPP_DISABLE_REQUIRED(x) \
!((x) & (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | \
DSPP_OP_PA_FOL_EN | DSPP_OP_PA_HUE_EN | \
DSPP_OP_PA_SAT_EN | DSPP_OP_PA_VAL_EN | \
- DSPP_OP_PA_CONT_EN | DSPP_OP_PA_LUTV_EN))
+ DSPP_OP_PA_CONT_EN | DSPP_OP_PA_HIST_EN | \
+ DSPP_OP_SZ_HUE_EN | DSPP_OP_SZ_SAT_EN | \
+ DSPP_OP_SZ_VAL_EN))
#define DSPP_OP_PCC_ENABLE BIT(0)
#define PCC_OP_MODE_OFF 0
@@ -116,30 +144,27 @@
static void __setup_pa_hue(struct sde_hw_blk_reg_map *hw,
- const struct sde_pp_blk *blk, uint32_t hue,
- int location)
+ const struct sde_pp_blk *blk, u32 hue, int loc)
{
u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_HUE_DSPP_OFF : PA_HUE_VIG_OFF;
- u32 op_hue_en = (location == DSPP) ? DSPP_OP_PA_HUE_EN :
- VIG_OP_PA_HUE_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 offset = (loc == DSPP) ? PA_HUE_DSPP_OFF : PA_HUE_VIG_OFF;
+ u32 op_hue_en = (loc == DSPP) ? DSPP_OP_PA_HUE_EN : VIG_OP_PA_HUE_EN;
+ u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
u32 disable_req;
u32 opmode;
- SDE_REG_WRITE(hw, base + offset, hue & PA_HUE_MASK);
-
opmode = SDE_REG_READ(hw, base);
+ SDE_REG_WRITE(hw, base + offset, hue & PA_HUE_MASK);
if (!hue) {
opmode &= ~op_hue_en;
- disable_req = (location == DSPP) ?
+ disable_req = (loc == DSPP) ?
PA_DSPP_DISABLE_REQUIRED(opmode) :
PA_VIG_DISABLE_REQUIRED(opmode);
if (disable_req)
opmode &= ~op_pa_en;
} else {
- opmode |= op_hue_en | op_pa_en;
+ opmode |= (op_hue_en | op_pa_en);
}
SDE_REG_WRITE(hw, base, opmode);
@@ -152,38 +177,28 @@
__setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic_blk, hue, SSPP);
}
-void sde_setup_dspp_pa_hue_v1_7(struct sde_hw_dspp *ctx, void *cfg)
-{
- uint32_t hue = *((uint32_t *)cfg);
-
- __setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic, hue, DSPP);
-}
-
static void __setup_pa_sat(struct sde_hw_blk_reg_map *hw,
- const struct sde_pp_blk *blk, uint32_t sat,
- int location)
+ const struct sde_pp_blk *blk, u32 sat, int loc)
{
u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_SAT_DSPP_OFF : PA_SAT_VIG_OFF;
- u32 op_sat_en = (location == DSPP) ?
- DSPP_OP_PA_SAT_EN : VIG_OP_PA_SAT_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 offset = (loc == DSPP) ? PA_SAT_DSPP_OFF : PA_SAT_VIG_OFF;
+ u32 op_sat_en = (loc == DSPP) ? DSPP_OP_PA_SAT_EN : VIG_OP_PA_SAT_EN;
+ u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
u32 disable_req;
u32 opmode;
- SDE_REG_WRITE(hw, base + offset, sat & PA_SAT_MASK);
-
opmode = SDE_REG_READ(hw, base);
+ SDE_REG_WRITE(hw, base + offset, sat & PA_SAT_MASK);
if (!sat) {
opmode &= ~op_sat_en;
- disable_req = (location == DSPP) ?
+ disable_req = (loc == DSPP) ?
PA_DSPP_DISABLE_REQUIRED(opmode) :
PA_VIG_DISABLE_REQUIRED(opmode);
if (disable_req)
opmode &= ~op_pa_en;
} else {
- opmode |= op_sat_en | op_pa_en;
+ opmode |= (op_sat_en | op_pa_en);
}
SDE_REG_WRITE(hw, base, opmode);
@@ -197,30 +212,27 @@
}
static void __setup_pa_val(struct sde_hw_blk_reg_map *hw,
- const struct sde_pp_blk *blk, uint32_t value,
- int location)
+ const struct sde_pp_blk *blk, u32 value, int loc)
{
u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_VAL_DSPP_OFF : PA_VAL_VIG_OFF;
- u32 op_val_en = (location == DSPP) ?
- DSPP_OP_PA_VAL_EN : VIG_OP_PA_VAL_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 offset = (loc == DSPP) ? PA_VAL_DSPP_OFF : PA_VAL_VIG_OFF;
+ u32 op_val_en = (loc == DSPP) ? DSPP_OP_PA_VAL_EN : VIG_OP_PA_VAL_EN;
+ u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
u32 disable_req;
u32 opmode;
- SDE_REG_WRITE(hw, base + offset, value & PA_VAL_MASK);
-
opmode = SDE_REG_READ(hw, base);
+ SDE_REG_WRITE(hw, base + offset, value & PA_VAL_MASK);
if (!value) {
opmode &= ~op_val_en;
- disable_req = (location == DSPP) ?
+ disable_req = (loc == DSPP) ?
PA_DSPP_DISABLE_REQUIRED(opmode) :
PA_VIG_DISABLE_REQUIRED(opmode);
if (disable_req)
opmode &= ~op_pa_en;
} else {
- opmode |= op_val_en | op_pa_en;
+ opmode |= (op_val_en | op_pa_en);
}
SDE_REG_WRITE(hw, base, opmode);
@@ -234,30 +246,28 @@
}
static void __setup_pa_cont(struct sde_hw_blk_reg_map *hw,
- const struct sde_pp_blk *blk, uint32_t contrast,
- int location)
+ const struct sde_pp_blk *blk, u32 contrast, int loc)
{
u32 base = blk->base;
- u32 offset = (location == DSPP) ? PA_CONT_DSPP_OFF : PA_CONT_VIG_OFF;
- u32 op_cont_en = (location == DSPP) ? DSPP_OP_PA_CONT_EN :
- VIG_OP_PA_CONT_EN;
- u32 op_pa_en = (location == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
+ u32 offset = (loc == DSPP) ? PA_CONT_DSPP_OFF : PA_CONT_VIG_OFF;
+ u32 op_cont_en = (loc == DSPP) ?
+ DSPP_OP_PA_CONT_EN : VIG_OP_PA_CONT_EN;
+ u32 op_pa_en = (loc == DSPP) ? DSPP_OP_PA_EN : VIG_OP_PA_EN;
u32 disable_req;
u32 opmode;
- SDE_REG_WRITE(hw, base + offset, contrast & PA_CONT_MASK);
-
opmode = SDE_REG_READ(hw, base);
+ SDE_REG_WRITE(hw, base + offset, contrast & PA_CONT_MASK);
if (!contrast) {
opmode &= ~op_cont_en;
- disable_req = (location == DSPP) ?
+ disable_req = (loc == DSPP) ?
PA_DSPP_DISABLE_REQUIRED(opmode) :
PA_VIG_DISABLE_REQUIRED(opmode);
if (disable_req)
opmode &= ~op_pa_en;
} else {
- opmode |= op_cont_en | op_pa_en;
+ opmode |= (op_cont_en | op_pa_en);
}
SDE_REG_WRITE(hw, base, opmode);
@@ -270,6 +280,120 @@
__setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic_blk, contrast, SSPP);
}
+void sde_setup_dspp_pa_hsic_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_pa_hsic *hsic_cfg;
+ u32 hue = 0;
+ u32 sat = 0;
+ u32 val = 0;
+ u32 cont = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ if (hw_cfg->payload &&
+ (hw_cfg->len != sizeof(struct drm_msm_pa_hsic))) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_pa_hsic));
+ return;
+ }
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable pa hsic feature\n");
+ } else {
+ hsic_cfg = hw_cfg->payload;
+ if (hsic_cfg->flags & PA_HSIC_HUE_ENABLE)
+ hue = hsic_cfg->hue;
+ if (hsic_cfg->flags & PA_HSIC_SAT_ENABLE)
+ sat = hsic_cfg->saturation;
+ if (hsic_cfg->flags & PA_HSIC_VAL_ENABLE)
+ val = hsic_cfg->value;
+ if (hsic_cfg->flags & PA_HSIC_CONT_ENABLE)
+ cont = hsic_cfg->contrast;
+ }
+
+ __setup_pa_hue(&ctx->hw, &ctx->cap->sblk->hsic, hue, DSPP);
+ __setup_pa_sat(&ctx->hw, &ctx->cap->sblk->hsic, sat, DSPP);
+ __setup_pa_val(&ctx->hw, &ctx->cap->sblk->hsic, val, DSPP);
+ __setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic, cont, DSPP);
+}
+
+void sde_setup_dspp_sixzone_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_sixzone *sixzone;
+ u32 opcode = 0, local_opcode = 0;
+ u32 reg = 0, hold = 0, local_hold = 0;
+ u32 addr = 0;
+ int i = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable sixzone feature\n");
+ opcode &= ~(DSPP_OP_SZ_HUE_EN | DSPP_OP_SZ_SAT_EN |
+ DSPP_OP_SZ_VAL_EN);
+ if (PA_DSPP_DISABLE_REQUIRED(opcode))
+ opcode &= ~DSPP_OP_PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_sixzone)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_sixzone));
+ return;
+ }
+
+ sixzone = hw_cfg->payload;
+
+ reg = BIT(26);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->sixzone.base, reg);
+
+ addr = ctx->cap->sblk->sixzone.base + DSPP_SZ_ADJ_CURVE_P1_OFF;
+ for (i = 0; i < SIXZONE_LUT_SIZE; i++) {
+ SDE_REG_WRITE(&ctx->hw, addr, sixzone->curve[i].p1);
+ SDE_REG_WRITE(&ctx->hw, (addr - 4), sixzone->curve[i].p0);
+ }
+
+ addr = ctx->cap->sblk->sixzone.base + DSPP_SZ_THRESHOLDS_OFF;
+ SDE_REG_WRITE(&ctx->hw, addr, sixzone->threshold);
+ SDE_REG_WRITE(&ctx->hw, (addr + 4), sixzone->adjust_p0);
+ SDE_REG_WRITE(&ctx->hw, (addr + 8), sixzone->adjust_p1);
+
+ hold = SDE_REG_READ(&ctx->hw,
+ (ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF));
+ local_hold = ((sixzone->sat_hold & REG_MASK(2)) << 12);
+ local_hold |= ((sixzone->val_hold & REG_MASK(2)) << 14);
+ hold &= ~REG_MASK_SHIFT(4, 12);
+ hold |= local_hold;
+ SDE_REG_WRITE(&ctx->hw,
+ (ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF),
+ hold);
+
+ if (sixzone->flags & SIXZONE_HUE_ENABLE)
+ local_opcode |= DSPP_OP_SZ_HUE_EN;
+ if (sixzone->flags & SIXZONE_SAT_ENABLE)
+ local_opcode |= DSPP_OP_SZ_SAT_EN;
+ if (sixzone->flags & SIXZONE_VAL_ENABLE)
+ local_opcode |= DSPP_OP_SZ_VAL_EN;
+
+ if (local_opcode)
+ local_opcode |= DSPP_OP_PA_EN;
+
+ opcode &= ~REG_MASK_SHIFT(3, 29);
+ opcode |= local_opcode;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx,
enum sde_memcolor_type type,
void *cfg)
@@ -333,6 +457,220 @@
SDE_REG_WRITE(&ctx->hw, base, op);
}
+static void __setup_dspp_memcol(struct sde_hw_dspp *ctx,
+ enum sde_memcolor_type type,
+ struct drm_msm_memcol *memcolor)
+{
+ u32 addr = 0, offset = 0, idx = 0;
+ u32 hold = 0, local_hold = 0, hold_shift = 0;
+
+ switch (type) {
+ case MEMCOLOR_SKIN:
+ idx = 0;
+ break;
+ case MEMCOLOR_SKY:
+ idx = 1;
+ break;
+ case MEMCOLOR_FOLIAGE:
+ idx = 2;
+ break;
+ default:
+ DRM_ERROR("Invalid memory color type %d\n", type);
+ return;
+ }
+
+ offset = DSPP_MEMCOL_PWL0_OFF + (idx * DSPP_MEMCOL_SIZE0);
+ addr = ctx->cap->sblk->memcolor.base + offset;
+ hold_shift = idx * DSPP_MEMCOL_HOLD_SIZE;
+
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->color_adjust_p0);
+ addr += 4;
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->color_adjust_p1);
+ addr += 4;
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->hue_region);
+ addr += 4;
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->sat_region);
+ addr += 4;
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->val_region);
+
+ offset = DSPP_MEMCOL_PWL2_OFF + (idx * DSPP_MEMCOL_SIZE1);
+ addr = ctx->cap->sblk->memcolor.base + offset;
+
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->color_adjust_p2);
+ addr += 4;
+ SDE_REG_WRITE(&ctx->hw, addr, memcolor->blend_gain);
+
+ addr = ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF;
+ hold = SDE_REG_READ(&ctx->hw, addr);
+ local_hold = ((memcolor->sat_hold & REG_MASK(2)) << hold_shift);
+ local_hold |=
+ ((memcolor->val_hold & REG_MASK(2)) << (hold_shift + 2));
+ hold &= ~REG_MASK_SHIFT(4, hold_shift);
+ hold |= local_hold;
+ SDE_REG_WRITE(&ctx->hw, addr, hold);
+}
+
+void sde_setup_dspp_memcol_skin_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_memcol *memcolor;
+ u32 opcode = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable memcolor skin feature\n");
+ opcode &= ~(DSPP_OP_PA_SKIN_EN);
+ if (PA_DSPP_DISABLE_REQUIRED(opcode))
+ opcode &= ~DSPP_OP_PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_memcol));
+ return;
+ }
+
+ memcolor = hw_cfg->payload;
+
+ __setup_dspp_memcol(ctx, MEMCOLOR_SKIN, memcolor);
+
+ opcode |= (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_EN);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
+void sde_setup_dspp_memcol_sky_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_memcol *memcolor;
+ u32 opcode = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable memcolor sky feature\n");
+ opcode &= ~(DSPP_OP_PA_SKY_EN);
+ if (PA_DSPP_DISABLE_REQUIRED(opcode))
+ opcode &= ~DSPP_OP_PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_memcol));
+ return;
+ }
+
+ memcolor = hw_cfg->payload;
+
+ __setup_dspp_memcol(ctx, MEMCOLOR_SKY, memcolor);
+
+ opcode |= (DSPP_OP_PA_SKY_EN | DSPP_OP_PA_EN);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
+void sde_setup_dspp_memcol_foliage_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_memcol *memcolor;
+ u32 opcode = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable memcolor foliage feature\n");
+ opcode &= ~(DSPP_OP_PA_FOL_EN);
+ if (PA_DSPP_DISABLE_REQUIRED(opcode))
+ opcode &= ~DSPP_OP_PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_memcol));
+ return;
+ }
+
+ memcolor = hw_cfg->payload;
+
+ __setup_dspp_memcol(ctx, MEMCOLOR_FOLIAGE, memcolor);
+
+ opcode |= (DSPP_OP_PA_FOL_EN | DSPP_OP_PA_EN);
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
+void sde_setup_dspp_memcol_prot_v17(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct drm_msm_memcol *memcolor;
+ u32 opcode = 0, local_opcode = 0;
+
+ if (!ctx || !cfg) {
+ DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
+ return;
+ }
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable memcolor prot feature\n");
+ opcode &= ~(DSPP_MEMCOL_PROT_MASK);
+ if (PA_DSPP_DISABLE_REQUIRED(opcode))
+ opcode &= ~DSPP_OP_PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_memcol));
+ return;
+ }
+
+ memcolor = hw_cfg->payload;
+
+ if (memcolor->prot_flags) {
+ if (memcolor->prot_flags & MEMCOL_PROT_HUE)
+ local_opcode |= DSPP_MEMCOL_PROT_HUE_EN;
+ if (memcolor->prot_flags & MEMCOL_PROT_SAT)
+ local_opcode |= DSPP_MEMCOL_PROT_SAT_EN;
+ if (memcolor->prot_flags & MEMCOL_PROT_VAL)
+ local_opcode |= DSPP_MEMCOL_PROT_VAL_EN;
+ if (memcolor->prot_flags & MEMCOL_PROT_CONT)
+ local_opcode |= DSPP_MEMCOL_PROT_CONT_EN;
+ if (memcolor->prot_flags & MEMCOL_PROT_SIXZONE)
+ local_opcode |= DSPP_MEMCOL_PROT_SIXZONE_EN;
+ if (memcolor->prot_flags & MEMCOL_PROT_BLEND)
+ local_opcode |= DSPP_MEMCOL_PROT_BLEND_EN;
+ }
+
+ if (local_opcode) {
+ local_opcode |= DSPP_OP_PA_EN;
+ opcode &= ~(DSPP_MEMCOL_PROT_MASK);
+ opcode |= local_opcode;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ }
+}
+
void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg)
{
struct sde_hw_cp_cfg *hw_cfg = cfg;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
index 74018a3..3c783ee 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.h
@@ -62,11 +62,46 @@
void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg);
/**
- * sde_setup_dspp_pa_hue_v1_7 - setup DSPP hue feature in v1.7 hardware
+ * sde_setup_dspp_pa_hsic_v17 - setup DSPP hsic feature in v1.7 hardware
* @ctx: Pointer to DSPP context
- * @cfg: Pointer to hue data
+ * @cfg: Pointer to hsic data
*/
-void sde_setup_dspp_pa_hue_v1_7(struct sde_hw_dspp *ctx, void *cfg);
+void sde_setup_dspp_pa_hsic_v17(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_memcol_skin_v17 - setup DSPP memcol skin in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to memcolor config data
+ */
+void sde_setup_dspp_memcol_skin_v17(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_memcol_sky_v17 - setup DSPP memcol sky in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to memcolor config data
+ */
+void sde_setup_dspp_memcol_sky_v17(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_memcol_foliage_v17 - setup DSPP memcol fol in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to memcolor config data
+ */
+void sde_setup_dspp_memcol_foliage_v17(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_memcol_prot_v17 - setup DSPP memcol prot in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to memcolor config data
+ */
+void sde_setup_dspp_memcol_prot_v17(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * sde_setup_dspp_sixzone_v17 - setup DSPP sixzone feature in v1.7 hardware
+ * @ctx: Pointer to DSPP context
+ * @cfg: Pointer to sixzone data
+ */
+void sde_setup_dspp_sixzone_v17(struct sde_hw_dspp *ctx, void *cfg);
/**
* sde_setup_dspp_pa_vlut_v1_7 - setup DSPP PA vLUT feature in v1.7 hardware
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ctl.c b/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
index 95b7a6d..3df7474 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ctl.c
@@ -378,10 +378,12 @@
int i;
for (i = 0; i < ctx->mixer_count; i++) {
- SDE_REG_WRITE(c, CTL_LAYER(LM_0 + i), 0);
- SDE_REG_WRITE(c, CTL_LAYER_EXT(LM_0 + i), 0);
- SDE_REG_WRITE(c, CTL_LAYER_EXT2(LM_0 + i), 0);
- SDE_REG_WRITE(c, CTL_LAYER_EXT3(LM_0 + i), 0);
+ int mixer_id = ctx->mixer_hw_caps[i].id;
+
+ SDE_REG_WRITE(c, CTL_LAYER(mixer_id), 0);
+ SDE_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0);
+ SDE_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0);
+ SDE_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0);
}
}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
index 36e30b7..b268e8f 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c
@@ -71,8 +71,28 @@
break;
case SDE_DSPP_HSIC:
if (c->cap->sblk->hsic.version ==
- (SDE_COLOR_PROCESS_VER(0x1, 0x7)))
- c->ops.setup_hue = sde_setup_dspp_pa_hue_v1_7;
+ SDE_COLOR_PROCESS_VER(0x1, 0x7))
+ c->ops.setup_pa_hsic =
+ sde_setup_dspp_pa_hsic_v17;
+ break;
+ case SDE_DSPP_MEMCOLOR:
+ if (c->cap->sblk->memcolor.version ==
+ SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
+ c->ops.setup_pa_memcol_skin =
+ sde_setup_dspp_memcol_skin_v17;
+ c->ops.setup_pa_memcol_sky =
+ sde_setup_dspp_memcol_sky_v17;
+ c->ops.setup_pa_memcol_foliage =
+ sde_setup_dspp_memcol_foliage_v17;
+ c->ops.setup_pa_memcol_prot =
+ sde_setup_dspp_memcol_prot_v17;
+ }
+ break;
+ case SDE_DSPP_SIXZONE:
+ if (c->cap->sblk->sixzone.version ==
+ SDE_COLOR_PROCESS_VER(0x1, 0x7))
+ c->ops.setup_sixzone =
+ sde_setup_dspp_sixzone_v17;
break;
case SDE_DSPP_VLUT:
if (c->cap->sblk->vlut.version ==
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.h b/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
index 4878fc6..2b64165 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.h
@@ -52,11 +52,11 @@
void (*setup_igc)(struct sde_hw_dspp *ctx, void *cfg);
/**
- * setup_pa - setup dspp pa
+ * setup_pa_hsic - setup dspp pa hsic
* @ctx: Pointer to dspp context
* @cfg: Pointer to configuration
*/
- void (*setup_pa)(struct sde_hw_dspp *dspp, void *cfg);
+ void (*setup_pa_hsic)(struct sde_hw_dspp *dspp, void *cfg);
/**
* setup_pcc - setup dspp pcc
@@ -73,11 +73,32 @@
void (*setup_sharpening)(struct sde_hw_dspp *ctx, void *cfg);
/**
- * setup_pa_memcolor - setup dspp memcolor
+ * setup_pa_memcol_skin - setup dspp memcolor skin
* @ctx: Pointer to dspp context
* @cfg: Pointer to configuration
*/
- void (*setup_pa_memcolor)(struct sde_hw_dspp *ctx, void *cfg);
+ void (*setup_pa_memcol_skin)(struct sde_hw_dspp *ctx, void *cfg);
+
+ /**
+ * setup_pa_memcol_sky - setup dspp memcolor sky
+ * @ctx: Pointer to dspp context
+ * @cfg: Pointer to configuration
+ */
+ void (*setup_pa_memcol_sky)(struct sde_hw_dspp *ctx, void *cfg);
+
+ /**
+ * setup_pa_memcol_foliage - setup dspp memcolor foliage
+ * @ctx: Pointer to dspp context
+ * @cfg: Pointer to configuration
+ */
+ void (*setup_pa_memcol_foliage)(struct sde_hw_dspp *ctx, void *cfg);
+
+ /**
+ * setup_pa_memcol_prot - setup dspp memcolor protection
+ * @ctx: Pointer to dspp context
+ * @cfg: Pointer to configuration
+ */
+ void (*setup_pa_memcol_prot)(struct sde_hw_dspp *ctx, void *cfg);
/**
* setup_sixzone - setup dspp six zone
@@ -101,34 +122,6 @@
void (*setup_dither)(struct sde_hw_dspp *ctx, void *cfg);
/**
- * setup_hue - setup dspp PA hue
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_hue)(struct sde_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_sat - setup dspp PA saturation
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_sat)(struct sde_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_val - setup dspp PA value
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_val)(struct sde_hw_dspp *ctx, void *cfg);
-
- /**
- * setup_cont - setup dspp PA contrast
- * @ctx: Pointer to dspp context
- * @cfg: Pointer to configuration
- */
- void (*setup_cont)(struct sde_hw_dspp *ctx, void *cfg);
-
- /**
* setup_vlut - setup dspp PA VLUT
* @ctx: Pointer to dspp context
* @cfg: Pointer to configuration
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
index b59dd16..0dc3fed 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c
@@ -39,7 +39,14 @@
#define PCC_MEM_SIZE (PCC_LEN + \
REG_DMA_HEADERS_BUFFER_SZ)
+#define HSIC_MEM_SIZE ((sizeof(struct drm_msm_pa_hsic)) + \
+ REG_DMA_HEADERS_BUFFER_SZ)
+
+#define SIXZONE_MEM_SIZE ((sizeof(struct drm_msm_sixzone)) + \
+ REG_DMA_HEADERS_BUFFER_SZ)
+
#define REG_MASK(n) ((BIT(n)) - 1)
+#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
static struct sde_reg_dma_buffer *dspp_buf[REG_DMA_FEATURES_MAX][DSPP_MAX];
@@ -49,9 +56,9 @@
[SDE_DSPP_IGC] = IGC,
[SDE_DSPP_PCC] = PCC,
[SDE_DSPP_GC] = GC,
- [SDE_DSPP_HSIC] = REG_DMA_FEATURES_MAX,
+ [SDE_DSPP_HSIC] = HSIC,
[SDE_DSPP_MEMCOLOR] = REG_DMA_FEATURES_MAX,
- [SDE_DSPP_SIXZONE] = REG_DMA_FEATURES_MAX,
+ [SDE_DSPP_SIXZONE] = SIX_ZONE,
[SDE_DSPP_DITHER] = REG_DMA_FEATURES_MAX,
[SDE_DSPP_HIST] = REG_DMA_FEATURES_MAX,
[SDE_DSPP_AD] = REG_DMA_FEATURES_MAX,
@@ -63,6 +70,8 @@
[SDE_DSPP_GC] = GC_LUT_MEM_SIZE,
[SDE_DSPP_IGC] = IGC_LUT_MEM_SIZE,
[SDE_DSPP_PCC] = PCC_MEM_SIZE,
+ [SDE_DSPP_HSIC] = HSIC_MEM_SIZE,
+ [SDE_DSPP_SIXZONE] = SIXZONE_MEM_SIZE,
};
static u32 dspp_mapping[DSPP_MAX] = {
@@ -295,8 +304,8 @@
if (!hw_cfg->payload) {
DRM_DEBUG_DRIVER("Disable vlut feature\n");
SDE_REG_WRITE(&ctx->hw, PA_LUTV_OPMODE_OFF, 0);
- if (op_mode & (~(BIT(20))))
- op_mode = 0;
+ if (PA_DISABLE_REQUIRED(op_mode))
+ op_mode &= ~PA_EN;
SDE_REG_WRITE(&ctx->hw, PA_OP_MODE_OFF, op_mode);
return;
}
@@ -919,6 +928,233 @@
kfree(data);
}
+void reg_dmav1_setup_dspp_pa_hsicv18(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_reg_dma_ops *dma_ops;
+ struct sde_reg_dma_kickoff_cfg kick_off;
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
+ struct drm_msm_pa_hsic *hsic_cfg;
+ u32 reg = 0, opcode = 0, local_opcode = 0;
+ int rc;
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ rc = reg_dma_dspp_check(ctx, cfg, HSIC);
+ if (rc)
+ return;
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable pa hsic feature\n");
+ opcode &= ~(PA_HUE_EN | PA_SAT_EN | PA_VAL_EN | PA_CONT_EN);
+ if (PA_DISABLE_REQUIRED(opcode))
+ opcode &= ~PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_pa_hsic)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_pa_hsic));
+ return;
+ }
+
+ hsic_cfg = hw_cfg->payload;
+
+ dma_ops = sde_reg_dma_get_ops();
+ dma_ops->reset_reg_dma_buf(dspp_buf[HSIC][ctx->idx]);
+
+ REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx],
+ HSIC, dspp_buf[HSIC][ctx->idx]);
+
+ REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("write decode select failed ret %d\n", rc);
+ return;
+ }
+
+ if (hsic_cfg->flags & PA_HSIC_HUE_ENABLE) {
+ reg = hsic_cfg->hue & PA_HUE_MASK;
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->hsic.base + PA_HUE_OFF,
+ ®, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("hsic hue write failed ret %d\n", rc);
+ return;
+ }
+ local_opcode |= PA_HUE_EN;
+ } else if (opcode & PA_HUE_EN)
+ opcode &= ~PA_HUE_EN;
+
+ if (hsic_cfg->flags & PA_HSIC_SAT_ENABLE) {
+ reg = hsic_cfg->saturation & PA_SAT_MASK;
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->hsic.base + PA_SAT_OFF,
+ ®, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("hsic saturation write failed ret %d\n", rc);
+ return;
+ }
+ local_opcode |= PA_SAT_EN;
+ } else if (opcode & PA_SAT_EN)
+ opcode &= ~PA_SAT_EN;
+
+ if (hsic_cfg->flags & PA_HSIC_VAL_ENABLE) {
+ reg = hsic_cfg->value & PA_VAL_MASK;
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->hsic.base + PA_VAL_OFF,
+ ®, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("hsic value write failed ret %d\n", rc);
+ return;
+ }
+ local_opcode |= PA_VAL_EN;
+ } else if (opcode & PA_VAL_EN)
+ opcode &= ~PA_VAL_EN;
+
+ if (hsic_cfg->flags & PA_HSIC_CONT_ENABLE) {
+ reg = hsic_cfg->contrast & PA_CONT_MASK;
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->hsic.base + PA_CONT_OFF,
+ ®, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("hsic contrast write failed ret %d\n", rc);
+ return;
+ }
+ local_opcode |= PA_CONT_EN;
+ } else if (opcode & PA_CONT_EN)
+ opcode &= ~PA_CONT_EN;
+
+ if (local_opcode)
+ opcode |= (local_opcode | PA_EN);
+ else {
+ DRM_ERROR("Invalid hsic config\n");
+ return;
+ }
+
+ REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, dspp_buf[HSIC][ctx->idx],
+ REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
+ rc = dma_ops->kick_off(&kick_off);
+ if (rc)
+ DRM_ERROR("failed to kick off ret %d\n", rc);
+
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
+void reg_dmav1_setup_dspp_sixzonev18(struct sde_hw_dspp *ctx, void *cfg)
+{
+ struct sde_hw_reg_dma_ops *dma_ops;
+ struct sde_reg_dma_kickoff_cfg kick_off;
+ struct sde_hw_cp_cfg *hw_cfg = cfg;
+ struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
+ struct drm_msm_sixzone *sixzone;
+ u32 reg = 0, hold = 0, local_hold = 0;
+ u32 opcode = 0, local_opcode = 0;
+ int rc;
+
+ opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);
+
+ rc = reg_dma_dspp_check(ctx, cfg, SIX_ZONE);
+ if (rc)
+ return;
+
+ if (!hw_cfg->payload) {
+ DRM_DEBUG_DRIVER("disable sixzone feature\n");
+ opcode &= ~(PA_SIXZONE_HUE_EN | PA_SIXZONE_SAT_EN |
+ PA_SIXZONE_VAL_EN);
+ if (PA_DISABLE_REQUIRED(opcode))
+ opcode &= ~PA_EN;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+ return;
+ }
+
+ if (hw_cfg->len != sizeof(struct drm_msm_sixzone)) {
+ DRM_ERROR("invalid size of payload len %d exp %zd\n",
+ hw_cfg->len, sizeof(struct drm_msm_sixzone));
+ return;
+ }
+
+ sixzone = hw_cfg->payload;
+
+ dma_ops = sde_reg_dma_get_ops();
+ dma_ops->reset_reg_dma_buf(dspp_buf[SIX_ZONE][ctx->idx]);
+
+ REG_DMA_INIT_OPS(dma_write_cfg, dspp_mapping[ctx->idx],
+ SIX_ZONE, dspp_buf[SIX_ZONE][ctx->idx]);
+
+ REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("write decode select failed ret %d\n", rc);
+ return;
+ }
+
+ reg = BIT(26);
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->sixzone.base,
+ ®, sizeof(reg), REG_SINGLE_WRITE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("setting lut index failed ret %d\n", rc);
+ return;
+ }
+
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ (ctx->cap->sblk->sixzone.base + SIXZONE_ADJ_CURVE_P1_OFF),
+ &sixzone->curve[0].p1, (SIXZONE_LUT_SIZE * sizeof(u32) * 2),
+ REG_BLK_WRITE_MULTIPLE, 2, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("write sixzone lut failed ret %d\n", rc);
+ return;
+ }
+
+ REG_DMA_SETUP_OPS(dma_write_cfg,
+ ctx->cap->sblk->sixzone.base + SIXZONE_THRESHOLDS_OFF,
+ &sixzone->threshold, 3 * sizeof(u32),
+ REG_BLK_WRITE_SINGLE, 0, 0);
+ rc = dma_ops->setup_payload(&dma_write_cfg);
+ if (rc) {
+ DRM_ERROR("write sixzone threshold failed ret %d\n", rc);
+ return;
+ }
+
+ REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,
+ dspp_buf[SIX_ZONE][ctx->idx],
+ REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE);
+ rc = dma_ops->kick_off(&kick_off);
+ if (rc)
+ DRM_ERROR("failed to kick off ret %d\n", rc);
+
+ hold = SDE_REG_READ(&ctx->hw,
+ (ctx->cap->sblk->hsic.base + PA_PWL_HOLD_OFF));
+ local_hold = ((sixzone->sat_hold & REG_MASK(2)) << 12);
+ local_hold |= ((sixzone->val_hold & REG_MASK(2)) << 14);
+ hold &= ~REG_MASK_SHIFT(4, 12);
+ hold |= local_hold;
+ SDE_REG_WRITE(&ctx->hw,
+ (ctx->cap->sblk->hsic.base + PA_PWL_HOLD_OFF), hold);
+
+ if (sixzone->flags & SIXZONE_HUE_ENABLE)
+ local_opcode |= PA_SIXZONE_HUE_EN;
+ if (sixzone->flags & SIXZONE_SAT_ENABLE)
+ local_opcode |= PA_SIXZONE_SAT_EN;
+ if (sixzone->flags & SIXZONE_VAL_ENABLE)
+ local_opcode |= PA_SIXZONE_VAL_EN;
+
+ if (local_opcode)
+ local_opcode |= PA_EN;
+
+ opcode &= ~REG_MASK_SHIFT(3, 29);
+ opcode |= local_opcode;
+ SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);
+}
+
int reg_dmav1_deinit_dspp_ops(enum sde_dspp idx)
{
int i;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h
index bb72c8f..a8115d6 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h
@@ -67,6 +67,20 @@
void reg_dmav1_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg);
/**
+ * reg_dmav1_setup_dspp_pa_hsicv18() - pa hsic v18 impl using reg dma v1.
+ * @ctx: dspp ctx info
+ * @cfg: pointer to struct sde_hw_cp_cfg
+ */
+void reg_dmav1_setup_dspp_pa_hsicv18(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
+ * reg_dmav1_setup_dspp_sixzonev18() - sixzone v18 impl using reg dma v1.
+ * @ctx: dspp ctx info
+ * @cfg: pointer to struct sde_hw_cp_cfg
+ */
+void reg_dmav1_setup_dspp_sixzonev18(struct sde_hw_dspp *ctx, void *cfg);
+
+/**
* reg_dmav1_deinit_dspp_ops() - deinitialize the dspp feature op for sde v4
* which were initialized.
* @idx: dspp idx
diff --git a/drivers/gpu/drm/msm/sde/sde_rm.c b/drivers/gpu/drm/msm/sde/sde_rm.c
index ebcf9e0..21fbcb5 100644
--- a/drivers/gpu/drm/msm/sde/sde_rm.c
+++ b/drivers/gpu/drm/msm/sde/sde_rm.c
@@ -419,8 +419,8 @@
struct sde_lm_cfg *lm = &cat->mixer[i];
if (lm->pingpong == PINGPONG_MAX) {
- SDE_DEBUG("skip mixer %d without pingpong\n", lm->id);
- continue;
+ SDE_ERROR("mixer %d without pingpong\n", lm->id);
+ goto fail;
}
rc = _sde_rm_hw_blk_create(rm, cat, mmio, SDE_HW_BLK_LM,
@@ -570,14 +570,16 @@
const struct sde_pingpong_cfg *pp_cfg;
struct sde_rm_hw_iter iter;
bool is_valid_dspp, is_valid_ds, ret;
+ u32 display_pref;
*dspp = NULL;
*ds = NULL;
*pp = NULL;
+ display_pref = lm_cfg->features & BIT(SDE_DISP_PRIMARY_PREF);
- SDE_DEBUG("check lm %d: dspp %d ds %d pp %d\n",
- lm_cfg->id, lm_cfg->dspp,
- lm_cfg->ds, lm_cfg->pingpong);
+ SDE_DEBUG("check lm %d: dspp %d ds %d pp %d display_pref: %d\n",
+ lm_cfg->id, lm_cfg->dspp, lm_cfg->ds,
+ lm_cfg->pingpong, display_pref);
/* Check if this layer mixer is a peer of the proposed primary LM */
if (primary_lm) {
@@ -591,28 +593,39 @@
}
}
- is_valid_dspp = (lm_cfg->dspp != DSPP_MAX) ? true : false;
- is_valid_ds = (lm_cfg->ds != DS_MAX) ? true : false;
+ /* bypass rest of the checks if LM for primary display is found */
+ if (!display_pref) {
+ is_valid_dspp = (lm_cfg->dspp != DSPP_MAX) ? true : false;
+ is_valid_ds = (lm_cfg->ds != DS_MAX) ? true : false;
- /**
- * RM_RQ_X: specification of which LMs to choose
- * is_valid_X: indicates whether LM is tied with block X
- * ret: true if given LM matches the user requirement, false otherwise
- */
- if (RM_RQ_DSPP(reqs) && RM_RQ_DS(reqs))
- ret = (is_valid_dspp && is_valid_ds);
- else if (RM_RQ_DSPP(reqs))
- ret = is_valid_dspp;
- else if (RM_RQ_DS(reqs))
- ret = is_valid_ds;
- else
- ret = !(is_valid_dspp || is_valid_ds);
+ /**
+ * RM_RQ_X: specification of which LMs to choose
+ * is_valid_X: indicates whether LM is tied with block X
+ * ret: true if given LM matches the user requirement,
+ * false otherwise
+ */
+ if (RM_RQ_DSPP(reqs) && RM_RQ_DS(reqs))
+ ret = (is_valid_dspp && is_valid_ds);
+ else if (RM_RQ_DSPP(reqs))
+ ret = is_valid_dspp;
+ else if (RM_RQ_DS(reqs))
+ ret = is_valid_ds;
+ else
+ ret = !(is_valid_dspp || is_valid_ds);
- if (!ret) {
- SDE_DEBUG("fail:lm(%d)req_dspp(%d)dspp(%d)req_ds(%d)ds(%d)\n",
- lm_cfg->id, (bool)(RM_RQ_DSPP(reqs)), lm_cfg->dspp,
- (bool)(RM_RQ_DS(reqs)), lm_cfg->ds);
- return ret;
+ if (!ret) {
+ SDE_DEBUG(
+ "fail:lm(%d)req_dspp(%d)dspp(%d)req_ds(%d)ds(%d)\n",
+ lm_cfg->id, (bool)(RM_RQ_DSPP(reqs)),
+ lm_cfg->dspp, (bool)(RM_RQ_DS(reqs)),
+ lm_cfg->ds);
+ return ret;
+ }
+ } else if (!(reqs->hw_res.is_primary && display_pref)) {
+ SDE_DEBUG(
+ "display preference is not met. is_primary: %d display_pref: %d\n",
+ (int)reqs->hw_res.is_primary, (int)display_pref);
+ return false;
}
/* Already reserved? */
@@ -804,6 +817,7 @@
static int _sde_rm_reserve_ctls(
struct sde_rm *rm,
struct sde_rm_rsvp *rsvp,
+ struct sde_rm_requirements *reqs,
const struct sde_rm_topology_def *top)
{
struct sde_rm_hw_blk *ctls[MAX_BLOCKS];
@@ -816,21 +830,34 @@
while (_sde_rm_get_hw_locked(rm, &iter)) {
const struct sde_hw_ctl *ctl = to_sde_hw_ctl(iter.blk->hw);
unsigned long features = ctl->caps->features;
- bool has_split_display, has_ppsplit;
+ bool has_split_display, has_ppsplit, primary_pref;
if (RESERVED_BY_OTHER(iter.blk, rsvp))
continue;
has_split_display = BIT(SDE_CTL_SPLIT_DISPLAY) & features;
has_ppsplit = BIT(SDE_CTL_PINGPONG_SPLIT) & features;
+ primary_pref = BIT(SDE_CTL_PRIMARY_PREF) & features;
SDE_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
- if (top->needs_split_display != has_split_display)
- continue;
+ /*
+ * bypass rest feature checks on finding CTL preferred
+ * for primary displays.
+ */
+ if (!primary_pref) {
+ if (top->needs_split_display != has_split_display)
+ continue;
- if (top->top_name == SDE_RM_TOPOLOGY_PPSPLIT && !has_ppsplit)
+ if (top->top_name == SDE_RM_TOPOLOGY_PPSPLIT &&
+ !has_ppsplit)
+ continue;
+ } else if (!(reqs->hw_res.is_primary && primary_pref)) {
+ SDE_DEBUG(
+ "display pref not met. is_primary: %d primary_pref: %d\n",
+ reqs->hw_res.is_primary, primary_pref);
continue;
+ }
ctls[i] = iter.blk;
SDE_DEBUG("ctl %d match\n", iter.blk->id);
@@ -1032,11 +1059,11 @@
* - Check mixers without Split Display
* - Only then allow to grab from CTLs with split display capability
*/
- _sde_rm_reserve_ctls(rm, rsvp, reqs->topology);
+ _sde_rm_reserve_ctls(rm, rsvp, reqs, reqs->topology);
if (ret && !reqs->topology->needs_split_display) {
memcpy(&topology, reqs->topology, sizeof(topology));
topology.needs_split_display = true;
- _sde_rm_reserve_ctls(rm, rsvp, &topology);
+ _sde_rm_reserve_ctls(rm, rsvp, reqs, &topology);
}
if (ret) {
SDE_ERROR("unable to find appropriate CTL\n");
@@ -1084,10 +1111,6 @@
return -EINVAL;
}
- /* DSC blocks are hardwired for control path 0 and 1 */
- if (reqs->topology->num_comp_enc)
- reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DSPP);
-
/**
* Set the requirement based on caps if not set from user space
* This will ensure to select LM tied with DS blocks
@@ -1145,6 +1168,33 @@
return NULL;
}
+int sde_rm_update_topology(struct drm_connector_state *conn_state,
+ struct msm_display_topology *topology)
+{
+ int i, ret = 0;
+ struct msm_display_topology top;
+ enum sde_rm_topology_name top_name = SDE_RM_TOPOLOGY_NONE;
+
+ if (!conn_state)
+ return -EINVAL;
+
+ if (topology) {
+ top = *topology;
+ for (i = 0; i < SDE_RM_TOPOLOGY_MAX; i++)
+ if (RM_IS_TOPOLOGY_MATCH(g_top_table[i], top)) {
+ top_name = g_top_table[i].top_name;
+ break;
+ }
+ }
+
+ ret = msm_property_set_property(
+ sde_connector_get_propinfo(conn_state->connector),
+ sde_connector_get_property_state(conn_state),
+ CONNECTOR_PROP_TOPOLOGY_NAME, top_name);
+
+ return ret;
+}
+
/**
* _sde_rm_release_rsvp - release resources and release a reservation
* @rm: KMS handle
@@ -1226,12 +1276,6 @@
SDE_DEBUG("release rsvp[s%de%d]\n", rsvp->seq,
rsvp->enc_id);
_sde_rm_release_rsvp(rm, rsvp, conn);
-
- (void) msm_property_set_property(
- sde_connector_get_propinfo(conn),
- sde_connector_get_property_state(conn->state),
- CONNECTOR_PROP_TOPOLOGY_NAME,
- SDE_RM_TOPOLOGY_NONE);
}
end:
@@ -1247,18 +1291,6 @@
enum sde_hw_blk_type type;
int ret = 0;
- ret = msm_property_set_property(
- sde_connector_get_propinfo(conn_state->connector),
- sde_connector_get_property_state(conn_state),
- CONNECTOR_PROP_TOPOLOGY_NAME,
- rsvp->topology);
- if (ret) {
- SDE_ERROR("failed to set topology name property, ret %d\n",
- ret);
- _sde_rm_release_rsvp(rm, rsvp, conn_state->connector);
- return ret;
- }
-
/* Swap next rsvp to be the active */
for (type = 0; type < SDE_HW_BLK_MAX; type++) {
list_for_each_entry(blk, &rm->hw_blks[type], list) {
@@ -1343,12 +1375,6 @@
_sde_rm_release_rsvp(rm, rsvp_cur, conn_state->connector);
rsvp_cur = NULL;
_sde_rm_print_rsvps(rm, SDE_RM_STAGE_AFTER_CLEAR);
- (void) msm_property_set_property(
- sde_connector_get_propinfo(
- conn_state->connector),
- sde_connector_get_property_state(conn_state),
- CONNECTOR_PROP_TOPOLOGY_NAME,
- SDE_RM_TOPOLOGY_NONE);
}
/* Check the proposed reservation, store it in hw's "next" field */
diff --git a/drivers/gpu/drm/msm/sde/sde_rm.h b/drivers/gpu/drm/msm/sde/sde_rm.h
index 1e48855..3b9b82f 100644
--- a/drivers/gpu/drm/msm/sde/sde_rm.h
+++ b/drivers/gpu/drm/msm/sde/sde_rm.h
@@ -197,4 +197,13 @@
*/
int sde_rm_check_property_topctl(uint64_t val);
+/**
+ * sde_rm_update_topology - sets topology property of the connector
+ * @conn_state: drm state of the connector
+ * @topology: topology selected for the display
+ * @return: 0 on success or error
+ */
+int sde_rm_update_topology(struct drm_connector_state *conn_state,
+ struct msm_display_topology *topology);
+
#endif /* __SDE_RM_H__ */
diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h
index d1dad8a..a56a593 100644
--- a/drivers/gpu/msm/adreno-gpulist.h
+++ b/drivers/gpu/msm/adreno-gpulist.h
@@ -346,7 +346,7 @@
.major = 3,
.minor = 0,
.patchid = ANY_ID,
- .features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_IFPC |
+ .features = ADRENO_64BIT | ADRENO_RPMH |
ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_LM,
.sqefw_name = "a630_sqe.fw",
.zap_name = "a630_zap",
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 8e5683f..3c2d214 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -112,6 +112,11 @@
.active_list_lock = __SPIN_LOCK_UNLOCKED(device_3d0.active_list_lock),
.gpu_llc_slice_enable = true,
.gpuhtw_llc_slice_enable = true,
+ .preempt = {
+ .preempt_level = 1,
+ .skipsaverestore = 1,
+ .usesgmem = 1,
+ },
};
/* Ptr to array for the current set of fault detect registers */
@@ -852,13 +857,13 @@
struct device_node *parent)
{
struct device_node *node, *child;
+ unsigned int bin = 0;
node = of_find_node_by_name(parent, "qcom,gpu-pwrlevel-bins");
if (node == NULL)
return adreno_of_get_legacy_pwrlevels(adreno_dev, parent);
for_each_child_of_node(node, child) {
- unsigned int bin;
if (of_property_read_u32(child, "qcom,speed-bin", &bin))
continue;
@@ -874,6 +879,8 @@
}
}
+ KGSL_CORE_ERR("GPU speed_bin:%d mismatch for efused bin:%d\n",
+ adreno_dev->speed_bin, bin);
return -ENODEV;
}
@@ -898,6 +905,7 @@
{ ADRENO_QUIRK_DISABLE_LMLOADKILL,
"qcom,gpu-quirk-lmloadkill-disable" },
{ ADRENO_QUIRK_HFI_USE_REG, "qcom,gpu-quirk-hfi-use-reg" },
+ { ADRENO_QUIRK_SECVID_SET_ONCE, "qcom,gpu-quirk-secvid-set-once" },
};
static int adreno_of_get_power(struct adreno_device *adreno_dev,
@@ -1266,6 +1274,10 @@
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
int ret;
+ if (!adreno_is_a3xx(adreno_dev))
+ kgsl_sharedmem_set(device, &device->scratch, 0, 0,
+ device->scratch.size);
+
ret = kgsl_pwrctrl_change_state(device, KGSL_STATE_INIT);
if (ret)
return ret;
@@ -1389,9 +1401,10 @@
static void _set_secvid(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+ static bool set;
/* Program GPU contect protection init values */
- if (device->mmu.secured) {
+ if (device->mmu.secured && !set) {
if (adreno_is_a4xx(adreno_dev))
adreno_writereg(adreno_dev,
ADRENO_REG_RBBM_SECVID_TRUST_CONFIG, 0x2);
@@ -1405,6 +1418,8 @@
adreno_writereg(adreno_dev,
ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,
KGSL_IOMMU_SECURE_SIZE);
+ if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_SECVID_SET_ONCE))
+ set = true;
}
}
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 3118375..fc7801b 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -140,6 +140,8 @@
#define ADRENO_QUIRK_DISABLE_LMLOADKILL BIT(5)
/* Allow HFI to use registers to send message to GMU */
#define ADRENO_QUIRK_HFI_USE_REG BIT(6)
+/* Only set protected SECVID registers once */
+#define ADRENO_QUIRK_SECVID_SET_ONCE BIT(7)
/* Flags to control command packet settings */
#define KGSL_CMD_FLAGS_NONE 0
@@ -258,6 +260,9 @@
* @work: A work struct for the preemption worker (for 5XX)
* @token_submit: Indicates if a preempt token has been submitted in
* current ringbuffer (for 4XX)
+ * preempt_level: The level of preemption (for 6XX)
+ * skipsaverestore: To skip saverestore during L1 preemption (for 6XX)
+ * usesgmem: enable GMEM save/restore across preemption (for 6XX)
*/
struct adreno_preemption {
atomic_t state;
@@ -265,6 +270,9 @@
struct timer_list timer;
struct work_struct work;
bool token_submit;
+ unsigned int preempt_level;
+ bool skipsaverestore;
+ bool usesgmem;
};
@@ -483,10 +491,6 @@
void *gpuhtw_llc_slice;
bool gpuhtw_llc_slice_enable;
unsigned int zap_loaded;
- unsigned int preempt_level;
- bool usesgmem;
- bool skipsaverestore;
-
};
/**
diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c
index cc3cfdd..453ef4f 100644
--- a/drivers/gpu/msm/adreno_a6xx.c
+++ b/drivers/gpu/msm/adreno_a6xx.c
@@ -65,10 +65,10 @@
unsigned int val;
};
static const struct kgsl_hwcg_reg a630_hwcg_regs[] = {
- {A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
- {A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
- {A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
- {A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
+ {A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {A6XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
+ {A6XX_RBBM_CLOCK_CNTL_SP2, 0x02222222},
+ {A6XX_RBBM_CLOCK_CNTL_SP3, 0x02222222},
{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
{A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
{A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
@@ -143,20 +143,20 @@
{A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
{A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
{A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
- {A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
- {A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
- {A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
- {A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
+ {A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00000000},
+ {A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00000000},
+ {A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00000000},
+ {A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00000000},
{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
{A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
{A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
{A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
- {A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
- {A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {A6XX_RBBM_CLOCK_CNTL_RAC, 0x00022022},
+ {A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005550},
{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
- {A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
- {A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
+ {A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222220},
+ {A6XX_RBBM_CLOCK_MODE_GPC, 0x00202222},
{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
diff --git a/drivers/gpu/msm/adreno_a6xx_preempt.c b/drivers/gpu/msm/adreno_a6xx_preempt.c
index ca011e4..1eec381 100644
--- a/drivers/gpu/msm/adreno_a6xx_preempt.c
+++ b/drivers/gpu/msm/adreno_a6xx_preempt.c
@@ -208,10 +208,11 @@
unsigned int contextidr;
unsigned long flags;
uint32_t preempt_level, usesgmem, skipsaverestore;
+ struct adreno_preemption *preempt = &adreno_dev->preempt;
- preempt_level = adreno_dev->preempt_level;
- usesgmem = adreno_dev->usesgmem;
- skipsaverestore = adreno_dev->skipsaverestore;
+ preempt_level = preempt->preempt_level;
+ usesgmem = preempt->usesgmem;
+ skipsaverestore = preempt->skipsaverestore;
/* Put ourselves into a possible trigger state */
if (!adreno_move_preempt_state(adreno_dev,
diff --git a/drivers/gpu/msm/adreno_a6xx_snapshot.c b/drivers/gpu/msm/adreno_a6xx_snapshot.c
index e865f20..4357518 100644
--- a/drivers/gpu/msm/adreno_a6xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a6xx_snapshot.c
@@ -1481,6 +1481,7 @@
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
+ unsigned int val;
if (!kgsl_gmu_isenabled(device))
return;
@@ -1488,10 +1489,16 @@
adreno_snapshot_registers(device, snapshot, a6xx_gmu_registers,
ARRAY_SIZE(a6xx_gmu_registers) / 2);
- if (gpudev->gx_is_on(adreno_dev))
+ if (gpudev->gx_is_on(adreno_dev)) {
+ /* Set fence to ALLOW mode so registers can be read */
+ kgsl_regwrite(device, A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
+ kgsl_regread(device, A6XX_GMU_AO_AHB_FENCE_CTRL, &val);
+
+ KGSL_DRV_ERR(device, "set FENCE to ALLOW mode:%x\n", val);
adreno_snapshot_registers(device, snapshot,
a6xx_gmu_gx_registers,
ARRAY_SIZE(a6xx_gmu_gx_registers) / 2);
+ }
}
/* a6xx_snapshot_sqe() - Dump SQE data in snapshot */
@@ -1579,9 +1586,6 @@
bool sptprac_on;
unsigned int i;
- /* Make sure the fence is in ALLOW mode so registers can be read */
- kgsl_regwrite(device, A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
-
/* GMU TCM data dumped through AHB */
a6xx_snapshot_gmu(adreno_dev, snapshot);
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index d248479..0965923 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -225,8 +225,9 @@
FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
kgsl_sharedmem_set(device, &(rb->buffer_desc),
0, 0xAA, KGSL_RB_SIZE);
- kgsl_sharedmem_writel(device, &device->scratch,
- SCRATCH_RPTR_OFFSET(rb->id), 0);
+ if (!adreno_is_a3xx(adreno_dev))
+ kgsl_sharedmem_writel(device, &device->scratch,
+ SCRATCH_RPTR_OFFSET(rb->id), 0);
rb->wptr = 0;
rb->_wptr = 0;
rb->wptr_preempt_end = 0xFFFFFFFF;
@@ -287,9 +288,16 @@
int adreno_ringbuffer_probe(struct adreno_device *adreno_dev, bool nopreempt)
{
- int status = 0;
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
- int i;
+ int i, status;
+
+ if (!adreno_is_a3xx(adreno_dev)) {
+ status = kgsl_allocate_global(device, &device->scratch,
+ PAGE_SIZE, 0, 0, "scratch");
+ if (status != 0)
+ return status;
+ }
if (nopreempt == false)
adreno_dev->num_ringbuffers = gpudev->num_prio_levels;
@@ -325,9 +333,13 @@
void adreno_ringbuffer_close(struct adreno_device *adreno_dev)
{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_ringbuffer *rb;
int i;
+ if (!adreno_is_a3xx(adreno_dev))
+ kgsl_free_global(device, &device->scratch);
+
FOR_EACH_RINGBUFFER(adreno_dev, rb, i)
_adreno_ringbuffer_close(adreno_dev, rb);
}
diff --git a/drivers/gpu/msm/adreno_sysfs.c b/drivers/gpu/msm/adreno_sysfs.c
index 704e79e..fcf0417 100644
--- a/drivers/gpu/msm/adreno_sysfs.c
+++ b/drivers/gpu/msm/adreno_sysfs.c
@@ -54,38 +54,50 @@
static int _preempt_level_store(struct adreno_device *adreno_dev,
unsigned int val)
{
+ struct adreno_preemption *preempt = &adreno_dev->preempt;
+
if (val <= 2)
- adreno_dev->preempt_level = val;
+ preempt->preempt_level = val;
return 0;
}
static unsigned int _preempt_level_show(struct adreno_device *adreno_dev)
{
- return adreno_dev->preempt_level;
+ struct adreno_preemption *preempt = &adreno_dev->preempt;
+
+ return preempt->preempt_level;
}
static int _usesgmem_store(struct adreno_device *adreno_dev,
unsigned int val)
{
- adreno_dev->usesgmem = val ? 1 : 0;
+ struct adreno_preemption *preempt = &adreno_dev->preempt;
+
+ preempt->usesgmem = val ? 1 : 0;
return 0;
}
static unsigned int _usesgmem_show(struct adreno_device *adreno_dev)
{
- return adreno_dev->usesgmem;
+ struct adreno_preemption *preempt = &adreno_dev->preempt;
+
+ return preempt->usesgmem;
}
static int _skipsaverestore_store(struct adreno_device *adreno_dev,
unsigned int val)
{
- adreno_dev->skipsaverestore = val ? 1 : 0;
+ struct adreno_preemption *preempt = &adreno_dev->preempt;
+
+ preempt->skipsaverestore = val ? 1 : 0;
return 0;
}
static unsigned int _skipsaverestore_show(struct adreno_device *adreno_dev)
{
- return adreno_dev->skipsaverestore;
+ struct adreno_preemption *preempt = &adreno_dev->preempt;
+
+ return preempt->skipsaverestore;
}
static int _ft_pagefault_policy_store(struct adreno_device *adreno_dev,
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 7da90c6..31868a0 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -1131,8 +1131,6 @@
atomic_inc(&device->active_cnt);
kgsl_sharedmem_set(device, &device->memstore, 0, 0,
device->memstore.size);
- kgsl_sharedmem_set(device, &device->scratch, 0, 0,
- device->scratch.size);
result = device->ftbl->init(device);
if (result)
@@ -4382,13 +4380,13 @@
if (!kgsl_memdesc_use_cpu_map(&entry->memdesc)) {
val = get_unmapped_area(NULL, addr, len, 0, flags);
if (IS_ERR_VALUE(val))
- KGSL_MEM_ERR(device,
+ KGSL_DRV_ERR_RATELIMIT(device,
"get_unmapped_area: pid %d addr %lx pgoff %lx len %ld failed error %d\n",
private->pid, addr, pgoff, len, (int) val);
} else {
val = _get_svm_area(private, entry, addr, len, flags);
if (IS_ERR_VALUE(val))
- KGSL_MEM_ERR(device,
+ KGSL_DRV_ERR_RATELIMIT(device,
"_get_svm_area: pid %d mmap_base %lx addr %lx pgoff %lx len %ld failed error %d\n",
private->pid, current->mm->mmap_base, addr,
pgoff, len, (int) val);
@@ -4689,11 +4687,6 @@
if (status != 0)
goto error_close_mmu;
- status = kgsl_allocate_global(device, &device->scratch,
- PAGE_SIZE, 0, 0, "scratch");
- if (status != 0)
- goto error_free_memstore;
-
/*
* The default request type PM_QOS_REQ_ALL_CORES is
* applicable to all CPU cores that are online and
@@ -4739,8 +4732,6 @@
return 0;
-error_free_memstore:
- kgsl_free_global(device, &device->memstore);
error_close_mmu:
kgsl_mmu_close(device);
error_pwrctrl_close:
@@ -4768,8 +4759,6 @@
idr_destroy(&device->context_idr);
- kgsl_free_global(device, &device->scratch);
-
kgsl_free_global(device, &device->memstore);
kgsl_mmu_close(device);
diff --git a/drivers/gpu/msm/kgsl_gmu.c b/drivers/gpu/msm/kgsl_gmu.c
index 31d7870..57148e0 100644
--- a/drivers/gpu/msm/kgsl_gmu.c
+++ b/drivers/gpu/msm/kgsl_gmu.c
@@ -10,6 +10,7 @@
* GNU General Public License for more details.
*
*/
+#include <linux/module.h>
#include <linux/types.h>
#include <linux/device.h>
#include <linux/iommu.h>
@@ -25,6 +26,13 @@
#include "a6xx_reg.h"
#include "adreno.h"
+#undef MODULE_PARAM_PREFIX
+#define MODULE_PARAM_PREFIX "kgsl_gmu."
+
+static bool nogmu;
+module_param(nogmu, bool, 0444);
+MODULE_PARM_DESC(nogmu, "Disable the GMU");
+
#define GMU_CONTEXT_USER 0
#define GMU_CONTEXT_KERNEL 1
#define GMU_KERNEL_ENTRIES 8
@@ -109,9 +117,9 @@
struct gmu_device *gmu = &device->gmu;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
- if (gmu->pdev && ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))
+ if (!nogmu && gmu->pdev &&
+ ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))
return true;
-
return false;
}
@@ -799,6 +807,15 @@
if (status & GMU_INT_HOST_AHB_BUS_ERR)
dev_err_ratelimited(&gmu->pdev->dev,
"AHB bus error interrupt received\n");
+ if (status & GMU_INT_FENCE_ERR) {
+ unsigned int fence_status;
+
+ adreno_read_gmureg(ADRENO_DEVICE(device),
+ ADRENO_REG_GMU_AHB_FENCE_STATUS, &fence_status);
+ dev_err_ratelimited(&gmu->pdev->dev,
+ "FENCE error interrupt received %x\n", fence_status);
+ }
+
if (status & ~GMU_AO_INT_MASK)
dev_err_ratelimited(&gmu->pdev->dev,
"Unhandled GMU interrupts 0x%lx\n",
@@ -1266,7 +1283,7 @@
return ret;
}
-#define CX_GDSC_TIMEOUT 500 /* ms */
+#define CX_GDSC_TIMEOUT 5000 /* ms */
static int gmu_disable_gdsc(struct gmu_device *gmu)
{
int ret;
@@ -1285,7 +1302,7 @@
/*
* After GX GDSC is off, CX GDSC must be off
* Voting off alone from GPU driver cannot
- * Guarantee CX GDSC off. Polling with 10ms
+ * Guarantee CX GDSC off. Polling with 5s
* timeout to ensure
*/
t = jiffies + msecs_to_jiffies(CX_GDSC_TIMEOUT);
@@ -1467,7 +1484,7 @@
struct gmu_device *gmu = &device->gmu;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
- bool idle = true;
+ int ret = 0;
if (!test_bit(GMU_CLK_ON, &gmu->flags))
return;
@@ -1475,38 +1492,37 @@
/* Wait for the lowest idle level we requested */
if (gpudev->wait_for_lowest_idle &&
gpudev->wait_for_lowest_idle(adreno_dev))
- idle = false;
+ goto error;
- gpudev->rpmh_gpu_pwrctrl(adreno_dev, GMU_NOTIFY_SLUMBER, 0, 0);
- if (!idle || (gpudev->wait_for_gmu_idle &&
- gpudev->wait_for_gmu_idle(adreno_dev))) {
- dev_err(&gmu->pdev->dev, "Stopping GMU before it is idle\n");
- idle = false;
- set_bit(GMU_FAULT, &gmu->flags);
- } else {
- idle = true;
- }
+ ret = gpudev->rpmh_gpu_pwrctrl(adreno_dev, GMU_NOTIFY_SLUMBER, 0, 0);
+ if (ret)
+ goto error;
- if (idle) {
- /* Pending message in all queues are abandoned */
- hfi_stop(gmu);
- clear_bit(GMU_HFI_ON, &gmu->flags);
- gmu_irq_disable(device);
+ if (gpudev->wait_for_gmu_idle &&
+ gpudev->wait_for_gmu_idle(adreno_dev))
+ goto error;
- gpudev->rpmh_gpu_pwrctrl(adreno_dev, GMU_FW_STOP, 0, 0);
- gmu_disable_clks(gmu);
- gmu_disable_gdsc(gmu);
- } else {
- /*
- * The power controller will change state to SLUMBER anyway
- * Set GMU_FAULT flag to indicate to power contrller
- * that hang recovery is needed to power on GPU
- */
- set_bit(GMU_FAULT, &gmu->flags);
- gmu_snapshot(device);
- }
+ /* Pending message in all queues are abandoned */
+ hfi_stop(gmu);
+ clear_bit(GMU_HFI_ON, &gmu->flags);
+ gmu_irq_disable(device);
+
+ gpudev->rpmh_gpu_pwrctrl(adreno_dev, GMU_FW_STOP, 0, 0);
+ gmu_disable_clks(gmu);
+ gmu_disable_gdsc(gmu);
msm_bus_scale_client_update_request(gmu->pcl, 0);
+ return;
+
+error:
+ /*
+ * The power controller will change state to SLUMBER anyway
+ * Set GMU_FAULT flag to indicate to power contrller
+ * that hang recovery is needed to power on GPU
+ */
+ set_bit(GMU_FAULT, &gmu->flags);
+ dev_err(&gmu->pdev->dev, "Failed to stop GMU\n");
+ gmu_snapshot(device);
}
void gmu_remove(struct kgsl_device *device)
diff --git a/drivers/gpu/msm/kgsl_gmu.h b/drivers/gpu/msm/kgsl_gmu.h
index adabbc2..e0c857f 100644
--- a/drivers/gpu/msm/kgsl_gmu.h
+++ b/drivers/gpu/msm/kgsl_gmu.h
@@ -22,11 +22,13 @@
#define GMU_INT_WDOG_BITE BIT(0)
#define GMU_INT_RSCC_COMP BIT(1)
+#define GMU_INT_FENCE_ERR BIT(3)
#define GMU_INT_DBD_WAKEUP BIT(4)
#define GMU_INT_HOST_AHB_BUS_ERR BIT(5)
#define GMU_AO_INT_MASK \
(GMU_INT_WDOG_BITE | \
- GMU_INT_HOST_AHB_BUS_ERR)
+ GMU_INT_HOST_AHB_BUS_ERR | \
+ GMU_INT_FENCE_ERR)
#define MAX_GMUFW_SIZE 0x2000 /* in dwords */
#define FENCE_RANGE_MASK ((0x1 << 31) | (0x0A << 18) | (0x8A0))
diff --git a/drivers/gpu/msm/kgsl_log.h b/drivers/gpu/msm/kgsl_log.h
index d79a410..4f1241b 100644
--- a/drivers/gpu/msm/kgsl_log.h
+++ b/drivers/gpu/msm/kgsl_log.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2002,2008-2011,2013-2014,2016 The Linux Foundation.
+/* Copyright (c) 2002,2008-2011,2013-2014,2016-2017 The Linux Foundation.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
@@ -67,6 +67,13 @@
__func__, ##args);\
} while (0)
+#define KGSL_LOG_ERR_RATELIMITED(dev, lvl, fmt, args...) \
+ do { \
+ if ((lvl) >= 3) \
+ dev_err_ratelimited(dev, "|%s| " fmt, \
+ __func__, ##args);\
+ } while (0)
+
#define KGSL_DRV_INFO(_dev, fmt, args...) \
KGSL_LOG_INFO(_dev->dev, _dev->drv_log, fmt, ##args)
#define KGSL_DRV_WARN(_dev, fmt, args...) \
@@ -77,6 +84,8 @@
KGSL_LOG_CRIT(_dev->dev, _dev->drv_log, fmt, ##args)
#define KGSL_DRV_CRIT_RATELIMIT(_dev, fmt, args...) \
KGSL_LOG_CRIT_RATELIMITED(_dev->dev, _dev->drv_log, fmt, ##args)
+#define KGSL_DRV_ERR_RATELIMIT(_dev, fmt, args...) \
+KGSL_LOG_ERR_RATELIMITED(_dev->dev, _dev->drv_log, fmt, ##args)
#define KGSL_DRV_FATAL(_dev, fmt, args...) \
KGSL_LOG_FATAL((_dev)->dev, (_dev)->drv_log, fmt, ##args)
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index cd26ca6..a8ab720 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -722,7 +722,7 @@
{
int i;
- for (i = pwr->num_pwrlevels - 1; i >= 0; i--) {
+ for (i = pwr->num_pwrlevels - 2; i >= 0; i--) {
if (abs(pwr->pwrlevels[i].gpu_freq - clock) < 5000000)
return i;
}
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 2460ba7..793cbb5 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -881,9 +881,17 @@
return ret;
if (gi2c->se_mode == UNINITIALIZED) {
- u32 se_mode = readl_relaxed(gi2c->base +
- GENI_IF_FIFO_DISABLE_RO);
+ int proto = get_se_proto(gi2c->base);
+ u32 se_mode;
+ if (unlikely(proto != I2C)) {
+ dev_err(gi2c->dev, "Invalid proto %d\n", proto);
+ se_geni_resources_off(&gi2c->i2c_rsc);
+ return -ENXIO;
+ }
+
+ se_mode = readl_relaxed(gi2c->base +
+ GENI_IF_FIFO_DISABLE_RO);
if (se_mode) {
gi2c->se_mode = GSI_ONLY;
geni_se_select_mode(gi2c->base, GSI_DMA);
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index a0e1f59..1bd8e89 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -101,6 +101,9 @@
#define sCR0_VMID16EN (1 << 31)
#define sCR0_BSU_SHIFT 14
#define sCR0_BSU_MASK 0x3
+#define sCR0_SHCFG_SHIFT 22
+#define sCR0_SHCFG_MASK 0x3
+#define sCR0_SHCFG_NSH 3
/* Auxiliary Configuration register */
#define ARM_SMMU_GR0_sACR 0x10
@@ -177,6 +180,9 @@
#define S2CR_CBNDX_MASK 0xff
#define S2CR_TYPE_SHIFT 16
#define S2CR_TYPE_MASK 0x3
+#define S2CR_SHCFG_SHIFT 8
+#define S2CR_SHCFG_MASK 0x3
+#define S2CR_SHCFG_NSH 0x3
enum arm_smmu_s2cr_type {
S2CR_TYPE_TRANS,
S2CR_TYPE_BYPASS,
@@ -251,6 +257,9 @@
#define ARM_SMMU_CB_ATS1PR 0x800
#define ARM_SMMU_CB_ATSR 0x8f0
+#define SCTLR_SHCFG_SHIFT 22
+#define SCTLR_SHCFG_MASK 0x3
+#define SCTLR_SHCFG_NSH 0x3
#define SCTLR_S1_ASIDPNE (1 << 12)
#define SCTLR_CFCFG (1 << 7)
#define SCTLR_HUPCF (1 << 8)
@@ -1181,6 +1190,7 @@
list_for_each_entry_safe(it, i, &smmu_domain->secure_pool_list, list) {
arm_smmu_unprepare_pgtable(smmu_domain, it->addr, it->size);
/* pages will be freed later (after being unassigned) */
+ list_del(&it->list);
kfree(it);
}
}
@@ -1526,6 +1536,9 @@
/* SCTLR */
reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE;
+ /* Ensure bypass transactions are Non-shareable */
+ reg |= SCTLR_SHCFG_NSH << SCTLR_SHCFG_SHIFT;
+
if (smmu_domain->attributes & (1 << DOMAIN_ATTR_CB_STALL_DISABLE)) {
reg &= ~SCTLR_CFCFG;
reg |= SCTLR_HUPCF;
@@ -1929,7 +1942,8 @@
struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;
u32 reg = (s2cr->type & S2CR_TYPE_MASK) << S2CR_TYPE_SHIFT |
(s2cr->cbndx & S2CR_CBNDX_MASK) << S2CR_CBNDX_SHIFT |
- (s2cr->privcfg & S2CR_PRIVCFG_MASK) << S2CR_PRIVCFG_SHIFT;
+ (s2cr->privcfg & S2CR_PRIVCFG_MASK) << S2CR_PRIVCFG_SHIFT |
+ S2CR_SHCFG_NSH << S2CR_SHCFG_SHIFT;
writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_S2CR(idx));
}
@@ -2392,10 +2406,6 @@
if (!ops)
return -ENODEV;
- ret = arm_smmu_domain_power_on(domain, smmu_domain->smmu);
- if (ret)
- return ret;
-
arm_smmu_secure_domain_lock(smmu_domain);
__saved_iova_start = iova;
@@ -2436,7 +2446,6 @@
iova = __saved_iova_start;
}
arm_smmu_secure_domain_unlock(smmu_domain);
- arm_smmu_domain_power_off(domain, smmu_domain->smmu);
return iova - __saved_iova_start;
}
@@ -3430,6 +3439,10 @@
if (smmu->features & ARM_SMMU_FEAT_VMID16)
reg |= sCR0_VMID16EN;
+ /* Force bypass transaction to be Non-Shareable & not io-coherent */
+ reg &= ~(sCR0_SHCFG_MASK << sCR0_SHCFG_SHIFT);
+ reg |= sCR0_SHCFG_NSH;
+
/* Push the button */
__arm_smmu_tlb_sync(smmu);
writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
diff --git a/drivers/irqchip/qcom/pdc-sdm845.c b/drivers/irqchip/qcom/pdc-sdm845.c
index 178cf1f0..2f90e10 100644
--- a/drivers/irqchip/qcom/pdc-sdm845.c
+++ b/drivers/irqchip/qcom/pdc-sdm845.c
@@ -130,10 +130,135 @@
{-1}
};
+static struct pdc_pin sdm845_data_v2[] = {
+ {0, 512}, /* rpmh_wake */
+ {1, 513}, /* ee0_apps_hlos_spmi_periph_irq */
+ {2, 514}, /* ee1_apps_trustzone_spmi_periph_irq */
+ {3, 515}, /* secure_wdog_expired */
+ {4, 516}, /* secure_wdog_bark_irq */
+ {5, 517}, /* aop_wdog_expired_irq */
+ {6, 518}, /* qmp_usb3_lfps_rxterm_irq */
+ {7, 519}, /* qmp_usb3_lfps_rxterm_irq */
+ {8, 520}, /* eud_p0_dmse_int_mx */
+ {9, 521}, /* eud_p0_dpse_int_mx */
+ {10, 522}, /* eud_p1_dmse_int_mx */
+ {11, 523}, /* eud_p1_dpse_int_mx */
+ {12, 524}, /* eud_int_mx[1] */
+ {13, 525}, /* ssc_xpu_irq_summary */
+ {14, 526}, /* wd_bite_apps */
+ {15, 527}, /* ssc_vmidmt_irq_summary */
+ {16, 528}, /* q6ss_irq_out_apps_ipc[4] */
+ {17, 529}, /* not-connected */
+ {18, 530}, /* aoss_pmic_arb_mpu_xpu_summary_irq */
+ {19, 531}, /* apps_pdc_irq_in_19 */
+ {20, 532}, /* apps_pdc_irq_in_20 */
+ {21, 533}, /* apps_pdc_irq_in_21 */
+ {22, 534}, /* pdc_apps_epcb_timeout_summary_irq */
+ {23, 535}, /* spmi_protocol_irq */
+ {24, 536}, /* tsense0_tsense_max_min_int */
+ {25, 537}, /* tsense1_tsense_max_min_int */
+ {26, 538}, /* tsense0_upper_lower_intr */
+ {27, 539}, /* tsense1_upper_lower_intr */
+ {28, 540}, /* tsense0_critical_intr */
+ {29, 541}, /* tsense1_critical_intr */
+ {30, 542}, /* core_bi_px_gpio_1 */
+ {31, 543}, /* core_bi_px_gpio_3 */
+ {32, 544}, /* core_bi_px_gpio_5 */
+ {33, 545}, /* core_bi_px_gpio_10 */
+ {34, 546}, /* core_bi_px_gpio_11 */
+ {35, 547}, /* core_bi_px_gpio_20 */
+ {36, 548}, /* core_bi_px_gpio_22 */
+ {37, 549}, /* core_bi_px_gpio_24 */
+ {38, 550}, /* core_bi_px_gpio_26 */
+ {39, 551}, /* core_bi_px_gpio_30 */
+ {41, 553}, /* core_bi_px_gpio_32 */
+ {42, 554}, /* core_bi_px_gpio_34 */
+ {43, 555}, /* core_bi_px_gpio_36 */
+ {44, 556}, /* core_bi_px_gpio_37 */
+ {45, 557}, /* core_bi_px_gpio_38 */
+ {46, 558}, /* core_bi_px_gpio_39 */
+ {47, 559}, /* core_bi_px_gpio_40 */
+ {49, 561}, /* core_bi_px_gpio_43 */
+ {50, 562}, /* core_bi_px_gpio_44 */
+ {51, 563}, /* core_bi_px_gpio_46 */
+ {52, 564}, /* core_bi_px_gpio_48 */
+ {54, 566}, /* core_bi_px_gpio_52 */
+ {55, 567}, /* core_bi_px_gpio_53 */
+ {56, 568}, /* core_bi_px_gpio_54 */
+ {57, 569}, /* core_bi_px_gpio_56 */
+ {58, 570}, /* core_bi_px_gpio_57 */
+ {59, 571}, /* core_bi_px_gpio_58 */
+ {60, 572}, /* core_bi_px_gpio_59 */
+ {61, 573}, /* core_bi_px_gpio_60 */
+ {62, 574}, /* core_bi_px_gpio_61 */
+ {63, 575}, /* core_bi_px_gpio_62 */
+ {64, 576}, /* core_bi_px_gpio_63 */
+ {65, 577}, /* core_bi_px_gpio_64 */
+ {66, 578}, /* core_bi_px_gpio_66 */
+ {67, 579}, /* core_bi_px_gpio_68 */
+ {68, 580}, /* core_bi_px_gpio_71 */
+ {69, 581}, /* core_bi_px_gpio_73 */
+ {70, 582}, /* core_bi_px_gpio_77 */
+ {71, 583}, /* core_bi_px_gpio_78 */
+ {72, 584}, /* core_bi_px_gpio_79 */
+ {73, 585}, /* core_bi_px_gpio_80 */
+ {74, 586}, /* core_bi_px_gpio_84 */
+ {75, 587}, /* core_bi_px_gpio_85 */
+ {76, 588}, /* core_bi_px_gpio_86 */
+ {77, 589}, /* core_bi_px_gpio_88 */
+ {79, 591}, /* core_bi_px_gpio_91 */
+ {80, 592}, /* core_bi_px_gpio_92 */
+ {81, 593}, /* core_bi_px_gpio_95 */
+ {82, 594}, /* core_bi_px_gpio_96 */
+ {83, 595}, /* core_bi_px_gpio_97 */
+ {84, 596}, /* core_bi_px_gpio_101 */
+ {85, 597}, /* core_bi_px_gpio_103 */
+ {86, 598}, /* core_bi_px_gpio_104 */
+ {87, 599}, /* core_bi_px_to_mpm[6] */
+ {88, 600}, /* core_bi_px_to_mpm[0] */
+ {89, 601}, /* core_bi_px_to_mpm[1] */
+ {90, 602}, /* core_bi_px_gpio_115 */
+ {91, 603}, /* core_bi_px_gpio_116 */
+ {92, 604}, /* core_bi_px_gpio_117 */
+ {93, 605}, /* core_bi_px_gpio_118 */
+ {94, 641}, /* core_bi_px_gpio_119 */
+ {95, 642}, /* core_bi_px_gpio_120 */
+ {96, 643}, /* core_bi_px_gpio_121 */
+ {97, 644}, /* core_bi_px_gpio_122 */
+ {98, 645}, /* core_bi_px_gpio_123 */
+ {99, 646}, /* core_bi_px_gpio_124 */
+ {100, 647}, /* core_bi_px_gpio_125 */
+ {101, 648}, /* core_bi_px_to_mpm[5] */
+ {102, 649}, /* core_bi_px_gpio_127 */
+ {103, 650}, /* core_bi_px_gpio_128 */
+ {104, 651}, /* core_bi_px_gpio_129 */
+ {105, 652}, /* core_bi_px_gpio_130 */
+ {106, 653}, /* core_bi_px_gpio_132 */
+ {107, 654}, /* core_bi_px_gpio_133 */
+ {108, 655}, /* core_bi_px_gpio_145 */
+ {119, 666}, /* core_bi_px_to_mpm[2] */
+ {120, 667}, /* core_bi_px_to_mpm[3] */
+ {121, 668}, /* core_bi_px_to_mpm[4] */
+ {115, 662}, /* core_bi_px_gpio_41 */
+ {116, 663}, /* core_bi_px_gpio_89 */
+ {117, 664}, /* core_bi_px_gpio_31 */
+ {118, 665}, /* core_bi_px_gpio_49 */
+ {-1}
+};
+
static int __init qcom_pdc_gic_init(struct device_node *node,
struct device_node *parent)
{
+ pr_info("PDC SDM845 v1 initialized\n");
return qcom_pdc_init(node, parent, sdm845_data);
}
+static int __init qcom_pdc_v2_gic_init(struct device_node *node,
+ struct device_node *parent)
+{
+ pr_info("PDC SDM845 v2 initialized\n");
+ return qcom_pdc_init(node, parent, sdm845_data_v2);
+}
+
IRQCHIP_DECLARE(pdc_sdm845, "qcom,pdc-sdm845", qcom_pdc_gic_init);
+IRQCHIP_DECLARE(pdc_sdm845_v2, "qcom,pdc-sdm845-v2", qcom_pdc_v2_gic_init);
diff --git a/drivers/leds/leds-qpnp-wled.c b/drivers/leds/leds-qpnp-wled.c
index 5c9c75c..579705d 100644
--- a/drivers/leds/leds-qpnp-wled.c
+++ b/drivers/leds/leds-qpnp-wled.c
@@ -106,10 +106,8 @@
#define QPNP_WLED_BOOST_DUTY_MIN_NS 26
#define QPNP_WLED_BOOST_DUTY_MAX_NS 156
#define QPNP_WLED_DEF_BOOST_DUTY_NS 104
-#define QPNP_WLED_SWITCH_FREQ_MASK 0x70
-#define QPNP_WLED_SWITCH_FREQ_800_KHZ 800
-#define QPNP_WLED_SWITCH_FREQ_1600_KHZ 1600
-#define QPNP_WLED_SWITCH_FREQ_OVERWRITE 0x80
+#define QPNP_WLED_SWITCH_FREQ_MASK GENMASK(3, 0)
+#define QPNP_WLED_SWITCH_FREQ_OVERWRITE BIT(7)
#define QPNP_WLED_OVP_MASK GENMASK(1, 0)
#define QPNP_WLED_TEST4_EN_DEB_BYPASS_ILIM_BIT BIT(6)
#define QPNP_WLED_TEST4_EN_SH_FOR_SS_BIT BIT(5)
@@ -404,6 +402,7 @@
bool ovp_irq_disabled;
bool auto_calib_enabled;
bool auto_calib_done;
+ bool module_dis_perm;
ktime_t start_ovp_fault_time;
};
@@ -600,6 +599,9 @@
{
int rc;
+ if (wled->module_dis_perm)
+ return 0;
+
rc = qpnp_wled_masked_write_reg(wled,
QPNP_WLED_MODULE_EN_REG(base_addr),
QPNP_WLED_MODULE_EN_MASK,
@@ -1098,7 +1100,7 @@
return 0;
}
-#define AUTO_CALIB_BRIGHTNESS 16
+#define AUTO_CALIB_BRIGHTNESS 200
static int wled_auto_calibrate(struct qpnp_wled *wled)
{
int rc = 0, i;
@@ -1128,6 +1130,17 @@
goto failed_calib;
}
+ if (wled->en_cabc) {
+ for (i = 0; i < wled->max_strings; i++) {
+ reg = 0;
+ rc = qpnp_wled_masked_write_reg(wled,
+ QPNP_WLED_CABC_REG(wled->sink_base, i),
+ QPNP_WLED_CABC_MASK, reg);
+ if (rc < 0)
+ goto failed_calib;
+ }
+ }
+
/* disable all sinks */
rc = qpnp_wled_write_reg(wled,
QPNP_WLED_CURR_SINK_REG(wled->sink_base), 0);
@@ -1136,21 +1149,6 @@
goto failed_calib;
}
- rc = qpnp_wled_masked_write_reg(wled,
- QPNP_WLED_MODULE_EN_REG(wled->ctrl_base),
- QPNP_WLED_MODULE_EN_MASK,
- QPNP_WLED_MODULE_EN_MASK);
- if (rc < 0) {
- pr_err("Failed to enable WLED module rc=%d\n", rc);
- goto failed_calib;
- }
- /*
- * Delay for the WLED soft-start, check the OVP status
- * only after soft-start is complete
- */
- usleep_range(QPNP_WLED_SOFT_START_DLY_US,
- QPNP_WLED_SOFT_START_DLY_US + 1000);
-
/* iterate through the strings one by one */
for (i = 0; i < wled->max_strings; i++) {
sink_test = 1 << (QPNP_WLED_CURR_SINK_SHIFT + i);
@@ -1174,6 +1172,15 @@
goto failed_calib;
}
+ /* Enable the module */
+ rc = qpnp_wled_masked_write_reg(wled,
+ QPNP_WLED_MODULE_EN_REG(wled->ctrl_base),
+ QPNP_WLED_MODULE_EN_MASK, QPNP_WLED_MODULE_EN_MASK);
+ if (rc < 0) {
+ pr_err("Failed to enable WLED module rc=%d\n", rc);
+ goto failed_calib;
+ }
+
/* delay for WLED soft-start */
usleep_range(QPNP_WLED_SOFT_START_DLY_US,
QPNP_WLED_SOFT_START_DLY_US + 1000);
@@ -1190,6 +1197,15 @@
i + 1);
else
sink_valid |= sink_test;
+
+ /* Disable the module */
+ rc = qpnp_wled_masked_write_reg(wled,
+ QPNP_WLED_MODULE_EN_REG(wled->ctrl_base),
+ QPNP_WLED_MODULE_EN_MASK, 0);
+ if (rc < 0) {
+ pr_err("Failed to disable WLED module rc=%d\n", rc);
+ goto failed_calib;
+ }
}
if (sink_valid == sink_config) {
@@ -1203,14 +1219,7 @@
if (!sink_config) {
pr_warn("No valid WLED sinks found\n");
- goto failed_calib;
- }
-
- rc = qpnp_wled_masked_write_reg(wled,
- QPNP_WLED_MODULE_EN_REG(wled->ctrl_base),
- QPNP_WLED_MODULE_EN_MASK, 0);
- if (rc < 0) {
- pr_err("Failed to disable WLED module rc=%d\n", rc);
+ wled->module_dis_perm = true;
goto failed_calib;
}
@@ -1224,6 +1233,15 @@
/* MODULATOR_EN setting for valid sinks */
for (i = 0; i < wled->max_strings; i++) {
+ if (wled->en_cabc) {
+ reg = 1 << QPNP_WLED_CABC_SHIFT;
+ rc = qpnp_wled_masked_write_reg(wled,
+ QPNP_WLED_CABC_REG(wled->sink_base, i),
+ QPNP_WLED_CABC_MASK, reg);
+ if (rc < 0)
+ goto failed_calib;
+ }
+
if (sink_config & (1 << (QPNP_WLED_CURR_SINK_SHIFT + i)))
reg = (QPNP_WLED_MOD_EN << QPNP_WLED_MOD_EN_SHFT);
else
@@ -1785,21 +1803,24 @@
return rc;
/* Configure the SWITCHING FREQ register */
- if (wled->switch_freq_khz == QPNP_WLED_SWITCH_FREQ_1600_KHZ)
- temp = QPNP_WLED_SWITCH_FREQ_1600_KHZ_CODE;
+ if (wled->switch_freq_khz == 1600)
+ reg = QPNP_WLED_SWITCH_FREQ_1600_KHZ_CODE;
else
- temp = QPNP_WLED_SWITCH_FREQ_800_KHZ_CODE;
+ reg = QPNP_WLED_SWITCH_FREQ_800_KHZ_CODE;
- rc = qpnp_wled_read_reg(wled,
- QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base), ®);
+ /*
+ * Do not set the overwrite bit when switching frequency is selected
+ * for AMOLED. This register is in logic reset block which can cause
+ * the value to be overwritten during module enable/disable.
+ */
+ mask = QPNP_WLED_SWITCH_FREQ_MASK | QPNP_WLED_SWITCH_FREQ_OVERWRITE;
+ if (!wled->disp_type_amoled)
+ reg |= QPNP_WLED_SWITCH_FREQ_OVERWRITE;
+
+ rc = qpnp_wled_masked_write_reg(wled,
+ QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base), mask, reg);
if (rc < 0)
return rc;
- reg &= QPNP_WLED_SWITCH_FREQ_MASK;
- reg |= (temp | QPNP_WLED_SWITCH_FREQ_OVERWRITE);
- rc = qpnp_wled_write_reg(wled,
- QPNP_WLED_SWITCH_FREQ_REG(wled->ctrl_base), reg);
- if (rc)
- return rc;
rc = qpnp_wled_ovp_config(wled);
if (rc < 0) {
@@ -2237,7 +2258,7 @@
return rc;
}
- wled->switch_freq_khz = QPNP_WLED_SWITCH_FREQ_800_KHZ;
+ wled->switch_freq_khz = wled->disp_type_amoled ? 1600 : 800;
rc = of_property_read_u32(pdev->dev.of_node,
"qcom,switch-freq-khz", &temp_val);
if (!rc) {
@@ -2442,7 +2463,7 @@
wled->pmic_rev_id->pmic_subtype, wled->pmic_rev_id->rev4);
prop = of_get_address_by_name(pdev->dev.of_node, QPNP_WLED_SINK_BASE,
- 0, 0);
+ NULL, NULL);
if (!prop) {
dev_err(&pdev->dev, "Couldnt find sink's addr rc %d\n", rc);
return rc;
@@ -2450,7 +2471,7 @@
wled->sink_base = be32_to_cpu(*prop);
prop = of_get_address_by_name(pdev->dev.of_node, QPNP_WLED_CTRL_BASE,
- 0, 0);
+ NULL, NULL);
if (!prop) {
dev_err(&pdev->dev, "Couldnt find ctrl's addr rc = %d\n", rc);
return rc;
diff --git a/drivers/md/dm-req-crypt.c b/drivers/md/dm-req-crypt.c
index 3ffe7e5..b4bdbc0 100644
--- a/drivers/md/dm-req-crypt.c
+++ b/drivers/md/dm-req-crypt.c
@@ -217,6 +217,7 @@
* this should never happen
*/
WARN_ON(1);
+ return;
}
} else {
DMERR("%s io is NULL\n", __func__);
@@ -225,6 +226,7 @@
* this should never happen
*/
WARN_ON(1);
+ return;
}
atomic_dec(&io->pending);
@@ -253,6 +255,7 @@
* this should never happen
*/
WARN_ON(1);
+ return;
}
} else {
DMERR("%s io is NULL\n",
@@ -262,6 +265,7 @@
* this should never happen
*/
WARN_ON(1);
+ return;
}
/* Should never get here if io or Clone is NULL */
@@ -445,6 +449,7 @@
if (!io || !io->cloned_request) {
DMERR("%s io is invalid\n", __func__);
WARN_ON(1); /* should not happen */
+ return;
}
clone = io->cloned_request;
@@ -696,6 +701,7 @@
if (!io || !io->cloned_request) {
DMERR("%s io is invalid\n", __func__);
WARN_ON(1); /* should not happen */
+ return;
}
clone = io->cloned_request;
@@ -740,6 +746,7 @@
err = DM_REQ_CRYPT_ERROR;
/* If io is not populated this should not be called */
WARN_ON(1);
+ return;
}
req = skcipher_request_alloc(tfm, GFP_KERNEL);
if (!req) {
diff --git a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c
index e3d46df..4b0cc74 100644
--- a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c
+++ b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c
@@ -372,6 +372,8 @@
&camnoc_info->specific[i].safe_lut);
cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
&camnoc_info->specific[i].ubwc_ctl);
+ cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
+ &camnoc_info->specific[i].flag_out_set0_low);
}
}
diff --git a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.h b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.h
index d5bb363..e3639a6 100644
--- a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.h
+++ b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.h
@@ -110,6 +110,7 @@
struct cam_cpas_reg danger_lut;
struct cam_cpas_reg safe_lut;
struct cam_cpas_reg ubwc_ctl;
+ struct cam_cpas_reg flag_out_set0_low;
};
/**
diff --git a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v170_110.h b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v170_110.h
index 918258d..55cb07b 100644
--- a/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v170_110.h
+++ b/drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v170_110.h
@@ -494,8 +494,15 @@
},
{
.port_type = CAM_CAMNOC_ICP,
- .enable = false,
- }
+ .enable = true,
+ .flag_out_set0_low = {
+ .enable = true,
+ .access_type = CAM_REG_TYPE_WRITE,
+ .masked_value = 0,
+ .offset = 0x2088,
+ .value = 0x100000,
+ },
+ },
};
static uint32_t cam_cpas110_slave_error_logger[] = {
diff --git a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c
index b8a5685..d9be53d 100644
--- a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c
+++ b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c
@@ -112,6 +112,9 @@
/* Before triggering reset to HW, clear the reset complete */
reinit_completion(&fd_core->reset_complete);
+ cam_fd_soc_register_write(soc_info, CAM_FD_REG_CORE,
+ hw_static_info->core_regs.control, 0x1);
+
if (hw_static_info->enable_errata_wa.single_irq_only) {
cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER,
hw_static_info->wrapper_regs.irq_mask,
@@ -126,9 +129,6 @@
if (time_left <= 0)
CAM_WARN(CAM_FD, "HW reset timeout time_left=%d", time_left);
- cam_fd_soc_register_write(soc_info, CAM_FD_REG_CORE,
- hw_static_info->core_regs.control, 0x1);
-
CAM_DBG(CAM_FD, "FD Wrapper SW Sync Reset complete");
return 0;
@@ -424,9 +424,10 @@
struct cam_fd_hw_req_private *req_private;
uint32_t base, face_cnt;
uint32_t *buffer;
+ unsigned long flags;
int i;
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
if ((fd_core->core_state != CAM_FD_CORE_STATE_IDLE) ||
(fd_core->results_valid == false) ||
!fd_core->hw_req_private) {
@@ -434,12 +435,12 @@
"Invalid state for results state=%d, results=%d %pK",
fd_core->core_state, fd_core->results_valid,
fd_core->hw_req_private);
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return -EINVAL;
}
fd_core->core_state = CAM_FD_CORE_STATE_READING_RESULTS;
req_private = fd_core->hw_req_private;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
/*
* Copy the register value as is into output buffers.
@@ -511,10 +512,10 @@
}
}
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
fd_core->hw_req_private = NULL;
fd_core->core_state = CAM_FD_CORE_STATE_IDLE;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return 0;
}
@@ -776,6 +777,9 @@
{
struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv;
struct cam_fd_core *fd_core;
+ struct cam_fd_hw_static_info *hw_static_info;
+ struct cam_hw_soc_info *soc_info;
+ unsigned long flags;
int rc;
if (!fd_hw) {
@@ -784,18 +788,23 @@
}
fd_core = (struct cam_fd_core *)fd_hw->core_info;
+ hw_static_info = fd_core->hw_static_info;
+ soc_info = &fd_hw->soc_info;
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
if (fd_core->core_state == CAM_FD_CORE_STATE_RESET_PROGRESS) {
CAM_ERR(CAM_FD, "Reset not allowed in %d state",
fd_core->core_state);
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return -EINVAL;
}
fd_core->results_valid = false;
fd_core->core_state = CAM_FD_CORE_STATE_RESET_PROGRESS;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
+
+ cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER,
+ hw_static_info->wrapper_regs.cgc_disable, 0x1);
rc = cam_fd_hw_util_fdwrapper_halt(fd_hw);
if (rc) {
@@ -809,9 +818,12 @@
return rc;
}
- spin_lock(&fd_core->spin_lock);
+ cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER,
+ hw_static_info->wrapper_regs.cgc_disable, 0x0);
+
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
fd_core->core_state = CAM_FD_CORE_STATE_IDLE;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return rc;
}
@@ -824,6 +836,7 @@
struct cam_fd_hw_cmd_start_args *start_args =
(struct cam_fd_hw_cmd_start_args *)hw_start_args;
struct cam_fd_ctx_hw_private *ctx_hw_private;
+ unsigned long flags;
int rc;
if (!hw_priv || !start_args) {
@@ -841,11 +854,11 @@
fd_core = (struct cam_fd_core *)fd_hw->core_info;
hw_static_info = fd_core->hw_static_info;
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
if (fd_core->core_state != CAM_FD_CORE_STATE_IDLE) {
CAM_ERR(CAM_FD, "Cannot start in %d state",
fd_core->core_state);
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return -EINVAL;
}
@@ -858,7 +871,7 @@
fd_core->hw_req_private = start_args->hw_req_private;
fd_core->core_state = CAM_FD_CORE_STATE_PROCESSING;
fd_core->results_valid = false;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
ctx_hw_private = start_args->ctx_hw_private;
@@ -903,9 +916,9 @@
return 0;
error:
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
fd_core->core_state = CAM_FD_CORE_STATE_IDLE;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return rc;
}
@@ -914,6 +927,9 @@
{
struct cam_hw_info *fd_hw = (struct cam_hw_info *)hw_priv;
struct cam_fd_core *fd_core;
+ struct cam_fd_hw_static_info *hw_static_info;
+ struct cam_hw_soc_info *soc_info;
+ unsigned long flags;
int rc;
if (!fd_hw) {
@@ -922,19 +938,24 @@
}
fd_core = (struct cam_fd_core *)fd_hw->core_info;
+ hw_static_info = fd_core->hw_static_info;
+ soc_info = &fd_hw->soc_info;
- spin_lock(&fd_core->spin_lock);
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
if ((fd_core->core_state == CAM_FD_CORE_STATE_POWERDOWN) ||
(fd_core->core_state == CAM_FD_CORE_STATE_RESET_PROGRESS)) {
CAM_ERR(CAM_FD, "Reset not allowed in %d state",
fd_core->core_state);
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return -EINVAL;
}
fd_core->results_valid = false;
fd_core->core_state = CAM_FD_CORE_STATE_RESET_PROGRESS;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
+
+ cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER,
+ hw_static_info->wrapper_regs.cgc_disable, 0x1);
rc = cam_fd_hw_util_fdwrapper_halt(fd_hw);
if (rc) {
@@ -949,9 +970,12 @@
return rc;
}
- spin_lock(&fd_core->spin_lock);
+ cam_fd_soc_register_write(soc_info, CAM_FD_REG_WRAPPER,
+ hw_static_info->wrapper_regs.cgc_disable, 0x0);
+
+ spin_lock_irqsave(&fd_core->spin_lock, flags);
fd_core->core_state = CAM_FD_CORE_STATE_IDLE;
- spin_unlock(&fd_core->spin_lock);
+ spin_unlock_irqrestore(&fd_core->spin_lock, flags);
return rc;
}
diff --git a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h
index bdd72af..3d9c5f0 100644
--- a/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h
+++ b/drivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h
@@ -30,7 +30,7 @@
#define CAM_FD_IRQ_TO_MASK(irq) (1 << (irq))
#define CAM_FD_MASK_TO_IRQ(mask, irq) ((mask) >> (irq))
-#define CAM_FD_HW_HALT_RESET_TIMEOUT 100
+#define CAM_FD_HW_HALT_RESET_TIMEOUT 750
/**
* enum cam_fd_core_state - FD Core internal states
diff --git a/drivers/media/platform/msm/camera/cam_icp/hfi.c b/drivers/media/platform/msm/camera/cam_icp/hfi.c
index a315268..cdb0cfa 100644
--- a/drivers/media/platform/msm/camera/cam_icp/hfi.c
+++ b/drivers/media/platform/msm/camera/cam_icp/hfi.c
@@ -385,10 +385,15 @@
ICP_FLAG_CSR_WAKE_UP_EN | ICP_CSR_EN_CLKGATE_WFI),
icp_base + HFI_REG_A5_CSR_A5_CONTROL);
} else {
+ /* Due to hardware bug in V1 ICP clock gating has to be
+ * disabled, this is supposed to be fixed in V-2. But enabling
+ * the clock gating is causing the firmware hang, hence
+ * disabling the clock gating on both V1 and V2 until the
+ * hardware team root causes this
+ */
cam_io_w((uint32_t)ICP_FLAG_CSR_A5_EN |
ICP_FLAG_CSR_WAKE_UP_EN |
- ((soc_version == SOC_VERSION_HW1) ?
- (ICP_CSR_EN_CLKGATE_WFI) : (0x0)),
+ ICP_CSR_EN_CLKGATE_WFI,
icp_base + HFI_REG_A5_CSR_A5_CONTROL);
}
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
index 6060278..8489780 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
@@ -778,10 +778,11 @@
uint32_t cid_res_id)
{
int rc = -1;
- int i, j;
+ int i;
struct cam_ife_hw_mgr *ife_hw_mgr;
struct cam_ife_hw_mgr_res *csid_res;
+ struct cam_ife_hw_mgr_res *cid_res;
struct cam_hw_intf *hw_intf;
struct cam_csid_hw_reserve_resource_args csid_acquire;
@@ -800,69 +801,64 @@
csid_acquire.in_port = in_port;
csid_acquire.out_port = in_port->data;
- if (in_port->usage_type)
- csid_acquire.sync_mode = CAM_ISP_HW_SYNC_MASTER;
- else
- csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE;
-
-
-
- for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) {
- if (!ife_hw_mgr->csid_devices[i])
- continue;
-
- hw_intf = ife_hw_mgr->csid_devices[i];
- rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, &csid_acquire,
- sizeof(csid_acquire));
- if (rc)
- continue;
- else
- break;
- }
-
- if (i == CAM_IFE_CSID_HW_NUM_MAX) {
- CAM_ERR(CAM_ISP, "Can not acquire ife csid ipp resource");
- goto err;
- }
-
- CAM_DBG(CAM_ISP, "acquired csid(%d) left ipp resource successfully",
- i);
-
csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH;
csid_res->res_id = CAM_IFE_PIX_PATH_RES_IPP;
csid_res->is_dual_vfe = in_port->usage_type;
- csid_res->hw_res[0] = csid_acquire.node_res;
- csid_res->hw_res[1] = NULL;
- if (csid_res->is_dual_vfe) {
- csid_acquire.sync_mode = CAM_ISP_HW_SYNC_SLAVE;
- csid_acquire.master_idx = csid_res->hw_res[0]->hw_intf->hw_idx;
+ if (in_port->usage_type)
+ csid_res->is_dual_vfe = 1;
+ else {
+ csid_res->is_dual_vfe = 0;
+ csid_acquire.sync_mode = CAM_ISP_HW_SYNC_MASTER;
+ }
- for (j = i + 1; j < CAM_IFE_CSID_HW_NUM_MAX; j++) {
- if (!ife_hw_mgr->csid_devices[j])
+ list_for_each_entry(cid_res, &ife_ctx->res_list_ife_cid,
+ list) {
+ if (cid_res->res_id != cid_res_id)
+ continue;
+
+ for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
+ if (!cid_res->hw_res[i])
continue;
- hw_intf = ife_hw_mgr->csid_devices[j];
+ csid_acquire.node_res = NULL;
+ if (csid_res->is_dual_vfe) {
+ if (i == CAM_ISP_HW_SPLIT_LEFT)
+ csid_acquire.sync_mode =
+ CAM_ISP_HW_SYNC_MASTER;
+ else
+ csid_acquire.sync_mode =
+ CAM_ISP_HW_SYNC_SLAVE;
+ }
+
+ hw_intf = ife_hw_mgr->csid_devices[
+ cid_res->hw_res[i]->hw_intf->hw_idx];
rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv,
&csid_acquire, sizeof(csid_acquire));
- if (rc)
- continue;
- else
- break;
+ if (rc) {
+ CAM_ERR(CAM_ISP,
+ "Cannot acquire ife csid ipp resource");
+ goto err;
+ }
+
+ csid_res->hw_res[i] = csid_acquire.node_res;
+ CAM_DBG(CAM_ISP,
+ "acquired csid(%s)=%d ipp rsrc successfully",
+ (i == 0) ? "left" : "right",
+ hw_intf->hw_idx);
+
}
- if (j == CAM_IFE_CSID_HW_NUM_MAX) {
+ if (i == CAM_IFE_CSID_HW_NUM_MAX) {
CAM_ERR(CAM_ISP,
- "Can not acquire ife csid rdi resrouce");
+ "Can not acquire ife csid ipp resource");
goto err;
}
- csid_res->hw_res[1] = csid_acquire.node_res;
- CAM_DBG(CAM_ISP,
- "acquired csid(%d)right ipp resrouce successfully", j);
-
+ csid_res->parent = cid_res;
+ cid_res->child[cid_res->num_children++] = csid_res;
}
- csid_res->parent = &ife_ctx->res_list_ife_in;
+
CAM_DBG(CAM_ISP, "acquire res %d", csid_acquire.res_id);
return 0;
@@ -909,7 +905,8 @@
struct cam_ife_hw_mgr *ife_hw_mgr;
struct cam_ife_hw_mgr_res *csid_res;
- struct cam_hw_intf *hw_intf;
+ struct cam_ife_hw_mgr_res *cid_res;
+ struct cam_hw_intf *hw_intf;
struct cam_isp_out_port_info *out_port;
struct cam_csid_hw_reserve_resource_args csid_acquire;
@@ -934,6 +931,7 @@
* between the csid rdi type and out port rdi type
*/
+ memset(&csid_acquire, 0, sizeof(csid_acquire));
csid_acquire.res_id =
cam_ife_hw_mgr_get_ife_csid_rdi_res_type(
out_port->res_type);
@@ -944,37 +942,58 @@
csid_acquire.out_port = out_port;
csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE;
- for (j = 0; j < CAM_IFE_CSID_HW_NUM_MAX; j++) {
- if (!ife_hw_mgr->csid_devices[j])
+ list_for_each_entry(cid_res, &ife_ctx->res_list_ife_cid,
+ list) {
+ if (cid_res->res_id != cid_res_id)
continue;
- hw_intf = ife_hw_mgr->csid_devices[j];
- rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv,
- &csid_acquire, sizeof(csid_acquire));
- if (rc)
- continue;
- else
+ for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) {
+ if (!cid_res->hw_res[j])
+ continue;
+
+ csid_acquire.node_res = NULL;
+
+ hw_intf = ife_hw_mgr->csid_devices[
+ cid_res->hw_res[j]->hw_intf->hw_idx];
+ rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv,
+ &csid_acquire, sizeof(csid_acquire));
+ if (rc) {
+ CAM_DBG(CAM_ISP,
+ "CSID Path reserve failed hw=%d rc=%d",
+ hw_intf->hw_idx, rc);
+ continue;
+ }
+
+ /* RDI does not need Dual ISP. Break */
break;
- }
+ }
- if (j == CAM_IFE_CSID_HW_NUM_MAX) {
- CAM_ERR(CAM_ISP,
- "Can not acquire ife csid rdi resource");
- goto err;
- }
+ if (j == CAM_ISP_HW_SPLIT_MAX &&
+ csid_acquire.node_res == NULL) {
+ CAM_ERR(CAM_ISP,
+ "acquire csid rdi rsrc failed, cid %d",
+ cid_res_id);
+ goto err;
+ }
- csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH;
- csid_res->res_id = csid_acquire.res_id;
- csid_res->is_dual_vfe = 0;
- csid_res->hw_res[0] = csid_acquire.node_res;
- csid_res->hw_res[1] = NULL;
- CAM_DBG(CAM_ISP, "acquire res %d", csid_acquire.res_id);
- csid_res->parent = &ife_ctx->res_list_ife_in;
+ csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH;
+ csid_res->res_id = csid_acquire.res_id;
+ csid_res->is_dual_vfe = 0;
+ csid_res->hw_res[0] = csid_acquire.node_res;
+ csid_res->hw_res[1] = NULL;
+ CAM_DBG(CAM_ISP, "acquire res %d",
+ csid_acquire.res_id);
+ csid_res->parent = cid_res;
+ cid_res->child[cid_res->num_children++] =
+ csid_res;
+
+ /* Done with cid_res_id. Break */
+ break;
+ }
}
return 0;
err:
- /* resource resources at entry funciton */
return rc;
}
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c
index dcbea8d..c6d5601 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c
@@ -613,7 +613,6 @@
i, j, need_th_processing[j]);
}
}
- read_unlock(&controller->rw_lock);
CAM_DBG(CAM_ISP, "unlocked controller %pK name %s rw_lock %pK",
controller, controller->name, &controller->rw_lock);
@@ -632,6 +631,7 @@
&controller->th_list_head[i]);
}
}
+ read_unlock(&controller->rw_lock);
return IRQ_HANDLED;
}
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
index 7d6e758..c5dd6ff 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
@@ -627,6 +627,12 @@
goto end;
}
+ if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_PHY_3 &&
+ csid_hw->hw_intf->hw_idx != 2) {
+ rc = -EINVAL;
+ goto end;
+ }
+
if (csid_hw->csi2_reserve_cnt) {
/* current configure res type should match requested res type */
if (csid_hw->res_type != cid_reserv->in_port->res_type) {
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c
index 77b830c..e4381d6 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c
@@ -507,8 +507,6 @@
core_info->vfe_top->top_priv, isp_res,
sizeof(struct cam_isp_resource_node));
} else if (isp_res->res_type == CAM_ISP_RESOURCE_VFE_OUT) {
- cam_irq_controller_unsubscribe_irq(
- core_info->vfe_irq_controller, isp_res->irq_handle);
rc = core_info->vfe_bus->hw_ops.stop(isp_res, NULL, 0);
} else {
CAM_ERR(CAM_ISP, "Invalid res type:%d", isp_res->res_type);
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/Makefile b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/Makefile
index 77e4eb3..39a5603 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/Makefile
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/Makefile
@@ -11,4 +11,4 @@
ccflags-y += -Idrivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus
ccflags-y += -Idrivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw
-obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe170.o
+obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe170.o cam_vfe_lite170.o
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe170.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe170.h
index e3a6f7b..5773bbe 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe170.h
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe170.h
@@ -222,11 +222,12 @@
.comp_error_status = 0x0000206C,
.comp_ovrwr_status = 0x00002070,
.dual_comp_error_status = 0x00002074,
- .dual_comp_error_status = 0x00002078,
+ .dual_comp_ovrwr_status = 0x00002078,
.addr_sync_cfg = 0x0000207C,
.addr_sync_frame_hdr = 0x00002080,
.addr_sync_no_sync = 0x00002084,
},
+ .num_client = 20,
.bus_client_reg = {
/* BUS Client 0 */
{
@@ -707,8 +708,24 @@
.addr_sync_mask = 0x0000209C,
},
},
+ .num_out = 18,
.vfe_out_hw_info = {
{
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
.vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_FULL,
.max_width = 4096,
.max_height = 4096,
@@ -739,21 +756,6 @@
.max_height = -1,
},
{
- .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
- .max_width = -1,
- .max_height = -1,
- },
- {
- .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
- .max_width = -1,
- .max_height = -1,
- },
- {
- .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
- .max_width = -1,
- .max_height = -1,
- },
- {
.vfe_out_type =
CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE,
.max_width = -1,
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.c
new file mode 100644
index 0000000..3c8abbf
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.c
@@ -0,0 +1,51 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include "cam_vfe_lite170.h"
+#include "cam_vfe_hw_intf.h"
+#include "cam_vfe_core.h"
+#include "cam_vfe_dev.h"
+
+static const struct of_device_id cam_vfe170_dt_match[] = {
+ {
+ .compatible = "qcom,vfe-lite170",
+ .data = &cam_vfe_lite170_hw_info,
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, cam_vfe170_dt_match);
+
+static struct platform_driver cam_vfe170_driver = {
+ .probe = cam_vfe_probe,
+ .remove = cam_vfe_remove,
+ .driver = {
+ .name = "cam_vfe_lite170",
+ .owner = THIS_MODULE,
+ .of_match_table = cam_vfe170_dt_match,
+ },
+};
+
+static int __init cam_vfe170_init_module(void)
+{
+ return platform_driver_register(&cam_vfe170_driver);
+}
+
+static void __exit cam_vfe170_exit_module(void)
+{
+ platform_driver_unregister(&cam_vfe170_driver);
+}
+
+module_init(cam_vfe170_init_module);
+module_exit(cam_vfe170_exit_module);
+MODULE_DESCRIPTION("CAM VFE170 driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.h
new file mode 100644
index 0000000..2f95feb
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe170/cam_vfe_lite170.h
@@ -0,0 +1,336 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CAM_VFE_LITE170_H_
+#define _CAM_VFE_LITE170_H_
+
+#include "cam_vfe_bus_ver2.h"
+#include "cam_irq_controller.h"
+#include "cam_vfe_top_ver2.h"
+#include "cam_vfe_core.h"
+
+static struct cam_irq_register_set vfe170_top_irq_reg_set[2] = {
+ {
+ .mask_reg_offset = 0x0000005C,
+ .clear_reg_offset = 0x00000064,
+ .status_reg_offset = 0x0000006C,
+ },
+ {
+ .mask_reg_offset = 0x00000060,
+ .clear_reg_offset = 0x00000068,
+ .status_reg_offset = 0x00000070,
+ },
+};
+
+static struct cam_irq_controller_reg_info vfe170_top_irq_reg_info = {
+ .num_registers = 2,
+ .irq_reg_set = vfe170_top_irq_reg_set,
+ .global_clear_offset = 0x00000058,
+ .global_clear_bitmask = 0x00000001,
+};
+
+static struct cam_vfe_top_ver2_reg_offset_common vfe170_top_common_reg = {
+ .hw_version = 0x00000000,
+ .hw_capability = 0x00000004,
+ .lens_feature = 0x00000008,
+ .stats_feature = 0x0000000C,
+ .color_feature = 0x00000010,
+ .zoom_feature = 0x00000014,
+ .global_reset_cmd = 0x00000018,
+ .module_ctrl = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ },
+ .bus_cgc_ovd = 0x0000003C,
+ .core_cfg = 0x00000000,
+ .three_D_cfg = 0x00000000,
+ .violation_status = 0x0000007C,
+ .reg_update_cmd = 0x000004AC,
+};
+
+static struct cam_vfe_rdi_ver2_reg vfe170_rdi_reg = {
+ .reg_update_cmd = 0x000004AC,
+};
+
+static struct cam_vfe_rdi_reg_data vfe170_rdi_0_data = {
+ .reg_update_cmd_data = 0x2,
+ .sof_irq_mask = 0x8000000,
+ .reg_update_irq_mask = 0x20,
+};
+
+static struct cam_vfe_rdi_reg_data vfe170_rdi_1_data = {
+ .reg_update_cmd_data = 0x4,
+ .sof_irq_mask = 0x10000000,
+ .reg_update_irq_mask = 0x40,
+};
+
+static struct cam_vfe_rdi_reg_data vfe170_rdi_2_data = {
+ .reg_update_cmd_data = 0x8,
+ .sof_irq_mask = 0x20000000,
+ .reg_update_irq_mask = 0x80,
+};
+
+static struct cam_vfe_rdi_reg_data vfe170_rdi_3_data = {
+ .reg_update_cmd_data = 0x10,
+ .sof_irq_mask = 0x40000000,
+ .reg_update_irq_mask = 0x100,
+};
+
+static struct cam_vfe_top_ver2_hw_info vfe170_top_hw_info = {
+ .common_reg = &vfe170_top_common_reg,
+ .camif_hw_info = {
+ .common_reg = NULL,
+ .camif_reg = NULL,
+ .reg_data = NULL,
+ },
+ .rdi_hw_info = {
+ .common_reg = &vfe170_top_common_reg,
+ .rdi_reg = &vfe170_rdi_reg,
+ .reg_data = {
+ &vfe170_rdi_0_data,
+ &vfe170_rdi_1_data,
+ &vfe170_rdi_2_data,
+ &vfe170_rdi_3_data,
+ },
+ },
+ .mux_type = {
+ CAM_VFE_RDI_VER_1_0,
+ CAM_VFE_RDI_VER_1_0,
+ CAM_VFE_RDI_VER_1_0,
+ CAM_VFE_RDI_VER_1_0,
+ },
+};
+
+static struct cam_irq_register_set vfe170_bus_irq_reg[3] = {
+ {
+ .mask_reg_offset = 0x00002044,
+ .clear_reg_offset = 0x00002050,
+ .status_reg_offset = 0x0000205C,
+ },
+ {
+ .mask_reg_offset = 0x00002048,
+ .clear_reg_offset = 0x00002054,
+ .status_reg_offset = 0x00002060,
+ },
+ {
+ .mask_reg_offset = 0x0000204C,
+ .clear_reg_offset = 0x00002058,
+ .status_reg_offset = 0x00002064,
+ },
+};
+
+static struct cam_vfe_bus_ver2_hw_info vfe170_bus_hw_info = {
+ .common_reg = {
+ .hw_version = 0x00002000,
+ .hw_capability = 0x00002004,
+ .sw_reset = 0x00002008,
+ .cgc_ovd = 0x0000200C,
+ .pwr_iso_cfg = 0x000020CC,
+ .dual_master_comp_cfg = 0x00002028,
+ .irq_reg_info = {
+ .num_registers = 3,
+ .irq_reg_set = vfe170_bus_irq_reg,
+ .global_clear_offset = 0x00002068,
+ .global_clear_bitmask = 0x00000001,
+ },
+ .comp_error_status = 0x0000206C,
+ .comp_ovrwr_status = 0x00002070,
+ .dual_comp_error_status = 0x00002074,
+ .dual_comp_ovrwr_status = 0x00002078,
+ .addr_sync_cfg = 0x0000207C,
+ .addr_sync_frame_hdr = 0x00002080,
+ .addr_sync_no_sync = 0x00002084,
+ },
+ .num_client = 4,
+ .bus_client_reg = {
+ /* BUS Client 0 */
+ {
+ .status0 = 0x00002200,
+ .status1 = 0x00002204,
+ .cfg = 0x00002208,
+ .header_addr = 0x0000220C,
+ .header_cfg = 0x00002210,
+ .image_addr = 0x00002214,
+ .image_addr_offset = 0x00002218,
+ .buffer_width_cfg = 0x0000221C,
+ .buffer_height_cfg = 0x00002220,
+ .packer_cfg = 0x00002224,
+ .stride = 0x00002228,
+ .irq_subsample_period = 0x00002248,
+ .irq_subsample_pattern = 0x0000224C,
+ .framedrop_period = 0x00002250,
+ .framedrop_pattern = 0x00002254,
+ .frame_inc = 0x00002258,
+ .burst_limit = 0x0000225C,
+ .ubwc_regs = NULL,
+ },
+ /* BUS Client 1 */
+ {
+ .status0 = 0x00002300,
+ .status1 = 0x00002304,
+ .cfg = 0x00002308,
+ .header_addr = 0x0000230C,
+ .header_cfg = 0x00002310,
+ .image_addr = 0x00002314,
+ .image_addr_offset = 0x00002318,
+ .buffer_width_cfg = 0x0000231C,
+ .buffer_height_cfg = 0x00002320,
+ .packer_cfg = 0x00002324,
+ .stride = 0x00002328,
+ .irq_subsample_period = 0x00002348,
+ .irq_subsample_pattern = 0x0000234C,
+ .framedrop_period = 0x00002350,
+ .framedrop_pattern = 0x00002354,
+ .frame_inc = 0x00002358,
+ .burst_limit = 0x0000235C,
+ .ubwc_regs = NULL,
+ },
+ /* BUS Client 2 */
+ {
+ .status0 = 0x00002400,
+ .status1 = 0x00002404,
+ .cfg = 0x00002408,
+ .header_addr = 0x0000240C,
+ .header_cfg = 0x00002410,
+ .image_addr = 0x00002414,
+ .image_addr_offset = 0x00002418,
+ .buffer_width_cfg = 0x0000241C,
+ .buffer_height_cfg = 0x00002420,
+ .packer_cfg = 0x00002424,
+ .stride = 0x00002428,
+ .irq_subsample_period = 0x00002448,
+ .irq_subsample_pattern = 0x0000244C,
+ .framedrop_period = 0x00002450,
+ .framedrop_pattern = 0x00002454,
+ .frame_inc = 0x00002458,
+ .burst_limit = 0x0000245C,
+ .ubwc_regs = NULL,
+ },
+ /* BUS Client 3 */
+ {
+ .status0 = 0x00002500,
+ .status1 = 0x00002504,
+ .cfg = 0x00002508,
+ .header_addr = 0x0000250C,
+ .header_cfg = 0x00002510,
+ .image_addr = 0x00002514,
+ .image_addr_offset = 0x00002518,
+ .buffer_width_cfg = 0x0000251C,
+ .buffer_height_cfg = 0x00002520,
+ .packer_cfg = 0x00002524,
+ .stride = 0x00002528,
+ .irq_subsample_period = 0x00002548,
+ .irq_subsample_pattern = 0x0000254C,
+ .framedrop_period = 0x00002550,
+ .framedrop_pattern = 0x00002554,
+ .frame_inc = 0x00002558,
+ .burst_limit = 0x0000255C,
+ .ubwc_regs = NULL,
+ },
+ },
+ .comp_grp_reg = {
+ /* CAM_VFE_BUS_VER2_COMP_GRP_0 */
+ {
+ .comp_mask = 0x00002010,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_1 */
+ {
+ .comp_mask = 0x00002014,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_2 */
+ {
+ .comp_mask = 0x00002018,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_3 */
+ {
+ .comp_mask = 0x0000201C,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_4 */
+ {
+ .comp_mask = 0x00002020,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_5 */
+ {
+ .comp_mask = 0x00002024,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_0 */
+ {
+ .comp_mask = 0x0000202C,
+ .addr_sync_mask = 0x00002088,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_1 */
+ {
+ .comp_mask = 0x00002030,
+ .addr_sync_mask = 0x0000208C,
+
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_2 */
+ {
+ .comp_mask = 0x00002034,
+ .addr_sync_mask = 0x00002090,
+
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_3 */
+ {
+ .comp_mask = 0x00002038,
+ .addr_sync_mask = 0x00002094,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_4 */
+ {
+ .comp_mask = 0x0000203C,
+ .addr_sync_mask = 0x00002098,
+ },
+ /* CAM_VFE_BUS_VER2_COMP_GRP_DUAL_5 */
+ {
+ .comp_mask = 0x00002040,
+ .addr_sync_mask = 0x0000209C,
+ },
+ },
+ .num_out = 4,
+ .vfe_out_hw_info = {
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ {
+ .vfe_out_type = CAM_VFE_BUS_VER2_VFE_OUT_RDI3,
+ .max_width = -1,
+ .max_height = -1,
+ },
+ },
+};
+
+static struct cam_vfe_hw_info cam_vfe_lite170_hw_info = {
+ .irq_reg_info = &vfe170_top_irq_reg_info,
+
+ .bus_version = CAM_VFE_BUS_VER_2_0,
+ .bus_hw_info = &vfe170_bus_hw_info,
+
+ .top_version = CAM_VFE_TOP_VER_2_0,
+ .top_hw_info = &vfe170_top_hw_info,
+
+};
+
+#endif /* _CAM_VFE_LITE170_H_ */
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c
index 005d7e0..cb5c0a7 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c
@@ -184,6 +184,8 @@
struct cam_vfe_bus_ver2_priv {
struct cam_vfe_bus_ver2_common_data common_data;
+ uint32_t num_client;
+ uint32_t num_out;
struct cam_isp_resource_node bus_client[CAM_VFE_BUS_VER2_MAX_CLIENTS];
struct cam_isp_resource_node comp_grp[CAM_VFE_BUS_VER2_COMP_GRP_MAX];
@@ -394,6 +396,8 @@
return CAM_VFE_BUS_VER2_VFE_OUT_RDI1;
case CAM_ISP_IFE_OUT_RES_RDI_2:
return CAM_VFE_BUS_VER2_VFE_OUT_RDI2;
+ case CAM_ISP_IFE_OUT_RES_RDI_3:
+ return CAM_VFE_BUS_VER2_VFE_OUT_RDI3;
case CAM_ISP_IFE_OUT_RES_STATS_HDR_BE:
return CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE;
case CAM_ISP_IFE_OUT_RES_STATS_HDR_BHIST:
@@ -425,6 +429,7 @@
case CAM_VFE_BUS_VER2_VFE_OUT_RDI0:
case CAM_VFE_BUS_VER2_VFE_OUT_RDI1:
case CAM_VFE_BUS_VER2_VFE_OUT_RDI2:
+ case CAM_VFE_BUS_VER2_VFE_OUT_RDI3:
switch (format) {
case CAM_FORMAT_MIPI_RAW_8:
case CAM_FORMAT_MIPI_RAW_10:
@@ -551,6 +556,42 @@
int wm_idx = -1;
switch (vfe_out_res_id) {
+ case CAM_VFE_BUS_VER2_VFE_OUT_RDI0:
+ switch (plane) {
+ case PLANE_Y:
+ wm_idx = 0;
+ break;
+ default:
+ break;
+ }
+ break;
+ case CAM_VFE_BUS_VER2_VFE_OUT_RDI1:
+ switch (plane) {
+ case PLANE_Y:
+ wm_idx = 1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case CAM_VFE_BUS_VER2_VFE_OUT_RDI2:
+ switch (plane) {
+ case PLANE_Y:
+ wm_idx = 2;
+ break;
+ default:
+ break;
+ }
+ break;
+ case CAM_VFE_BUS_VER2_VFE_OUT_RDI3:
+ switch (plane) {
+ case PLANE_Y:
+ wm_idx = 3;
+ break;
+ default:
+ break;
+ }
+ break;
case CAM_VFE_BUS_VER2_VFE_OUT_FULL:
switch (plane) {
case PLANE_Y:
@@ -611,33 +652,6 @@
break;
}
break;
- case CAM_VFE_BUS_VER2_VFE_OUT_RDI0:
- switch (plane) {
- case PLANE_Y:
- wm_idx = 0;
- break;
- default:
- break;
- }
- break;
- case CAM_VFE_BUS_VER2_VFE_OUT_RDI1:
- switch (plane) {
- case PLANE_Y:
- wm_idx = 1;
- break;
- default:
- break;
- }
- break;
- case CAM_VFE_BUS_VER2_VFE_OUT_RDI2:
- switch (plane) {
- case PLANE_Y:
- wm_idx = 2;
- break;
- default:
- break;
- }
- break;
case CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE:
switch (plane) {
case PLANE_Y:
@@ -792,7 +806,7 @@
/* No need to allocate for BUS VER2. VFE OUT to WM is fixed. */
wm_idx = cam_vfe_bus_get_wm_idx(vfe_out_res_id, plane);
- if (wm_idx < 0 || wm_idx >= CAM_VFE_BUS_VER2_MAX_CLIENTS) {
+ if (wm_idx < 0 || wm_idx >= ver2_bus_priv->num_client) {
CAM_ERR(CAM_ISP, "Unsupported VFE out %d plane %d",
vfe_out_res_id, plane);
return -EINVAL;
@@ -2168,7 +2182,8 @@
vfe_out->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE;
INIT_LIST_HEAD(&vfe_out->list);
- rsrc_data->out_type = index;
+ rsrc_data->out_type =
+ ver2_hw_info->vfe_out_hw_info[index].vfe_out_type;
rsrc_data->common_data = &ver2_bus_priv->common_data;
rsrc_data->max_width =
ver2_hw_info->vfe_out_hw_info[index].max_width;
@@ -2783,6 +2798,8 @@
}
vfe_bus_local->bus_priv = bus_priv;
+ bus_priv->num_client = ver2_hw_info->num_client;
+ bus_priv->num_out = ver2_hw_info->num_out;
bus_priv->common_data.num_sec_out = 0;
bus_priv->common_data.secure_mode = CAM_SECURE_MODE_NON_SECURE;
bus_priv->common_data.core_index = soc_info->index;
@@ -2808,7 +2825,7 @@
INIT_LIST_HEAD(&bus_priv->free_dual_comp_grp);
INIT_LIST_HEAD(&bus_priv->used_comp_grp);
- for (i = 0; i < CAM_VFE_BUS_VER2_MAX_CLIENTS; i++) {
+ for (i = 0; i < bus_priv->num_client; i++) {
rc = cam_vfe_bus_init_wm_resource(i, bus_priv, bus_hw_info,
&bus_priv->bus_client[i]);
if (rc < 0) {
@@ -2826,7 +2843,7 @@
}
}
- for (i = 0; i < CAM_VFE_BUS_VER2_VFE_OUT_MAX; i++) {
+ for (i = 0; i < bus_priv->num_out; i++) {
rc = cam_vfe_bus_init_vfe_out_resource(i, bus_priv, bus_hw_info,
&bus_priv->vfe_out[i]);
if (rc < 0) {
@@ -2859,7 +2876,7 @@
deinit_vfe_out:
if (i < 0)
- i = CAM_VFE_BUS_VER2_VFE_OUT_MAX;
+ i = bus_priv->num_out;
for (--i; i >= 0; i--)
cam_vfe_bus_deinit_vfe_out_resource(&bus_priv->vfe_out[i]);
@@ -2871,7 +2888,7 @@
deinit_wm:
if (i < 0)
- i = CAM_VFE_BUS_VER2_MAX_CLIENTS;
+ i = bus_priv->num_client;
for (--i; i >= 0; i--)
cam_vfe_bus_deinit_wm_resource(&bus_priv->bus_client[i]);
@@ -2909,7 +2926,7 @@
for (i = 0; i < CAM_VFE_BUS_VER2_PAYLOAD_MAX; i++)
INIT_LIST_HEAD(&bus_priv->common_data.evt_payload[i].list);
- for (i = 0; i < CAM_VFE_BUS_VER2_MAX_CLIENTS; i++) {
+ for (i = 0; i < bus_priv->num_client; i++) {
rc = cam_vfe_bus_deinit_wm_resource(&bus_priv->bus_client[i]);
if (rc < 0)
CAM_ERR(CAM_ISP,
@@ -2923,7 +2940,7 @@
"Deinit Comp Grp failed rc=%d", rc);
}
- for (i = 0; i < CAM_VFE_BUS_VER2_VFE_OUT_MAX; i++) {
+ for (i = 0; i < bus_priv->num_out; i++) {
rc = cam_vfe_bus_deinit_vfe_out_resource(&bus_priv->vfe_out[i]);
if (rc < 0)
CAM_ERR(CAM_ISP,
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h
index c90d4ce..8b55309 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.h
@@ -42,15 +42,16 @@
};
enum cam_vfe_bus_ver2_vfe_out_type {
+ CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
+ CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
+ CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
+ CAM_VFE_BUS_VER2_VFE_OUT_RDI3,
CAM_VFE_BUS_VER2_VFE_OUT_FULL,
CAM_VFE_BUS_VER2_VFE_OUT_DS4,
CAM_VFE_BUS_VER2_VFE_OUT_DS16,
CAM_VFE_BUS_VER2_VFE_OUT_RAW_DUMP,
CAM_VFE_BUS_VER2_VFE_OUT_FD,
CAM_VFE_BUS_VER2_VFE_OUT_PDAF,
- CAM_VFE_BUS_VER2_VFE_OUT_RDI0,
- CAM_VFE_BUS_VER2_VFE_OUT_RDI1,
- CAM_VFE_BUS_VER2_VFE_OUT_RDI2,
CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BE,
CAM_VFE_BUS_VER2_VFE_OUT_STATS_HDR_BHIST,
CAM_VFE_BUS_VER2_VFE_OUT_STATS_TL_BG,
@@ -160,11 +161,13 @@
* @vfe_out_hw_info: VFE output capability
*/
struct cam_vfe_bus_ver2_hw_info {
- struct cam_vfe_bus_ver2_reg_offset_common common_reg;
+ struct cam_vfe_bus_ver2_reg_offset_common common_reg;
+ uint32_t num_client;
struct cam_vfe_bus_ver2_reg_offset_bus_client
bus_client_reg[CAM_VFE_BUS_VER2_MAX_CLIENTS];
struct cam_vfe_bus_ver2_reg_offset_comp_grp
comp_grp_reg[CAM_VFE_BUS_VER2_COMP_GRP_MAX];
+ uint32_t num_out;
struct cam_vfe_bus_ver2_vfe_out_hw_info
vfe_out_hw_info[CAM_VFE_BUS_VER2_VFE_OUT_MAX];
};
diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h
index c089911..0763bca 100644
--- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h
+++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include/cam_vfe_bus.h
@@ -17,8 +17,8 @@
#include "cam_hw_intf.h"
#include "cam_isp_hw.h"
-#define CAM_VFE_BUS_VER_1_0 0x1000
-#define CAM_VFE_BUS_VER_2_0 0x2000
+#define CAM_VFE_BUS_VER_1_0 0x1000
+#define CAM_VFE_BUS_VER_2_0 0x2000
enum cam_vfe_bus_plane_type {
PLANE_Y,
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c
index 2cd6b04..35c2717 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c
@@ -28,8 +28,6 @@
#include "cam_hw_mgr_intf.h"
#include "cam_jpeg_hw_mgr_intf.h"
#include "cam_jpeg_hw_mgr.h"
-#include "cam_enc_hw_intf.h"
-#include "cam_dma_hw_intf.h"
#include "cam_smmu_api.h"
#include "cam_mem_mgr.h"
#include "cam_req_mgr_workq.h"
@@ -38,6 +36,9 @@
#include "cam_debug_util.h"
#define CAM_JPEG_HW_ENTRIES_MAX 20
+#define CAM_JPEG_CHBASE 0
+#define CAM_JPEG_CFG 1
+#define CAM_JPEG_PARAM 2
static struct cam_jpeg_hw_mgr g_jpeg_hw_mgr;
@@ -88,13 +89,20 @@
}
rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd(
hw_mgr->devices[dev_type][0]->hw_priv,
- CAM_JPEG_ENC_CMD_SET_IRQ_CB,
+ CAM_JPEG_CMD_SET_IRQ_CB,
&irq_cb, sizeof(irq_cb));
if (rc) {
CAM_ERR(CAM_JPEG, "CMD_SET_IRQ_CB failed %d", rc);
return rc;
}
+ if (hw_mgr->devices[dev_type][0]->hw_ops.deinit) {
+ rc = hw_mgr->devices[dev_type][0]->hw_ops.deinit(
+ hw_mgr->devices[dev_type][0]->hw_priv, NULL, 0);
+ if (rc)
+ CAM_ERR(CAM_JPEG, "Failed to Deinit %d HW", dev_type);
+ }
+
mutex_lock(&g_jpeg_hw_mgr.hw_mgr_mutex);
hw_mgr->device_in_use[dev_type][0] = false;
p_cfg_req = hw_mgr->dev_hw_cfg_args[dev_type][0];
@@ -126,7 +134,8 @@
}
rc = cam_mem_get_cpu_buf(
- p_cfg_req->hw_cfg_args.hw_update_entries[1].handle,
+ p_cfg_req->hw_cfg_args.
+ hw_update_entries[CAM_JPEG_PARAM].handle,
(uint64_t *)&kaddr, &cmd_buf_len);
if (rc) {
CAM_ERR(CAM_JPEG, "unable to get info for cmd buf: %x %d",
@@ -137,8 +146,8 @@
cmd_buf_kaddr = (uint32_t *)kaddr;
cmd_buf_kaddr =
- (cmd_buf_kaddr +
- (p_cfg_req->hw_cfg_args.hw_update_entries[1].offset/4));
+ (cmd_buf_kaddr + (p_cfg_req->hw_cfg_args.
+ hw_update_entries[CAM_JPEG_PARAM].offset / sizeof(uint32_t)));
p_params = (struct cam_jpeg_config_inout_param_info *)cmd_buf_kaddr;
@@ -234,6 +243,59 @@
return 0;
}
+static int cam_jpeg_insert_cdm_change_base(
+ struct cam_hw_config_args *config_args,
+ struct cam_jpeg_hw_ctx_data *ctx_data,
+ struct cam_jpeg_hw_mgr *hw_mgr)
+{
+ int rc;
+ uint32_t dev_type;
+ struct cam_cdm_bl_request *cdm_cmd;
+ uint32_t size;
+ uint32_t mem_cam_base;
+ uint64_t iova_addr;
+ uint32_t *ch_base_iova_addr;
+ size_t ch_base_len;
+
+ rc = cam_mem_get_cpu_buf(config_args->
+ hw_update_entries[CAM_JPEG_CHBASE].handle,
+ &iova_addr, &ch_base_len);
+ if (rc) {
+ CAM_ERR(CAM_JPEG,
+ "unable to get src buf info for cmd buf: %d", rc);
+ return rc;
+ }
+ CAM_DBG(CAM_JPEG, "iova %pK len %zu offset %d",
+ (void *)iova_addr, ch_base_len,
+ config_args->hw_update_entries[CAM_JPEG_CHBASE].offset);
+ ch_base_iova_addr = (uint32_t *)iova_addr;
+ ch_base_iova_addr = (ch_base_iova_addr +
+ (config_args->hw_update_entries[CAM_JPEG_CHBASE].offset /
+ sizeof(uint32_t)));
+
+ dev_type = ctx_data->jpeg_dev_acquire_info.dev_type;
+ mem_cam_base = hw_mgr->cdm_reg_map[dev_type][0]->mem_cam_base;
+ size = hw_mgr->cdm_info[dev_type][0].cdm_ops->
+ cdm_required_size_changebase();
+ hw_mgr->cdm_info[dev_type][0].cdm_ops->
+ cdm_write_changebase(ch_base_iova_addr, mem_cam_base);
+
+ cdm_cmd = ctx_data->cdm_cmd;
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].bl_addr.mem_handle =
+ config_args->hw_update_entries[CAM_JPEG_CHBASE].handle;
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].offset =
+ config_args->hw_update_entries[CAM_JPEG_CHBASE].offset;
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].len = size * sizeof(uint32_t);
+ cdm_cmd->cmd_arrary_count++;
+
+ ch_base_iova_addr += size;
+ *ch_base_iova_addr = 0;
+ ch_base_iova_addr += size;
+ *ch_base_iova_addr = 0;
+
+ return rc;
+}
+
static int cam_jpeg_mgr_process_cmd(void *priv, void *data)
{
int rc;
@@ -249,11 +311,10 @@
uint32_t dev_type;
struct cam_jpeg_set_irq_cb irq_cb;
struct cam_jpeg_hw_cfg_req *p_cfg_req = NULL;
+ struct cam_hw_done_event_data buf_data;
uint32_t size = 0;
uint32_t mem_cam_base = 0;
- struct cam_hw_done_event_data buf_data;
- CAM_DBG(CAM_JPEG, "in cam_jpeg_mgr_process_cmd");
if (!hw_mgr || !task_data) {
CAM_ERR(CAM_JPEG, "Invalid arguments %pK %pK",
hw_mgr, task_data);
@@ -296,7 +357,8 @@
if (!config_args->num_hw_update_entries) {
CAM_ERR(CAM_JPEG, "No hw update enteries are available");
- return -EINVAL;
+ rc = -EINVAL;
+ goto end_unusedev;
}
mutex_lock(&hw_mgr->hw_mgr_mutex);
@@ -304,7 +366,8 @@
if (!ctx_data->in_use) {
CAM_ERR(CAM_JPEG, "ctx is not in use");
mutex_unlock(&hw_mgr->hw_mgr_mutex);
- return -EINVAL;
+ rc = -EINVAL;
+ goto end_unusedev;
}
mutex_unlock(&hw_mgr->hw_mgr_mutex);
@@ -313,99 +376,123 @@
if (dev_type != p_cfg_req->dev_type)
CAM_WARN(CAM_JPEG, "dev types not same something wrong");
+ if (!hw_mgr->devices[dev_type][0]->hw_ops.init) {
+ CAM_ERR(CAM_JPEG, "hw op init null ");
+ rc = -EFAULT;
+ goto end;
+ }
+ rc = hw_mgr->devices[dev_type][0]->hw_ops.init(
+ hw_mgr->devices[dev_type][0]->hw_priv,
+ ctx_data,
+ sizeof(ctx_data));
+ if (rc) {
+ CAM_ERR(CAM_JPEG, "Failed to Init %d HW", dev_type);
+ goto end;
+ }
+
irq_cb.jpeg_hw_mgr_cb = cam_jpeg_hw_mgr_cb;
irq_cb.data = (void *)ctx_data;
irq_cb.b_set_cb = true;
if (!hw_mgr->devices[dev_type][0]->hw_ops.process_cmd) {
CAM_ERR(CAM_JPEG, "op process_cmd null ");
- return -EINVAL;
+ rc = -EFAULT;
+ goto end_callcb;
}
rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd(
hw_mgr->devices[dev_type][0]->hw_priv,
- CAM_JPEG_ENC_CMD_SET_IRQ_CB,
+ CAM_JPEG_CMD_SET_IRQ_CB,
&irq_cb, sizeof(irq_cb));
if (rc) {
CAM_ERR(CAM_JPEG, "SET_IRQ_CB failed %d", rc);
- return -EINVAL;
+ goto end_callcb;
}
if (!hw_mgr->devices[dev_type][0]->hw_ops.reset) {
CAM_ERR(CAM_JPEG, "op reset null ");
- return -EINVAL;
+ rc = -EFAULT;
+ goto end_callcb;
}
rc = hw_mgr->devices[dev_type][0]->hw_ops.reset(
hw_mgr->devices[dev_type][0]->hw_priv,
NULL, 0);
if (rc) {
CAM_ERR(CAM_JPEG, "jpeg hw reset failed %d", rc);
- return -EINVAL;
+ goto end_callcb;
}
- mem_cam_base = (uint64_t)hw_mgr->cdm_reg_map[dev_type][0]->
- mem_cam_base;
- size = hw_mgr->cdm_info[dev_type][0].cdm_ops->
- cdm_required_size_changebase();
- hw_mgr->cdm_info[dev_type][0].cdm_ops->
- cdm_write_changebase(ctx_data->cmd_chbase_buf_addr,
- (uint64_t)hw_mgr->cdm_reg_map[dev_type][0]->mem_cam_base);
- ctx_data->cdm_cmd_chbase->cmd_arrary_count = 1;
- ctx_data->cdm_cmd_chbase->type = CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA;
- ctx_data->cdm_cmd_chbase->flag = false;
- ctx_data->cdm_cmd_chbase->userdata = NULL;
- ctx_data->cdm_cmd_chbase->cookie = 0;
- ctx_data->cdm_cmd_chbase->cmd[0].bl_addr.kernel_iova =
- ctx_data->cmd_chbase_buf_addr;
- ctx_data->cdm_cmd_chbase->cmd[0].offset = 0;
- ctx_data->cdm_cmd_chbase->cmd[0].len = size;
- rc = cam_cdm_submit_bls(hw_mgr->cdm_info[dev_type][0].cdm_handle,
- ctx_data->cdm_cmd_chbase);
- if (rc)
- CAM_ERR(CAM_JPEG, "failed cdm cmd %d", rc);
+ cdm_cmd = ctx_data->cdm_cmd;
+ cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE;
+ cdm_cmd->flag = false;
+ cdm_cmd->userdata = NULL;
+ cdm_cmd->cookie = 0;
+ cdm_cmd->cmd_arrary_count = 0;
- CAM_DBG(CAM_JPEG, "cfg e %pK num %d",
- config_args->hw_update_entries,
- config_args->num_hw_update_entries);
-
- if (config_args->num_hw_update_entries > 0) {
- cdm_cmd = ctx_data->cdm_cmd;
- cdm_cmd->cmd_arrary_count =
- config_args->num_hw_update_entries - 1;
- cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE;
- cdm_cmd->flag = false;
- cdm_cmd->userdata = NULL;
- cdm_cmd->cookie = 0;
-
- for (i = 0; i <= cdm_cmd->cmd_arrary_count; i++) {
- cmd = (config_args->hw_update_entries + i);
- cdm_cmd->cmd[i].bl_addr.mem_handle = cmd->handle;
- cdm_cmd->cmd[i].offset = cmd->offset;
- cdm_cmd->cmd[i].len = cmd->len;
- }
-
- rc = cam_cdm_submit_bls(
- hw_mgr->cdm_info[dev_type][0].cdm_handle,
- cdm_cmd);
+ /* if for backward compat */
+ if (config_args->hw_update_entries[CAM_JPEG_CHBASE].handle) {
+ rc = cam_jpeg_insert_cdm_change_base(config_args,
+ ctx_data, hw_mgr);
if (rc) {
- CAM_ERR(CAM_JPEG, "Failed to apply the configs %d",
- rc);
- goto end_callcb;
- }
-
- if (!hw_mgr->devices[dev_type][0]->hw_ops.start) {
- CAM_ERR(CAM_JPEG, "op start null ");
- rc = -EINVAL;
- goto end_callcb;
- }
- rc = hw_mgr->devices[dev_type][0]->hw_ops.start(
- hw_mgr->devices[dev_type][0]->hw_priv,
- NULL, 0);
- if (rc) {
- CAM_ERR(CAM_JPEG, "Failed to apply the configs %d",
- rc);
+ CAM_ERR(CAM_JPEG, "insert change base failed %d", rc);
goto end_callcb;
}
} else {
- CAM_ERR(CAM_JPEG, "No commands to config");
+ mem_cam_base = hw_mgr->cdm_reg_map[dev_type][0]->
+ mem_cam_base;
+ size = hw_mgr->cdm_info[dev_type][0].cdm_ops->
+ cdm_required_size_changebase();
+ hw_mgr->cdm_info[dev_type][0].cdm_ops->
+ cdm_write_changebase(ctx_data->cmd_chbase_buf_addr,
+ hw_mgr->cdm_reg_map[dev_type][0]->mem_cam_base);
+ ctx_data->cdm_cmd_chbase->cmd_arrary_count = 1;
+ ctx_data->cdm_cmd_chbase->type =
+ CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA;
+ ctx_data->cdm_cmd_chbase->flag = false;
+ ctx_data->cdm_cmd_chbase->userdata = NULL;
+ ctx_data->cdm_cmd_chbase->cookie = 0;
+ ctx_data->cdm_cmd_chbase->cmd[0].bl_addr.kernel_iova =
+ ctx_data->cmd_chbase_buf_addr;
+ ctx_data->cdm_cmd_chbase->cmd[0].offset = 0;
+ ctx_data->cdm_cmd_chbase->cmd[0].len = size;
+ cam_cdm_submit_bls(hw_mgr->cdm_info[dev_type][0].
+ cdm_handle,
+ ctx_data->cdm_cmd_chbase);
+ }
+
+ CAM_DBG(CAM_JPEG, "num hw up %d", config_args->num_hw_update_entries);
+ for (i = CAM_JPEG_CFG; i < (config_args->num_hw_update_entries - 1);
+ i++) {
+ cmd = (config_args->hw_update_entries + i);
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].
+ bl_addr.mem_handle = cmd->handle;
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].offset =
+ cmd->offset;
+ cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].len =
+ cmd->len;
+ CAM_DBG(CAM_JPEG, "i %d entry h %d o %d l %d",
+ i, cmd->handle, cmd->offset, cmd->len);
+ cdm_cmd->cmd_arrary_count++;
+ }
+
+ rc = cam_cdm_submit_bls(
+ hw_mgr->cdm_info[dev_type][0].cdm_handle,
+ cdm_cmd);
+ if (rc) {
+ CAM_ERR(CAM_JPEG, "Failed to apply the configs %d", rc);
+ goto end_callcb;
+ }
+
+ if (!hw_mgr->devices[dev_type][0]->hw_ops.start) {
+ CAM_ERR(CAM_JPEG, "op start null ");
+ rc = -EINVAL;
+ goto end_callcb;
+ }
+ rc = hw_mgr->devices[dev_type][0]->hw_ops.start(
+ hw_mgr->devices[dev_type][0]->hw_priv,
+ NULL, 0);
+ if (rc) {
+ CAM_ERR(CAM_JPEG, "Failed to apply the configs %d",
+ rc);
+ goto end_callcb;
}
return rc;
@@ -423,6 +510,12 @@
(uint64_t)p_cfg_req->hw_cfg_args.priv;
ctx_data->ctxt_event_cb(ctx_data->context_priv, 0, &buf_data);
}
+end_unusedev:
+ mutex_lock(&hw_mgr->hw_mgr_mutex);
+ hw_mgr->device_in_use[p_cfg_req->dev_type][0] = false;
+ hw_mgr->dev_hw_cfg_args[p_cfg_req->dev_type][0] = NULL;
+ mutex_unlock(&hw_mgr->hw_mgr_mutex);
+
end:
return rc;
@@ -535,6 +628,7 @@
struct cam_packet *packet = NULL;
struct cam_cmd_buf_desc *cmd_desc = NULL;
struct cam_buf_io_cfg *io_cfg_ptr = NULL;
+ struct cam_kmd_buf_info kmd_buf;
if (!prepare_args || !hw_mgr) {
CAM_ERR(CAM_JPEG, "Invalid args %pK %pK",
@@ -564,7 +658,17 @@
packet->header.op_code & 0xff);
return -EINVAL;
}
- if ((packet->num_cmd_buf > 2) || !packet->num_patches ||
+
+ /* if for backward compat */
+ if (packet->kmd_cmd_buf_index != -1) {
+ rc = cam_packet_util_validate_packet(packet);
+ if (rc) {
+ CAM_ERR(CAM_JPEG, "invalid packet %d", rc);
+ return rc;
+ }
+ }
+
+ if ((packet->num_cmd_buf > 5) || !packet->num_patches ||
!packet->num_io_configs) {
CAM_ERR(CAM_JPEG, "wrong number of cmd/patch info: %u %u",
packet->num_cmd_buf,
@@ -611,16 +715,35 @@
i, io_cfg_ptr[i].direction, io_cfg_ptr[i].fence);
}
- for (i = 0; i < packet->num_cmd_buf; i++) {
- prepare_args->hw_update_entries[i].len =
- (uint32_t)cmd_desc[i].length;
- prepare_args->hw_update_entries[i].handle =
- (uint32_t)cmd_desc[i].mem_handle;
- prepare_args->hw_update_entries[i].offset =
- (uint32_t)cmd_desc[i].offset;
- prepare_args->num_hw_update_entries++;
+ j = prepare_args->num_hw_update_entries;
+ /* if-else for backward compat */
+ if (packet->kmd_cmd_buf_index != -1) {
+ rc = cam_packet_util_get_kmd_buffer(packet, &kmd_buf);
+ if (rc) {
+ CAM_ERR(CAM_JPEG, "get kmd buf failed %d", rc);
+ return rc;
+ }
+ } else {
+ memset(&kmd_buf, 0x0, sizeof(kmd_buf));
}
+ /* fill kmd buf info into 1st hw update entry */
+ prepare_args->hw_update_entries[j].len =
+ (uint32_t)kmd_buf.used_bytes;
+ prepare_args->hw_update_entries[j].handle =
+ (uint32_t)kmd_buf.handle;
+ prepare_args->hw_update_entries[j].offset =
+ (uint32_t)kmd_buf.offset;
+ j++;
+ for (i = 0; i < packet->num_cmd_buf; i++, j++) {
+ prepare_args->hw_update_entries[j].len =
+ (uint32_t)cmd_desc[i].length;
+ prepare_args->hw_update_entries[j].handle =
+ (uint32_t)cmd_desc[i].mem_handle;
+ prepare_args->hw_update_entries[j].offset =
+ (uint32_t)cmd_desc[i].offset;
+ }
+ prepare_args->num_hw_update_entries = j;
prepare_args->priv = (void *)packet->header.request_id;
CAM_DBG(CAM_JPEG, "will wait on input sync sync_id %d",
@@ -651,6 +774,11 @@
dev_type = ctx_data->jpeg_dev_acquire_info.dev_type;
mutex_lock(&hw_mgr->hw_mgr_mutex);
+ if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 0) {
+ mutex_unlock(&hw_mgr->hw_mgr_mutex);
+ CAM_ERR(CAM_JPEG, "Error Unbalanced deinit");
+ return -EFAULT;
+ }
hw_mgr->cdm_info[dev_type][0].ref_cnt--;
if (!(hw_mgr->cdm_info[dev_type][0].ref_cnt)) {
@@ -663,12 +791,6 @@
cam_cdm_release(hw_mgr->cdm_info[dev_type][0].cdm_handle);
}
- if (g_jpeg_hw_mgr.devices[dev_type][0]->hw_ops.deinit) {
- rc = g_jpeg_hw_mgr.devices[dev_type][0]->hw_ops.deinit(
- g_jpeg_hw_mgr.devices[dev_type][0]->hw_priv, NULL, 0);
- if (rc)
- CAM_ERR(CAM_JPEG, "Failed to Init %d HW", dev_type);
- }
mutex_unlock(&hw_mgr->hw_mgr_mutex);
rc = cam_jpeg_mgr_release_ctx(hw_mgr, ctx_data);
@@ -787,20 +909,6 @@
goto start_cdm_hdl_failed;
}
- if (!g_jpeg_hw_mgr.devices[dev_type][0]->hw_ops.init) {
- CAM_ERR(CAM_JPEG, "hw op init null ");
- rc = -EINVAL;
- goto start_cdm_hdl_failed;
- }
- rc = g_jpeg_hw_mgr.devices[dev_type][0]->hw_ops.init(
- g_jpeg_hw_mgr.devices[dev_type][0]->hw_priv,
- ctx_data,
- sizeof(ctx_data));
- if (rc) {
- CAM_ERR(CAM_JPEG, "Failed to Init %d HW", dev_type);
- goto start_cdm_hdl_failed;
- }
-
if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 1)
if (cam_cdm_stream_on(
hw_mgr->cdm_info[dev_type][0].cdm_handle)) {
@@ -833,9 +941,12 @@
return rc;
copy_to_user_failed:
- cam_cdm_stream_off(hw_mgr->cdm_info[dev_type][0].cdm_handle);
+ if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 1)
+ cam_cdm_stream_off(hw_mgr->cdm_info[dev_type][0].cdm_handle);
start_cdm_hdl_failed:
- cam_cdm_release(hw_mgr->cdm_info[dev_type][0].cdm_handle);
+ if (hw_mgr->cdm_info[dev_type][0].ref_cnt == 1)
+ cam_cdm_release(hw_mgr->cdm_info[dev_type][0].cdm_handle);
+ hw_mgr->cdm_info[dev_type][0].ref_cnt--;
acq_cdm_hdl_failed:
kfree(ctx_data->cdm_cmd);
cam_jpeg_mgr_release_ctx(hw_mgr, ctx_data);
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_enc_hw_intf.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_enc_hw_intf.h
deleted file mode 100644
index f0b4e00..0000000
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_enc_hw_intf.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef CAM_JPEG_ENC_HW_INTF_H
-#define CAM_JPEG_ENC_HW_INTF_H
-
-#include <uapi/media/cam_defs.h>
-#include <media/cam_jpeg.h>
-
-#include "cam_hw_mgr_intf.h"
-#include "cam_jpeg_hw_intf.h"
-
-enum cam_jpeg_enc_cmd_type {
- CAM_JPEG_ENC_CMD_CDM_CFG,
- CAM_JPEG_ENC_CMD_SET_IRQ_CB,
- CAM_JPEG_ENC_CMD_MAX,
-};
-
-#endif /* CAM_JPEG_ENC_HW_INTF_H */
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h
index 3204388..44b134a 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h
@@ -13,14 +13,32 @@
#ifndef CAM_JPEG_HW_INTF_H
#define CAM_JPEG_HW_INTF_H
+#include "cam_cpas_api.h"
+
#define CAM_JPEG_CTX_MAX 8
#define CAM_JPEG_DEV_PER_TYPE_MAX 1
#define CAM_JPEG_CMD_BUF_MAX_SIZE 128
#define CAM_JPEG_MSG_BUF_MAX_SIZE CAM_JPEG_CMD_BUF_MAX_SIZE
+#define JPEG_VOTE 640000000
+
enum cam_jpeg_hw_type {
CAM_JPEG_DEV_ENC,
CAM_JPEG_DEV_DMA,
};
+
+struct cam_jpeg_set_irq_cb {
+ int32_t (*jpeg_hw_mgr_cb)(uint32_t irq_status,
+ int32_t result_size, void *data);
+ void *data;
+ uint32_t b_set_cb;
+};
+
+enum cam_jpeg_cmd_type {
+ CAM_JPEG_CMD_CDM_CFG,
+ CAM_JPEG_CMD_SET_IRQ_CB,
+ CAM_JPEG_CMD_MAX,
+};
+
#endif
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h
index d5c8c9d..5fb4e3ad 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h
@@ -17,34 +17,8 @@
#include <uapi/media/cam_defs.h>
#include <linux/of.h>
-#include "cam_cpas_api.h"
-
-#define JPEG_TURBO_VOTE 640000000
int cam_jpeg_hw_mgr_init(struct device_node *of_node,
uint64_t *hw_mgr_hdl);
-/**
- * struct cam_jpeg_cpas_vote
- * @ahb_vote: AHB vote info
- * @axi_vote: AXI vote info
- * @ahb_vote_valid: Flag for ahb vote data
- * @axi_vote_valid: Flag for axi vote data
- */
-struct cam_jpeg_cpas_vote {
- struct cam_ahb_vote ahb_vote;
- struct cam_axi_vote axi_vote;
- uint32_t ahb_vote_valid;
- uint32_t axi_vote_valid;
-};
-
-struct cam_jpeg_set_irq_cb {
- int32_t (*jpeg_hw_mgr_cb)(
- uint32_t irq_status,
- int32_t result_size,
- void *data);
- void *data;
- uint32_t b_set_cb;
-};
-
#endif /* CAM_JPEG_HW_MGR_INTF_H */
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c
index 0a15f71..2d343dd 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c
@@ -26,7 +26,6 @@
#include "jpeg_dma_soc.h"
#include "cam_soc_util.h"
#include "cam_io_util.h"
-#include "cam_dma_hw_intf.h"
#include "cam_jpeg_hw_intf.h"
#include "cam_jpeg_hw_mgr_intf.h"
#include "cam_cpas_api.h"
@@ -38,7 +37,8 @@
struct cam_hw_info *jpeg_dma_dev = device_priv;
struct cam_hw_soc_info *soc_info = NULL;
struct cam_jpeg_dma_device_core_info *core_info = NULL;
- struct cam_jpeg_cpas_vote cpas_vote;
+ struct cam_ahb_vote ahb_vote;
+ struct cam_axi_vote axi_vote;
int rc;
if (!device_priv) {
@@ -57,20 +57,19 @@
return -EINVAL;
}
-
mutex_lock(&core_info->core_mutex);
if (++core_info->ref_count > 1) {
mutex_unlock(&core_info->core_mutex);
return 0;
}
- cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE;
- cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE;
- cpas_vote.axi_vote.compressed_bw = JPEG_TURBO_VOTE;
- cpas_vote.axi_vote.uncompressed_bw = JPEG_TURBO_VOTE;
+ ahb_vote.type = CAM_VOTE_ABSOLUTE;
+ ahb_vote.vote.level = CAM_SVS_VOTE;
+ axi_vote.compressed_bw = JPEG_VOTE;
+ axi_vote.uncompressed_bw = JPEG_VOTE;
rc = cam_cpas_start(core_info->cpas_handle,
- &cpas_vote.ahb_vote, &cpas_vote.axi_vote);
+ &ahb_vote, &axi_vote);
if (rc) {
CAM_ERR(CAM_JPEG, "cpass start failed: %d", rc);
goto cpas_failed;
@@ -91,6 +90,7 @@
cpas_failed:
--core_info->ref_count;
mutex_unlock(&core_info->core_mutex);
+
return rc;
}
@@ -154,7 +154,7 @@
return -EINVAL;
}
- if (cmd_type >= CAM_JPEG_DMA_CMD_MAX) {
+ if (cmd_type >= CAM_JPEG_CMD_MAX) {
CAM_ERR(CAM_JPEG, "Invalid command : %x", cmd_type);
return -EINVAL;
}
@@ -164,7 +164,7 @@
core_info;
switch (cmd_type) {
- case CAM_JPEG_DMA_CMD_SET_IRQ_CB:
+ case CAM_JPEG_CMD_SET_IRQ_CB:
{
struct cam_jpeg_set_irq_cb *irq_cb = cmd_args;
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h
index 1e0c2e2..a4d5d89 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h
@@ -19,16 +19,12 @@
#include <linux/platform_device.h>
#include <linux/dma-buf.h>
+#include "cam_jpeg_hw_intf.h"
+
struct cam_jpeg_dma_device_hw_info {
uint32_t reserved;
};
-struct cam_jpeg_dma_set_irq_cb {
- int32_t (*jpeg_hw_mgr_cb)(uint32_t irq_status,
- int32_t result_size, void *data);
- void *data;
-};
-
enum cam_jpeg_dma_core_state {
CAM_JPEG_DMA_CORE_NOT_READY,
CAM_JPEG_DMA_CORE_READY,
@@ -40,7 +36,7 @@
enum cam_jpeg_dma_core_state core_state;
struct cam_jpeg_dma_device_hw_info *jpeg_dma_hw_info;
uint32_t cpas_handle;
- struct cam_jpeg_dma_set_irq_cb irq_cb;
+ struct cam_jpeg_set_irq_cb irq_cb;
int32_t ref_count;
struct mutex core_mutex;
};
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h
new file mode 100644
index 0000000..725af47
--- /dev/null
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h
@@ -0,0 +1,74 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef CAM_JPEG_ENC_HW_INFO_TITAN170_H
+#define CAM_JPEG_ENC_HW_INFO_TITAN170_H
+
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001
+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000
+
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000
+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a
+
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800
+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b
+
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF (0x1<<19)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR (0x1<<20)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR (0x1<<21)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW (0x1<<23)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM (0x1<<24)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ (0x1<<25)
+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM (0x1<<26)
+#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK (0x1<<29)
+
+#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \
+ CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK
+#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \
+ CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK
+#define CAM_JPEG_HW_MASK_COMP_ERR \
+ (CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \
+ CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \
+ CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK)
+
+static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_hw_info = {
+ .reg_offset = {
+ .hw_version = 0x0,
+ .int_clr = 0x1c,
+ .int_status = 0x20,
+ .int_mask = 0x18,
+ .hw_cmd = 0x10,
+ .reset_cmd = 0x8,
+ .encode_size = 0x180,
+ },
+ .reg_val = {
+ .int_clr_clearall = 0xFFFFFFFF,
+ .int_mask_disable_all = 0x00000000,
+ .int_mask_enable_all = 0xFFFFFFFF,
+ .hw_cmd_start = 0x00000001,
+ .reset_cmd = 0x00032093,
+ },
+ .int_status = {
+ .framedone = CAM_JPEG_HW_MASK_COMP_FRAMEDONE,
+ .resetdone = CAM_JPEG_HW_MASK_COMP_RESET_ACK,
+ .iserror = CAM_JPEG_HW_MASK_COMP_ERR,
+ }
+};
+
+#endif /* CAM_JPEG_ENC_HW_INFO_TITAN170_H */
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c
index 06ad260..a7c4e06 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c
@@ -26,52 +26,17 @@
#include "jpeg_enc_soc.h"
#include "cam_soc_util.h"
#include "cam_io_util.h"
-#include "cam_enc_hw_intf.h"
#include "cam_jpeg_hw_intf.h"
#include "cam_jpeg_hw_mgr_intf.h"
#include "cam_cpas_api.h"
#include "cam_debug_util.h"
-#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001
-#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000
-
-#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000
-#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a
-
-#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800
-#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b
-
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF (0x1<<19)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR (0x1<<20)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR (0x1<<21)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW (0x1<<23)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM (0x1<<24)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ (0x1<<25)
-#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM (0x1<<26)
-#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK (0x1<<29)
-
-#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \
- CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK
-#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \
- CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK
-#define CAM_JPEG_HW_MASK_COMP_ERR \
- (CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \
- CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \
- CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK)
-
-#define CAM_JPEG_HW_IRQ_IS_FRAME_DONE(jpeg_irq_status) \
- (jpeg_irq_status & CAM_JPEG_HW_MASK_COMP_FRAMEDONE)
-#define CAM_JPEG_HW_IRQ_IS_RESET_ACK(jpeg_irq_status) \
- (jpeg_irq_status & CAM_JPEG_HW_MASK_COMP_RESET_ACK)
-#define CAM_JPEG_HW_IRQ_IS_ERR(jpeg_irq_status) \
- (jpeg_irq_status & CAM_JPEG_HW_MASK_COMP_ERR)
+#define CAM_JPEG_HW_IRQ_IS_FRAME_DONE(jpeg_irq_status, hi) \
+ ((jpeg_irq_status) & (hi)->int_status.framedone)
+#define CAM_JPEG_HW_IRQ_IS_RESET_ACK(jpeg_irq_status, hi) \
+ ((jpeg_irq_status) & (hi)->int_status.resetdone)
+#define CAM_JPEG_HW_IRQ_IS_ERR(jpeg_irq_status, hi) \
+ ((jpeg_irq_status) & (hi)->int_status.iserror)
#define CAM_JPEG_ENC_RESET_TIMEOUT msecs_to_jiffies(500)
@@ -81,7 +46,8 @@
struct cam_hw_info *jpeg_enc_dev = device_priv;
struct cam_hw_soc_info *soc_info = NULL;
struct cam_jpeg_enc_device_core_info *core_info = NULL;
- struct cam_jpeg_cpas_vote cpas_vote;
+ struct cam_ahb_vote ahb_vote;
+ struct cam_axi_vote axi_vote;
int rc;
if (!device_priv) {
@@ -100,20 +66,19 @@
return -EINVAL;
}
-
mutex_lock(&core_info->core_mutex);
if (++core_info->ref_count > 1) {
mutex_unlock(&core_info->core_mutex);
return 0;
}
- cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE;
- cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE;
- cpas_vote.axi_vote.compressed_bw = JPEG_TURBO_VOTE;
- cpas_vote.axi_vote.uncompressed_bw = JPEG_TURBO_VOTE;
+ ahb_vote.type = CAM_VOTE_ABSOLUTE;
+ ahb_vote.vote.level = CAM_SVS_VOTE;
+ axi_vote.compressed_bw = JPEG_VOTE;
+ axi_vote.uncompressed_bw = JPEG_VOTE;
rc = cam_cpas_start(core_info->cpas_handle,
- &cpas_vote.ahb_vote, &cpas_vote.axi_vote);
+ &ahb_vote, &axi_vote);
if (rc) {
CAM_ERR(CAM_JPEG, "cpass start failed: %d", rc);
goto cpas_failed;
@@ -134,6 +99,7 @@
cpas_failed:
--core_info->ref_count;
mutex_unlock(&core_info->core_mutex);
+
return rc;
}
@@ -174,7 +140,7 @@
rc = cam_jpeg_enc_disable_soc_resources(soc_info);
if (rc)
- CAM_ERR(CAM_JPEG, "soc enable failed %d", rc);
+ CAM_ERR(CAM_JPEG, "soc disable failed %d", rc);
rc = cam_cpas_stop(core_info->cpas_handle);
if (rc)
@@ -207,17 +173,19 @@
mem_base = soc_info->reg_map[0].mem_base;
irq_status = cam_io_r_mb(mem_base +
- core_info->jpeg_enc_hw_info->int_status);
+ core_info->jpeg_enc_hw_info->reg_offset.int_status);
cam_io_w_mb(irq_status,
soc_info->reg_map[0].mem_base +
- core_info->jpeg_enc_hw_info->int_clr);
+ core_info->jpeg_enc_hw_info->reg_offset.int_clr);
CAM_DBG(CAM_JPEG, "irq_num %d irq_status = %x , core_state %d",
irq_num, irq_status, core_info->core_state);
- if (CAM_JPEG_HW_IRQ_IS_FRAME_DONE(irq_status)) {
+ if (CAM_JPEG_HW_IRQ_IS_FRAME_DONE(irq_status, hw_info)) {
if (core_info->core_state == CAM_JPEG_ENC_CORE_READY) {
- encoded_size = cam_io_r_mb(mem_base + 0x180);
+ encoded_size = cam_io_r_mb(mem_base +
+ core_info->jpeg_enc_hw_info->reg_offset.
+ encode_size);
if (core_info->irq_cb.jpeg_hw_mgr_cb) {
core_info->irq_cb.jpeg_hw_mgr_cb(irq_status,
encoded_size,
@@ -229,7 +197,7 @@
core_info->core_state = CAM_JPEG_ENC_CORE_NOT_READY;
}
- if (CAM_JPEG_HW_IRQ_IS_RESET_ACK(irq_status)) {
+ if (CAM_JPEG_HW_IRQ_IS_RESET_ACK(irq_status, hw_info)) {
if (core_info->core_state == CAM_JPEG_ENC_CORE_RESETTING) {
core_info->core_state = CAM_JPEG_ENC_CORE_READY;
complete(&jpeg_enc_dev->hw_complete);
@@ -238,7 +206,7 @@
}
}
/* Unexpected/unintended HW interrupt */
- if (CAM_JPEG_HW_IRQ_IS_ERR(irq_status)) {
+ if (CAM_JPEG_HW_IRQ_IS_ERR(irq_status, hw_info)) {
core_info->core_state = CAM_JPEG_ENC_CORE_NOT_READY;
CAM_ERR_RATE_LIMIT(CAM_JPEG,
"error irq_num %d irq_status = %x , core_state %d",
@@ -285,10 +253,14 @@
core_info->core_state = CAM_JPEG_ENC_CORE_RESETTING;
- cam_io_w_mb(0x00000000, mem_base + hw_info->int_mask);
- cam_io_w_mb(0xFFFFFFFF, mem_base + hw_info->int_clr);
- cam_io_w_mb(0xFFFFFFFF, mem_base + hw_info->int_mask);
- cam_io_w_mb(0x00032093, mem_base + hw_info->reset_cmd);
+ cam_io_w_mb(hw_info->reg_val.int_mask_disable_all,
+ mem_base + hw_info->reg_offset.int_mask);
+ cam_io_w_mb(hw_info->reg_val.int_clr_clearall,
+ mem_base + hw_info->reg_offset.int_clr);
+ cam_io_w_mb(hw_info->reg_val.int_mask_enable_all,
+ mem_base + hw_info->reg_offset.int_mask);
+ cam_io_w_mb(hw_info->reg_val.reset_cmd,
+ mem_base + hw_info->reg_offset.reset_cmd);
rem_jiffies = wait_for_completion_timeout(&jpeg_enc_dev->hw_complete,
CAM_JPEG_ENC_RESET_TIMEOUT);
@@ -325,7 +297,8 @@
return -EINVAL;
}
- cam_io_w_mb(0x00000001, mem_base + 0x00000010);
+ cam_io_w_mb(hw_info->reg_val.hw_cmd_start,
+ mem_base + hw_info->reg_offset.hw_cmd);
return 0;
}
@@ -342,7 +315,7 @@
return -EINVAL;
}
- if (cmd_type >= CAM_JPEG_ENC_CMD_MAX) {
+ if (cmd_type >= CAM_JPEG_CMD_MAX) {
CAM_ERR(CAM_JPEG, "Invalid command : %x", cmd_type);
return -EINVAL;
}
@@ -352,7 +325,7 @@
core_info;
switch (cmd_type) {
- case CAM_JPEG_ENC_CMD_SET_IRQ_CB:
+ case CAM_JPEG_CMD_SET_IRQ_CB:
{
struct cam_jpeg_set_irq_cb *irq_cb = cmd_args;
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h
index eb5caef..4f5d625 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h
@@ -19,18 +19,36 @@
#include <linux/platform_device.h>
#include <linux/dma-buf.h>
-struct cam_jpeg_enc_device_hw_info {
+#include "cam_jpeg_hw_intf.h"
+
+struct cam_jpeg_enc_reg_offsets {
uint32_t hw_version;
uint32_t int_status;
uint32_t int_clr;
uint32_t int_mask;
+ uint32_t hw_cmd;
+ uint32_t reset_cmd;
+ uint32_t encode_size;
+};
+
+struct cam_jpeg_enc_regval {
+ uint32_t int_clr_clearall;
+ uint32_t int_mask_disable_all;
+ uint32_t int_mask_enable_all;
+ uint32_t hw_cmd_start;
uint32_t reset_cmd;
};
-struct cam_jpeg_enc_set_irq_cb {
- int32_t (*jpeg_hw_mgr_cb)(uint32_t irq_status,
- int32_t result_size, void *data);
- void *data;
+struct cam_jpeg_enc_int_status {
+ uint32_t framedone;
+ uint32_t resetdone;
+ uint32_t iserror;
+};
+
+struct cam_jpeg_enc_device_hw_info {
+ struct cam_jpeg_enc_reg_offsets reg_offset;
+ struct cam_jpeg_enc_regval reg_val;
+ struct cam_jpeg_enc_int_status int_status;
};
enum cam_jpeg_enc_core_state {
@@ -44,7 +62,7 @@
enum cam_jpeg_enc_core_state core_state;
struct cam_jpeg_enc_device_hw_info *jpeg_enc_hw_info;
uint32_t cpas_handle;
- struct cam_jpeg_enc_set_irq_cb irq_cb;
+ struct cam_jpeg_set_irq_cb irq_cb;
int32_t ref_count;
struct mutex core_mutex;
};
diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c
index 570d9f9..735bd21 100644
--- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c
+++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_dev.c
@@ -25,15 +25,7 @@
#include "cam_jpeg_hw_mgr_intf.h"
#include "cam_cpas_api.h"
#include "cam_debug_util.h"
-
-static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_hw_info = {
- .int_clr = 0x1c,
- .int_status = 0x20,
- .int_mask = 0x18,
- .reset_cmd = 0x8,
- .hw_version = 0x0,
-};
-EXPORT_SYMBOL(cam_jpeg_enc_hw_info);
+#include "cam_jpeg_enc_hw_info_ver_4_2_0.h"
static int cam_jpeg_enc_register_cpas(struct cam_hw_soc_info *soc_info,
struct cam_jpeg_enc_device_core_info *core_info,
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c
index c3475b6..ff0d32c 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.c
@@ -317,7 +317,7 @@
cmd_buf += (sizeof(struct cam_cmd_i2c_info)/sizeof(uint32_t));
i2c_data->init_settings.request_id = 0;
i2c_reg_settings->is_settings_valid = 1;
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
&cmd_desc[1], 1);
if (rc < 0) {
CAM_ERR(CAM_ACTUATOR, "Actuator pkt parsing failed: %d",
@@ -338,7 +338,7 @@
offset = (uint32_t *)&csl_packet->payload;
offset += csl_packet->cmd_buf_offset / sizeof(uint32_t);
cmd_desc = (struct cam_cmd_buf_desc *)(offset);
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
cmd_desc, 1);
if (rc < 0) {
CAM_ERR(CAM_ACTUATOR, "Actuator pkt parsing failed: %d",
@@ -358,7 +358,7 @@
offset = (uint32_t *)&csl_packet->payload;
offset += csl_packet->cmd_buf_offset / sizeof(uint32_t);
cmd_desc = (struct cam_cmd_buf_desc *)(offset);
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
cmd_desc, 1);
if (rc < 0) {
CAM_ERR(CAM_ACTUATOR, "Actuator pkt parsing failed: %d",
@@ -401,12 +401,16 @@
return -EINVAL;
}
- if (config)
+ if (config) {
+ rc = cam_soc_util_request_platform_resource(soc_info,
+ NULL, NULL);
rc = cam_soc_util_enable_platform_resource(soc_info, false, 0,
false);
- else
+ } else {
rc = cam_soc_util_disable_platform_resource(soc_info, false,
false);
+ rc = cam_soc_util_release_platform_resource(soc_info);
+ }
return rc;
}
@@ -429,15 +433,6 @@
if (soc_info->gpio_data &&
gpio_num_info &&
gpio_num_info->valid[SENSOR_VAF] == 1) {
- rc = cam_soc_util_request_platform_resource(&a_ctrl->soc_info,
- NULL, NULL);
- rc = cam_soc_util_enable_platform_resource(&a_ctrl->soc_info,
- false, 0, false);
- if (rc < 0) {
- CAM_ERR(CAM_ACTUATOR, "Failed in req gpio: %d", rc);
- return rc;
- }
-
gpio_set_value_cansleep(
gpio_num_info->gpio_num[SENSOR_VAF],
1);
@@ -456,12 +451,6 @@
&a_ctrl->soc_info;
struct msm_camera_gpio_num_info *gpio_num_info = NULL;
- rc = cam_actuator_vreg_control(a_ctrl, 0);
- if (rc < 0) {
- CAM_ERR(CAM_ACTUATOR, "Failed %d");
- return rc;
- }
-
gpio_num_info = a_ctrl->gpio_num_info;
if (soc_info->gpio_data &&
@@ -471,15 +460,12 @@
gpio_set_value_cansleep(
gpio_num_info->gpio_num[SENSOR_VAF],
GPIOF_OUT_INIT_LOW);
-
- rc = cam_soc_util_release_platform_resource(&a_ctrl->soc_info);
- rc |= cam_soc_util_disable_platform_resource(&a_ctrl->soc_info,
- 0, 0);
- if (rc < 0)
- CAM_ERR(CAM_ACTUATOR,
- "Failed to disable platform resources: %d", rc);
}
+ rc = cam_actuator_vreg_control(a_ctrl, 0);
+ if (rc < 0)
+ CAM_ERR(CAM_ACTUATOR, "Disable Regulator Failed: %d", rc);
+
return rc;
}
@@ -594,6 +580,9 @@
}
break;
case CAM_STOP_DEV: {
+ struct i2c_settings_array *i2c_set = NULL;
+ int i;
+
rc = camera_io_release(&a_ctrl->io_master_info);
if (rc < 0)
CAM_ERR(CAM_ACTUATOR, "Failed in releasing CCI");
@@ -602,6 +591,17 @@
CAM_ERR(CAM_ACTUATOR, "Actuator Power down failed");
goto release_mutex;
}
+ for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) {
+ i2c_set = &(a_ctrl->i2c_data.per_frame[i]);
+
+ if (i2c_set->is_settings_valid == 1) {
+ rc = delete_request(i2c_set);
+ if (rc < 0)
+ CAM_ERR(CAM_SENSOR,
+ "delete request: %lld rc: %d",
+ i2c_set->request_id, rc);
+ }
+ }
}
break;
case CAM_CONFIG_DEV: {
@@ -642,3 +642,50 @@
return rc;
}
+
+int32_t cam_actuator_flush_request(struct cam_req_mgr_flush_request *flush_req)
+{
+ int32_t rc = 0, i;
+ uint32_t cancel_req_id_found = 0;
+ struct cam_actuator_ctrl_t *a_ctrl = NULL;
+ struct i2c_settings_array *i2c_set = NULL;
+
+ if (!flush_req)
+ return -EINVAL;
+
+ a_ctrl = (struct cam_actuator_ctrl_t *)
+ cam_get_device_priv(flush_req->dev_hdl);
+ if (!a_ctrl) {
+ CAM_ERR(CAM_ACTUATOR, "Device data is NULL");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) {
+ i2c_set = &(a_ctrl->i2c_data.per_frame[i]);
+
+ if ((flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ)
+ && (i2c_set->request_id != flush_req->req_id))
+ continue;
+
+ if (i2c_set->is_settings_valid == 1) {
+ rc = delete_request(i2c_set);
+ if (rc < 0)
+ CAM_ERR(CAM_ACTUATOR,
+ "delete request: %lld rc: %d",
+ i2c_set->request_id, rc);
+
+ if (flush_req->type ==
+ CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ) {
+ cancel_req_id_found = 1;
+ break;
+ }
+ }
+ }
+
+ if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_CANCEL_REQ &&
+ !cancel_req_id_found)
+ CAM_DBG(CAM_ACTUATOR,
+ "Flush request id:%lld not found in the pending list",
+ flush_req->req_id);
+ return rc;
+}
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.h
index d2cb96d..e5676e6 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.h
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_core.h
@@ -30,6 +30,14 @@
int32_t cam_actuator_publish_dev_info(struct cam_req_mgr_device_info *info);
/**
+ * @flush: Req mgr structure for flushing request
+ *
+ * This API flushes the request that is mentioned
+ */
+int cam_actuator_flush_request(struct cam_req_mgr_flush_request *flush);
+
+
+/**
* @link: Link setup info
*
* This API establishes link actuator subdevice with req mgr
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_dev.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_dev.c
index 45dbba1..1559145 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_dev.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_actuator/cam_actuator_dev.c
@@ -307,6 +307,8 @@
cam_actuator_establish_link;
a_ctrl->bridge_intf.ops.apply_req =
cam_actuator_apply_request;
+ a_ctrl->bridge_intf.ops.flush_req =
+ cam_actuator_flush_request;
platform_set_drvdata(pdev, a_ctrl);
v4l2_set_subdevdata(&a_ctrl->v4l2_dev_str.sd, a_ctrl);
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c
index a173954..8a631ae 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_eeprom/cam_eeprom_core.c
@@ -668,7 +668,7 @@
case CAM_EEPROM_PACKET_OPCODE_INIT:
if (e_ctrl->userspace_probe == false) {
rc = cam_eeprom_parse_read_memory_map(
- e_ctrl->pdev->dev.of_node, e_ctrl);
+ e_ctrl->soc_info.dev->of_node, e_ctrl);
if (rc < 0) {
CAM_ERR(CAM_EEPROM, "Failed: rc : %d", rc);
return rc;
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c
index 0a283ab..7971b79 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_ois/cam_ois_core.c
@@ -77,12 +77,16 @@
return -EINVAL;
}
- if (config)
+ if (config) {
+ rc = cam_soc_util_request_platform_resource(soc_info,
+ NULL, NULL);
rc = cam_soc_util_enable_platform_resource(soc_info, false, 0,
false);
- else
+ } else {
rc = cam_soc_util_disable_platform_resource(soc_info, false,
false);
+ rc = cam_soc_util_release_platform_resource(soc_info);
+ }
return rc;
}
@@ -105,15 +109,6 @@
if (soc_info->gpio_data &&
gpio_num_info &&
gpio_num_info->valid[SENSOR_VAF] == 1) {
- rc = cam_soc_util_request_platform_resource(&o_ctrl->soc_info,
- NULL, NULL);
- rc = cam_soc_util_enable_platform_resource(&o_ctrl->soc_info,
- false, 0, false);
- if (rc < 0) {
- CAM_ERR(CAM_OIS, "Failed in req gpio: %d", rc);
- return rc;
- }
-
gpio_set_value_cansleep(
gpio_num_info->gpio_num[SENSOR_VAF],
1);
@@ -132,12 +127,6 @@
&o_ctrl->soc_info;
struct msm_camera_gpio_num_info *gpio_num_info = NULL;
- rc = cam_ois_vreg_control(o_ctrl, 0);
- if (rc < 0) {
- CAM_ERR(CAM_OIS, "Failed %d");
- return rc;
- }
-
gpio_num_info = o_ctrl->gpio_num_info;
if (soc_info->gpio_data &&
@@ -147,15 +136,12 @@
gpio_set_value_cansleep(
gpio_num_info->gpio_num[SENSOR_VAF],
GPIOF_OUT_INIT_LOW);
-
- rc = cam_soc_util_release_platform_resource(&o_ctrl->soc_info);
- rc |= cam_soc_util_disable_platform_resource(&o_ctrl->soc_info,
- 0, 0);
- if (rc < 0)
- CAM_ERR(CAM_OIS,
- "Failed to disable platform resources: %d", rc);
}
+ rc = cam_ois_vreg_control(o_ctrl, 0);
+ if (rc < 0)
+ CAM_ERR(CAM_OIS, "Disable regualtor Failed %d", rc);
+
return rc;
}
@@ -430,7 +416,7 @@
i2c_reg_settings = &(o_ctrl->i2c_init_data);
i2c_reg_settings->is_settings_valid = 1;
i2c_reg_settings->request_id = 0;
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
&cmd_desc[1], 1);
if (rc < 0) {
CAM_ERR(CAM_OIS, "OIS pkt parsing failed: %d",
@@ -442,7 +428,7 @@
i2c_reg_settings = &(o_ctrl->i2c_calib_data);
i2c_reg_settings->is_settings_valid = 1;
i2c_reg_settings->request_id = 0;
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
&cmd_desc[2], 1);
if (rc < 0) {
CAM_ERR(CAM_OIS,
@@ -458,7 +444,7 @@
i2c_reg_settings = &(o_ctrl->i2c_mode_data);
i2c_reg_settings->is_settings_valid = 1;
i2c_reg_settings->request_id = 0;
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings,
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings,
cmd_desc, 1);
if (rc < 0) {
CAM_ERR(CAM_OIS, "OIS pkt parsing failed: %d", rc);
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c
index cd96129..856dbeb 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c
@@ -17,6 +17,27 @@
#include "cam_soc_util.h"
#include "cam_trace.h"
+
+static void cam_sensor_update_req_mgr(
+ struct cam_sensor_ctrl_t *s_ctrl,
+ struct cam_packet *csl_packet)
+{
+ struct cam_req_mgr_add_request add_req;
+
+ add_req.link_hdl = s_ctrl->bridge_intf.link_hdl;
+ add_req.req_id = csl_packet->header.request_id;
+ CAM_DBG(CAM_SENSOR, " Rxed Req Id: %lld",
+ csl_packet->header.request_id);
+ add_req.dev_hdl = s_ctrl->bridge_intf.device_hdl;
+ add_req.skip_before_applying = 0;
+ if (s_ctrl->bridge_intf.crm_cb &&
+ s_ctrl->bridge_intf.crm_cb->add_req)
+ s_ctrl->bridge_intf.crm_cb->add_req(&add_req);
+
+ CAM_DBG(CAM_SENSOR, " add req to req mgr: %lld",
+ add_req.req_id);
+}
+
static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl,
void *arg)
{
@@ -30,7 +51,6 @@
uint32_t *offset = NULL;
struct cam_config_dev_cmd config;
struct i2c_data_settings *i2c_data = NULL;
- struct cam_req_mgr_add_request add_req;
ioctl_ctrl = (struct cam_control *)arg;
@@ -63,13 +83,32 @@
i2c_data = &(s_ctrl->i2c_data);
CAM_DBG(CAM_SENSOR, "Header OpCode: %d", csl_packet->header.op_code);
- if ((csl_packet->header.op_code & 0xFFFFFF) ==
- CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG) {
+ switch (csl_packet->header.op_code & 0xFFFFFF) {
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG: {
i2c_reg_settings = &i2c_data->init_settings;
i2c_reg_settings->request_id = 0;
i2c_reg_settings->is_settings_valid = 1;
- } else if ((csl_packet->header.op_code & 0xFFFFFF) ==
- CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE) {
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_RESCONFIG: {
+ i2c_reg_settings = &i2c_data->res_settings;
+ i2c_reg_settings->request_id = 0;
+ i2c_reg_settings->is_settings_valid = 1;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON: {
+ i2c_reg_settings = &i2c_data->streamon_settings;
+ i2c_reg_settings->request_id = 0;
+ i2c_reg_settings->is_settings_valid = 1;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF: {
+ i2c_reg_settings = &i2c_data->streamoff_settings;
+ i2c_reg_settings->request_id = 0;
+ i2c_reg_settings->is_settings_valid = 1;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE: {
i2c_reg_settings =
&i2c_data->
per_frame[csl_packet->header.request_id %
@@ -91,10 +130,14 @@
i2c_reg_settings->request_id =
csl_packet->header.request_id;
i2c_reg_settings->is_settings_valid = 1;
- } else if ((csl_packet->header.op_code & 0xFFFFFF) ==
- CAM_PKT_NOP_OPCODE) {
- goto update_req_mgr;
- } else {
+ cam_sensor_update_req_mgr(s_ctrl, csl_packet);
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_NOP: {
+ cam_sensor_update_req_mgr(s_ctrl, csl_packet);
+ return rc;
+ }
+ default:
CAM_ERR(CAM_SENSOR, "Invalid Packet Header");
return -EINVAL;
}
@@ -103,28 +146,11 @@
offset += csl_packet->cmd_buf_offset / 4;
cmd_desc = (struct cam_cmd_buf_desc *)(offset);
- rc = cam_sensor_i2c_pkt_parser(i2c_reg_settings, cmd_desc, 1);
+ rc = cam_sensor_i2c_command_parser(i2c_reg_settings, cmd_desc, 1);
if (rc < 0) {
CAM_ERR(CAM_SENSOR, "Fail parsing I2C Pkt: %d", rc);
return rc;
}
-
-update_req_mgr:
- if (((csl_packet->header.op_code & 0xFFFFFF) ==
- CAM_PKT_NOP_OPCODE) || (csl_packet->header.op_code ==
- CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE)) {
- add_req.link_hdl = s_ctrl->bridge_intf.link_hdl;
- add_req.req_id = csl_packet->header.request_id;
- CAM_DBG(CAM_SENSOR, " Rxed Req Id: %lld",
- csl_packet->header.request_id);
- add_req.dev_hdl = s_ctrl->bridge_intf.device_hdl;
- add_req.skip_before_applying = 0;
- if (s_ctrl->bridge_intf.crm_cb &&
- s_ctrl->bridge_intf.crm_cb->add_req)
- s_ctrl->bridge_intf.crm_cb->add_req(&add_req);
- CAM_DBG(CAM_SENSOR, " add req to req mgr: %lld",
- add_req.req_id);
- }
return rc;
}
@@ -511,8 +537,12 @@
goto release_mutex;
}
- CAM_DBG(CAM_SENSOR, "Probe Succeeded on the slot: %d",
- s_ctrl->soc_info.index);
+ CAM_INFO(CAM_SENSOR,
+ "Probe Succees, slot:%d slave_addr: 0x%x, slave_id: %d",
+ s_ctrl->soc_info.index,
+ s_ctrl->sensordata->slave_info.sensor_slave_addr,
+ s_ctrl->sensordata->slave_info.sensor_id);
+
rc = cam_sensor_power_down(s_ctrl);
if (rc < 0) {
CAM_ERR(CAM_SENSOR, "fail in Sensor Power Down");
@@ -595,31 +625,67 @@
break;
}
case CAM_START_DEV: {
- rc = cam_sensor_power_up(s_ctrl);
- if (rc < 0) {
- CAM_ERR(CAM_SENSOR, "Sensor Power up failed");
- goto release_mutex;
- }
- rc = cam_sensor_apply_settings(s_ctrl, 0);
- if (rc < 0) {
- CAM_ERR(CAM_SENSOR, "cannot apply settings");
- goto release_mutex;
- }
- rc = delete_request(&s_ctrl->i2c_data.init_settings);
- if (rc < 0) {
- CAM_ERR(CAM_SENSOR,
- "Fail in deleting the Init settings");
- rc = -EINVAL;
- goto release_mutex;
+ if (s_ctrl->i2c_data.streamon_settings.is_settings_valid &&
+ (s_ctrl->i2c_data.streamon_settings.request_id == 0)) {
+ rc = cam_sensor_apply_settings(s_ctrl, 0,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "cannot apply streamon settings");
+ goto release_mutex;
+ }
+ rc = delete_request(
+ &s_ctrl->i2c_data.streamon_settings);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "Fail in deleting the streamon settings");
+ goto release_mutex;
+ }
+ s_ctrl->i2c_data.streamon_settings.request_id = -1;
}
}
break;
case CAM_STOP_DEV: {
+ struct i2c_settings_array *i2c_set = NULL;
+ int i;
+
+ if (s_ctrl->i2c_data.streamoff_settings.is_settings_valid &&
+ (s_ctrl->i2c_data.streamoff_settings.request_id == 0)) {
+ rc = cam_sensor_apply_settings(s_ctrl, 0,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "cannot apply streamoff settings");
+ goto release_mutex;
+ }
+ rc = delete_request(
+ &s_ctrl->i2c_data.streamoff_settings);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "Fail in deleting the Streaomoff settings");
+ rc = -EINVAL;
+ goto release_mutex;
+ }
+ s_ctrl->i2c_data.streamoff_settings.request_id = -1;
+ }
rc = cam_sensor_power_down(s_ctrl);
if (rc < 0) {
CAM_ERR(CAM_SENSOR, "Sensor Power Down failed");
goto release_mutex;
}
+
+ for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) {
+ i2c_set = &(s_ctrl->i2c_data.per_frame[i]);
+
+ if (i2c_set->is_settings_valid == 1) {
+ rc = delete_request(i2c_set);
+ if (rc < 0)
+ CAM_ERR(CAM_SENSOR,
+ "delete request: %lld rc: %d",
+ i2c_set->request_id, rc);
+ }
+ }
+
}
break;
case CAM_CONFIG_DEV: {
@@ -628,6 +694,46 @@
CAM_ERR(CAM_SENSOR, "Failed CCI Config: %d", rc);
goto release_mutex;
}
+ if (s_ctrl->i2c_data.init_settings.is_settings_valid &&
+ (s_ctrl->i2c_data.init_settings.request_id == 0)) {
+ rc = cam_sensor_power_up(s_ctrl);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR, "Sensor Power up failed");
+ goto release_mutex;
+ }
+ rc = cam_sensor_apply_settings(s_ctrl, 0,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "cannot apply init settings");
+ goto release_mutex;
+ }
+ rc = delete_request(&s_ctrl->i2c_data.init_settings);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "Fail in deleting the Init settings");
+ goto release_mutex;
+ }
+ s_ctrl->i2c_data.init_settings.request_id = -1;
+ }
+
+ if (s_ctrl->i2c_data.res_settings.is_settings_valid &&
+ (s_ctrl->i2c_data.res_settings.request_id == 0)) {
+ rc = cam_sensor_apply_settings(s_ctrl, 0,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_RESCONFIG);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "cannot apply res settings");
+ goto release_mutex;
+ }
+ rc = delete_request(&s_ctrl->i2c_data.res_settings);
+ if (rc < 0) {
+ CAM_ERR(CAM_SENSOR,
+ "Fail in deleting the res settings");
+ goto release_mutex;
+ }
+ s_ctrl->i2c_data.res_settings.request_id = -1;
+ }
}
break;
case CAM_SD_SHUTDOWN:
@@ -769,14 +875,35 @@
}
int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl,
- int64_t req_id)
+ int64_t req_id, enum cam_sensor_packet_opcodes opcode)
{
int rc = 0, offset, del_req_id;
struct i2c_settings_array *i2c_set = NULL;
struct i2c_settings_list *i2c_list;
if (req_id == 0) {
- i2c_set = &s_ctrl->i2c_data.init_settings;
+ switch (opcode) {
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON: {
+ i2c_set = &s_ctrl->i2c_data.streamon_settings;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG: {
+ i2c_set = &s_ctrl->i2c_data.init_settings;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_RESCONFIG: {
+ i2c_set = &s_ctrl->i2c_data.res_settings;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF: {
+ i2c_set = &s_ctrl->i2c_data.streamoff_settings;
+ break;
+ }
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE:
+ case CAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE:
+ default:
+ return 0;
+ }
if (i2c_set->is_settings_valid == 1) {
list_for_each_entry(i2c_list,
&(i2c_set->list_head), list) {
@@ -790,12 +917,7 @@
return rc;
}
}
- rc = delete_request(&(s_ctrl->i2c_data.init_settings));
i2c_set->is_settings_valid = 0;
- if (rc < 0) {
- CAM_ERR(CAM_SENSOR,
- "Failed in deleting the Init request: %d", rc);
- }
}
} else {
offset = req_id % MAX_PER_FRAME_ARRAY;
@@ -836,6 +958,7 @@
del_req_id, rc);
}
}
+
return rc;
}
@@ -855,7 +978,8 @@
}
CAM_DBG(CAM_SENSOR, " Req Id: %lld", apply->request_id);
trace_cam_apply_req("Sensor", apply->request_id);
- rc = cam_sensor_apply_settings(s_ctrl, apply->request_id);
+ rc = cam_sensor_apply_settings(s_ctrl, apply->request_id,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE);
return rc;
}
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.h
index c8158fa..adc2e37 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.h
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.h
@@ -40,10 +40,12 @@
/**
* @s_ctrl: Sensor ctrl structure
* @req_id: Request id
+ * @opcode: opcode for settings
*
* This API applies the req_id settings to sensor
*/
-int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl, int64_t req_id);
+int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl, int64_t req_id,
+ enum cam_sensor_packet_opcodes opcode);
/**
* @apply: Req mgr structure for applying request
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_dev.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_dev.c
index 122aa3e..74d8212 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_dev.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_dev.c
@@ -163,6 +163,9 @@
}
INIT_LIST_HEAD(&(s_ctrl->i2c_data.init_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.res_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamon_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamoff_settings.list_head));
for (i = 0; i < MAX_PER_FRAME_ARRAY; i++)
INIT_LIST_HEAD(&(s_ctrl->i2c_data.per_frame[i].list_head));
@@ -269,6 +272,9 @@
}
INIT_LIST_HEAD(&(s_ctrl->i2c_data.init_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.res_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamon_settings.list_head));
+ INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamoff_settings.list_head));
for (i = 0; i < MAX_PER_FRAME_ARRAY; i++)
INIT_LIST_HEAD(&(s_ctrl->i2c_data.per_frame[i].list_head));
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h
index 97b4c01..ac1e23b 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h
@@ -153,7 +153,10 @@
CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON,
CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE,
CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG,
- CAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_RESCONFIG,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF,
+ CAM_SENSOR_PACKET_OPCODE_SENSOR_NOP = 127
};
enum cam_actuator_packet_opcodes {
@@ -279,6 +282,9 @@
struct i2c_data_settings {
struct i2c_settings_array init_settings;
+ struct i2c_settings_array res_settings;
+ struct i2c_settings_array streamon_settings;
+ struct i2c_settings_array streamoff_settings;
struct i2c_settings_array *per_frame;
};
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
index bcdaf6d..85d7b74 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c
@@ -250,7 +250,7 @@
}
/**
- * Name : cam_sensor_i2c_pkt_parser
+ * Name : cam_sensor_i2c_command_parser
* Description : Parse CSL CCI packet and apply register settings
* Parameters : s_ctrl input/output sub_device
* arg input cam_control
@@ -260,7 +260,7 @@
* WAIT + n x RND_WR with num_cmd_buf = 1. Do not exepect RD/WR
* with different cmd_type and op_code in one command buffer.
*/
-int cam_sensor_i2c_pkt_parser(struct i2c_settings_array *i2c_reg_settings,
+int cam_sensor_i2c_command_parser(struct i2c_settings_array *i2c_reg_settings,
struct cam_cmd_buf_desc *cmd_desc, int32_t num_cmd_buffers)
{
int16_t rc = 0, i = 0;
diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h
index 8a26369..d2079b0 100644
--- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h
+++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h
@@ -34,7 +34,7 @@
int msm_camera_pinctrl_init
(struct msm_pinctrl_info *sensor_pctrl, struct device *dev);
-int cam_sensor_i2c_pkt_parser(struct i2c_settings_array *i2c_reg_settings,
+int cam_sensor_i2c_command_parser(struct i2c_settings_array *i2c_reg_settings,
struct cam_cmd_buf_desc *cmd_desc, int32_t num_cmd_buffers);
int32_t delete_request(struct i2c_settings_array *i2c_array);
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c
index f81cd2f..976155e 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c
@@ -1162,7 +1162,6 @@
struct sde_rotator_request *request)
{
struct sde_rotator_ctx *ctx;
- struct sde_rot_entry_container *req;
if (!request || !request->ctx) {
SDEROT_ERR("invalid parameters\n");
@@ -1170,11 +1169,7 @@
}
ctx = request->ctx;
- req = request->req;
-
- if (req && req->entries && req->count)
- ctx->retired_sequence_id =
- req->entries[req->count - 1].item.sequence_id;
+ ctx->retired_sequence_id = request->sequence_id;
wake_up(&ctx->wait_queue);
@@ -1199,6 +1194,7 @@
ctx = request->ctx;
request->req = NULL;
+ request->sequence_id = 0;
request->committed = false;
spin_lock(&ctx->list_lock);
list_del_init(&request->list);
@@ -1216,17 +1212,14 @@
static bool sde_rotator_is_request_retired(struct sde_rotator_request *request)
{
struct sde_rotator_ctx *ctx;
- struct sde_rot_entry_container *req;
u32 sequence_id;
s32 retire_delta;
- if (!request || !request->ctx || !request->req ||
- !request->req->entries || !request->req->count)
+ if (!request || !request->ctx)
return true;
ctx = request->ctx;
- req = request->req;
- sequence_id = req->entries[req->count - 1].item.sequence_id;
+ sequence_id = request->sequence_id;
retire_delta = (s32) (ctx->retired_sequence_id - sequence_id);
@@ -1643,6 +1636,7 @@
}
request->req = req;
+ request->sequence_id = req->entries[0].item.sequence_id;
spin_lock(&ctx->list_lock);
list_del_init(&request->list);
@@ -3000,6 +2994,8 @@
sde_rotator_queue_request(rot_dev->mgr, ctx->private, req);
request->req = req;
+ request->sequence_id = item.sequence_id;
+ request->committed = true;
return 0;
error_handle_request:
@@ -3008,6 +3004,8 @@
error_fence_wait:
error_null_buffer:
request->req = NULL;
+ request->sequence_id = 0;
+ request->committed = false;
return ret;
}
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.h b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.h
index 5ea9e15..a464a39 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.h
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.h
@@ -90,9 +90,12 @@
* @list: list head for submit/retire list
* @submit_work: submit work structure
* @retire_work: retire work structure
- * @request: Pointer to core layer rotator manager request
+ * @req: Pointer to core layer rotator manager request
+ * Request can be freed by core layer during sde_rotator_stop_streaming.
+ * Avoid dereference in dev layer if possible.
* @ctx: Pointer to parent context
* @committed: true if request committed to hardware
+ * @sequence_id: sequence identifier of this request
*/
struct sde_rotator_request {
struct list_head list;
@@ -101,6 +104,7 @@
struct sde_rot_entry_container *req;
struct sde_rotator_ctx *ctx;
bool committed;
+ u32 sequence_id;
};
/*
diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c
index 68611b6..c042007 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc.c
@@ -846,7 +846,8 @@
/* For decoder No need to sanity till LOAD_RESOURCES */
if (inst->session_type == MSM_VIDC_DECODER &&
- inst->state < MSM_VIDC_LOAD_RESOURCES_DONE) {
+ (inst->state < MSM_VIDC_LOAD_RESOURCES_DONE ||
+ inst->state >= MSM_VIDC_RELEASE_RESOURCES_DONE)) {
dprintk(VIDC_DBG,
"No need to verify buffer counts : %pK\n", inst);
return 0;
@@ -1499,6 +1500,16 @@
HAL_BUFFER_INPUT);
return -EINVAL;
}
+
+ if (inst->session_type == MSM_VIDC_DECODER &&
+ !(inst->flags & VIDC_THUMBNAIL) &&
+ inst->fmts[OUTPUT_PORT].fourcc ==
+ V4L2_PIX_FMT_VP9 &&
+ bufreq->buffer_count_min_host <
+ MIN_NUM_OUTPUT_BUFFERS_VP9)
+ bufreq->buffer_count_min_host =
+ MIN_NUM_OUTPUT_BUFFERS_VP9;
+
ctrl->val = bufreq->buffer_count_min_host;
break;
case V4L2_CID_MPEG_VIDC_VIDEO_TME_PAYLOAD_VERSION:
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
index f2f6d58..5183ddd 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c
@@ -22,6 +22,19 @@
#define MSM_VIDC_MIN_UBWC_COMPRESSION_RATIO (1 << 16)
#define MSM_VIDC_MAX_UBWC_COMPRESSION_RATIO (5 << 16)
+static inline void msm_dcvs_print_dcvs_stats(struct clock_data *dcvs)
+{
+ dprintk(VIDC_PROF,
+ "DCVS: Load_Low %d, Load Norm %d, Load High %d\n",
+ dcvs->load_low,
+ dcvs->load_norm,
+ dcvs->load_high);
+
+ dprintk(VIDC_PROF,
+ "DCVS: min_threshold %d, max_threshold %d\n",
+ dcvs->min_threshold, dcvs->max_threshold);
+}
+
static inline unsigned long int get_ubwc_compression_ratio(
struct ubwc_cr_stats_info_type ubwc_stats_info)
{
@@ -509,6 +522,14 @@
unsigned long vpp_cycles = 0, vsp_cycles = 0;
u32 vpp_cycles_per_mb;
u32 mbs_per_second;
+ struct msm_vidc_core *core = NULL;
+ int i = 0;
+ struct allowed_clock_rates_table *allowed_clks_tbl = NULL;
+ u64 rate = 0;
+ struct clock_data *dcvs = NULL;
+
+ core = inst->core;
+ dcvs = &inst->clk_data;
mbs_per_second = msm_comm_get_inst_load_per_core(inst,
LOAD_CALC_NO_QUIRKS);
@@ -544,6 +565,22 @@
freq = max(vpp_cycles, vsp_cycles);
+ dprintk(VIDC_DBG, "Update DCVS Load\n");
+ allowed_clks_tbl = core->resources.allowed_clks_tbl;
+ for (i = core->resources.allowed_clks_tbl_size - 1; i >= 0; i--) {
+ rate = allowed_clks_tbl[i].clock_rate;
+ if (rate >= freq)
+ break;
+ }
+
+ dcvs->load_norm = rate;
+ dcvs->load_low = i < (core->resources.allowed_clks_tbl_size - 1) ?
+ allowed_clks_tbl[i+1].clock_rate : dcvs->load_norm;
+ dcvs->load_high = i > 0 ? allowed_clks_tbl[i-1].clock_rate :
+ dcvs->load_norm;
+
+ msm_dcvs_print_dcvs_stats(dcvs);
+
dprintk(VIDC_PROF, "%s Inst %pK : Filled Len = %d Freq = %lu\n",
__func__, inst, filled_len, freq);
@@ -652,7 +689,9 @@
operating_rate = operating_rate >> 16;
- if ((curr_operating_rate + ops_left) >= operating_rate) {
+ if ((curr_operating_rate + ops_left) >= operating_rate ||
+ !msm_vidc_clock_scaling ||
+ inst->clk_data.buffer_counter < DCVS_FTB_WINDOW) {
dprintk(VIDC_DBG,
"Requestd operating rate is valid %u\n",
operating_rate);
@@ -796,19 +835,6 @@
return rc;
}
-static inline void msm_dcvs_print_dcvs_stats(struct clock_data *dcvs)
-{
- dprintk(VIDC_PROF,
- "DCVS: Load_Low %d, Load Norm %d, Load High %d\n",
- dcvs->load_low,
- dcvs->load_norm,
- dcvs->load_high);
-
- dprintk(VIDC_PROF,
- "DCVS: min_threshold %d, max_threshold %d\n",
- dcvs->min_threshold, dcvs->max_threshold);
-}
-
void msm_clock_data_reset(struct msm_vidc_inst *inst)
{
struct msm_vidc_core *core;
@@ -852,6 +878,10 @@
}
dcvs->max_threshold = output_buf_req->buffer_count_actual -
output_buf_req->buffer_count_min_host + 1;
+ /* Compensate for decode only frames */
+ if (inst->fmts[OUTPUT_PORT].fourcc == V4L2_PIX_FMT_VP9)
+ dcvs->max_threshold += 2;
+
dcvs->min_threshold =
msm_vidc_get_extra_buff_count(inst, dcvs->buffer_type);
} else {
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.c b/drivers/media/platform/msm/vidc/msm_vidc_common.c
index f8c5798..11e21c4 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_common.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_common.c
@@ -3336,20 +3336,11 @@
}
mutex_lock(&core->lock);
- if (core->state != VIDC_CORE_INIT_DONE) {
- dprintk(VIDC_ERR,
- "%s - fw is not in proper state, skip suspend\n",
- __func__);
- rc = -EINVAL;
- goto exit;
- }
-
rc = call_hfi_op(hdev, suspend, hdev->hfi_device_data);
if (rc)
dprintk(VIDC_WARN, "Failed to suspend\n");
-
-exit:
mutex_unlock(&core->lock);
+
return rc;
}
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_internal.h b/drivers/media/platform/msm/vidc/msm_vidc_internal.h
index 37645fe..2e2dd13 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_internal.h
+++ b/drivers/media/platform/msm/vidc/msm_vidc_internal.h
@@ -45,6 +45,7 @@
#define MIN_SUPPORTED_HEIGHT 32
#define DEFAULT_FPS 15
#define MIN_NUM_OUTPUT_BUFFERS 1
+#define MIN_NUM_OUTPUT_BUFFERS_VP9 6
#define MIN_NUM_CAPTURE_BUFFERS 1
#define MAX_NUM_OUTPUT_BUFFERS VIDEO_MAX_FRAME // same as VB2_MAX_FRAME
#define MAX_NUM_CAPTURE_BUFFERS VIDEO_MAX_FRAME // same as VB2_MAX_FRAME
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_platform.c b/drivers/media/platform/msm/vidc/msm_vidc_platform.c
index 56524ccd4..1818788 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_platform.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_platform.c
@@ -66,6 +66,7 @@
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 125, 675, 320),
CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_ENCODER, 125, 675, 320),
+ CODEC_ENTRY(V4L2_PIX_FMT_TME, MSM_VIDC_ENCODER, 0, 540, 540),
CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 50, 200, 200),
CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 50, 200, 200),
diff --git a/drivers/media/platform/msm/vidc/venus_hfi.c b/drivers/media/platform/msm/vidc/venus_hfi.c
index e260886..60169e9 100644
--- a/drivers/media/platform/msm/vidc/venus_hfi.c
+++ b/drivers/media/platform/msm/vidc/venus_hfi.c
@@ -1029,8 +1029,10 @@
flush_delayed_work(&venus_hfi_pm_work);
mutex_lock(&device->lock);
- if (device->power_enabled)
+ if (device->power_enabled) {
+ dprintk(VIDC_WARN, "%s: Venus is busy\n", __func__);
rc = -EBUSY;
+ }
mutex_unlock(&device->lock);
return rc;
}
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index eb14f0f..a209aa6 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -3461,6 +3461,8 @@
else
mrq->data->error = -ETIMEDOUT;
+ host->err_stats[MMC_ERR_CMDQ_REQ_TIMEOUT]++;
+
if (mrq->cmd && mrq->cmd->error) {
if (!(mrq->req->cmd_flags & REQ_PREFLUSH)) {
/*
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 727b301..edbf682 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -4134,6 +4134,7 @@
if (!host->max_busy_timeout ||
(host->caps2 & MMC_CAP2_MAX_DISCARD_SIZE))
+ return UINT_MAX;
/*
* Without erase_group_def set, MMC erase timeout depends on clock
@@ -4424,6 +4425,7 @@
goto out;
}
mmc_rescan_try_freq(host, host->f_min);
+ host->err_stats[MMC_ERR_CMD_TIMEOUT] = 0;
mmc_release_host(host);
out:
diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
index d1a0235..7163e34 100644
--- a/drivers/mmc/core/debugfs.c
+++ b/drivers/mmc/core/debugfs.c
@@ -381,6 +381,79 @@
DEFINE_SIMPLE_ATTRIBUTE(mmc_err_state, mmc_err_state_get,
mmc_err_state_clear, "%llu\n");
+static int mmc_err_stats_show(struct seq_file *file, void *data)
+{
+ struct mmc_host *host = (struct mmc_host *)file->private;
+
+ if (!host)
+ return -EINVAL;
+
+ seq_printf(file, "# Command Timeout Occurred:\t %d\n",
+ host->err_stats[MMC_ERR_CMD_TIMEOUT]);
+
+ seq_printf(file, "# Command CRC Errors Occurred:\t %d\n",
+ host->err_stats[MMC_ERR_CMD_CRC]);
+
+ seq_printf(file, "# Data Timeout Occurred:\t %d\n",
+ host->err_stats[MMC_ERR_DAT_TIMEOUT]);
+
+ seq_printf(file, "# Data CRC Errors Occurred:\t %d\n",
+ host->err_stats[MMC_ERR_DAT_CRC]);
+
+ seq_printf(file, "# Auto-Cmd Error Occurred:\t %d\n",
+ host->err_stats[MMC_ERR_ADMA]);
+
+ seq_printf(file, "# ADMA Error Occurred:\t %d\n",
+ host->err_stats[MMC_ERR_ADMA]);
+
+ seq_printf(file, "# Tuning Error Occurred:\t %d\n",
+ host->err_stats[MMC_ERR_TUNING]);
+
+ seq_printf(file, "# CMDQ RED Errors:\t\t %d\n",
+ host->err_stats[MMC_ERR_CMDQ_RED]);
+
+ seq_printf(file, "# CMDQ GCE Errors:\t\t %d\n",
+ host->err_stats[MMC_ERR_CMDQ_GCE]);
+
+ seq_printf(file, "# CMDQ ICCE Errors:\t\t %d\n",
+ host->err_stats[MMC_ERR_CMDQ_ICCE]);
+
+ seq_printf(file, "# Request Timedout:\t %d\n",
+ host->err_stats[MMC_ERR_REQ_TIMEOUT]);
+
+ seq_printf(file, "# CMDQ Request Timedout:\t %d\n",
+ host->err_stats[MMC_ERR_CMDQ_REQ_TIMEOUT]);
+
+ seq_printf(file, "# ICE Config Errors:\t\t %d\n",
+ host->err_stats[MMC_ERR_ICE_CFG]);
+ return 0;
+}
+
+static int mmc_err_stats_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, mmc_err_stats_show, inode->i_private);
+}
+
+static ssize_t mmc_err_stats_write(struct file *filp, const char __user *ubuf,
+ size_t cnt, loff_t *ppos)
+{
+ struct mmc_host *host = filp->f_mapping->host->i_private;
+
+ if (!host)
+ return -EINVAL;
+
+ pr_debug("%s: Resetting MMC error statistics", __func__);
+ memset(host->err_stats, 0, sizeof(host->err_stats));
+
+ return cnt;
+}
+
+static const struct file_operations mmc_err_stats_fops = {
+ .open = mmc_err_stats_open,
+ .read = seq_read,
+ .write = mmc_err_stats_write,
+};
+
void mmc_add_host_debugfs(struct mmc_host *host)
{
struct dentry *root;
@@ -430,6 +503,10 @@
&mmc_err_state))
goto err_node;
+ if (!debugfs_create_file("err_stats", 0600, root, host,
+ &mmc_err_stats_fops))
+ goto err_node;
+
#ifdef CONFIG_MMC_CLKGATE
if (!debugfs_create_u32("clk_delay", (S_IRUSR | S_IWUSR),
root, &host->clk_delay))
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index bc89472..df78c3df2 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1604,12 +1604,19 @@
/* For Enhance Strobe HS400 flow */
if (card->ext_csd.strobe_support &&
card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400 &&
- card->host->caps & MMC_CAP_8_BIT_DATA)
- err = mmc_select_hs400es(card);
- else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200)
+ card->host->caps & MMC_CAP_8_BIT_DATA) {
+ err = mmc_select_hs400(card);
+ if (err) {
+ pr_err("%s: %s: mmc_select_hs400 failed : %d\n",
+ mmc_hostname(card->host), __func__,
+ err);
+ err = mmc_select_hs400es(card);
+ }
+ } else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200) {
err = mmc_select_hs200(card);
- else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS)
+ } else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS) {
err = mmc_select_hs(card);
+ }
if (err && err != -EBADMSG)
return err;
diff --git a/drivers/mmc/host/cmdq_hci.c b/drivers/mmc/host/cmdq_hci.c
index 591d6b2..f16a999 100644
--- a/drivers/mmc/host/cmdq_hci.c
+++ b/drivers/mmc/host/cmdq_hci.c
@@ -803,6 +803,7 @@
if (cq_host->ops->crypto_cfg) {
err = cq_host->ops->crypto_cfg(mmc, mrq, tag, &ice_ctx);
if (err) {
+ mmc->err_stats[MMC_ERR_ICE_CFG]++;
pr_err("%s: failed to configure crypto: err %d tag %d\n",
mmc_hostname(mmc), err, tag);
goto out;
@@ -1015,6 +1016,7 @@
mmc->card->bkops.needs_check = true;
mrq->cmdq_req->resp_err = true;
+ mmc->err_stats[MMC_ERR_CMDQ_RED]++;
pr_err("%s: Response error (0x%08x) from card !!!",
mmc_hostname(mmc), cmdq_readl(cq_host, CQCRA));
@@ -1030,6 +1032,7 @@
if (stat_err & CQIS_GCE) {
if (mrq->data)
mrq->data->error = -EIO;
+ mmc->err_stats[MMC_ERR_CMDQ_GCE]++;
pr_err("%s: Crypto generic error while processing task %lu!",
mmc_hostname(mmc), tag);
MMC_TRACE(mmc, "%s: GCE error detected with tag %lu\n",
@@ -1054,6 +1057,7 @@
if (dbr_set ^ dev_pend_set)
tag = ffs(dbr_set ^ dev_pend_set) - 1;
mrq = get_req_by_tag(cq_host, tag);
+ mmc->err_stats[MMC_ERR_CMDQ_ICCE]++;
pr_err("%s: Crypto config error while processing task %lu!",
mmc_hostname(mmc), tag);
MMC_TRACE(mmc, "%s: ICCE error with tag %lu\n",
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 55d9cf5..5be0689 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1281,6 +1281,11 @@
pr_debug("%s: %s: found *** good *** phase = %d\n",
mmc_hostname(mmc), __func__, phase);
} else {
+ /* Ignore crc errors occurred during tuning */
+ if (cmd.error)
+ mmc->err_stats[MMC_ERR_CMD_CRC]--;
+ else if (data.error)
+ mmc->err_stats[MMC_ERR_DAT_CRC]--;
pr_debug("%s: %s: found ## bad ## phase = %d\n",
mmc_hostname(mmc), __func__, phase);
}
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 4476e51..566be69 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2491,6 +2491,8 @@
*/
mmc_retune_disable(mmc);
err = host->ops->platform_execute_tuning(host, opcode);
+ if (err)
+ host->mmc->err_stats[MMC_ERR_TUNING]++;
mmc_retune_enable(mmc);
return err;
}
@@ -2701,8 +2703,8 @@
data->host_cookie = COOKIE_UNMAPPED;
- if (host->ops->pre_req)
- host->ops->pre_req(host, mrq);
+ if (host->ops->post_req)
+ host->ops->post_req(host, mrq);
}
static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
@@ -2714,6 +2716,9 @@
if (host->flags & SDHCI_REQ_USE_DMA)
sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
+
+ if (host->ops->pre_req)
+ host->ops->pre_req(host, mrq);
}
static inline bool sdhci_has_requests(struct sdhci_host *host)
@@ -2916,8 +2921,10 @@
spin_lock_irqsave(&host->lock, flags);
if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
+ host->mmc->err_stats[MMC_ERR_REQ_TIMEOUT]++;
pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
mmc_hostname(host->mmc));
+ MMC_TRACE(host->mmc, "Timeout waiting for h/w interrupt\n");
sdhci_dumpregs(host);
host->cmd->error = -ETIMEDOUT;
@@ -2939,6 +2946,7 @@
if (host->data || host->data_cmd ||
(host->cmd && sdhci_data_line_cmd(host->cmd))) {
+ host->mmc->err_stats[MMC_ERR_REQ_TIMEOUT]++;
pr_err("%s: Timeout waiting for hardware interrupt.\n",
mmc_hostname(host->mmc));
MMC_TRACE(host->mmc, "Timeout waiting for h/w interrupt\n");
@@ -2997,13 +3005,17 @@
if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
SDHCI_INT_END_BIT | SDHCI_INT_INDEX |
SDHCI_INT_AUTO_CMD_ERR)) {
- if (intmask & SDHCI_INT_TIMEOUT)
+ if (intmask & SDHCI_INT_TIMEOUT) {
host->cmd->error = -ETIMEDOUT;
- else
+ host->mmc->err_stats[MMC_ERR_CMD_TIMEOUT]++;
+ } else {
host->cmd->error = -EILSEQ;
+ host->mmc->err_stats[MMC_ERR_CMD_CRC]++;
+ }
if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
auto_cmd_status = host->auto_cmd_err_sts;
+ host->mmc->err_stats[MMC_ERR_AUTO_CMD]++;
pr_err_ratelimited("%s: %s: AUTO CMD err sts 0x%08x\n",
mmc_hostname(host->mmc), __func__, auto_cmd_status);
if (auto_cmd_status & (SDHCI_AUTO_CMD12_NOT_EXEC |
@@ -3131,6 +3143,7 @@
if (intmask & SDHCI_INT_DATA_TIMEOUT) {
host->data_cmd = NULL;
data_cmd->error = -ETIMEDOUT;
+ host->mmc->err_stats[MMC_ERR_CMD_TIMEOUT]++;
sdhci_finish_mrq(host, data_cmd->mrq);
return;
}
@@ -3154,16 +3167,21 @@
return;
}
- if (intmask & SDHCI_INT_DATA_TIMEOUT)
+ if (intmask & SDHCI_INT_DATA_TIMEOUT) {
host->data->error = -ETIMEDOUT;
+ host->mmc->err_stats[MMC_ERR_DAT_TIMEOUT]++;
+ }
else if (intmask & SDHCI_INT_DATA_END_BIT)
host->data->error = -EILSEQ;
else if ((intmask & SDHCI_INT_DATA_CRC) &&
- (command != MMC_BUS_TEST_R))
+ (command != MMC_BUS_TEST_R)) {
host->data->error = -EILSEQ;
+ host->mmc->err_stats[MMC_ERR_DAT_CRC]++;
+ }
else if (intmask & SDHCI_INT_ADMA_ERROR) {
pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
sdhci_adma_show_error(host);
+ host->mmc->err_stats[MMC_ERR_ADMA]++;
host->data->error = -EIO;
if (host->ops->adma_workaround)
host->ops->adma_workaround(host, intmask);
@@ -3242,24 +3260,31 @@
}
#ifdef CONFIG_MMC_CQ_HCI
-static int sdhci_get_cmd_err(u32 intmask)
+static int sdhci_get_cmd_err(struct sdhci_host *host, u32 intmask)
{
- if (intmask & SDHCI_INT_TIMEOUT)
+ if (intmask & SDHCI_INT_TIMEOUT) {
+ host->mmc->err_stats[MMC_ERR_CMD_TIMEOUT]++;
return -ETIMEDOUT;
- else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
- SDHCI_INT_INDEX))
+ } else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
+ SDHCI_INT_INDEX)) {
+ host->mmc->err_stats[MMC_ERR_CMD_CRC]++;
return -EILSEQ;
+ }
return 0;
}
-static int sdhci_get_data_err(u32 intmask)
+static int sdhci_get_data_err(struct sdhci_host *host, u32 intmask)
{
- if (intmask & SDHCI_INT_DATA_TIMEOUT)
+ if (intmask & SDHCI_INT_DATA_TIMEOUT) {
+ host->mmc->err_stats[MMC_ERR_DAT_TIMEOUT]++;
return -ETIMEDOUT;
- else if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
+ } else if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) {
+ host->mmc->err_stats[MMC_ERR_DAT_CRC]++;
return -EILSEQ;
- else if (intmask & SDHCI_INT_ADMA_ERROR)
+ } else if (intmask & MMC_ERR_ADMA) {
+ host->mmc->err_stats[MMC_ERR_ADMA]++;
return -EIO;
+ }
return 0;
}
@@ -3270,9 +3295,9 @@
irqreturn_t ret;
if (intmask & SDHCI_INT_CMD_MASK)
- err = sdhci_get_cmd_err(intmask);
+ err = sdhci_get_cmd_err(host, intmask);
else if (intmask & SDHCI_INT_DATA_MASK)
- err = sdhci_get_data_err(intmask);
+ err = sdhci_get_data_err(host, intmask);
ret = cmdq_irq(host->mmc, err);
if (err) {
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c
index 57dc4a0..050d98d 100644
--- a/drivers/pci/host/pci-msm.c
+++ b/drivers/pci/host/pci-msm.c
@@ -19,6 +19,7 @@
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
+#include <linux/jiffies.h>
#include <linux/gpio.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
@@ -120,6 +121,12 @@
#define PCIE20_PLR_IATU_LTAR 0x918
#define PCIE20_PLR_IATU_UTAR 0x91c
+
+#define PCIE20_PORT_LINK_CTRL_REG 0x710
+#define PCIE20_GEN3_RELATED_REG 0x890
+#define PCIE20_PIPE_LOOPBACK_CONTROL 0x8b8
+#define LOOPBACK_BASE_ADDR_OFFSET 0x8000
+
#define PCIE20_CTRL1_TYPE_CFG0 0x04
#define PCIE20_CTRL1_TYPE_CFG1 0x05
@@ -140,11 +147,15 @@
#define PERST_PROPAGATION_DELAY_US_MIN 1000
#define PERST_PROPAGATION_DELAY_US_MAX 1005
+#define SWITCH_DELAY_MAX 20
#define REFCLK_STABILIZATION_DELAY_US_MIN 1000
#define REFCLK_STABILIZATION_DELAY_US_MAX 1005
#define LINK_UP_TIMEOUT_US_MIN 5000
#define LINK_UP_TIMEOUT_US_MAX 5100
#define LINK_UP_CHECK_MAX_COUNT 20
+#define EP_UP_TIMEOUT_US_MIN 1000
+#define EP_UP_TIMEOUT_US_MAX 1005
+#define EP_UP_TIMEOUT_US 1000000
#define PHY_STABILIZATION_DELAY_US_MIN 995
#define PHY_STABILIZATION_DELAY_US_MAX 1005
#define POWER_DOWN_DELAY_US_MIN 10
@@ -492,6 +503,7 @@
uint32_t max_link_speed;
bool ext_ref_clk;
uint32_t ep_latency;
+ uint32_t switch_latency;
uint32_t wr_halt_size;
uint32_t slv_addr_space_size;
uint32_t cpl_timeout;
@@ -546,12 +558,37 @@
struct msm_pcie_device_info pcidev_table[MAX_DEVICE_NUM];
};
-
/* debug mask sys interface */
static int msm_pcie_debug_mask;
module_param_named(debug_mask, msm_pcie_debug_mask,
int, 0644);
+/*
+ * For each bit set, invert the default capability
+ * option for the corresponding root complex
+ * and its devices.
+ */
+static int msm_pcie_invert_l0s_support;
+module_param_named(invert_l0s_support, msm_pcie_invert_l0s_support,
+ int, 0644);
+static int msm_pcie_invert_l1_support;
+module_param_named(invert_l1_support, msm_pcie_invert_l1_support,
+ int, 0644);
+static int msm_pcie_invert_l1ss_support;
+module_param_named(invert_l1ss_support, msm_pcie_invert_l1ss_support,
+ int, 0644);
+static int msm_pcie_invert_aer_support;
+module_param_named(invert_aer_support, msm_pcie_invert_aer_support,
+ int, 0644);
+
+/*
+ * For each bit set, keep the resources on when link training fails
+ * or linkdown occurs for the corresponding root complex
+ */
+static int msm_pcie_keep_resources_on;
+module_param_named(keep_resources_on, msm_pcie_keep_resources_on,
+ int, 0644);
+
/* debugfs values */
static u32 rc_sel;
static u32 base_sel;
@@ -1112,6 +1149,8 @@
dev->n_fts);
PCIE_DBG_FS(dev, "ep_latency: %dms\n",
dev->ep_latency);
+ PCIE_DBG_FS(dev, "switch_latency: %dms\n",
+ dev->switch_latency);
PCIE_DBG_FS(dev, "wr_halt_size: 0x%x\n",
dev->wr_halt_size);
PCIE_DBG_FS(dev, "slv_addr_space_size: 0x%x\n",
@@ -1184,6 +1223,14 @@
static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
u32 testcase)
{
+ phys_addr_t dbi_base_addr =
+ dev->res[MSM_PCIE_RES_DM_CORE].resource->start;
+ phys_addr_t loopback_lbar_phy =
+ dbi_base_addr + LOOPBACK_BASE_ADDR_OFFSET;
+ static uint32_t loopback_val = 0x1;
+ static u64 loopback_ddr_phy;
+ static uint32_t *loopback_ddr_vir;
+ static void __iomem *loopback_lbar_vir;
int ret, i;
u32 base_sel_size = 0;
u32 val = 0;
@@ -1597,6 +1644,282 @@
readl_relaxed(dev->res[base_sel - 1].base + (i + 28)));
}
break;
+ case 14:
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: Allocate 4K DDR memory and map LBAR.\n",
+ dev->rc_idx);
+ loopback_ddr_vir = dma_alloc_coherent(&dev->pdev->dev,
+ (SZ_1K * sizeof(*loopback_ddr_vir)),
+ &loopback_ddr_phy, GFP_KERNEL);
+ if (!loopback_ddr_vir) {
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: failed to dma_alloc_coherent.\n",
+ dev->rc_idx);
+ } else {
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: VIR DDR memory address: 0x%pK\n",
+ dev->rc_idx, loopback_ddr_vir);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PHY DDR memory address: 0x%llx\n",
+ dev->rc_idx, loopback_ddr_phy);
+ }
+
+ PCIE_DBG_FS(dev, "PCIe: RC%d: map LBAR: 0x%llx\n",
+ dev->rc_idx, loopback_lbar_phy);
+ loopback_lbar_vir = devm_ioremap(&dev->pdev->dev,
+ loopback_lbar_phy, SZ_4K);
+ if (!loopback_lbar_vir) {
+ PCIE_DBG_FS(dev, "PCIe: RC%d: failed to map 0x%llx\n",
+ dev->rc_idx, loopback_lbar_phy);
+ } else {
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: successfully mapped 0x%llx to 0x%pK\n",
+ dev->rc_idx, loopback_lbar_phy,
+ loopback_lbar_vir);
+ }
+ break;
+ case 15:
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: Release 4K DDR memory and unmap LBAR.\n",
+ dev->rc_idx);
+
+ if (loopback_ddr_vir) {
+ dma_free_coherent(&dev->pdev->dev, SZ_4K,
+ loopback_ddr_vir, loopback_ddr_phy);
+ loopback_ddr_vir = NULL;
+ }
+
+ if (loopback_lbar_vir) {
+ devm_iounmap(&dev->pdev->dev,
+ loopback_lbar_vir);
+ loopback_lbar_vir = NULL;
+ }
+ break;
+ case 16:
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: Print DDR and LBAR addresses.\n",
+ dev->rc_idx);
+
+ if (!loopback_ddr_vir || !loopback_lbar_vir) {
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: DDR or LBAR address is not mapped\n",
+ dev->rc_idx);
+ break;
+ }
+
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PHY DDR address: 0x%llx\n",
+ dev->rc_idx, loopback_ddr_phy);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: VIR DDR address: 0x%pK\n",
+ dev->rc_idx, loopback_ddr_vir);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PHY LBAR address: 0x%llx\n",
+ dev->rc_idx, loopback_lbar_phy);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: VIR LBAR address: 0x%pK\n",
+ dev->rc_idx, loopback_lbar_vir);
+ break;
+ case 17:
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: Configure Loopback.\n",
+ dev->rc_idx);
+
+ writel_relaxed(0x10000,
+ dev->dm_core + PCIE20_GEN3_RELATED_REG);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: 0x%llx: 0x%x\n",
+ dev->rc_idx,
+ dbi_base_addr + PCIE20_GEN3_RELATED_REG,
+ readl_relaxed(dev->dm_core +
+ PCIE20_GEN3_RELATED_REG));
+
+ writel_relaxed(0x80000001,
+ dev->dm_core + PCIE20_PIPE_LOOPBACK_CONTROL);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: 0x%llx: 0x%x\n",
+ dev->rc_idx,
+ dbi_base_addr + PCIE20_PIPE_LOOPBACK_CONTROL,
+ readl_relaxed(dev->dm_core +
+ PCIE20_PIPE_LOOPBACK_CONTROL));
+
+ writel_relaxed(0x00010124,
+ dev->dm_core + PCIE20_PORT_LINK_CTRL_REG);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: 0x%llx: 0x%x\n",
+ dev->rc_idx,
+ dbi_base_addr + PCIE20_PORT_LINK_CTRL_REG,
+ readl_relaxed(dev->dm_core +
+ PCIE20_PORT_LINK_CTRL_REG));
+ break;
+ case 18:
+ PCIE_DBG_FS(dev, "PCIe: RC%d: Setup iATU.\n", dev->rc_idx);
+
+ if (!loopback_ddr_vir) {
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: DDR address is not mapped.\n",
+ dev->rc_idx);
+ break;
+ }
+
+ writel_relaxed(0x0, dev->dm_core + PCIE20_PLR_IATU_VIEWPORT);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PCIE20_PLR_IATU_VIEWPORT:\t0x%llx: 0x%x\n",
+ dev->rc_idx, dbi_base_addr + PCIE20_PLR_IATU_VIEWPORT,
+ readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_VIEWPORT));
+
+ writel_relaxed(0x0, dev->dm_core + PCIE20_PLR_IATU_CTRL1);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PCIE20_PLR_IATU_CTRL1:\t0x%llx: 0x%x\n",
+ dev->rc_idx, dbi_base_addr + PCIE20_PLR_IATU_CTRL1,
+ readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_CTRL1));
+
+ writel_relaxed(loopback_lbar_phy,
+ dev->dm_core + PCIE20_PLR_IATU_LBAR);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PCIE20_PLR_IATU_LBAR:\t0x%llx: 0x%x\n",
+ dev->rc_idx, dbi_base_addr + PCIE20_PLR_IATU_LBAR,
+ readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_LBAR));
+
+ writel_relaxed(0x0, dev->dm_core + PCIE20_PLR_IATU_UBAR);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PCIE20_PLR_IATU_UBAR:\t0x%llx: 0x%x\n",
+ dev->rc_idx, dbi_base_addr + PCIE20_PLR_IATU_UBAR,
+ readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_UBAR));
+
+ writel_relaxed(loopback_lbar_phy + 0xfff,
+ dev->dm_core + PCIE20_PLR_IATU_LAR);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PCIE20_PLR_IATU_LAR:\t0x%llx: 0x%x\n",
+ dev->rc_idx, dbi_base_addr + PCIE20_PLR_IATU_LAR,
+ readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_LAR));
+
+ writel_relaxed(loopback_ddr_phy,
+ dev->dm_core + PCIE20_PLR_IATU_LTAR);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PCIE20_PLR_IATU_LTAR:\t0x%llx: 0x%x\n",
+ dev->rc_idx, dbi_base_addr + PCIE20_PLR_IATU_LTAR,
+ readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_LTAR));
+
+ writel_relaxed(0, dev->dm_core + PCIE20_PLR_IATU_UTAR);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PCIE20_PLR_IATU_UTAR:\t0x%llx: 0x%x\n",
+ dev->rc_idx, dbi_base_addr + PCIE20_PLR_IATU_UTAR,
+ readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_UTAR));
+
+ writel_relaxed(0x80000000,
+ dev->dm_core + PCIE20_PLR_IATU_CTRL2);
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: PCIE20_PLR_IATU_CTRL2:\t0x%llx: 0x%x\n",
+ dev->rc_idx, dbi_base_addr + PCIE20_PLR_IATU_CTRL2,
+ readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_CTRL2));
+ break;
+ case 19:
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: Read DDR values.\n",
+ dev->rc_idx);
+
+ if (!loopback_ddr_vir) {
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: DDR is not mapped\n",
+ dev->rc_idx);
+ break;
+ }
+
+ for (i = 0; i < SZ_1K; i += 8) {
+ PCIE_DBG_FS(dev,
+ "0x%04x %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ i,
+ loopback_ddr_vir[i],
+ loopback_ddr_vir[i + 1],
+ loopback_ddr_vir[i + 2],
+ loopback_ddr_vir[i + 3],
+ loopback_ddr_vir[i + 4],
+ loopback_ddr_vir[i + 5],
+ loopback_ddr_vir[i + 6],
+ loopback_ddr_vir[i + 7]);
+ }
+ break;
+ case 20:
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: Read LBAR values.\n",
+ dev->rc_idx);
+
+ if (!loopback_lbar_vir) {
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: LBAR address is not mapped\n",
+ dev->rc_idx);
+ break;
+ }
+
+ for (i = 0; i < SZ_4K; i += 32) {
+ PCIE_DBG_FS(dev,
+ "0x%04x %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ i,
+ readl_relaxed(loopback_lbar_vir + i),
+ readl_relaxed(loopback_lbar_vir + (i + 4)),
+ readl_relaxed(loopback_lbar_vir + (i + 8)),
+ readl_relaxed(loopback_lbar_vir + (i + 12)),
+ readl_relaxed(loopback_lbar_vir + (i + 16)),
+ readl_relaxed(loopback_lbar_vir + (i + 20)),
+ readl_relaxed(loopback_lbar_vir + (i + 24)),
+ readl_relaxed(loopback_lbar_vir + (i + 28)));
+ }
+ break;
+ case 21:
+ PCIE_DBG_FS(dev, "PCIe: RC%d: Write 0x%x to DDR.\n",
+ dev->rc_idx, loopback_val);
+
+ if (!loopback_ddr_vir) {
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: DDR address is not mapped\n",
+ dev->rc_idx);
+ break;
+ }
+
+ memset(loopback_ddr_vir, loopback_val,
+ (SZ_1K * sizeof(*loopback_ddr_vir)));
+
+ if (unlikely(loopback_val == UINT_MAX))
+ loopback_val = 1;
+ else
+ loopback_val++;
+ break;
+ case 22:
+ PCIE_DBG_FS(dev, "PCIe: RC%d: Write 0x%x to LBAR.\n",
+ dev->rc_idx, loopback_val);
+
+ if (!loopback_lbar_vir) {
+ PCIE_DBG_FS(dev,
+ "PCIe: RC%d: LBAR address is not mapped\n",
+ dev->rc_idx);
+ break;
+ }
+
+ for (i = 0; i < SZ_4K; i += 32) {
+ writel_relaxed(loopback_val,
+ loopback_lbar_vir + i),
+ writel_relaxed(loopback_val,
+ loopback_lbar_vir + (i + 4)),
+ writel_relaxed(loopback_val,
+ loopback_lbar_vir + (i + 8)),
+ writel_relaxed(loopback_val,
+ loopback_lbar_vir + (i + 12)),
+ writel_relaxed(loopback_val,
+ loopback_lbar_vir + (i + 16)),
+ writel_relaxed(loopback_val,
+ loopback_lbar_vir + (i + 20)),
+ writel_relaxed(loopback_val,
+ loopback_lbar_vir + (i + 24)),
+ writel_relaxed(loopback_val,
+ loopback_lbar_vir + (i + 28));
+ }
+
+ if (unlikely(loopback_val == UINT_MAX))
+ loopback_val = 1;
+ else
+ loopback_val++;
+ break;
default:
PCIE_DBG_FS(dev, "Invalid testcase: %d.\n", testcase);
break;
@@ -3622,6 +3945,7 @@
uint32_t val;
long int retries = 0;
int link_check_count = 0;
+ unsigned long ep_up_timeout = 0;
PCIE_DBG(dev, "RC%d: entry\n", dev->rc_idx);
@@ -3782,6 +4106,8 @@
1 - dev->gpio[MSM_PCIE_GPIO_PERST].on);
usleep_range(dev->perst_delay_us_min, dev->perst_delay_us_max);
+ ep_up_timeout = jiffies + usecs_to_jiffies(EP_UP_TIMEOUT_US);
+
/* setup Gen3 specific configurations */
if (dev->max_link_speed == GEN3_SPEED)
msm_pcie_setup_gen3(dev);
@@ -3821,8 +4147,45 @@
goto link_fail;
}
+ dev->link_status = MSM_PCIE_LINK_ENABLED;
+ dev->power_on = true;
+ dev->suspending = false;
+ dev->link_turned_on_counter++;
+
+ if (dev->switch_latency) {
+ PCIE_DBG(dev, "switch_latency: %dms\n",
+ dev->switch_latency);
+ if (dev->switch_latency <= SWITCH_DELAY_MAX)
+ usleep_range(dev->switch_latency * 1000,
+ dev->switch_latency * 1000);
+ else
+ msleep(dev->switch_latency);
+ }
+
msm_pcie_config_controller(dev);
+ /* check endpoint configuration space is accessible */
+ while (time_before(jiffies, ep_up_timeout)) {
+ if (readl_relaxed(dev->conf) != PCIE_LINK_DOWN)
+ break;
+ usleep_range(EP_UP_TIMEOUT_US_MIN, EP_UP_TIMEOUT_US_MAX);
+ }
+
+ if (readl_relaxed(dev->conf) != PCIE_LINK_DOWN) {
+ PCIE_DBG(dev,
+ "PCIe: RC%d: endpoint config space is accessible\n",
+ dev->rc_idx);
+ } else {
+ PCIE_ERR(dev,
+ "PCIe: RC%d: endpoint config space is not accessible\n",
+ dev->rc_idx);
+ dev->link_status = MSM_PCIE_LINK_DISABLED;
+ dev->power_on = false;
+ dev->link_turned_off_counter++;
+ ret = -ENODEV;
+ goto link_fail;
+ }
+
if (!dev->msi_gicm_addr)
msm_pcie_config_msi_controller(dev);
@@ -3831,14 +4194,12 @@
if (dev->enumerated)
pci_walk_bus(dev->dev->bus, &msm_pcie_config_device, dev);
- dev->link_status = MSM_PCIE_LINK_ENABLED;
- dev->power_on = true;
- dev->suspending = false;
- dev->link_turned_on_counter++;
-
goto out;
link_fail:
+ if (msm_pcie_keep_resources_on & BIT(dev->rc_idx))
+ goto out;
+
if (dev->gpio[MSM_PCIE_GPIO_EP].num)
gpio_set_value(dev->gpio[MSM_PCIE_GPIO_EP].num,
1 - dev->gpio[MSM_PCIE_GPIO_EP].on);
@@ -4032,8 +4393,9 @@
if (pcie_dev->num_ep > 1)
pcie_dev->pending_ep_reg = true;
- msm_pcie_config_ep_aer(pcie_dev,
- &dev_table_t[index]);
+ if (pcie_dev->aer_enable)
+ msm_pcie_config_ep_aer(pcie_dev,
+ &dev_table_t[index]);
break;
}
@@ -4547,8 +4909,10 @@
panic("User has chosen to panic on linkdown\n");
/* assert PERST */
- gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
- dev->gpio[MSM_PCIE_GPIO_PERST].on);
+ if (!(msm_pcie_keep_resources_on & BIT(dev->rc_idx)))
+ gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num,
+ dev->gpio[MSM_PCIE_GPIO_PERST].on);
+
PCIE_ERR(dev, "PCIe link is down for RC%d\n", dev->rc_idx);
if (dev->num_ep > 1) {
@@ -5251,16 +5615,25 @@
msm_pcie_dev[rc_idx].l0s_supported =
of_property_read_bool((&pdev->dev)->of_node,
"qcom,l0s-supported");
+ if (msm_pcie_invert_l0s_support & BIT(rc_idx))
+ msm_pcie_dev[rc_idx].l0s_supported =
+ !msm_pcie_dev[rc_idx].l0s_supported;
PCIE_DBG(&msm_pcie_dev[rc_idx], "L0s is %s supported.\n",
msm_pcie_dev[rc_idx].l0s_supported ? "" : "not");
msm_pcie_dev[rc_idx].l1_supported =
of_property_read_bool((&pdev->dev)->of_node,
"qcom,l1-supported");
+ if (msm_pcie_invert_l1_support & BIT(rc_idx))
+ msm_pcie_dev[rc_idx].l1_supported =
+ !msm_pcie_dev[rc_idx].l1_supported;
PCIE_DBG(&msm_pcie_dev[rc_idx], "L1 is %s supported.\n",
msm_pcie_dev[rc_idx].l1_supported ? "" : "not");
msm_pcie_dev[rc_idx].l1ss_supported =
of_property_read_bool((&pdev->dev)->of_node,
"qcom,l1ss-supported");
+ if (msm_pcie_invert_l1ss_support & BIT(rc_idx))
+ msm_pcie_dev[rc_idx].l1ss_supported =
+ !msm_pcie_dev[rc_idx].l1ss_supported;
PCIE_DBG(&msm_pcie_dev[rc_idx], "L1ss is %s supported.\n",
msm_pcie_dev[rc_idx].l1ss_supported ? "" : "not");
msm_pcie_dev[rc_idx].common_clk_en =
@@ -5366,6 +5739,20 @@
PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: ep-latency: 0x%x.\n",
rc_idx, msm_pcie_dev[rc_idx].ep_latency);
+ msm_pcie_dev[rc_idx].switch_latency = 0;
+ ret = of_property_read_u32((&pdev->dev)->of_node,
+ "qcom,switch-latency",
+ &msm_pcie_dev[rc_idx].switch_latency);
+
+ if (ret)
+ PCIE_DBG(&msm_pcie_dev[rc_idx],
+ "RC%d: switch-latency does not exist.\n",
+ rc_idx);
+ else
+ PCIE_DBG(&msm_pcie_dev[rc_idx],
+ "RC%d: switch-latency: 0x%x.\n",
+ rc_idx, msm_pcie_dev[rc_idx].switch_latency);
+
msm_pcie_dev[rc_idx].wr_halt_size = 0;
ret = of_property_read_u32(pdev->dev.of_node,
"qcom,wr-halt-size",
@@ -5500,6 +5887,8 @@
msm_pcie_dev[rc_idx].suspending = false;
msm_pcie_dev[rc_idx].wake_counter = 0;
msm_pcie_dev[rc_idx].aer_enable = true;
+ if (msm_pcie_invert_aer_support)
+ msm_pcie_dev[rc_idx].aer_enable = false;
msm_pcie_dev[rc_idx].power_on = false;
msm_pcie_dev[rc_idx].use_msi = false;
msm_pcie_dev[rc_idx].use_pinctrl = false;
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 13e9a0d..e63f1a0 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
@@ -747,11 +748,46 @@
.irq_set_wake = msm_gpio_irq_set_wake,
};
+static bool is_gpio_dual_edge(struct irq_data *d, irq_hw_number_t *dir_conn_irq)
+{
+ struct irq_desc *desc = irq_data_to_desc(d);
+ struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq);
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
+ int i;
+
+ if (!parent_data)
+ return false;
+
+ for (i = 0; i < pctrl->soc->n_dir_conns; i++) {
+ const struct msm_dir_conn *dir_conn = &pctrl->soc->dir_conn[i];
+
+ if (dir_conn->gpio == d->hwirq && (dir_conn->hwirq + 32)
+ != parent_data->hwirq) {
+ *dir_conn_irq = dir_conn->hwirq + 32;
+ return true;
+ }
+ }
+ return false;
+}
+
static void msm_dirconn_irq_mask(struct irq_data *d)
{
struct irq_desc *desc = irq_data_to_desc(d);
struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq);
+ irq_hw_number_t dir_conn_irq = 0;
+ if (!parent_data)
+ return;
+
+ if (is_gpio_dual_edge(d, &dir_conn_irq)) {
+ struct irq_data *dir_conn_data =
+ irq_get_irq_data(irq_find_mapping(parent_data->domain,
+ dir_conn_irq));
+
+ if (dir_conn_data && dir_conn_data->chip->irq_mask)
+ dir_conn_data->chip->irq_mask(dir_conn_data);
+ }
if (parent_data->chip->irq_mask)
parent_data->chip->irq_mask(parent_data);
}
@@ -760,7 +796,19 @@
{
struct irq_desc *desc = irq_data_to_desc(d);
struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq);
+ irq_hw_number_t dir_conn_irq = 0;
+ if (!parent_data)
+ return;
+
+ if (is_gpio_dual_edge(d, &dir_conn_irq)) {
+ struct irq_data *dir_conn_data =
+ irq_get_irq_data(irq_find_mapping(parent_data->domain,
+ dir_conn_irq));
+
+ if (dir_conn_data && dir_conn_data->chip->irq_unmask)
+ dir_conn_data->chip->irq_unmask(dir_conn_data);
+ }
if (parent_data->chip->irq_unmask)
parent_data->chip->irq_unmask(parent_data);
}
@@ -789,6 +837,9 @@
struct irq_desc *desc = irq_data_to_desc(d);
struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq);
+ if (!parent_data)
+ return 0;
+
if (parent_data->chip->irq_set_affinity)
return parent_data->chip->irq_set_affinity(parent_data,
maskval, force);
@@ -807,10 +858,158 @@
return 0;
}
+static void msm_dirconn_cfg_reg(struct irq_data *d, u32 offset)
+{
+ u32 val = 0;
+ const struct msm_pingroup *g;
+ unsigned long flags;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
+
+ spin_lock_irqsave(&pctrl->lock, flags);
+ g = &pctrl->soc->groups[d->hwirq];
+
+ val = readl_relaxed(pctrl->regs + g->dir_conn_reg + (offset * 4));
+ val = (d->hwirq) & 0xFF;
+
+ writel_relaxed(val, pctrl->regs + g->dir_conn_reg + (offset * 4));
+
+ //write the dir_conn_en bit
+ val = readl_relaxed(pctrl->regs + g->intr_cfg_reg);
+ val |= BIT(g->dir_conn_en_bit);
+ writel_relaxed(val, pctrl->regs + g->intr_cfg_reg);
+ spin_unlock_irqrestore(&pctrl->lock, flags);
+}
+
+static void msm_dirconn_uncfg_reg(struct irq_data *d, u32 offset)
+{
+ const struct msm_pingroup *g;
+ unsigned long flags;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
+
+ spin_lock_irqsave(&pctrl->lock, flags);
+ g = &pctrl->soc->groups[d->hwirq];
+
+ writel_relaxed(BIT(8), pctrl->regs + g->dir_conn_reg + (offset * 4));
+ spin_unlock_irqrestore(&pctrl->lock, flags);
+}
+
+static int select_dir_conn_mux(struct irq_data *d, irq_hw_number_t *irq)
+{
+ struct msm_dir_conn *dc = NULL;
+ struct irq_desc *desc = irq_data_to_desc(d);
+ struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq);
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
+ int i;
+
+ if (!parent_data)
+ return -EINVAL;
+
+ for (i = 0; i < pctrl->soc->n_dir_conns; i++) {
+ struct msm_dir_conn *dir_conn =
+ (struct msm_dir_conn *)&pctrl->soc->dir_conn[i];
+
+ /* Check if there is already mux assigned for this gpio */
+ if (dir_conn->gpio == d->hwirq && (dir_conn->hwirq + 32) !=
+ parent_data->hwirq) {
+ *irq = dir_conn->hwirq + 32;
+ return pctrl->soc->dir_conn_irq_base - dir_conn->hwirq;
+ }
+
+ if (dir_conn->gpio)
+ continue;
+
+ /* Use the first unused direct connect available */
+ dc = dir_conn;
+ break;
+ }
+
+ if (dc) {
+ *irq = dc->hwirq + 32;
+ dc->gpio = (u32)d->hwirq;
+ return pctrl->soc->dir_conn_irq_base - (u32)dc->hwirq;
+ }
+
+ pr_err("%s: No direct connects available for interrupt %lu\n",
+ __func__, d->hwirq);
+ return -EINVAL;
+}
+
+static void add_dirconn_tlmm(struct irq_data *d, irq_hw_number_t irq)
+{
+ struct irq_desc *desc = irq_data_to_desc(d);
+ struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq);
+ struct irq_data *dir_conn_data = NULL;
+ int offset = 0;
+ unsigned int virt = 0;
+
+ offset = select_dir_conn_mux(d, &irq);
+ if (offset < 0 || !parent_data)
+ return;
+
+ virt = irq_find_mapping(parent_data->domain, irq);
+ msm_dirconn_cfg_reg(d, offset);
+ irq_set_handler_data(virt, d);
+ desc = irq_to_desc(virt);
+ if (!desc)
+ return;
+
+ dir_conn_data = &(desc->irq_data);
+
+ if (dir_conn_data) {
+ if (dir_conn_data->chip && dir_conn_data->chip->irq_set_type)
+ dir_conn_data->chip->irq_set_type(dir_conn_data,
+ IRQ_TYPE_EDGE_RISING);
+ if (dir_conn_data->chip && dir_conn_data->chip->irq_unmask)
+ dir_conn_data->chip->irq_unmask(dir_conn_data);
+ }
+}
+
+static void remove_dirconn_tlmm(struct irq_data *d, irq_hw_number_t irq)
+{
+ struct irq_desc *desc = irq_data_to_desc(d);
+ struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq);
+ struct irq_data *dir_conn_data = NULL;
+ int offset = 0;
+ unsigned int virt = 0;
+
+ virt = irq_find_mapping(parent_data->domain, irq);
+ msm_dirconn_uncfg_reg(d, offset);
+ irq_set_handler_data(virt, NULL);
+ desc = irq_to_desc(virt);
+ if (!desc)
+ return;
+
+ dir_conn_data = &(desc->irq_data);
+
+ if (dir_conn_data) {
+ if (dir_conn_data->chip && dir_conn_data->chip->irq_mask)
+ dir_conn_data->chip->irq_mask(dir_conn_data);
+ }
+}
+
static int msm_dirconn_irq_set_type(struct irq_data *d, unsigned int type)
{
struct irq_desc *desc = irq_data_to_desc(d);
struct irq_data *parent_data = irq_get_irq_data(desc->parent_irq);
+ irq_hw_number_t irq = 0;
+
+ if (!parent_data)
+ return 0;
+
+ if (type == IRQ_TYPE_EDGE_BOTH) {
+ add_dirconn_tlmm(d, irq);
+ } else {
+ if (is_gpio_dual_edge(d, &irq))
+ remove_dirconn_tlmm(d, irq);
+ }
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+ irq_set_handler_locked(d, handle_level_irq);
+ else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
+ irq_set_handler_locked(d, handle_edge_irq);
if (parent_data->chip->irq_set_type)
return parent_data->chip->irq_set_type(parent_data, type);
@@ -904,14 +1103,19 @@
fwspec.param_count = 3;
parent_irq = irq_create_fwspec_mapping(&fwspec);
- irq = irq_find_mapping(pctrl->chip.irqdomain, dirconn->gpio);
+ if (dirconn->gpio != 0) {
+ irq = irq_find_mapping(pctrl->chip.irqdomain,
+ dirconn->gpio);
- irq_set_parent(irq, parent_irq);
- irq_set_chip(irq, &msm_dirconn_irq_chip);
- irq_set_chip_data(irq, irq_get_irq_data(parent_irq));
- __irq_set_handler(parent_irq, msm_gpio_dirconn_handler,
+ irq_set_parent(irq, parent_irq);
+ irq_set_chip(irq, &msm_dirconn_irq_chip);
+ __irq_set_handler(parent_irq, msm_gpio_dirconn_handler,
false, NULL);
- irq_set_handler_data(parent_irq, irq_get_irq_data(irq));
+ irq_set_handler_data(parent_irq, irq_get_irq_data(irq));
+ } else {
+ __irq_set_handler(parent_irq, msm_gpio_dirconn_handler,
+ false, NULL);
+ }
}
}
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 988b7ca..1c6df2f 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -43,6 +43,8 @@
* @intr_status_reg: Offset of the register holding the status bits for this group.
* @intr_target_reg: Offset of the register specifying routing of the interrupts
* from this group.
+ * @dir_conn_reg: Offset of the register specifying direct connect
+ * setup of this group.
* @mux_bit: Offset in @ctl_reg for the pinmux function selection.
* @pull_bit: Offset in @ctl_reg for the bias configuration.
* @drv_bit: Offset in @ctl_reg for the drive strength configuration.
@@ -75,6 +77,7 @@
u32 intr_cfg_reg;
u32 intr_status_reg;
u32 intr_target_reg;
+ u32 dir_conn_reg;
unsigned mux_bit:5;
@@ -95,6 +98,7 @@
unsigned intr_polarity_bit:5;
unsigned intr_detection_bit:5;
unsigned intr_detection_width:5;
+ unsigned dir_conn_en_bit:8;
}
/**
@@ -118,6 +122,8 @@
* @ngpio: The number of pingroups the driver should expose as GPIOs.
* @dir_conn: An array describing all the pins directly connected to GIC.
* @ndirconns: The number of pins directly connected to GIC
+ * @dir_conn_offsets: Direct connect register offsets for each tile.
+ * @dir_conn_irq_base: Direct connect interrupt base register for kpss.
*/
struct msm_pinctrl_soc_data {
const struct pinctrl_pin_desc *pins;
@@ -129,6 +135,7 @@
unsigned ngpios;
const struct msm_dir_conn *dir_conn;
unsigned int n_dir_conns;
+ unsigned int dir_conn_irq_base;
};
int msm_pinctrl_probe(struct platform_device *pdev,
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845-v2.c b/drivers/pinctrl/qcom/pinctrl-sdm845-v2.c
index f7d551e..e77dcd9 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845-v2.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845-v2.c
@@ -53,6 +53,8 @@
.intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
.intr_status_reg = base + 0xc + REG_SIZE * id, \
.intr_target_reg = base + 0x8 + REG_SIZE * id, \
+ .dir_conn_reg = (base == NORTH) ? base + 0xa4000 : \
+ ((base == SOUTH) ? base + 0xa8000 : base + 0x9e000), \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@@ -67,6 +69,7 @@
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
+ .dir_conn_en_bit = 8, \
}
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
@@ -1689,7 +1692,7 @@
{24, 517},
{26, 518},
{30, 519},
- {31, 639},
+ {31, 632},
{32, 521},
{34, 522},
{36, 523},
@@ -1697,12 +1700,12 @@
{38, 525},
{39, 526},
{40, 527},
- {41, 637},
+ {41, 630},
{43, 529},
{44, 530},
{46, 531},
{48, 532},
- {49, 640},
+ {49, 633 },
{52, 534},
{53, 535},
{54, 536},
@@ -1727,7 +1730,7 @@
{85, 555},
{86, 556},
{88, 557},
- {89, 638},
+ {89, 631},
{91, 559},
{92, 560},
{95, 561},
@@ -1747,6 +1750,7 @@
{123, 613},
{124, 614},
{125, 615},
+ {126, 616},
{127, 617},
{128, 618},
{129, 619},
@@ -1754,6 +1758,14 @@
{132, 621},
{133, 622},
{145, 623},
+ {0, 216},
+ {0, 215},
+ {0, 214},
+ {0, 213},
+ {0, 212},
+ {0, 211},
+ {0, 210},
+ {0, 209},
};
static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
@@ -1766,6 +1778,7 @@
.ngpios = 150,
.dir_conn = sdm845_dir_conn,
.n_dir_conns = ARRAY_SIZE(sdm845_dir_conn),
+ .dir_conn_irq_base = 216,
};
static int sdm845_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index b7e06b6..ee5bd19 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -52,6 +52,8 @@
.intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
.intr_status_reg = base + 0xc + REG_SIZE * id, \
.intr_target_reg = base + 0x8 + REG_SIZE * id, \
+ .dir_conn_reg = (base == NORTH) ? base + 0xa5000 :\
+ base + 0xa8000, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
@@ -66,6 +68,7 @@
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
+ .dir_conn_en_bit = 8, \
}
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
@@ -117,6 +120,7 @@
.intr_detection_bit = -1, \
.intr_detection_width = -1, \
}
+
static const struct pinctrl_pin_desc sdm845_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
@@ -1648,7 +1652,7 @@
[153] = UFS_RESET(ufs_reset, 0x99f000),
};
-static const struct msm_dir_conn sdm845_dir_conn[] = {
+static struct msm_dir_conn sdm845_dir_conn[] = {
{1, 510},
{3, 511},
{5, 512},
@@ -1659,7 +1663,7 @@
{24, 517},
{26, 518},
{30, 519},
- {31, 639},
+ {31, 632},
{32, 521},
{34, 522},
{36, 523},
@@ -1667,12 +1671,12 @@
{38, 525},
{39, 526},
{40, 527},
- {41, 637},
+ {41, 630},
{43, 529},
{44, 530},
{46, 531},
{48, 532},
- {49, 640},
+ {49, 633},
{52, 534},
{53, 535},
{54, 536},
@@ -1697,7 +1701,7 @@
{85, 555},
{86, 556},
{88, 557},
- {89, 638},
+ {89, 631},
{91, 559},
{92, 560},
{95, 561},
@@ -1717,6 +1721,7 @@
{123, 613},
{124, 614},
{125, 615},
+ {126, 616},
{127, 617},
{128, 618},
{129, 619},
@@ -1724,6 +1729,14 @@
{132, 621},
{133, 622},
{145, 623},
+ {0, 216},
+ {0, 215},
+ {0, 214},
+ {0, 213},
+ {0, 212},
+ {0, 211},
+ {0, 210},
+ {0, 209},
};
static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
@@ -1736,6 +1749,7 @@
.ngpios = 150,
.dir_conn = sdm845_dir_conn,
.n_dir_conns = ARRAY_SIZE(sdm845_dir_conn),
+ .dir_conn_irq_base = 216,
};
static int sdm845_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/platform/msm/ipa/ipa_api.c b/drivers/platform/msm/ipa/ipa_api.c
index 4a9232e..abb714d 100644
--- a/drivers/platform/msm/ipa/ipa_api.c
+++ b/drivers/platform/msm/ipa/ipa_api.c
@@ -3004,6 +3004,57 @@
}
EXPORT_SYMBOL(ipa_ntn_uc_dereg_rdyCB);
+/**
+ * ipa_conn_wdi3_pipes() - connect wdi3 pipes
+ */
+int ipa_conn_wdi3_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out)
+{
+ int ret;
+
+ IPA_API_DISPATCH_RETURN(ipa_conn_wdi3_pipes, in, out);
+
+ return ret;
+}
+
+/**
+ * ipa_disconn_wdi3_pipes() - disconnect wdi3 pipes
+ */
+int ipa_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ int ret;
+
+ IPA_API_DISPATCH_RETURN(ipa_disconn_wdi3_pipes, ipa_ep_idx_tx,
+ ipa_ep_idx_rx);
+
+ return ret;
+}
+
+/**
+ * ipa_enable_wdi3_pipes() - enable wdi3 pipes
+ */
+int ipa_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ int ret;
+
+ IPA_API_DISPATCH_RETURN(ipa_enable_wdi3_pipes, ipa_ep_idx_tx,
+ ipa_ep_idx_rx);
+
+ return ret;
+}
+
+/**
+ * ipa_disable_wdi3_pipes() - disable wdi3 pipes
+ */
+int ipa_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ int ret;
+
+ IPA_API_DISPATCH_RETURN(ipa_disable_wdi3_pipes, ipa_ep_idx_tx,
+ ipa_ep_idx_rx);
+
+ return ret;
+}
static const struct dev_pm_ops ipa_pm_ops = {
.suspend_noirq = ipa_ap_suspend,
diff --git a/drivers/platform/msm/ipa/ipa_api.h b/drivers/platform/msm/ipa/ipa_api.h
index 20471eb..7a48b68 100644
--- a/drivers/platform/msm/ipa/ipa_api.h
+++ b/drivers/platform/msm/ipa/ipa_api.h
@@ -12,6 +12,7 @@
#include <linux/ipa_mhi.h>
#include <linux/ipa_uc_offload.h>
+#include <linux/ipa_wdi3.h>
#include "ipa_common_i.h"
#ifndef _IPA_API_H_
@@ -385,6 +386,18 @@
void *user_data);
void (*ipa_ntn_uc_dereg_rdyCB)(void);
+
+ int (*ipa_conn_wdi3_pipes)(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out);
+
+ int (*ipa_disconn_wdi3_pipes)(int ipa_ep_idx_tx,
+ int ipa_ep_idx_rx);
+
+ int (*ipa_enable_wdi3_pipes)(int ipa_ep_idx_tx,
+ int ipa_ep_idx_rx);
+
+ int (*ipa_disable_wdi3_pipes)(int ipa_ep_idx_tx,
+ int ipa_ep_idx_rx);
};
#ifdef CONFIG_IPA
diff --git a/drivers/platform/msm/ipa/ipa_clients/Makefile b/drivers/platform/msm/ipa/ipa_clients/Makefile
index 61625f5..738d88f 100644
--- a/drivers/platform/msm/ipa/ipa_clients/Makefile
+++ b/drivers/platform/msm/ipa/ipa_clients/Makefile
@@ -1,4 +1,4 @@
-obj-$(CONFIG_IPA3) += ipa_usb.o odu_bridge.o ipa_mhi_client.o ipa_uc_offload.o
-obj-$(CONFIG_IPA) += odu_bridge.o ipa_mhi_client.o ipa_uc_offload.o
+obj-$(CONFIG_IPA3) += ipa_usb.o odu_bridge.o ipa_mhi_client.o ipa_uc_offload.o ipa_wdi3.o
+obj-$(CONFIG_IPA) += odu_bridge.o ipa_mhi_client.o ipa_uc_offload.o ipa_wdi3.o
obj-$(CONFIG_ECM_IPA) += ecm_ipa.o
obj-$(CONFIG_RNDIS_IPA) += rndis_ipa.o
diff --git a/drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c b/drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c
new file mode 100644
index 0000000..f4c8763
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_clients/ipa_wdi3.c
@@ -0,0 +1,526 @@
+/* Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/ipa_wdi3.h>
+#include <linux/msm_ipa.h>
+#include <linux/string.h>
+#include "../ipa_common_i.h"
+
+#define OFFLOAD_DRV_NAME "ipa_wdi3"
+#define IPA_WDI3_DBG(fmt, args...) \
+ do { \
+ pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \
+ __func__, __LINE__, ## args); \
+ IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \
+ OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \
+ IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \
+ OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \
+ } while (0)
+
+#define IPA_WDI3_DBG_LOW(fmt, args...) \
+ do { \
+ pr_debug(OFFLOAD_DRV_NAME " %s:%d " fmt, \
+ __func__, __LINE__, ## args); \
+ IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \
+ OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \
+ } while (0)
+
+#define IPA_WDI3_ERR(fmt, args...) \
+ do { \
+ pr_err(OFFLOAD_DRV_NAME " %s:%d " fmt, \
+ __func__, __LINE__, ## args); \
+ IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \
+ OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \
+ IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \
+ OFFLOAD_DRV_NAME " %s:%d " fmt, ## args); \
+ } while (0)
+
+struct ipa_wdi3_intf_info {
+ char netdev_name[IPA_RESOURCE_NAME_MAX];
+ u8 hdr_len;
+ u32 partial_hdr_hdl[IPA_IP_MAX];
+ struct list_head link;
+};
+
+struct ipa_wdi3_context {
+ struct list_head head_intf_list;
+ ipa_notify_cb notify;
+ void *priv;
+ struct completion wdi3_completion;
+ struct mutex lock;
+};
+
+static struct ipa_wdi3_context *ipa_wdi3_ctx;
+
+static int ipa_wdi3_commit_partial_hdr(
+ struct ipa_ioc_add_hdr *hdr,
+ const char *netdev_name,
+ struct ipa_wdi3_hdr_info *hdr_info)
+{
+ int i;
+
+ if (!hdr || !hdr_info || !netdev_name) {
+ IPA_WDI3_ERR("Invalid input\n");
+ return -EINVAL;
+ }
+
+ hdr->commit = 1;
+ hdr->num_hdrs = 2;
+
+ snprintf(hdr->hdr[0].name, sizeof(hdr->hdr[0].name),
+ "%s_ipv4", netdev_name);
+ snprintf(hdr->hdr[1].name, sizeof(hdr->hdr[1].name),
+ "%s_ipv6", netdev_name);
+ for (i = IPA_IP_v4; i < IPA_IP_MAX; i++) {
+ hdr->hdr[i].hdr_len = hdr_info[i].hdr_len;
+ memcpy(hdr->hdr[i].hdr, hdr_info[i].hdr, hdr->hdr[i].hdr_len);
+ hdr->hdr[i].type = hdr_info[i].hdr_type;
+ hdr->hdr[i].is_partial = 1;
+ hdr->hdr[i].is_eth2_ofst_valid = 1;
+ hdr->hdr[i].eth2_ofst = hdr_info[i].dst_mac_addr_offset;
+ }
+
+ if (ipa_add_hdr(hdr)) {
+ IPA_WDI3_ERR("fail to add partial headers\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+int ipa_wdi3_reg_intf(struct ipa_wdi3_reg_intf_in_params *in)
+{
+ struct ipa_ioc_add_hdr *hdr;
+ struct ipa_wdi3_intf_info *new_intf;
+ struct ipa_wdi3_intf_info *entry;
+ struct ipa_tx_intf tx;
+ struct ipa_rx_intf rx;
+ struct ipa_ioc_tx_intf_prop tx_prop[2];
+ struct ipa_ioc_rx_intf_prop rx_prop[2];
+ u32 len;
+ int ret = 0;
+
+ if (in == NULL) {
+ IPA_WDI3_ERR("invalid params in=%pK\n", in);
+ return -EINVAL;
+ }
+
+ if (!ipa_wdi3_ctx) {
+ ipa_wdi3_ctx = kzalloc(sizeof(*ipa_wdi3_ctx), GFP_KERNEL);
+ if (ipa_wdi3_ctx == NULL) {
+ IPA_WDI3_ERR("fail to alloc wdi3 ctx\n");
+ return -ENOMEM;
+ }
+ mutex_init(&ipa_wdi3_ctx->lock);
+ INIT_LIST_HEAD(&ipa_wdi3_ctx->head_intf_list);
+ }
+
+ IPA_WDI3_DBG("register interface for netdev %s\n",
+ in->netdev_name);
+
+ mutex_lock(&ipa_wdi3_ctx->lock);
+ list_for_each_entry(entry, &ipa_wdi3_ctx->head_intf_list, link)
+ if (strcmp(entry->netdev_name, in->netdev_name) == 0) {
+ IPA_WDI3_DBG("intf was added before.\n");
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return 0;
+ }
+
+ IPA_WDI3_DBG("intf was not added before, proceed.\n");
+ new_intf = kzalloc(sizeof(*new_intf), GFP_KERNEL);
+ if (new_intf == NULL) {
+ IPA_WDI3_ERR("fail to alloc new intf\n");
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return -ENOMEM;
+ }
+
+ INIT_LIST_HEAD(&new_intf->link);
+ strlcpy(new_intf->netdev_name, in->netdev_name,
+ sizeof(new_intf->netdev_name));
+ new_intf->hdr_len = in->hdr_info[0].hdr_len;
+
+ /* add partial header */
+ len = sizeof(struct ipa_ioc_add_hdr) + 2 * sizeof(struct ipa_hdr_add);
+ hdr = kzalloc(len, GFP_KERNEL);
+ if (hdr == NULL) {
+ IPA_WDI3_ERR("fail to alloc %d bytes\n", len);
+ ret = -EFAULT;
+ goto fail_alloc_hdr;
+ }
+
+ if (ipa_wdi3_commit_partial_hdr(hdr, in->netdev_name, in->hdr_info)) {
+ IPA_WDI3_ERR("fail to commit partial headers\n");
+ ret = -EFAULT;
+ goto fail_commit_hdr;
+ }
+
+ new_intf->partial_hdr_hdl[IPA_IP_v4] = hdr->hdr[IPA_IP_v4].hdr_hdl;
+ new_intf->partial_hdr_hdl[IPA_IP_v6] = hdr->hdr[IPA_IP_v6].hdr_hdl;
+ IPA_WDI3_DBG("IPv4 hdr hdl: %d IPv6 hdr hdl: %d\n",
+ hdr->hdr[IPA_IP_v4].hdr_hdl, hdr->hdr[IPA_IP_v6].hdr_hdl);
+
+ /* populate tx prop */
+ tx.num_props = 2;
+ tx.prop = tx_prop;
+
+ memset(tx_prop, 0, sizeof(tx_prop));
+ tx_prop[0].ip = IPA_IP_v4;
+ tx_prop[0].dst_pipe = IPA_CLIENT_WLAN1_CONS;
+ tx_prop[0].hdr_l2_type = in->hdr_info[0].hdr_type;
+ strlcpy(tx_prop[0].hdr_name, hdr->hdr[IPA_IP_v4].name,
+ sizeof(tx_prop[0].hdr_name));
+
+ tx_prop[1].ip = IPA_IP_v6;
+ tx_prop[1].dst_pipe = IPA_CLIENT_WLAN1_CONS;
+ tx_prop[1].hdr_l2_type = in->hdr_info[1].hdr_type;
+ strlcpy(tx_prop[1].hdr_name, hdr->hdr[IPA_IP_v6].name,
+ sizeof(tx_prop[1].hdr_name));
+
+ /* populate rx prop */
+ rx.num_props = 2;
+ rx.prop = rx_prop;
+
+ memset(rx_prop, 0, sizeof(rx_prop));
+ rx_prop[0].ip = IPA_IP_v4;
+ rx_prop[0].src_pipe = IPA_CLIENT_WLAN1_PROD;
+ rx_prop[0].hdr_l2_type = in->hdr_info[0].hdr_type;
+ if (in->is_meta_data_valid) {
+ rx_prop[0].attrib.attrib_mask |= IPA_FLT_META_DATA;
+ rx_prop[0].attrib.meta_data = in->meta_data;
+ rx_prop[0].attrib.meta_data_mask = in->meta_data_mask;
+ }
+
+ rx_prop[1].ip = IPA_IP_v6;
+ rx_prop[1].src_pipe = IPA_CLIENT_WLAN1_PROD;
+ rx_prop[1].hdr_l2_type = in->hdr_info[1].hdr_type;
+ if (in->is_meta_data_valid) {
+ rx_prop[1].attrib.attrib_mask |= IPA_FLT_META_DATA;
+ rx_prop[1].attrib.meta_data = in->meta_data;
+ rx_prop[1].attrib.meta_data_mask = in->meta_data_mask;
+ }
+
+ if (ipa_register_intf(in->netdev_name, &tx, &rx)) {
+ IPA_WDI3_ERR("fail to add interface prop\n");
+ ret = -EFAULT;
+ goto fail_commit_hdr;
+ }
+
+ list_add(&new_intf->link, &ipa_wdi3_ctx->head_intf_list);
+ init_completion(&ipa_wdi3_ctx->wdi3_completion);
+
+ kfree(hdr);
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return 0;
+
+fail_commit_hdr:
+ kfree(hdr);
+fail_alloc_hdr:
+ kfree(new_intf);
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return ret;
+}
+EXPORT_SYMBOL(ipa_wdi3_reg_intf);
+
+int ipa_wdi3_dereg_intf(const char *netdev_name)
+{
+ int len, ret = 0;
+ struct ipa_ioc_del_hdr *hdr = NULL;
+ struct ipa_wdi3_intf_info *entry;
+ struct ipa_wdi3_intf_info *next;
+
+ if (!netdev_name) {
+ IPA_WDI3_ERR("no netdev name.\n");
+ return -EINVAL;
+ }
+
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("wdi3 ctx is not initialized.\n");
+ return -EPERM;
+ }
+
+ mutex_lock(&ipa_wdi3_ctx->lock);
+ list_for_each_entry_safe(entry, next, &ipa_wdi3_ctx->head_intf_list,
+ link)
+ if (strcmp(entry->netdev_name, netdev_name) == 0) {
+ len = sizeof(struct ipa_ioc_del_hdr) +
+ 2 * sizeof(struct ipa_hdr_del);
+ hdr = kzalloc(len, GFP_KERNEL);
+ if (hdr == NULL) {
+ IPA_WDI3_ERR("fail to alloc %d bytes\n", len);
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return -ENOMEM;
+ }
+
+ hdr->commit = 1;
+ hdr->num_hdls = 2;
+ hdr->hdl[0].hdl = entry->partial_hdr_hdl[0];
+ hdr->hdl[1].hdl = entry->partial_hdr_hdl[1];
+ IPA_WDI3_DBG("IPv4 hdr hdl: %d IPv6 hdr hdl: %d\n",
+ hdr->hdl[0].hdl, hdr->hdl[1].hdl);
+
+ if (ipa_del_hdr(hdr)) {
+ IPA_WDI3_ERR("fail to delete partial header\n");
+ ret = -EFAULT;
+ goto fail;
+ }
+
+ if (ipa_deregister_intf(entry->netdev_name)) {
+ IPA_WDI3_ERR("fail to del interface props\n");
+ ret = -EFAULT;
+ goto fail;
+ }
+ list_del(&entry->link);
+ kfree(entry);
+
+ break;
+ }
+
+fail:
+ kfree(hdr);
+ mutex_unlock(&ipa_wdi3_ctx->lock);
+ return ret;
+}
+EXPORT_SYMBOL(ipa_wdi3_dereg_intf);
+
+static void ipa_wdi3_rm_notify(void *user_data, enum ipa_rm_event event,
+ unsigned long data)
+{
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("Invalid context\n");
+ return;
+ }
+
+ switch (event) {
+ case IPA_RM_RESOURCE_GRANTED:
+ complete_all(&ipa_wdi3_ctx->wdi3_completion);
+ break;
+
+ case IPA_RM_RESOURCE_RELEASED:
+ break;
+
+ default:
+ IPA_WDI3_ERR("Invalid RM Evt: %d", event);
+ break;
+ }
+}
+
+static int ipa_wdi3_cons_release(void)
+{
+ return 0;
+}
+
+static int ipa_wdi3_cons_request(void)
+{
+ int ret = 0;
+
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("wdi3 ctx is not initialized\n");
+ ret = -EFAULT;
+ }
+
+ return ret;
+}
+
+int ipa_wdi3_conn_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out)
+{
+ int ret = 0;
+ struct ipa_rm_create_params param;
+
+ if (!(in && out)) {
+ IPA_WDI3_ERR("empty parameters. in=%pK out=%pK\n", in, out);
+ return -EINVAL;
+ }
+
+ if (!ipa_wdi3_ctx) {
+ ipa_wdi3_ctx = kzalloc(sizeof(*ipa_wdi3_ctx), GFP_KERNEL);
+ if (ipa_wdi3_ctx == NULL) {
+ IPA_WDI3_ERR("fail to alloc wdi3 ctx\n");
+ return -EFAULT;
+ }
+ mutex_init(&ipa_wdi3_ctx->lock);
+ INIT_LIST_HEAD(&ipa_wdi3_ctx->head_intf_list);
+ }
+ ipa_wdi3_ctx->notify = in->notify;
+ ipa_wdi3_ctx->priv = in->priv;
+
+ memset(¶m, 0, sizeof(param));
+ param.name = IPA_RM_RESOURCE_WLAN_PROD;
+ param.reg_params.user_data = ipa_wdi3_ctx;
+ param.reg_params.notify_cb = ipa_wdi3_rm_notify;
+ param.floor_voltage = IPA_VOLTAGE_SVS;
+ ret = ipa_rm_create_resource(¶m);
+ if (ret) {
+ IPA_WDI3_ERR("fail to create WLAN_PROD resource\n");
+ return -EFAULT;
+ }
+
+ memset(¶m, 0, sizeof(param));
+ param.name = IPA_RM_RESOURCE_WLAN_CONS;
+ param.request_resource = ipa_wdi3_cons_request;
+ param.release_resource = ipa_wdi3_cons_release;
+ ret = ipa_rm_create_resource(¶m);
+ if (ret) {
+ IPA_WDI3_ERR("fail to create WLAN_CONS resource\n");
+ goto fail_create_rm_cons;
+ }
+
+ if (ipa_rm_add_dependency(IPA_RM_RESOURCE_WLAN_PROD,
+ IPA_RM_RESOURCE_APPS_CONS)) {
+ IPA_WDI3_ERR("fail to add rm dependency\n");
+ ret = -EFAULT;
+ goto fail;
+ }
+
+ if (ipa_conn_wdi3_pipes(in, out)) {
+ IPA_WDI3_ERR("fail to setup wdi3 pipes\n");
+ ret = -EFAULT;
+ goto fail;
+ }
+
+ return 0;
+
+fail:
+ ipa_rm_delete_resource(IPA_RM_RESOURCE_WLAN_CONS);
+fail_create_rm_cons:
+ ipa_rm_delete_resource(IPA_RM_RESOURCE_WLAN_PROD);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_wdi3_conn_pipes);
+
+int ipa_wdi3_disconn_pipes(void)
+{
+ int ipa_ep_idx_rx, ipa_ep_idx_tx;
+
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("wdi3 ctx is not initialized\n");
+ return -EPERM;
+ }
+
+ ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD);
+ ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS);
+ if (ipa_disconn_wdi3_pipes(ipa_ep_idx_rx, ipa_ep_idx_tx)) {
+ IPA_WDI3_ERR("fail to tear down wdi3 pipes\n");
+ return -EFAULT;
+ }
+
+ if (ipa_rm_delete_dependency(IPA_RM_RESOURCE_WLAN_PROD,
+ IPA_RM_RESOURCE_APPS_CONS)) {
+ IPA_WDI3_ERR("fail to delete rm dependency\n");
+ return -EFAULT;
+ }
+
+ if (ipa_rm_delete_resource(IPA_RM_RESOURCE_WLAN_PROD)) {
+ IPA_WDI3_ERR("fail to delete WLAN_PROD resource\n");
+ return -EFAULT;
+ }
+
+ if (ipa_rm_delete_resource(IPA_RM_RESOURCE_WLAN_CONS)) {
+ IPA_WDI3_ERR("fail to delete WLAN_CONS resource\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_wdi3_disconn_pipes);
+
+int ipa_wdi3_enable_pipes(void)
+{
+ int ret;
+ int ipa_ep_idx_tx, ipa_ep_idx_rx;
+
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("wdi3 ctx is not initialized.\n");
+ return -EPERM;
+ }
+
+ ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD);
+ ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS);
+ if (ipa_enable_wdi3_pipes(ipa_ep_idx_tx, ipa_ep_idx_rx)) {
+ IPA_WDI3_ERR("fail to enable wdi3 pipes\n");
+ return -EFAULT;
+ }
+
+ ret = ipa_rm_request_resource(IPA_RM_RESOURCE_WLAN_PROD);
+ if (ret == -EINPROGRESS) {
+ if (wait_for_completion_timeout(&ipa_wdi3_ctx->wdi3_completion,
+ 10*HZ) == 0) {
+ IPA_WDI3_ERR("WLAN_PROD resource req time out\n");
+ return -EFAULT;
+ }
+ } else if (ret != 0) {
+ IPA_WDI3_ERR("fail to request resource\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_wdi3_enable_pipes);
+
+int ipa_wdi3_disable_pipes(void)
+{
+ int ret;
+ int ipa_ep_idx_tx, ipa_ep_idx_rx;
+
+ if (!ipa_wdi3_ctx) {
+ IPA_WDI3_ERR("wdi3 ctx is not initialized.\n");
+ return -EPERM;
+ }
+
+ ret = ipa_rm_release_resource(IPA_RM_RESOURCE_WLAN_PROD);
+ if (ret != 0) {
+ IPA_WDI3_ERR("fail to release resource\n");
+ return -EFAULT;
+ }
+
+ ipa_ep_idx_rx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_PROD);
+ ipa_ep_idx_tx = ipa_get_ep_mapping(IPA_CLIENT_WLAN1_CONS);
+ if (ipa_disable_wdi3_pipes(ipa_ep_idx_tx, ipa_ep_idx_rx)) {
+ IPA_WDI3_ERR("fail to disable wdi3 pipes\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_wdi3_disable_pipes);
+
+int ipa_wdi3_set_perf_profile(struct ipa_wdi3_perf_profile *profile)
+{
+ struct ipa_rm_perf_profile rm_profile;
+ enum ipa_rm_resource_name resource_name;
+
+ if (profile == NULL) {
+ IPA_WDI3_ERR("Invalid input\n");
+ return -EINVAL;
+ }
+
+ rm_profile.max_supported_bandwidth_mbps =
+ profile->max_supported_bw_mbps;
+
+ if (profile->client == IPA_CLIENT_WLAN1_PROD) {
+ resource_name = IPA_RM_RESOURCE_WLAN_PROD;
+ } else if (profile->client == IPA_CLIENT_WLAN1_CONS) {
+ resource_name = IPA_RM_RESOURCE_WLAN_CONS;
+ } else {
+ IPA_WDI3_ERR("not supported\n");
+ return -EINVAL;
+ }
+
+ if (ipa_rm_set_perf_profile(resource_name, &rm_profile)) {
+ IPA_WDI3_ERR("fail to setup rm perf profile\n");
+ return -EFAULT;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ipa_wdi3_set_perf_profile);
diff --git a/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c b/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c
index 1c47e69..2e87bd2 100644
--- a/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_clients/rndis_ipa.c
@@ -2490,9 +2490,13 @@
(struct file *file,
const char __user *buf, size_t count, loff_t *ppos)
{
- struct rndis_ipa_dev *rndis_ipa_ctx = file->private_data;
+ struct rndis_ipa_dev *rndis_ipa_ctx = NULL;
int result;
+ if (file == NULL)
+ return -EFAULT;
+ rndis_ipa_ctx = file->private_data;
+
result = ipa_cfg_ep(rndis_ipa_ctx->usb_to_ipa_hdl, &ipa_to_usb_ep_cfg);
if (result) {
pr_err("failed to re-configure USB to IPA point\n");
diff --git a/drivers/platform/msm/ipa/ipa_common_i.h b/drivers/platform/msm/ipa/ipa_common_i.h
index a487bf4..fe8cbc0 100644
--- a/drivers/platform/msm/ipa/ipa_common_i.h
+++ b/drivers/platform/msm/ipa/ipa_common_i.h
@@ -18,6 +18,7 @@
#include <linux/ipc_logging.h>
#include <linux/ipa.h>
#include <linux/ipa_uc_offload.h>
+#include <linux/ipa_wdi3.h>
#define __FILENAME__ \
(strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__)
@@ -383,6 +384,16 @@
int ipa_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *user_data),
void *user_data);
void ipa_ntn_uc_dereg_rdyCB(void);
+
+int ipa_conn_wdi3_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out);
+
+int ipa_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+
+int ipa_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+
+int ipa_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+
const char *ipa_get_version_string(enum ipa_hw_type ver);
int ipa_start_gsi_channel(u32 clnt_hdl);
diff --git a/drivers/platform/msm/ipa/ipa_v2/Makefile b/drivers/platform/msm/ipa/ipa_v2/Makefile
index 69b8a4c..fb03970 100644
--- a/drivers/platform/msm/ipa/ipa_v2/Makefile
+++ b/drivers/platform/msm/ipa/ipa_v2/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_IPA) += ipat.o
ipat-y := ipa.o ipa_debugfs.o ipa_hdr.o ipa_flt.o ipa_rt.o ipa_dp.o ipa_client.o \
ipa_utils.o ipa_nat.o ipa_intf.o teth_bridge.o ipa_interrupts.o \
- ipa_uc.o ipa_uc_wdi.o ipa_dma.o ipa_uc_mhi.o ipa_mhi.o ipa_uc_ntn.o
+ ipa_uc.o ipa_uc_wdi.o ipa_dma.o ipa_uc_mhi.o ipa_mhi.o ipa_uc_ntn.o \
+ ipa_wdi3_i.o
obj-$(CONFIG_RMNET_IPA) += rmnet_ipa.o ipa_qmi_service_v01.o ipa_qmi_service.o rmnet_ipa_fd_ioctl.o
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c b/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c
index f7b0864..918630f 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c
@@ -23,10 +23,10 @@
static int ipa_generate_hw_rule_from_eq(
const struct ipa_ipfltri_rule_eq *attrib, u8 **buf)
{
- int num_offset_meq_32 = attrib->num_offset_meq_32;
- int num_ihl_offset_range_16 = attrib->num_ihl_offset_range_16;
- int num_ihl_offset_meq_32 = attrib->num_ihl_offset_meq_32;
- int num_offset_meq_128 = attrib->num_offset_meq_128;
+ uint8_t num_offset_meq_32 = attrib->num_offset_meq_32;
+ uint8_t num_ihl_offset_range_16 = attrib->num_ihl_offset_range_16;
+ uint8_t num_ihl_offset_meq_32 = attrib->num_ihl_offset_meq_32;
+ uint8_t num_offset_meq_128 = attrib->num_offset_meq_128;
int i;
if (attrib->tos_eq_present) {
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c b/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c
index d4e39d7..2f72d88 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c
@@ -1374,6 +1374,7 @@
return -EINVAL;
}
mutex_lock(&ipa_ctx->lock);
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_hdr(lookup->name);
if (entry) {
lookup->hdl = entry->id;
@@ -1496,6 +1497,7 @@
return -EINVAL;
}
mutex_lock(&ipa_ctx->lock);
+ copy->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_hdr(copy->name);
if (entry) {
memcpy(copy->hdr, entry->hdr, entry->hdr_len);
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_i.h b/drivers/platform/msm/ipa/ipa_v2/ipa_i.h
index 9bfdcdc..67b0be6 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_i.h
@@ -1546,6 +1546,12 @@
int ipa2_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *), void *priv);
void ipa2_ntn_uc_dereg_rdyCB(void);
+int ipa2_conn_wdi3_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out);
+int ipa2_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+int ipa2_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+int ipa2_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+
/*
* To retrieve doorbell physical address of
* wlan pipes
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c b/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c
index e6954b7..e6048d1 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c
@@ -234,6 +234,7 @@
}
mutex_lock(&ipa_ctx->lock);
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
list_for_each_entry(entry, &ipa_ctx->intf_list, link) {
if (!strcmp(entry->name, lookup->name)) {
lookup->num_tx_props = entry->num_tx_props;
@@ -269,6 +270,7 @@
}
mutex_lock(&ipa_ctx->lock);
+ tx->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
list_for_each_entry(entry, &ipa_ctx->intf_list, link) {
if (!strcmp(entry->name, tx->name)) {
/* add the entry check */
@@ -310,6 +312,7 @@
}
mutex_lock(&ipa_ctx->lock);
+ rx->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
list_for_each_entry(entry, &ipa_ctx->intf_list, link) {
if (!strcmp(entry->name, rx->name)) {
/* add the entry check */
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c b/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c
index 2608e1d..825c538 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c
@@ -512,6 +512,7 @@
struct ipa_install_fltr_rule_resp_msg_v01 resp;
struct msg_desc req_desc, resp_desc;
int rc;
+ int i;
/* check if the filter rules from IPACM is valid */
if (req->filter_spec_list_len == 0) {
@@ -521,6 +522,38 @@
req->filter_spec_list_len);
}
+ if (req->filter_spec_list_len >= QMI_IPA_MAX_FILTERS_V01) {
+ IPAWANDBG(
+ "IPACM passes the number of filtering rules exceed limit\n");
+ return -EINVAL;
+ } else if (req->source_pipe_index_valid != 0) {
+ IPAWANDBG(
+ "IPACM passes source_pipe_index_valid not zero 0 != %d\n",
+ req->source_pipe_index_valid);
+ return -EINVAL;
+ } else if (req->source_pipe_index >= ipa_ctx->ipa_num_pipes) {
+ IPAWANDBG(
+ "IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
+ }
+ for (i = 0; i < req->filter_spec_list_len; i++) {
+ if ((req->filter_spec_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V4_V01) &&
+ (req->filter_spec_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V6_V01))
+ return -EINVAL;
+ if (req->filter_spec_list[i].is_mux_id_valid == false)
+ return -EINVAL;
+ if (req->filter_spec_list[i].is_routing_table_index_valid
+ == false)
+ return -EINVAL;
+ if ((req->filter_spec_list[i].filter_action <=
+ QMI_IPA_FILTER_ACTION_INVALID_V01) &&
+ (req->filter_spec_list[i].filter_action >
+ QMI_IPA_FILTER_ACTION_EXCEPTION_V01))
+ return -EINVAL;
+ }
mutex_lock(&ipa_qmi_lock);
if (ipa_qmi_ctx != NULL) {
/* cache the qmi_filter_request */
@@ -673,6 +706,25 @@
req->filter_index_list[i].filter_handle,
req->filter_index_list[i].filter_index);
return -EINVAL;
+ } else if (req->install_status != IPA_QMI_RESULT_SUCCESS_V01) {
+ IPAWANERR(" UL filter rule for pipe %d install_status = %d\n",
+ req->source_pipe_index, req->install_status);
+ return -EINVAL;
+ } else if (req->source_pipe_index >= ipa_ctx->ipa_num_pipes) {
+ IPAWANERR("IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
+ } else if (((req->embedded_pipe_index_valid != true) ||
+ (req->embedded_call_mux_id_valid != true)) &&
+ ((req->embedded_pipe_index_valid != false) ||
+ (req->embedded_call_mux_id_valid != false))) {
+ IPAWANERR(
+ "IPACM passes embedded pipe and mux valid not valid\n");
+ return -EINVAL;
+ } else if (req->embedded_pipe_index >= ipa_ctx->ipa_num_pipes) {
+ IPAWANERR("IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
}
mutex_lock(&ipa_qmi_lock);
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c b/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c
index bada5cc..321cc89 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c
@@ -863,6 +863,7 @@
mutex_lock(&ipa_ctx->lock);
/* check if this table exists */
+ in->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_rt_tbl(in->ip, in->name);
if (!entry) {
mutex_unlock(&ipa_ctx->lock);
@@ -1099,6 +1100,7 @@
mutex_lock(&ipa_ctx->lock);
for (i = 0; i < rules->num_rules; i++) {
+ rules->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0';
if (__ipa_add_rt_rule(rules->ip, rules->rt_tbl_name,
&rules->rules[i].rule,
rules->rules[i].at_rear,
@@ -1368,6 +1370,7 @@
return -EINVAL;
}
mutex_lock(&ipa_ctx->lock);
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_rt_tbl(lookup->ip, lookup->name);
if (entry && entry->cookie == IPA_RT_TBL_COOKIE) {
if (entry->ref_cnt == U32_MAX) {
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_uc_offload_i.h b/drivers/platform/msm/ipa/ipa_v2/ipa_uc_offload_i.h
index a98d602..afe6368 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_uc_offload_i.h
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_uc_offload_i.h
@@ -26,6 +26,9 @@
#define IPA_NTN_TX_DIR 1
#define IPA_NTN_RX_DIR 2
+#define IPA_WDI3_TX_DIR 1
+#define IPA_WDI3_RX_DIR 2
+
/**
* @brief Enum value determined based on the feature it
* corresponds to
@@ -45,16 +48,20 @@
* enum ipa_hw_features - Values that represent the features supported in IPA HW
* @IPA_HW_FEATURE_COMMON : Feature related to common operation of IPA HW
* @IPA_HW_FEATURE_MHI : Feature related to MHI operation in IPA HW
+ * @IPA_HW_FEATURE_POWER_COLLAPSE: Feature related to IPA Power collapse
* @IPA_HW_FEATURE_WDI : Feature related to WDI operation in IPA HW
* @IPA_HW_FEATURE_NTN : Feature related to NTN operation in IPA HW
* @IPA_HW_FEATURE_OFFLOAD : Feature related to NTN operation in IPA HW
+ * @IPA_HW_FEATURE_WDI3 : Feature related to WDI operation in IPA HW
*/
enum ipa_hw_features {
IPA_HW_FEATURE_COMMON = 0x0,
IPA_HW_FEATURE_MHI = 0x1,
+ IPA_HW_FEATURE_POWER_COLLAPSE = 0x2,
IPA_HW_FEATURE_WDI = 0x3,
IPA_HW_FEATURE_NTN = 0x4,
IPA_HW_FEATURE_OFFLOAD = 0x5,
+ IPA_HW_FEATURE_WDI3 = 0x6,
IPA_HW_FEATURE_MAX = IPA_HW_NUM_FEATURES
};
@@ -277,6 +284,33 @@
} __packed;
+struct IpaHwWdi3SetUpCmdData_t {
+ u32 transfer_ring_base_pa;
+ u32 transfer_ring_base_pa_hi;
+
+ u32 transfer_ring_size;
+
+ u32 transfer_ring_doorbell_pa;
+ u32 transfer_ring_doorbell_pa_hi;
+
+ u32 event_ring_base_pa;
+ u32 event_ring_base_pa_hi;
+
+ u32 event_ring_size;
+
+ u32 event_ring_doorbell_pa;
+ u32 event_ring_doorbell_pa_hi;
+
+ u16 num_pkt_buffers;
+ u8 ipa_pipe_number;
+ u8 dir;
+
+ u16 pkt_offset;
+ u16 reserved0;
+
+ u32 desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE];
+} __packed;
+
/**
* struct IpaHwNtnCommonChCmdData_t - Structure holding the
* parameters for Ntn Tear down command data params
@@ -291,6 +325,13 @@
uint32_t raw32b;
} __packed;
+union IpaHwWdi3CommonChCmdData_t {
+ struct IpaHwWdi3CommonChCmdParams_t {
+ u32 ipa_pipe_number :8;
+ u32 reserved :24;
+ } __packed params;
+ u32 raw32b;
+} __packed;
/**
* struct IpaHwNTNErrorEventData_t - Structure holding the
@@ -408,13 +449,30 @@
* the offload commands from CPU
* @IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP : Command to set up
* Offload protocol's Tx/Rx Path
- * @IPA_CPU_2_HW_CMD_OFFLOAD_RX_SET_UP : Command to tear down
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN : Command to tear down
+ * Offload protocol's Tx/ Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE : Command to enable
+ * Offload protocol's Tx/Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE : Command to disable
+ * Offload protocol's Tx/ Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND : Command to suspend
+ * Offload protocol's Tx/Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_RESUME : Command to resume
* Offload protocol's Tx/ Rx Path
*/
enum ipa_cpu_2_hw_offload_commands {
IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 1),
- IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN,
+ IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 2),
+ IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 3),
+ IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 4),
+ IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 5),
+ IPA_CPU_2_HW_CMD_OFFLOAD_RESUME =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 6),
};
@@ -525,6 +583,7 @@
*/
union IpaHwSetUpCmd {
struct IpaHwNtnSetUpCmdData_t NtnSetupCh_params;
+ struct IpaHwWdi3SetUpCmdData_t Wdi3SetupCh_params;
} __packed;
/**
@@ -545,6 +604,7 @@
*/
union IpaHwCommonChCmd {
union IpaHwNtnCommonChCmdData_t NtnCommonCh_params;
+ union IpaHwWdi3CommonChCmdData_t Wdi3CommonCh_params;
} __packed;
struct IpaHwOffloadCommonChCmdData_t {
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c
index 2c88244..210ddfe 100644
--- a/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c
@@ -5088,6 +5088,10 @@
api_ctrl->ipa_get_pdev = ipa2_get_pdev;
api_ctrl->ipa_ntn_uc_reg_rdyCB = ipa2_ntn_uc_reg_rdyCB;
api_ctrl->ipa_ntn_uc_dereg_rdyCB = ipa2_ntn_uc_dereg_rdyCB;
+ api_ctrl->ipa_conn_wdi3_pipes = ipa2_conn_wdi3_pipes;
+ api_ctrl->ipa_disconn_wdi3_pipes = ipa2_disconn_wdi3_pipes;
+ api_ctrl->ipa_enable_wdi3_pipes = ipa2_enable_wdi3_pipes;
+ api_ctrl->ipa_disable_wdi3_pipes = ipa2_disable_wdi3_pipes;
return 0;
}
diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_wdi3_i.c b/drivers/platform/msm/ipa/ipa_v2/ipa_wdi3_i.c
new file mode 100644
index 0000000..a2c33a1
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_v2/ipa_wdi3_i.c
@@ -0,0 +1,406 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include "ipa_i.h"
+#include "ipa_uc_offload_i.h"
+#include <linux/ipa_wdi3.h>
+
+#define IPA_HW_WDI3_RX_MBOX_START_INDEX 48
+#define IPA_HW_WDI3_TX_MBOX_START_INDEX 50
+
+static int ipa_send_wdi3_setup_pipe_cmd(
+ struct ipa_wdi3_setup_info *info, u8 dir)
+{
+ int ipa_ep_idx;
+ int result = 0;
+ struct ipa_mem_buffer cmd;
+ struct IpaHwWdi3SetUpCmdData_t *wdi3_params;
+ struct IpaHwOffloadSetUpCmdData_t *cmd_data;
+
+ if (info == NULL) {
+ IPAERR("invalid input\n");
+ return -EINVAL;
+ }
+
+ ipa_ep_idx = ipa_get_ep_mapping(info->client);
+ IPAERR("ep number: %d\n", ipa_ep_idx);
+ if (ipa_ep_idx == -1) {
+ IPAERR("fail to get ep idx.\n");
+ return -EFAULT;
+ }
+
+ IPAERR("client=%d ep=%d\n", info->client, ipa_ep_idx);
+ IPAERR("ring_base_pa = 0x%pad\n", &info->transfer_ring_base_pa);
+ IPAERR("ring_size = %hu\n", info->transfer_ring_size);
+ IPAERR("ring_db_pa = 0x%pad\n", &info->transfer_ring_doorbell_pa);
+ IPAERR("evt_ring_base_pa = 0x%pad\n", &info->event_ring_base_pa);
+ IPAERR("evt_ring_size = %hu\n", info->event_ring_size);
+ IPAERR("evt_ring_db_pa = 0x%pad\n", &info->event_ring_doorbell_pa);
+ IPAERR("num_pkt_buffers = %hu\n", info->num_pkt_buffers);
+ IPAERR("pkt_offset = %d.\n", info->pkt_offset);
+
+ cmd.size = sizeof(*cmd_data);
+ cmd.base = dma_alloc_coherent(ipa_ctx->uc_pdev, cmd.size,
+ &cmd.phys_base, GFP_KERNEL);
+ if (cmd.base == NULL) {
+ IPAERR("fail to get DMA memory.\n");
+ return -ENOMEM;
+ }
+ IPAERR("suceeded in allocating memory.\n");
+
+ cmd_data = (struct IpaHwOffloadSetUpCmdData_t *)cmd.base;
+ cmd_data->protocol = IPA_HW_FEATURE_WDI3;
+
+ wdi3_params = &cmd_data->SetupCh_params.Wdi3SetupCh_params;
+ wdi3_params->transfer_ring_base_pa = (u32)info->transfer_ring_base_pa;
+ wdi3_params->transfer_ring_base_pa_hi =
+ (u32)((u64)info->transfer_ring_base_pa >> 32);
+ wdi3_params->transfer_ring_size = info->transfer_ring_size;
+ wdi3_params->transfer_ring_doorbell_pa =
+ (u32)info->transfer_ring_doorbell_pa;
+ wdi3_params->transfer_ring_doorbell_pa_hi =
+ (u32)((u64)info->transfer_ring_doorbell_pa >> 32);
+ wdi3_params->event_ring_base_pa = (u32)info->event_ring_base_pa;
+ wdi3_params->event_ring_base_pa_hi =
+ (u32)((u64)info->event_ring_base_pa >> 32);
+ wdi3_params->event_ring_size = info->event_ring_size;
+ wdi3_params->event_ring_doorbell_pa =
+ (u32)info->event_ring_doorbell_pa;
+ wdi3_params->event_ring_doorbell_pa_hi =
+ (u32)((u64)info->event_ring_doorbell_pa >> 32);
+ wdi3_params->num_pkt_buffers = info->num_pkt_buffers;
+ wdi3_params->ipa_pipe_number = ipa_ep_idx;
+ wdi3_params->dir = dir;
+ wdi3_params->pkt_offset = info->pkt_offset;
+ memcpy(wdi3_params->desc_format_template, info->desc_format_template,
+ sizeof(wdi3_params->desc_format_template));
+ IPAERR("suceeded in populating the command memory.\n");
+
+ result = ipa_uc_send_cmd((u32)(cmd.phys_base),
+ IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP,
+ IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
+ false, 10*HZ);
+ if (result) {
+ IPAERR("uc setup channel cmd failed: %d\n", result);
+ result = -EFAULT;
+ }
+
+ dma_free_coherent(ipa_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);
+ IPAERR("suceeded in freeing memory.\n");
+ return result;
+}
+
+int ipa2_conn_wdi3_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out)
+{
+ struct ipa_ep_context *ep_rx;
+ struct ipa_ep_context *ep_tx;
+ int ipa_ep_idx_rx;
+ int ipa_ep_idx_tx;
+ int result = 0;
+
+ if (in == NULL || out == NULL) {
+ IPAERR("invalid input\n");
+ return -EINVAL;
+ }
+
+ ipa_ep_idx_rx = ipa_get_ep_mapping(in->rx.client);
+ ipa_ep_idx_tx = ipa_get_ep_mapping(in->tx.client);
+ if (ipa_ep_idx_rx == -1 || ipa_ep_idx_tx == -1) {
+ IPAERR("fail to alloc EP.\n");
+ return -EFAULT;
+ }
+
+ ep_rx = &ipa_ctx->ep[ipa_ep_idx_rx];
+ ep_tx = &ipa_ctx->ep[ipa_ep_idx_tx];
+
+ if (ep_rx->valid || ep_tx->valid) {
+ IPAERR("EP already allocated.\n");
+ return -EFAULT;
+ }
+
+ memset(ep_rx, 0, offsetof(struct ipa_ep_context, sys));
+ memset(ep_tx, 0, offsetof(struct ipa_ep_context, sys));
+
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+
+ /* setup rx ep cfg */
+ ep_rx->valid = 1;
+ ep_rx->client = in->rx.client;
+ result = ipa_disable_data_path(ipa_ep_idx_rx);
+ if (result) {
+ IPAERR("disable data path failed res=%d clnt=%d.\n", result,
+ ipa_ep_idx_rx);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return -EFAULT;
+ }
+ ep_rx->client_notify = in->notify;
+ ep_rx->priv = in->priv;
+
+ memcpy(&ep_rx->cfg, &in->rx.ipa_ep_cfg, sizeof(ep_rx->cfg));
+
+ if (ipa_cfg_ep(ipa_ep_idx_rx, &ep_rx->cfg)) {
+ IPAERR("fail to setup rx pipe cfg\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ IPAERR("configured RX EP.\n");
+
+ if (ipa_send_wdi3_setup_pipe_cmd(&in->rx, IPA_WDI3_RX_DIR)) {
+ IPAERR("fail to send cmd to uc for rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ IPAERR("rx pipe was setup.\n");
+
+ ipa_install_dflt_flt_rules(ipa_ep_idx_rx);
+ out->rx_uc_db_pa = ipa_ctx->ipa_wrapper_base +
+ IPA_REG_BASE_OFST_v2_5 +
+ IPA_UC_MAILBOX_m_n_OFFS_v2_5(
+ IPA_HW_WDI3_RX_MBOX_START_INDEX/32,
+ IPA_HW_WDI3_RX_MBOX_START_INDEX % 32);
+ IPADBG("client %d (ep: %d) connected\n", in->rx.client,
+ ipa_ep_idx_rx);
+
+ /* setup dl ep cfg */
+ ep_tx->valid = 1;
+ ep_tx->client = in->tx.client;
+ result = ipa_disable_data_path(ipa_ep_idx_tx);
+ if (result) {
+ IPAERR("disable data path failed res=%d clnt=%d.\n", result,
+ ipa_ep_idx_tx);
+ result = -EFAULT;
+ goto fail;
+ }
+
+ memcpy(&ep_tx->cfg, &in->tx.ipa_ep_cfg, sizeof(ep_tx->cfg));
+
+ if (ipa_cfg_ep(ipa_ep_idx_tx, &ep_tx->cfg)) {
+ IPAERR("fail to setup tx pipe cfg\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ IPAERR("configured TX EP in DMA mode.\n");
+
+ if (ipa_send_wdi3_setup_pipe_cmd(&in->tx, IPA_WDI3_TX_DIR)) {
+ IPAERR("fail to send cmd to uc for tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ IPAERR("tx pipe was setup.\n");
+
+ out->tx_uc_db_pa = ipa_ctx->ipa_wrapper_base +
+ IPA_REG_BASE_OFST_v2_5 +
+ IPA_UC_MAILBOX_m_n_OFFS_v2_5(
+ IPA_HW_WDI3_TX_MBOX_START_INDEX/32,
+ IPA_HW_WDI3_TX_MBOX_START_INDEX % 32);
+ out->tx_uc_db_va = ioremap(out->tx_uc_db_pa, 4);
+ IPADBG("client %d (ep: %d) connected\n", in->tx.client,
+ ipa_ep_idx_tx);
+
+fail:
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return result;
+}
+
+static int ipa_send_wdi3_common_ch_cmd(int ipa_ep_idx, int command)
+{
+ struct ipa_mem_buffer cmd;
+ struct IpaHwOffloadCommonChCmdData_t *cmd_data;
+ union IpaHwWdi3CommonChCmdData_t *wdi3;
+ int result = 0;
+
+ cmd.size = sizeof(*cmd_data);
+ cmd.base = dma_alloc_coherent(ipa_ctx->uc_pdev, cmd.size,
+ &cmd.phys_base, GFP_KERNEL);
+ if (cmd.base == NULL) {
+ IPAERR("fail to get DMA memory.\n");
+ return -ENOMEM;
+ }
+
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+ /* enable the TX pipe */
+ cmd_data = (struct IpaHwOffloadCommonChCmdData_t *)cmd.base;
+ cmd_data->protocol = IPA_HW_FEATURE_WDI3;
+
+ wdi3 = &cmd_data->CommonCh_params.Wdi3CommonCh_params;
+ wdi3->params.ipa_pipe_number = ipa_ep_idx;
+ IPAERR("cmd: %d ep_idx: %d\n", command, ipa_ep_idx);
+ result = ipa_uc_send_cmd((u32)(cmd.phys_base), command,
+ IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
+ false, 10*HZ);
+ if (result) {
+ result = -EFAULT;
+ goto fail;
+ }
+
+fail:
+ dma_free_coherent(ipa_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return result;
+}
+
+int ipa2_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ struct ipa_ep_context *ep_tx, *ep_rx;
+ int result = 0;
+
+ IPADBG("ep_tx = %d\n", ipa_ep_idx_tx);
+ IPADBG("ep_rx = %d\n", ipa_ep_idx_rx);
+
+ ep_tx = &ipa_ctx->ep[ipa_ep_idx_tx];
+ ep_rx = &ipa_ctx->ep[ipa_ep_idx_rx];
+
+ /* tear down tx pipe */
+ if (ipa_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN)) {
+ IPAERR("fail to tear down tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ ipa_disable_data_path(ipa_ep_idx_tx);
+ memset(ep_tx, 0, sizeof(struct ipa_ep_context));
+ IPADBG("tx client (ep: %d) disconnected\n", ipa_ep_idx_tx);
+
+ /* tear down rx pipe */
+ if (ipa_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN)) {
+ IPAERR("fail to tear down rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ ipa_disable_data_path(ipa_ep_idx_rx);
+ ipa_delete_dflt_flt_rules(ipa_ep_idx_rx);
+ memset(ep_rx, 0, sizeof(struct ipa_ep_context));
+ IPADBG("rx client (ep: %d) disconnected\n", ipa_ep_idx_rx);
+
+fail:
+ return result;
+}
+
+int ipa2_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ struct ipa_ep_context *ep_tx, *ep_rx;
+ int result = 0;
+
+ IPAERR("ep_tx = %d\n", ipa_ep_idx_tx);
+ IPAERR("ep_rx = %d\n", ipa_ep_idx_rx);
+
+ ep_tx = &ipa_ctx->ep[ipa_ep_idx_tx];
+ ep_rx = &ipa_ctx->ep[ipa_ep_idx_rx];
+
+ /* enable tx pipe */
+ if (ipa_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE)) {
+ IPAERR("fail to enable tx pipe\n");
+ WARN_ON(1);
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* resume tx pipe */
+ if (ipa_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_RESUME)) {
+ IPAERR("fail to resume tx pipe\n");
+ WARN_ON(1);
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* enable rx pipe */
+ if (ipa_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE)) {
+ IPAERR("fail to enable rx pipe\n");
+ WARN_ON(1);
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* resume rx pipe */
+ if (ipa_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_RESUME)) {
+ IPAERR("fail to resume rx pipe\n");
+ WARN_ON(1);
+ result = -EFAULT;
+ goto fail;
+ }
+
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+
+ /* enable data path */
+ result = ipa_enable_data_path(ipa_ep_idx_rx);
+ if (result) {
+ IPAERR("enable data path failed res=%d clnt=%d.\n", result,
+ ipa_ep_idx_rx);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return -EFAULT;
+ }
+
+ result = ipa_enable_data_path(ipa_ep_idx_tx);
+ if (result) {
+ IPAERR("enable data path failed res=%d clnt=%d.\n", result,
+ ipa_ep_idx_tx);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return -EFAULT;
+ }
+
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+
+fail:
+ return result;
+}
+
+int ipa2_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ struct ipa_ep_context *ep_tx, *ep_rx;
+ int result = 0;
+
+ IPADBG("ep_tx = %d\n", ipa_ep_idx_tx);
+ IPADBG("ep_rx = %d\n", ipa_ep_idx_rx);
+
+ ep_tx = &ipa_ctx->ep[ipa_ep_idx_tx];
+ ep_rx = &ipa_ctx->ep[ipa_ep_idx_rx];
+
+ /* suspend tx pipe */
+ if (ipa_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND)) {
+ IPAERR("fail to suspend tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* disable tx pipe */
+ if (ipa_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE)) {
+ IPAERR("fail to disable tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* suspend rx pipe */
+ if (ipa_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND)) {
+ IPAERR("fail to suspend rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* disable rx pipe */
+ if (ipa_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE)) {
+ IPAERR("fail to disable rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+fail:
+ return result;
+}
diff --git a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c
index 39a1cc2..8ea1d99 100644
--- a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c
@@ -649,6 +649,8 @@
return -ENOMEM;
}
+ memset(req, 0, sizeof(struct ipa_fltr_installed_notif_req_msg_v01));
+
param->commit = 1;
param->ep = IPA_CLIENT_APPS_LAN_WAN_PROD;
param->global = false;
@@ -1516,8 +1518,8 @@
/* Get driver name */
case RMNET_IOCTL_GET_DRIVER_NAME:
memcpy(&extend_ioctl_data.u.if_name,
- ipa_netdevs[0]->name,
- sizeof(IFNAMSIZ));
+ ipa_netdevs[0]->name, IFNAMSIZ);
+ extend_ioctl_data.u.if_name[IFNAMSIZ - 1] = '\0';
if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data,
&extend_ioctl_data,
sizeof(struct rmnet_ioctl_extended_s)))
@@ -1540,6 +1542,8 @@
mutex_unlock(&add_mux_channel_lock);
return -EFAULT;
}
+ extend_ioctl_data.u.rmnet_mux_val.vchannel_name
+ [IFNAMSIZ-1] = '\0';
IPAWANDBG("ADD_MUX_CHANNEL(%d, name: %s)\n",
extend_ioctl_data.u.rmnet_mux_val.mux_id,
extend_ioctl_data.u.rmnet_mux_val.vchannel_name);
@@ -1661,6 +1665,7 @@
sizeof(wan_msg->upstream_ifname);
strlcpy(wan_msg->upstream_ifname,
extend_ioctl_data.u.if_name, len);
+ wan_msg->upstream_ifname[len - 1] = '\0';
memset(&msg_meta, 0, sizeof(struct ipa_msg_meta));
msg_meta.msg_type = WAN_XLAT_CONNECT;
msg_meta.msg_len = sizeof(struct ipa_wan_msg);
diff --git a/drivers/platform/msm/ipa/ipa_v3/Makefile b/drivers/platform/msm/ipa/ipa_v3/Makefile
index 5db2545..ae4dccf 100644
--- a/drivers/platform/msm/ipa/ipa_v3/Makefile
+++ b/drivers/platform/msm/ipa/ipa_v3/Makefile
@@ -4,6 +4,6 @@
ipat-y := ipa.o ipa_debugfs.o ipa_hdr.o ipa_flt.o ipa_rt.o ipa_dp.o ipa_client.o \
ipa_utils.o ipa_nat.o ipa_intf.o teth_bridge.o ipa_interrupts.o \
ipa_uc.o ipa_uc_wdi.o ipa_dma.o ipa_uc_mhi.o ipa_mhi.o ipa_uc_ntn.o \
- ipa_hw_stats.o ipa_pm.o
+ ipa_hw_stats.o ipa_pm.o ipa_wdi3_i.o
obj-$(CONFIG_RMNET_IPA3) += rmnet_ipa.o ipa_qmi_service_v01.o ipa_qmi_service.o rmnet_ipa_fd_ioctl.o
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c
index e9df986..a40d038 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c
@@ -255,7 +255,7 @@
bool present;
bool arm_smmu;
bool fast_map;
- bool s1_bypass;
+ bool s1_bypass_arr[IPA_SMMU_CB_MAX];
bool use_64_bit_dma_mask;
u32 ipa_base;
u32 ipa_size;
@@ -436,14 +436,6 @@
flags);
}
-enum ipa_smmu_cb_type {
- IPA_SMMU_CB_AP,
- IPA_SMMU_CB_WLAN,
- IPA_SMMU_CB_UC,
- IPA_SMMU_CB_MAX
-
-};
-
static struct ipa_smmu_cb_ctx smmu_cb[IPA_SMMU_CB_MAX];
struct iommu_domain *ipa3_get_smmu_domain(void)
@@ -4430,8 +4422,6 @@
if (IS_ERR_OR_NULL(subsystem_get_retval)) {
IPAERR("Unable to trigger PIL process for FW loading\n");
return -EINVAL;
- } else {
- subsystem_put(subsystem_get_retval);
}
IPADBG("PIL FW loading process is complete\n");
@@ -4456,6 +4446,9 @@
return -EFAULT;
}
+ if (count > 0)
+ dbg_buff[count - 1] = '\0';
+
/* Prevent consequent calls from trying to load the FW again. */
if (ipa3_is_ready())
return count;
@@ -4643,10 +4636,14 @@
ipa3_ctx->pdev = ipa_dev;
ipa3_ctx->uc_pdev = ipa_dev;
ipa3_ctx->smmu_present = smmu_info.present;
- if (!ipa3_ctx->smmu_present)
- ipa3_ctx->smmu_s1_bypass = true;
- else
- ipa3_ctx->smmu_s1_bypass = smmu_info.s1_bypass;
+ if (!ipa3_ctx->smmu_present) {
+ for (i = 0; i < IPA_SMMU_CB_MAX; i++)
+ ipa3_ctx->s1_bypass_arr[i] = true;
+ } else {
+ for (i = 0; i < IPA_SMMU_CB_MAX; i++)
+ ipa3_ctx->s1_bypass_arr[i] = smmu_info.s1_bypass_arr[i];
+ }
+
ipa3_ctx->ipa_wrapper_base = resource_p->ipa_mem_base;
ipa3_ctx->ipa_wrapper_size = resource_p->ipa_mem_size;
ipa3_ctx->ipa_hw_type = resource_p->ipa_hw_type;
@@ -5489,7 +5486,8 @@
}
cb->valid = true;
- if (smmu_info.s1_bypass) {
+ if (of_property_read_bool(dev->of_node, "qcom,smmu-s1-bypass")) {
+ smmu_info.s1_bypass_arr[IPA_SMMU_CB_WLAN] = true;
if (iommu_domain_set_attr(cb->iommu,
DOMAIN_ATTR_S1_BYPASS,
&bypass)) {
@@ -5497,8 +5495,9 @@
cb->valid = false;
return -EIO;
}
- IPADBG("SMMU S1 BYPASS\n");
+ IPADBG("WLAN SMMU S1 BYPASS\n");
} else {
+ smmu_info.s1_bypass_arr[IPA_SMMU_CB_WLAN] = false;
if (iommu_domain_set_attr(cb->iommu,
DOMAIN_ATTR_ATOMIC,
&atomic_ctx)) {
@@ -5506,7 +5505,7 @@
cb->valid = false;
return -EIO;
}
- IPADBG("SMMU ATTR ATOMIC\n");
+ IPADBG(" WLAN SMMU ATTR ATOMIC\n");
if (smmu_info.fast_map) {
if (iommu_domain_set_attr(cb->iommu,
@@ -5520,6 +5519,9 @@
}
}
+ pr_info("IPA smmu_info.s1_bypass_arr[WLAN]=%d smmu_info.fast_map=%d\n",
+ smmu_info.s1_bypass_arr[IPA_SMMU_CB_WLAN], smmu_info.fast_map);
+
ret = iommu_attach_device(cb->iommu, dev);
if (ret) {
IPAERR("could not attach device ret=%d\n", ret);
@@ -5607,20 +5609,23 @@
cb->valid = true;
IPADBG("UC CB PROBE sub pdev=%p set attribute\n", dev);
- if (smmu_info.s1_bypass) {
+
+ if (of_property_read_bool(dev->of_node, "qcom,smmu-s1-bypass")) {
+ smmu_info.s1_bypass_arr[IPA_SMMU_CB_UC] = true;
if (iommu_domain_set_attr(cb->mapping->domain,
- DOMAIN_ATTR_S1_BYPASS,
- &bypass)) {
+ DOMAIN_ATTR_S1_BYPASS,
+ &bypass)) {
IPAERR("couldn't set bypass\n");
arm_iommu_release_mapping(cb->mapping);
cb->valid = false;
return -EIO;
}
- IPADBG("SMMU S1 BYPASS\n");
+ IPADBG("UC SMMU S1 BYPASS\n");
} else {
+ smmu_info.s1_bypass_arr[IPA_SMMU_CB_UC] = false;
if (iommu_domain_set_attr(cb->mapping->domain,
- DOMAIN_ATTR_ATOMIC,
- &atomic_ctx)) {
+ DOMAIN_ATTR_ATOMIC,
+ &atomic_ctx)) {
IPAERR("couldn't set domain as atomic\n");
arm_iommu_release_mapping(cb->mapping);
cb->valid = false;
@@ -5630,8 +5635,8 @@
if (smmu_info.fast_map) {
if (iommu_domain_set_attr(cb->mapping->domain,
- DOMAIN_ATTR_FAST,
- &fast)) {
+ DOMAIN_ATTR_FAST,
+ &fast)) {
IPAERR("couldn't set fast map\n");
arm_iommu_release_mapping(cb->mapping);
cb->valid = false;
@@ -5641,6 +5646,9 @@
}
}
+ pr_info("IPA smmu_info.s1_bypass_arr[UC]=%d smmu_info.fast_map=%d\n",
+ smmu_info.s1_bypass_arr[IPA_SMMU_CB_UC], smmu_info.fast_map);
+
IPADBG("UC CB PROBE sub pdev=%p attaching IOMMU device\n", dev);
ret = arm_iommu_attach_device(cb->dev, cb->mapping);
if (ret) {
@@ -5707,7 +5715,9 @@
IPADBG("SMMU mapping created\n");
cb->valid = true;
- if (smmu_info.s1_bypass) {
+ if (of_property_read_bool(dev->of_node,
+ "qcom,smmu-s1-bypass")) {
+ smmu_info.s1_bypass_arr[IPA_SMMU_CB_AP] = true;
if (iommu_domain_set_attr(cb->mapping->domain,
DOMAIN_ATTR_S1_BYPASS,
&bypass)) {
@@ -5716,8 +5726,9 @@
cb->valid = false;
return -EIO;
}
- IPADBG("SMMU S1 BYPASS\n");
+ IPADBG("AP/USB SMMU S1 BYPASS\n");
} else {
+ smmu_info.s1_bypass_arr[IPA_SMMU_CB_AP] = false;
if (iommu_domain_set_attr(cb->mapping->domain,
DOMAIN_ATTR_ATOMIC,
&atomic_ctx)) {
@@ -5726,7 +5737,7 @@
cb->valid = false;
return -EIO;
}
- IPADBG("SMMU atomic set\n");
+ IPADBG("AP/USB SMMU atomic set\n");
if (iommu_domain_set_attr(cb->mapping->domain,
DOMAIN_ATTR_FAST,
@@ -5739,6 +5750,9 @@
IPADBG("SMMU fast map set\n");
}
+ pr_info("IPA smmu_info.s1_bypass_arr[AP]=%d smmu_info.fast_map=%d\n",
+ smmu_info.s1_bypass_arr[IPA_SMMU_CB_AP], smmu_info.fast_map);
+
result = arm_iommu_attach_device(cb->dev, cb->mapping);
if (result) {
IPAERR("couldn't attach to IOMMU ret=%d\n", result);
@@ -5922,17 +5936,12 @@
if (of_property_read_bool(pdev_p->dev.of_node, "qcom,arm-smmu")) {
if (of_property_read_bool(pdev_p->dev.of_node,
- "qcom,smmu-s1-bypass"))
- smmu_info.s1_bypass = true;
- if (of_property_read_bool(pdev_p->dev.of_node,
"qcom,smmu-fast-map"))
smmu_info.fast_map = true;
if (of_property_read_bool(pdev_p->dev.of_node,
"qcom,use-64-bit-dma-mask"))
smmu_info.use_64_bit_dma_mask = true;
smmu_info.arm_smmu = true;
- pr_info("IPA smmu_info.s1_bypass=%d smmu_info.fast_map=%d\n",
- smmu_info.s1_bypass, smmu_info.fast_map);
} else if (of_property_read_bool(pdev_p->dev.of_node,
"qcom,msm-smmu")) {
IPAERR("Legacy IOMMU not supported\n");
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c
index 1af968e..c9a0b50 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c
@@ -488,7 +488,7 @@
struct iommu_domain *smmu_domain;
int res;
- if (ipa3_ctx->smmu_s1_bypass)
+ if (ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP])
return 0;
smmu_domain = ipa3_get_smmu_domain();
@@ -520,7 +520,7 @@
struct iommu_domain *smmu_domain;
int res;
- if (ipa3_ctx->smmu_s1_bypass)
+ if (ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP])
return 0;
smmu_domain = ipa3_get_smmu_domain();
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
index 7f30a10..ee312c7 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c
@@ -136,8 +136,8 @@
DMA_TO_DEVICE);
} else {
dma_unmap_page(ipa3_ctx->pdev,
- next_pkt->mem.phys_base,
- next_pkt->mem.size,
+ tx_pkt->mem.phys_base,
+ tx_pkt->mem.size,
DMA_TO_DEVICE);
}
}
@@ -3816,7 +3816,7 @@
cnt += IPA_WAN_AGGR_PKT_CNT;
total_cnt++;
- if (ep->sys->len == 0 || total_cnt >= ep->sys->rx_pool_sz) {
+ if (ep->sys->len == 0) {
total_cnt = 0;
cnt = cnt-1;
break;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c b/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
index cc29f8f..34624c0 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c
@@ -1133,6 +1133,7 @@
return -EINVAL;
}
mutex_lock(&ipa3_ctx->lock);
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_hdr(lookup->name);
if (entry) {
lookup->hdl = entry->id;
@@ -1255,6 +1256,7 @@
return -EINVAL;
}
mutex_lock(&ipa3_ctx->lock);
+ copy->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa_find_hdr(copy->name);
if (entry) {
memcpy(copy->hdr, entry->hdr, entry->hdr_len);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
index 3e1d188..fb3c3a0 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h
@@ -1098,6 +1098,13 @@
struct ipa_msg_meta msg_meta;
};
+enum ipa_smmu_cb_type {
+ IPA_SMMU_CB_AP,
+ IPA_SMMU_CB_WLAN,
+ IPA_SMMU_CB_UC,
+ IPA_SMMU_CB_MAX
+};
+
/**
* struct ipa3_context - IPA context
* @class: pointer to the struct class
@@ -1296,7 +1303,7 @@
bool apply_rg10_wa;
bool gsi_ch20_wa;
bool smmu_present;
- bool smmu_s1_bypass;
+ bool s1_bypass_arr[IPA_SMMU_CB_MAX];
u32 wdi_map_cnt;
struct wakeup_source w_lock;
struct ipa3_wakelock_ref_cnt wakelock_ref_cnt;
@@ -1825,6 +1832,11 @@
int ipa3_tear_down_uc_offload_pipes(int ipa_ep_idx_ul, int ipa_ep_idx_dl);
int ipa3_ntn_uc_reg_rdyCB(void (*ipauc_ready_cb)(void *), void *priv);
void ipa3_ntn_uc_dereg_rdyCB(void);
+int ipa3_conn_wdi3_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out);
+int ipa3_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+int ipa3_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
+int ipa3_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx);
/*
* To retrieve doorbell physical address of
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c b/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c
index 2bd7b79..4ada018 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_intf.c
@@ -225,6 +225,7 @@
return result;
}
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
if (strnlen(lookup->name, IPA_RESOURCE_NAME_MAX) ==
IPA_RESOURCE_NAME_MAX) {
IPAERR_RL("Interface name too long. (%s)\n", lookup->name);
@@ -267,6 +268,7 @@
return result;
}
+ tx->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
if (strnlen(tx->name, IPA_RESOURCE_NAME_MAX) == IPA_RESOURCE_NAME_MAX) {
IPAERR_RL("Interface name too long. (%s)\n", tx->name);
return result;
@@ -314,6 +316,7 @@
return result;
}
+ rx->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
if (strnlen(rx->name, IPA_RESOURCE_NAME_MAX) == IPA_RESOURCE_NAME_MAX) {
IPAERR_RL("Interface name too long. (%s)\n", rx->name);
return result;
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
index fbaa4ae..e3a3821 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c
@@ -603,15 +603,49 @@
struct ipa_install_fltr_rule_resp_msg_v01 resp;
struct msg_desc req_desc, resp_desc;
int rc;
+ int i;
/* check if the filter rules from IPACM is valid */
- if (req->filter_spec_ex_list_len == 0) {
+ if (req->filter_spec_list_len == 0) {
IPAWANDBG("IPACM pass zero rules to Q6\n");
} else {
IPAWANDBG("IPACM pass %u rules to Q6\n",
req->filter_spec_ex_list_len);
}
+ if (req->filter_spec_list_len >= QMI_IPA_MAX_FILTERS_V01) {
+ IPAWANDBG(
+ "IPACM passes the number of filtering rules exceed limit\n");
+ return -EINVAL;
+ } else if (req->source_pipe_index_valid != 0) {
+ IPAWANDBG(
+ "IPACM passes source_pipe_index_valid not zero 0 != %d\n",
+ req->source_pipe_index_valid);
+ return -EINVAL;
+ } else if (req->source_pipe_index >= ipa3_ctx->ipa_num_pipes) {
+ IPAWANDBG(
+ "IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
+ }
+ for (i = 0; i < req->filter_spec_list_len; i++) {
+ if ((req->filter_spec_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V4_V01) &&
+ (req->filter_spec_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V6_V01))
+ return -EINVAL;
+ if (req->filter_spec_list[i].is_mux_id_valid == false)
+ return -EINVAL;
+ if (req->filter_spec_list[i].is_routing_table_index_valid
+ == false)
+ return -EINVAL;
+ if ((req->filter_spec_list[i].filter_action <=
+ QMI_IPA_FILTER_ACTION_INVALID_V01) &&
+ (req->filter_spec_list[i].filter_action >
+ QMI_IPA_FILTER_ACTION_EXCEPTION_V01))
+ return -EINVAL;
+ }
+
mutex_lock(&ipa3_qmi_lock);
if (ipa3_qmi_ctx != NULL) {
/* cache the qmi_filter_request */
@@ -653,6 +687,7 @@
struct ipa_install_fltr_rule_resp_ex_msg_v01 resp;
struct msg_desc req_desc, resp_desc;
int rc;
+ int i;
/* check if the filter rules from IPACM is valid */
if (req->filter_spec_ex_list_len == 0) {
@@ -662,6 +697,34 @@
req->filter_spec_ex_list_len);
}
+ if (req->filter_spec_ex_list_len >= QMI_IPA_MAX_FILTERS_EX_V01) {
+ IPAWANDBG(
+ "IPACM pass the number of filtering rules exceed limit\n");
+ return -EINVAL;
+ } else if (req->source_pipe_index_valid != 0) {
+ IPAWANDBG(
+ "IPACM passes source_pipe_index_valid not zero 0 != %d\n",
+ req->source_pipe_index_valid);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < req->filter_spec_ex_list_len-1; i++) {
+ if ((req->filter_spec_ex_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V4_V01) &&
+ (req->filter_spec_ex_list[i].ip_type !=
+ QMI_IPA_IP_TYPE_V6_V01))
+ return -EINVAL;
+ if (req->filter_spec_ex_list[i].is_mux_id_valid == false)
+ return -EINVAL;
+ if (req->filter_spec_ex_list[i].is_routing_table_index_valid
+ == false)
+ return -EINVAL;
+ if ((req->filter_spec_ex_list[i].filter_action <=
+ QMI_IPA_FILTER_ACTION_INVALID_V01) &&
+ (req->filter_spec_ex_list[i].filter_action >
+ QMI_IPA_FILTER_ACTION_EXCEPTION_V01))
+ return -EINVAL;
+ }
mutex_lock(&ipa3_qmi_lock);
if (ipa3_qmi_ctx != NULL) {
/* cache the qmi_filter_request */
@@ -805,6 +868,30 @@
req->source_pipe_index,
req->rule_id_len);
return -EINVAL;
+ } else if (req->install_status != IPA_QMI_RESULT_SUCCESS_V01) {
+ IPAWANERR(" UL filter rule for pipe %d install_status = %d\n",
+ req->source_pipe_index, req->install_status);
+ return -EINVAL;
+ } else if (req->rule_id_valid != 1) {
+ IPAWANERR(" UL filter rule for pipe %d rule_id_valid = %d\n",
+ req->source_pipe_index, req->rule_id_valid);
+ return -EINVAL;
+ } else if (req->source_pipe_index >= ipa3_ctx->ipa_num_pipes) {
+ IPAWANDBG(
+ "IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
+ } else if (((req->embedded_pipe_index_valid != true) ||
+ (req->embedded_call_mux_id_valid != true)) &&
+ ((req->embedded_pipe_index_valid != false) ||
+ (req->embedded_call_mux_id_valid != false))) {
+ IPAWANERR(
+ "IPACM passes embedded pipe and mux valid not valid\n");
+ return -EINVAL;
+ } else if (req->embedded_pipe_index >= ipa3_ctx->ipa_num_pipes) {
+ IPAWANERR("IPACM passes source pipe index not valid ID = %d\n",
+ req->source_pipe_index);
+ return -EINVAL;
}
if (req->source_pipe_index == -1) {
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
index 8bd7d30..8d7b107 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c
@@ -732,6 +732,7 @@
}
mutex_lock(&ipa3_ctx->lock);
+ in->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
/* check if this table exists */
entry = __ipa3_find_rt_tbl(in->ip, in->name);
if (!entry) {
@@ -1081,6 +1082,7 @@
mutex_lock(&ipa3_ctx->lock);
for (i = 0; i < rules->num_rules; i++) {
+ rules->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0';
if (__ipa_add_rt_rule(rules->ip, rules->rt_tbl_name,
&rules->rules[i].rule,
rules->rules[i].at_rear,
@@ -1126,7 +1128,7 @@
}
mutex_lock(&ipa3_ctx->lock);
-
+ rules->rt_tbl_name[IPA_RESOURCE_NAME_MAX-1] = '\0';
tbl = __ipa3_find_rt_tbl(rules->ip, rules->rt_tbl_name);
if (tbl == NULL || (tbl->cookie != IPA_RT_TBL_COOKIE)) {
IPAERR_RL("failed finding rt tbl name = %s\n",
@@ -1456,6 +1458,7 @@
return -EINVAL;
}
mutex_lock(&ipa3_ctx->lock);
+ lookup->name[IPA_RESOURCE_NAME_MAX-1] = '\0';
entry = __ipa3_find_rt_tbl(lookup->ip, lookup->name);
if (entry && entry->cookie == IPA_RT_TBL_COOKIE) {
if (entry->ref_cnt == U32_MAX) {
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h
index 44afb28..8d415a1 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_offload_i.h
@@ -26,6 +26,9 @@
#define IPA_NTN_TX_DIR 1
#define IPA_NTN_RX_DIR 2
+#define IPA_WDI3_TX_DIR 1
+#define IPA_WDI3_RX_DIR 2
+
/**
* @brief Enum value determined based on the feature it
* corresponds to
@@ -48,9 +51,9 @@
* @IPA_HW_FEATURE_MHI : Feature related to MHI operation in IPA HW
* @IPA_HW_FEATURE_POWER_COLLAPSE: Feature related to IPA Power collapse
* @IPA_HW_FEATURE_WDI : Feature related to WDI operation in IPA HW
- * @IPA_HW_FEATURE_ZIP: Feature related to CMP/DCMP operation in IPA HW
* @IPA_HW_FEATURE_NTN : Feature related to NTN operation in IPA HW
* @IPA_HW_FEATURE_OFFLOAD : Feature related to NTN operation in IPA HW
+ * @IPA_HW_FEATURE_WDI3 : Feature related to WDI operation in IPA HW
*/
enum ipa3_hw_features {
IPA_HW_FEATURE_COMMON = 0x0,
@@ -59,7 +62,8 @@
IPA_HW_FEATURE_WDI = 0x3,
IPA_HW_FEATURE_ZIP = 0x4,
IPA_HW_FEATURE_NTN = 0x5,
- IPA_HW_FEATURE_OFFLOAD = 0x6,
+ IPA_HW_FEATURE_OFFLOAD = 0x6,
+ IPA_HW_FEATURE_WDI3 = 0x7,
IPA_HW_FEATURE_MAX = IPA_HW_NUM_FEATURES
};
@@ -343,6 +347,33 @@
} __packed;
+struct IpaHwWdi3SetUpCmdData_t {
+ u32 transfer_ring_base_pa;
+ u32 transfer_ring_base_pa_hi;
+
+ u32 transfer_ring_size;
+
+ u32 transfer_ring_doorbell_pa;
+ u32 transfer_ring_doorbell_pa_hi;
+
+ u32 event_ring_base_pa;
+ u32 event_ring_base_pa_hi;
+
+ u32 event_ring_size;
+
+ u32 event_ring_doorbell_pa;
+ u32 event_ring_doorbell_pa_hi;
+
+ u16 num_pkt_buffers;
+ u8 ipa_pipe_number;
+ u8 dir;
+
+ u16 pkt_offset;
+ u16 reserved0;
+
+ u32 desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE];
+} __packed;
+
/**
* struct Ipa3HwNtnCommonChCmdData_t - Structure holding the
* parameters for Ntn Tear down command data params
@@ -357,6 +388,13 @@
uint32_t raw32b;
} __packed;
+union IpaHwWdi3CommonChCmdData_t {
+ struct IpaHwWdi3CommonChCmdParams_t {
+ u32 ipa_pipe_number :8;
+ u32 reserved :24;
+ } __packed params;
+ u32 raw32b;
+} __packed;
/**
* struct Ipa3HwNTNErrorEventData_t - Structure holding the
@@ -447,13 +485,30 @@
* the offload commands from CPU
* @IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP : Command to set up
* Offload protocol's Tx/Rx Path
- * @IPA_CPU_2_HW_CMD_OFFLOAD_RX_SET_UP : Command to tear down
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN : Command to tear down
+ * Offload protocol's Tx/ Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE : Command to enable
+ * Offload protocol's Tx/Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE : Command to disable
+ * Offload protocol's Tx/ Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND : Command to suspend
+ * Offload protocol's Tx/Rx Path
+ * @IPA_CPU_2_HW_CMD_OFFLOAD_RESUME : Command to resume
* Offload protocol's Tx/ Rx Path
*/
enum ipa_cpu_2_hw_offload_commands {
IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 1),
- IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN,
+ IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 2),
+ IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 3),
+ IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 4),
+ IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 5),
+ IPA_CPU_2_HW_CMD_OFFLOAD_RESUME =
+ FEATURE_ENUM_VAL(IPA_HW_FEATURE_OFFLOAD, 6),
};
@@ -523,6 +578,7 @@
*/
union IpaHwSetUpCmd {
struct Ipa3HwNtnSetUpCmdData_t NtnSetupCh_params;
+ struct IpaHwWdi3SetUpCmdData_t Wdi3SetupCh_params;
} __packed;
/**
@@ -553,6 +609,7 @@
*/
union IpaHwCommonChCmd {
union Ipa3HwNtnCommonChCmdData_t NtnCommonCh_params;
+ union IpaHwWdi3CommonChCmdData_t Wdi3CommonCh_params;
} __packed;
struct IpaHwOffloadCommonChCmdData_t {
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c
index c97d2b3..b8928da 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c
@@ -672,19 +672,19 @@
unsigned long *iova)
{
/* support for SMMU on WLAN but no SMMU on IPA */
- if (wlan_smmu_en && ipa3_ctx->smmu_s1_bypass) {
+ if (wlan_smmu_en && ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC]) {
IPAERR("Unsupported SMMU pairing\n");
return -EINVAL;
}
/* legacy: no SMMUs on either end */
- if (!wlan_smmu_en && ipa3_ctx->smmu_s1_bypass) {
+ if (!wlan_smmu_en && ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC]) {
*iova = pa;
return 0;
}
/* no SMMU on WLAN but SMMU on IPA */
- if (!wlan_smmu_en && !ipa3_ctx->smmu_s1_bypass) {
+ if (!wlan_smmu_en && !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC]) {
if (ipa_create_uc_smmu_mapping_pa(pa, len,
(res_idx == IPA_WDI_CE_DB_RES) ? true : false, iova)) {
IPAERR("Fail to create mapping res %d\n", res_idx);
@@ -695,7 +695,7 @@
}
/* SMMU on WLAN and SMMU on IPA */
- if (wlan_smmu_en && !ipa3_ctx->smmu_s1_bypass) {
+ if (wlan_smmu_en && !ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_UC]) {
switch (res_idx) {
case IPA_WDI_RX_RING_RP_RES:
case IPA_WDI_RX_COMP_RING_WP_RES:
@@ -1821,6 +1821,11 @@
return -EINVAL;
}
+ if (ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_WLAN]) {
+ IPAERR("IPA SMMU not enabled\n");
+ return -EINVAL;
+ }
+
for (i = 0; i < num_buffers; i++) {
IPADBG("i=%d pa=0x%pa iova=0x%lx sz=0x%zx\n", i,
&info[i].pa, info[i].iova, info[i].size);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index f717264..ae05880 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -4497,6 +4497,10 @@
api_ctrl->ipa_get_pdev = ipa3_get_pdev;
api_ctrl->ipa_ntn_uc_reg_rdyCB = ipa3_ntn_uc_reg_rdyCB;
api_ctrl->ipa_ntn_uc_dereg_rdyCB = ipa3_ntn_uc_dereg_rdyCB;
+ api_ctrl->ipa_conn_wdi3_pipes = ipa3_conn_wdi3_pipes;
+ api_ctrl->ipa_disconn_wdi3_pipes = ipa3_disconn_wdi3_pipes;
+ api_ctrl->ipa_enable_wdi3_pipes = ipa3_enable_wdi3_pipes;
+ api_ctrl->ipa_disable_wdi3_pipes = ipa3_disable_wdi3_pipes;
return 0;
}
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c b/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c
new file mode 100644
index 0000000..7801745
--- /dev/null
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c
@@ -0,0 +1,407 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include "ipa_i.h"
+#include <linux/ipa_wdi3.h>
+
+#define IPA_HW_WDI3_RX_MBOX_START_INDEX 48
+#define IPA_HW_WDI3_TX_MBOX_START_INDEX 50
+
+static int ipa3_send_wdi3_setup_pipe_cmd(
+ struct ipa_wdi3_setup_info *info, u8 dir)
+{
+ int ipa_ep_idx;
+ int result = 0;
+ struct ipa_mem_buffer cmd;
+ struct IpaHwWdi3SetUpCmdData_t *wdi3_params;
+ struct IpaHwOffloadSetUpCmdData_t *cmd_data;
+
+ if (info == NULL) {
+ IPAERR("invalid input\n");
+ return -EINVAL;
+ }
+
+ ipa_ep_idx = ipa_get_ep_mapping(info->client);
+ if (ipa_ep_idx == -1) {
+ IPAERR("fail to get ep idx.\n");
+ return -EFAULT;
+ }
+
+ IPADBG("client=%d ep=%d\n", info->client, ipa_ep_idx);
+ IPADBG("ring_base_pa = 0x%pad\n", &info->transfer_ring_base_pa);
+ IPADBG("ring_size = %hu\n", info->transfer_ring_size);
+ IPADBG("ring_db_pa = 0x%pad\n", &info->transfer_ring_doorbell_pa);
+ IPADBG("evt_ring_base_pa = 0x%pad\n", &info->event_ring_base_pa);
+ IPADBG("evt_ring_size = %hu\n", info->event_ring_size);
+ IPADBG("evt_ring_db_pa = 0x%pad\n", &info->event_ring_doorbell_pa);
+ IPADBG("num_pkt_buffers = %hu\n", info->num_pkt_buffers);
+ IPADBG("pkt_offset = %d\n", info->pkt_offset);
+
+ cmd.size = sizeof(*cmd_data);
+ cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size,
+ &cmd.phys_base, GFP_KERNEL);
+ if (cmd.base == NULL) {
+ IPAERR("fail to get DMA memory.\n");
+ return -ENOMEM;
+ }
+
+ cmd_data = (struct IpaHwOffloadSetUpCmdData_t *)cmd.base;
+ cmd_data->protocol = IPA_HW_FEATURE_WDI3;
+
+ wdi3_params = &cmd_data->SetupCh_params.Wdi3SetupCh_params;
+ wdi3_params->transfer_ring_base_pa = (u32)info->transfer_ring_base_pa;
+ wdi3_params->transfer_ring_base_pa_hi =
+ (u32)((u64)info->transfer_ring_base_pa >> 32);
+ wdi3_params->transfer_ring_size = info->transfer_ring_size;
+ wdi3_params->transfer_ring_doorbell_pa =
+ (u32)info->transfer_ring_doorbell_pa;
+ wdi3_params->transfer_ring_doorbell_pa_hi =
+ (u32)((u64)info->transfer_ring_doorbell_pa >> 32);
+ wdi3_params->event_ring_base_pa = (u32)info->event_ring_base_pa;
+ wdi3_params->event_ring_base_pa_hi =
+ (u32)((u64)info->event_ring_base_pa >> 32);
+ wdi3_params->event_ring_size = info->event_ring_size;
+ wdi3_params->event_ring_doorbell_pa =
+ (u32)info->event_ring_doorbell_pa;
+ wdi3_params->event_ring_doorbell_pa_hi =
+ (u32)((u64)info->event_ring_doorbell_pa >> 32);
+ wdi3_params->num_pkt_buffers = info->num_pkt_buffers;
+ wdi3_params->ipa_pipe_number = ipa_ep_idx;
+ wdi3_params->dir = dir;
+ wdi3_params->pkt_offset = info->pkt_offset;
+ memcpy(wdi3_params->desc_format_template, info->desc_format_template,
+ sizeof(wdi3_params->desc_format_template));
+
+ result = ipa3_uc_send_cmd((u32)(cmd.phys_base),
+ IPA_CPU_2_HW_CMD_OFFLOAD_CHANNEL_SET_UP,
+ IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
+ false, 10*HZ);
+ if (result) {
+ IPAERR("uc setup channel cmd failed: %d\n", result);
+ result = -EFAULT;
+ }
+
+ dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);
+ return result;
+}
+
+int ipa3_conn_wdi3_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out)
+{
+ struct ipa3_ep_context *ep_rx;
+ struct ipa3_ep_context *ep_tx;
+ int ipa_ep_idx_rx;
+ int ipa_ep_idx_tx;
+ int result = 0;
+
+ if (in == NULL || out == NULL) {
+ IPAERR("invalid input\n");
+ return -EINVAL;
+ }
+
+ ipa_ep_idx_rx = ipa_get_ep_mapping(in->rx.client);
+ ipa_ep_idx_tx = ipa_get_ep_mapping(in->tx.client);
+ if (ipa_ep_idx_rx == -1 || ipa_ep_idx_tx == -1) {
+ IPAERR("fail to alloc EP.\n");
+ return -EFAULT;
+ }
+ if (ipa_ep_idx_rx >= IPA3_MAX_NUM_PIPES ||
+ ipa_ep_idx_tx >= IPA3_MAX_NUM_PIPES) {
+ IPAERR("ep out of range.\n");
+ return -EFAULT;
+ }
+
+ ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx];
+ ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx];
+
+ if (ep_rx->valid || ep_tx->valid) {
+ IPAERR("EP already allocated.\n");
+ return -EFAULT;
+ }
+
+ memset(ep_rx, 0, offsetof(struct ipa3_ep_context, sys));
+ memset(ep_tx, 0, offsetof(struct ipa3_ep_context, sys));
+
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+
+ /* setup rx ep cfg */
+ ep_rx->valid = 1;
+ ep_rx->client = in->rx.client;
+ result = ipa3_disable_data_path(ipa_ep_idx_rx);
+ if (result) {
+ IPAERR("disable data path failed res=%d clnt=%d.\n", result,
+ ipa_ep_idx_rx);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return -EFAULT;
+ }
+ ep_rx->client_notify = in->notify;
+ ep_rx->priv = in->priv;
+
+ memcpy(&ep_rx->cfg, &in->rx.ipa_ep_cfg, sizeof(ep_rx->cfg));
+
+ if (ipa3_cfg_ep(ipa_ep_idx_rx, &ep_rx->cfg)) {
+ IPAERR("fail to setup rx pipe cfg\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ if (ipa3_send_wdi3_setup_pipe_cmd(&in->rx, IPA_WDI3_RX_DIR)) {
+ IPAERR("fail to send cmd to uc for rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ ipa3_install_dflt_flt_rules(ipa_ep_idx_rx);
+ out->rx_uc_db_pa = ipa3_ctx->ipa_wrapper_base +
+ ipahal_get_reg_base() +
+ ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n,
+ IPA_HW_WDI3_RX_MBOX_START_INDEX/32,
+ IPA_HW_WDI3_RX_MBOX_START_INDEX % 32);
+
+ IPADBG("client %d (ep: %d) connected\n", in->rx.client,
+ ipa_ep_idx_rx);
+
+ /* setup dl ep cfg */
+ ep_tx->valid = 1;
+ ep_tx->client = in->tx.client;
+ result = ipa3_disable_data_path(ipa_ep_idx_tx);
+ if (result) {
+ IPAERR("disable data path failed res=%d ep=%d.\n", result,
+ ipa_ep_idx_tx);
+ result = -EFAULT;
+ goto fail;
+ }
+
+ memcpy(&ep_tx->cfg, &in->tx.ipa_ep_cfg, sizeof(ep_tx->cfg));
+
+ if (ipa3_cfg_ep(ipa_ep_idx_tx, &ep_tx->cfg)) {
+ IPAERR("fail to setup tx pipe cfg\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ if (ipa3_send_wdi3_setup_pipe_cmd(&in->tx, IPA_WDI3_TX_DIR)) {
+ IPAERR("fail to send cmd to uc for tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ out->tx_uc_db_pa = ipa3_ctx->ipa_wrapper_base +
+ ipahal_get_reg_base() +
+ ipahal_get_reg_mn_ofst(IPA_UC_MAILBOX_m_n,
+ IPA_HW_WDI3_TX_MBOX_START_INDEX/32,
+ IPA_HW_WDI3_TX_MBOX_START_INDEX % 32);
+ out->tx_uc_db_va = ioremap(out->tx_uc_db_pa, 4);
+ if (!out->tx_uc_db_va) {
+ IPAERR("fail to ioremap tx uc db\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ IPADBG("client %d (ep: %d) connected\n", in->tx.client,
+ ipa_ep_idx_tx);
+
+fail:
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return result;
+}
+
+static int ipa3_send_wdi3_common_ch_cmd(int ipa_ep_idx, int command)
+{
+ struct ipa_mem_buffer cmd;
+ struct IpaHwOffloadCommonChCmdData_t *cmd_data;
+ union IpaHwWdi3CommonChCmdData_t *wdi3;
+ int result = 0;
+
+ cmd.size = sizeof(*cmd_data);
+ cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size,
+ &cmd.phys_base, GFP_KERNEL);
+ if (cmd.base == NULL) {
+ IPAERR("fail to get DMA memory.\n");
+ return -ENOMEM;
+ }
+
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+ /* enable the TX pipe */
+ cmd_data = (struct IpaHwOffloadCommonChCmdData_t *)cmd.base;
+ cmd_data->protocol = IPA_HW_FEATURE_WDI3;
+
+ wdi3 = &cmd_data->CommonCh_params.Wdi3CommonCh_params;
+ wdi3->params.ipa_pipe_number = ipa_ep_idx;
+ result = ipa3_uc_send_cmd((u32)(cmd.phys_base), command,
+ IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
+ false, 10*HZ);
+ if (result) {
+ result = -EFAULT;
+ goto fail;
+ }
+
+fail:
+ dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return result;
+}
+
+int ipa3_disconn_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ struct ipa3_ep_context *ep_tx, *ep_rx;
+ int result = 0;
+
+ IPADBG("ep_tx = %d\n", ipa_ep_idx_tx);
+ IPADBG("ep_rx = %d\n", ipa_ep_idx_rx);
+
+ if (ipa_ep_idx_tx < 0 || ipa_ep_idx_tx >= IPA3_MAX_NUM_PIPES ||
+ ipa_ep_idx_rx < 0 || ipa_ep_idx_rx >= IPA3_MAX_NUM_PIPES) {
+ IPAERR("invalid ipa ep index\n");
+ return -EINVAL;
+ }
+
+ ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx];
+ ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx];
+
+ /* tear down tx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN)) {
+ IPAERR("fail to tear down tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ ipa3_disable_data_path(ipa_ep_idx_tx);
+ memset(ep_tx, 0, sizeof(struct ipa3_ep_context));
+ IPADBG("tx client (ep: %d) disconnected\n", ipa_ep_idx_tx);
+
+ /* tear down rx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_TEAR_DOWN)) {
+ IPAERR("fail to tear down rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+ ipa3_disable_data_path(ipa_ep_idx_rx);
+ ipa3_delete_dflt_flt_rules(ipa_ep_idx_rx);
+ memset(ep_rx, 0, sizeof(struct ipa3_ep_context));
+ IPADBG("rx client (ep: %d) disconnected\n", ipa_ep_idx_rx);
+
+fail:
+ return result;
+}
+
+int ipa3_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ struct ipa3_ep_context *ep_tx, *ep_rx;
+ int result = 0;
+
+ IPADBG("ep_tx = %d\n", ipa_ep_idx_tx);
+ IPADBG("ep_rx = %d\n", ipa_ep_idx_rx);
+
+ ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx];
+ ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx];
+
+ /* enable tx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE)) {
+ IPAERR("fail to enable tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* resume tx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_RESUME)) {
+ IPAERR("fail to resume tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* enable rx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_ENABLE)) {
+ IPAERR("fail to enable rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* resume rx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_RESUME)) {
+ IPAERR("fail to resume rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ IPA_ACTIVE_CLIENTS_INC_SIMPLE();
+
+ /* enable data path */
+ result = ipa3_enable_data_path(ipa_ep_idx_rx);
+ if (result) {
+ IPAERR("enable data path failed res=%d clnt=%d.\n", result,
+ ipa_ep_idx_rx);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return -EFAULT;
+ }
+
+ result = ipa3_enable_data_path(ipa_ep_idx_tx);
+ if (result) {
+ IPAERR("enable data path failed res=%d clnt=%d.\n", result,
+ ipa_ep_idx_tx);
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+ return -EFAULT;
+ }
+
+ IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
+
+fail:
+ return result;
+}
+
+int ipa3_disable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx)
+{
+ struct ipa3_ep_context *ep_tx, *ep_rx;
+ int result = 0;
+
+ IPADBG("ep_tx = %d\n", ipa_ep_idx_tx);
+ IPADBG("ep_rx = %d\n", ipa_ep_idx_rx);
+
+ ep_tx = &ipa3_ctx->ep[ipa_ep_idx_tx];
+ ep_rx = &ipa3_ctx->ep[ipa_ep_idx_rx];
+
+ /* suspend tx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND)) {
+ IPAERR("fail to suspend tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* disable tx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_tx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE)) {
+ IPAERR("fail to disable tx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* suspend rx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_SUSPEND)) {
+ IPAERR("fail to suspend rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+ /* disable rx pipe */
+ if (ipa3_send_wdi3_common_ch_cmd(ipa_ep_idx_rx,
+ IPA_CPU_2_HW_CMD_OFFLOAD_DISABLE)) {
+ IPAERR("fail to disable rx pipe\n");
+ result = -EFAULT;
+ goto fail;
+ }
+
+fail:
+ return result;
+}
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c
index acc72f0..d6dbc85 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c
@@ -1500,10 +1500,10 @@
static int ipa_fltrt_generate_hw_rule_bdy_from_eq(
const struct ipa_ipfltri_rule_eq *attrib, u8 **buf)
{
- int num_offset_meq_32 = attrib->num_offset_meq_32;
- int num_ihl_offset_range_16 = attrib->num_ihl_offset_range_16;
- int num_ihl_offset_meq_32 = attrib->num_ihl_offset_meq_32;
- int num_offset_meq_128 = attrib->num_offset_meq_128;
+ uint8_t num_offset_meq_32 = attrib->num_offset_meq_32;
+ uint8_t num_ihl_offset_range_16 = attrib->num_ihl_offset_range_16;
+ uint8_t num_ihl_offset_meq_32 = attrib->num_ihl_offset_meq_32;
+ uint8_t num_offset_meq_128 = attrib->num_offset_meq_128;
int i;
int extra_bytes;
u8 *extra;
diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
index e5791b1..e93210d 100644
--- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
@@ -677,6 +677,8 @@
param->global = false;
param->num_rules = (uint8_t)1;
+ memset(req, 0, sizeof(struct ipa_fltr_installed_notif_req_msg_v01));
+
for (i = 0; i < rmnet_ipa3_ctx->num_q6_rules; i++) {
param->ip = ipa3_qmi_ctx->q6_ul_filter_rule[i].ip;
memset(&flt_rule_entry, 0, sizeof(struct ipa_flt_rule_add));
@@ -1639,8 +1641,8 @@
/* Get driver name */
case RMNET_IOCTL_GET_DRIVER_NAME:
memcpy(&extend_ioctl_data.u.if_name,
- IPA_NETDEV()->name,
- sizeof(IFNAMSIZ));
+ IPA_NETDEV()->name, IFNAMSIZ);
+ extend_ioctl_data.u.if_name[IFNAMSIZ - 1] = '\0';
if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data,
&extend_ioctl_data,
sizeof(struct rmnet_ioctl_extended_s)))
@@ -1665,6 +1667,8 @@
add_mux_channel_lock);
return -EFAULT;
}
+ extend_ioctl_data.u.rmnet_mux_val.vchannel_name
+ [IFNAMSIZ-1] = '\0';
IPAWANDBG("ADD_MUX_CHANNEL(%d, name: %s)\n",
extend_ioctl_data.u.rmnet_mux_val.mux_id,
extend_ioctl_data.u.rmnet_mux_val.vchannel_name);
@@ -1731,6 +1735,7 @@
sizeof(wan_msg->upstream_ifname);
strlcpy(wan_msg->upstream_ifname,
extend_ioctl_data.u.if_name, len);
+ wan_msg->upstream_ifname[len-1] = '\0';
memset(&msg_meta, 0, sizeof(struct ipa_msg_meta));
msg_meta.msg_type = WAN_XLAT_CONNECT;
msg_meta.msg_len = sizeof(struct ipa_wan_msg);
diff --git a/drivers/platform/msm/ipa/test/ipa_ut_framework.c b/drivers/platform/msm/ipa/test/ipa_ut_framework.c
index 3bf9ac1..dfc8442 100644
--- a/drivers/platform/msm/ipa/test/ipa_ut_framework.c
+++ b/drivers/platform/msm/ipa/test/ipa_ut_framework.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -215,6 +215,10 @@
IPA_UT_DBG("Entry\n");
mutex_lock(&ipa_ut_ctx->lock);
+ if (file == NULL) {
+ rc = -EFAULT;
+ goto unlock_mutex;
+ }
suite = file->f_inode->i_private;
ipa_assert_on(!suite);
meta_type = (long)(file->private_data);
@@ -470,6 +474,10 @@
IPA_UT_DBG("Entry\n");
mutex_lock(&ipa_ut_ctx->lock);
+ if (file == NULL) {
+ rc = -EFAULT;
+ goto unlock_mutex;
+ }
test = file->f_inode->i_private;
ipa_assert_on(!test);
diff --git a/drivers/platform/msm/qcom-geni-se.c b/drivers/platform/msm/qcom-geni-se.c
index 707c95e..423c8f1 100644
--- a/drivers/platform/msm/qcom-geni-se.c
+++ b/drivers/platform/msm/qcom-geni-se.c
@@ -1284,10 +1284,9 @@
geni_se_dev = dev_get_drvdata(rsc->wrapper_dev);
if (unlikely(!geni_se_dev || !geni_se_dev->bus_bw))
return;
- mutex_lock(&geni_se_dev->ab_ib_lock);
if (unlikely(list_empty(&rsc->ab_list) || list_empty(&rsc->ib_list))) {
GENI_SE_DBG(ipc, false, NULL, "%s: Clocks not on\n", __func__);
- goto exit_geni_se_dump_dbg_regs;
+ return;
}
m_cmd0 = geni_read_reg(base, SE_GENI_M_CMD0);
m_irq_status = geni_read_reg(base, SE_GENI_M_IRQ_STATUS);
@@ -1315,8 +1314,6 @@
se_dma_dbg, m_cmd_ctrl, se_dma_rx_len, se_dma_rx_len_in);
GENI_SE_DBG(ipc, false, NULL,
"dma_txlen:0x%x, dma_txlen_in:0x%x\n", se_dma_tx_len, se_dma_tx_len_in);
-exit_geni_se_dump_dbg_regs:
- mutex_unlock(&geni_se_dev->ab_ib_lock);
}
EXPORT_SYMBOL(geni_se_dump_dbg_regs);
diff --git a/drivers/power/reset/msm-poweroff.c b/drivers/power/reset/msm-poweroff.c
index 8d023a8..c090b2a 100644
--- a/drivers/power/reset/msm-poweroff.c
+++ b/drivers/power/reset/msm-poweroff.c
@@ -533,7 +533,7 @@
pr_err("unable to map imem KASLR offset\n");
}
- if (kaslr_imem_addr && scm_is_secure_device()) {
+ if (kaslr_imem_addr) {
__raw_writel(0xdead4ead, kaslr_imem_addr);
__raw_writel(KASLR_OFFSET_BIT_MASK &
(kimage_vaddr - KIMAGE_VADDR), kaslr_imem_addr + 4);
@@ -603,7 +603,6 @@
if (scm_is_call_available(SCM_SVC_PWR, SCM_IO_DEASSERT_PS_HOLD) > 0)
scm_deassert_ps_hold_supported = true;
- download_mode = scm_is_secure_device();
set_dload_mode(download_mode);
return 0;
diff --git a/drivers/power/supply/qcom/Kconfig b/drivers/power/supply/qcom/Kconfig
index b3a00e8..25ad740 100644
--- a/drivers/power/supply/qcom/Kconfig
+++ b/drivers/power/supply/qcom/Kconfig
@@ -1,5 +1,14 @@
menu "Qualcomm Technologies Inc Charger and Fuel Gauge support"
+config QPNP_FG
+ tristate "QPNP fuel gauge driver"
+ depends on MFD_SPMI_PMIC
+ help
+ Say Y here to enable the Fuel Gauge driver. This adds support for
+ battery fuel gauging and state of charge of battery connected to the
+ fuel gauge. The state of charge is reported through a BMS power
+ supply property and also sends uevents when the capacity is updated.
+
config QPNP_FG_GEN3
tristate "QPNP GEN3 fuel gauge driver"
depends on MFD_SPMI_PMIC
diff --git a/drivers/power/supply/qcom/Makefile b/drivers/power/supply/qcom/Makefile
index c2b0fd9..21f63ee 100644
--- a/drivers/power/supply/qcom/Makefile
+++ b/drivers/power/supply/qcom/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_QPNP_FG) += qpnp-fg.o
obj-$(CONFIG_QPNP_FG_GEN3) += qpnp-fg-gen3.o fg-memif.o fg-util.o
obj-$(CONFIG_QPNP_SMBCHARGER) += qpnp-smbcharger.o pmic-voter.o
obj-$(CONFIG_SMB135X_CHARGER) += smb135x-charger.o pmic-voter.o
diff --git a/drivers/power/supply/qcom/fg-core.h b/drivers/power/supply/qcom/fg-core.h
index 3ca5def..7c10e63 100644
--- a/drivers/power/supply/qcom/fg-core.h
+++ b/drivers/power/supply/qcom/fg-core.h
@@ -426,6 +426,7 @@
int batt_id_ohms;
int ki_coeff_full_soc;
int charge_status;
+ int prev_charge_status;
int charge_done;
int charge_type;
int online_status;
diff --git a/drivers/power/supply/qcom/fg-util.c b/drivers/power/supply/qcom/fg-util.c
index fc60b26..622bfad 100644
--- a/drivers/power/supply/qcom/fg-util.c
+++ b/drivers/power/supply/qcom/fg-util.c
@@ -266,8 +266,7 @@
int fg_sram_write(struct fg_chip *chip, u16 address, u8 offset,
u8 *val, int len, int flags)
{
- int rc = 0;
- bool tried_again = false;
+ int rc = 0, tries = 0;
bool atomic_access = false;
if (!chip)
@@ -292,7 +291,7 @@
enable_irq(chip->irqs[SOC_UPDATE_IRQ].irq);
atomic_access = true;
}
-wait:
+
/*
* Atomic access mean waiting upon SOC_UPDATE interrupt from
* FG_ALG and do the transaction after that. This is to make
@@ -301,16 +300,20 @@
* FG cycle (~1.47 seconds).
*/
if (atomic_access) {
- /* Wait for SOC_UPDATE completion */
- rc = wait_for_completion_interruptible_timeout(
- &chip->soc_update,
- msecs_to_jiffies(SOC_UPDATE_WAIT_MS));
+ for (tries = 0; tries < 2; tries++) {
+ /* Wait for SOC_UPDATE completion */
+ rc = wait_for_completion_interruptible_timeout(
+ &chip->soc_update,
+ msecs_to_jiffies(SOC_UPDATE_WAIT_MS));
+ if (rc > 0) {
+ rc = 0;
+ break;
+ } else if (!rc) {
+ rc = -ETIMEDOUT;
+ }
+ }
- /* If we were interrupted wait again one more time. */
- if (rc == -ERESTARTSYS && !tried_again) {
- tried_again = true;
- goto wait;
- } else if (rc <= 0) {
+ if (rc < 0) {
pr_err("wait for soc_update timed out rc=%d\n", rc);
goto out;
}
diff --git a/drivers/power/supply/qcom/qpnp-fg-gen3.c b/drivers/power/supply/qcom/qpnp-fg-gen3.c
index fc34a8c9..2a47442 100644
--- a/drivers/power/supply/qcom/qpnp-fg-gen3.c
+++ b/drivers/power/supply/qcom/qpnp-fg-gen3.c
@@ -562,6 +562,21 @@
return 0;
}
+#define BATT_SOC_32BIT GENMASK(31, 0)
+static int fg_get_charge_counter_shadow(struct fg_chip *chip, int *val)
+{
+ int rc, batt_soc;
+
+ rc = fg_get_sram_prop(chip, FG_SRAM_BATT_SOC, &batt_soc);
+ if (rc < 0) {
+ pr_err("Error in getting BATT_SOC, rc=%d\n", rc);
+ return rc;
+ }
+
+ *val = div_u64((u32)batt_soc * chip->cl.learned_cc_uah, BATT_SOC_32BIT);
+ return 0;
+}
+
static int fg_get_charge_counter(struct fg_chip *chip, int *val)
{
int rc, cc_soc;
@@ -1148,7 +1163,7 @@
enable_irq_wake(chip->irqs[BATT_MISSING_IRQ].irq);
} else {
disable_irq_wake(chip->irqs[BATT_MISSING_IRQ].irq);
- disable_irq(chip->irqs[BATT_MISSING_IRQ].irq);
+ disable_irq_nosync(chip->irqs[BATT_MISSING_IRQ].irq);
}
return 0;
@@ -1167,7 +1182,7 @@
enable_irq_wake(chip->irqs[BSOC_DELTA_IRQ].irq);
} else {
disable_irq_wake(chip->irqs[BSOC_DELTA_IRQ].irq);
- disable_irq(chip->irqs[BSOC_DELTA_IRQ].irq);
+ disable_irq_nosync(chip->irqs[BSOC_DELTA_IRQ].irq);
}
return 0;
@@ -1249,6 +1264,21 @@
return true;
}
+static int fg_prime_cc_soc_sw(struct fg_chip *chip, int cc_soc_sw)
+{
+ int rc;
+
+ rc = fg_sram_write(chip, chip->sp[FG_SRAM_CC_SOC_SW].addr_word,
+ chip->sp[FG_SRAM_CC_SOC_SW].addr_byte, (u8 *)&cc_soc_sw,
+ chip->sp[FG_SRAM_CC_SOC_SW].len, FG_IMA_ATOMIC);
+ if (rc < 0)
+ pr_err("Error in writing cc_soc_sw, rc=%d\n", rc);
+ else
+ fg_dbg(chip, FG_STATUS, "cc_soc_sw: %x\n", cc_soc_sw);
+
+ return rc;
+}
+
static int fg_save_learned_cap_to_sram(struct fg_chip *chip)
{
int16_t cc_mah;
@@ -1434,7 +1464,6 @@
return 0;
}
-#define BATT_SOC_32BIT GENMASK(31, 0)
static int fg_cap_learning_begin(struct fg_chip *chip, u32 batt_soc)
{
int rc, cc_soc_sw, batt_soc_msb;
@@ -1453,16 +1482,13 @@
/* Prime cc_soc_sw with battery SOC when capacity learning begins */
cc_soc_sw = div64_s64((int64_t)batt_soc * CC_SOC_30BIT,
BATT_SOC_32BIT);
- rc = fg_sram_write(chip, chip->sp[FG_SRAM_CC_SOC_SW].addr_word,
- chip->sp[FG_SRAM_CC_SOC_SW].addr_byte, (u8 *)&cc_soc_sw,
- chip->sp[FG_SRAM_CC_SOC_SW].len, FG_IMA_ATOMIC);
+ rc = fg_prime_cc_soc_sw(chip, cc_soc_sw);
if (rc < 0) {
pr_err("Error in writing cc_soc_sw, rc=%d\n", rc);
goto out;
}
chip->cl.init_cc_soc_sw = cc_soc_sw;
- chip->cl.active = true;
fg_dbg(chip, FG_CAP_LEARN, "Capacity learning started @ battery SOC %d init_cc_soc_sw:%d\n",
batt_soc_msb, chip->cl.init_cc_soc_sw);
out:
@@ -1482,9 +1508,7 @@
/* Write a FULL value to cc_soc_sw */
cc_soc_sw = CC_SOC_30BIT;
- rc = fg_sram_write(chip, chip->sp[FG_SRAM_CC_SOC_SW].addr_word,
- chip->sp[FG_SRAM_CC_SOC_SW].addr_byte, (u8 *)&cc_soc_sw,
- chip->sp[FG_SRAM_CC_SOC_SW].len, FG_IMA_ATOMIC);
+ rc = fg_prime_cc_soc_sw(chip, cc_soc_sw);
if (rc < 0) {
pr_err("Error in writing cc_soc_sw, rc=%d\n", rc);
goto out;
@@ -1497,8 +1521,9 @@
static void fg_cap_learning_update(struct fg_chip *chip)
{
- int rc, batt_soc, batt_soc_msb;
+ int rc, batt_soc, batt_soc_msb, cc_soc_sw;
bool input_present = is_input_present(chip);
+ bool prime_cc = false;
mutex_lock(&chip->cl.lock);
@@ -1511,6 +1536,9 @@
goto out;
}
+ if (chip->charge_status == chip->prev_charge_status)
+ goto out;
+
rc = fg_get_sram_prop(chip, FG_SRAM_BATT_SOC, &batt_soc);
if (rc < 0) {
pr_err("Error in getting ACT_BATT_CAP, rc=%d\n", rc);
@@ -1526,8 +1554,12 @@
if (chip->charge_status == POWER_SUPPLY_STATUS_CHARGING) {
rc = fg_cap_learning_begin(chip, batt_soc);
chip->cl.active = (rc == 0);
+ } else {
+ if ((chip->charge_status ==
+ POWER_SUPPLY_STATUS_DISCHARGING) ||
+ chip->charge_done)
+ prime_cc = true;
}
-
} else {
if (chip->charge_done) {
rc = fg_cap_learning_done(chip);
@@ -1545,6 +1577,7 @@
batt_soc_msb);
chip->cl.active = false;
chip->cl.init_cc_uah = 0;
+ prime_cc = true;
}
}
@@ -1561,10 +1594,29 @@
batt_soc_msb);
chip->cl.active = false;
chip->cl.init_cc_uah = 0;
+ prime_cc = true;
}
}
}
+ /*
+ * Prime CC_SOC_SW when the device is not charging or during charge
+ * termination when the capacity learning is not active.
+ */
+
+ if (prime_cc) {
+ if (chip->charge_done)
+ cc_soc_sw = CC_SOC_30BIT;
+ else
+ cc_soc_sw = div_u64((u32)batt_soc *
+ CC_SOC_30BIT, BATT_SOC_32BIT);
+
+ rc = fg_prime_cc_soc_sw(chip, cc_soc_sw);
+ if (rc < 0)
+ pr_err("Error in writing cc_soc_sw, rc=%d\n",
+ rc);
+ }
+
out:
mutex_unlock(&chip->cl.lock);
}
@@ -1779,7 +1831,8 @@
fg_dbg(chip, FG_STATUS, "Terminated charging @ SOC%d\n",
msoc);
}
- } else if (msoc_raw <= recharge_soc && chip->charge_full) {
+ } else if ((msoc_raw <= recharge_soc || !chip->charge_done)
+ && chip->charge_full) {
if (chip->dt.linearize_soc) {
chip->delta_soc = FULL_CAPACITY - msoc;
@@ -2563,7 +2616,7 @@
}
fg_ttf_update(chip);
-
+ chip->prev_charge_status = chip->charge_status;
out:
fg_dbg(chip, FG_POWER_SUPPLY, "charge_status:%d charge_type:%d charge_done:%d\n",
chip->charge_status, chip->charge_type, chip->charge_done);
@@ -3555,6 +3608,9 @@
case POWER_SUPPLY_PROP_CHARGE_COUNTER:
rc = fg_get_charge_counter(chip, &pval->intval);
break;
+ case POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW:
+ rc = fg_get_charge_counter_shadow(chip, &pval->intval);
+ break;
case POWER_SUPPLY_PROP_TIME_TO_FULL_AVG:
rc = fg_get_time_to_full(chip, &pval->intval);
break;
@@ -3765,6 +3821,7 @@
POWER_SUPPLY_PROP_CHARGE_NOW,
POWER_SUPPLY_PROP_CHARGE_FULL,
POWER_SUPPLY_PROP_CHARGE_COUNTER,
+ POWER_SUPPLY_PROP_CHARGE_COUNTER_SHADOW,
POWER_SUPPLY_PROP_TIME_TO_FULL_AVG,
POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
POWER_SUPPLY_PROP_SOC_REPORTING_READY,
@@ -4585,7 +4642,7 @@
#define DEFAULT_BATT_TEMP_HOT 50
#define DEFAULT_CL_START_SOC 15
#define DEFAULT_CL_MIN_TEMP_DECIDEGC 150
-#define DEFAULT_CL_MAX_TEMP_DECIDEGC 450
+#define DEFAULT_CL_MAX_TEMP_DECIDEGC 500
#define DEFAULT_CL_MAX_INC_DECIPERC 5
#define DEFAULT_CL_MAX_DEC_DECIPERC 100
#define DEFAULT_CL_MIN_LIM_DECIPERC 0
@@ -5000,6 +5057,7 @@
chip->debug_mask = &fg_gen3_debug_mask;
chip->irqs = fg_irqs;
chip->charge_status = -EINVAL;
+ chip->prev_charge_status = -EINVAL;
chip->ki_coeff_full_soc = -EINVAL;
chip->online_status = -EINVAL;
chip->regmap = dev_get_regmap(chip->dev->parent, NULL);
diff --git a/drivers/power/supply/qcom/qpnp-fg.c b/drivers/power/supply/qcom/qpnp-fg.c
new file mode 100644
index 0000000..17b9c1d3
--- /dev/null
+++ b/drivers/power/supply/qcom/qpnp-fg.c
@@ -0,0 +1,7028 @@
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "FG: %s: " fmt, __func__
+
+#include <linux/atomic.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+#include <linux/of.h>
+#include <linux/rtc.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/init.h>
+#include <linux/spmi.h>
+#include <linux/platform_device.h>
+#include <linux/of_irq.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/ktime.h>
+#include <linux/power_supply.h>
+#include <linux/of_batterydata.h>
+#include <linux/string_helpers.h>
+#include <linux/alarmtimer.h>
+#include <linux/qpnp/qpnp-revid.h>
+
+/* Register offsets */
+
+/* Interrupt offsets */
+#define INT_RT_STS(base) (base + 0x10)
+#define INT_EN_CLR(base) (base + 0x16)
+
+/* SPMI Register offsets */
+#define SOC_MONOTONIC_SOC 0x09
+#define SOC_BOOT_MOD 0x50
+#define SOC_RESTART 0x51
+
+#define REG_OFFSET_PERP_SUBTYPE 0x05
+
+/* RAM register offsets */
+#define RAM_OFFSET 0x400
+
+/* Bit/Mask definitions */
+#define FULL_PERCENT 0xFF
+#define MAX_TRIES_SOC 5
+#define MA_MV_BIT_RES 39
+#define MSB_SIGN BIT(7)
+#define IBAT_VBAT_MASK 0x7F
+#define NO_OTP_PROF_RELOAD BIT(6)
+#define REDO_FIRST_ESTIMATE BIT(3)
+#define RESTART_GO BIT(0)
+#define THERM_DELAY_MASK 0xE0
+
+/* SUBTYPE definitions */
+#define FG_SOC 0x9
+#define FG_BATT 0xA
+#define FG_ADC 0xB
+#define FG_MEMIF 0xC
+
+#define QPNP_FG_DEV_NAME "qcom,qpnp-fg"
+#define MEM_IF_TIMEOUT_MS 5000
+#define BUCKET_COUNT 8
+#define BUCKET_SOC_PCT (256 / BUCKET_COUNT)
+
+#define BCL_MA_TO_ADC(_current, _adc_val) { \
+ _adc_val = (u8)((_current) * 100 / 976); \
+}
+
+/* Debug Flag Definitions */
+enum {
+ FG_SPMI_DEBUG_WRITES = BIT(0), /* Show SPMI writes */
+ FG_SPMI_DEBUG_READS = BIT(1), /* Show SPMI reads */
+ FG_IRQS = BIT(2), /* Show interrupts */
+ FG_MEM_DEBUG_WRITES = BIT(3), /* Show SRAM writes */
+ FG_MEM_DEBUG_READS = BIT(4), /* Show SRAM reads */
+ FG_POWER_SUPPLY = BIT(5), /* Show POWER_SUPPLY */
+ FG_STATUS = BIT(6), /* Show FG status changes */
+ FG_AGING = BIT(7), /* Show FG aging algorithm */
+};
+
+/* PMIC REVISIONS */
+#define REVID_RESERVED 0
+#define REVID_VARIANT 1
+#define REVID_ANA_MAJOR 2
+#define REVID_DIG_MAJOR 3
+
+enum dig_major {
+ DIG_REV_1 = 0x1,
+ DIG_REV_2 = 0x2,
+ DIG_REV_3 = 0x3,
+};
+
+enum pmic_subtype {
+ PMI8994 = 10,
+ PMI8950 = 17,
+ PMI8996 = 19,
+ PMI8937 = 55,
+};
+
+enum wa_flags {
+ IADC_GAIN_COMP_WA = BIT(0),
+ USE_CC_SOC_REG = BIT(1),
+ PULSE_REQUEST_WA = BIT(2),
+ BCL_HI_POWER_FOR_CHGLED_WA = BIT(3)
+};
+
+enum current_sense_type {
+ INTERNAL_CURRENT_SENSE,
+ EXTERNAL_CURRENT_SENSE,
+};
+
+struct fg_mem_setting {
+ u16 address;
+ u8 offset;
+ int value;
+};
+
+struct fg_mem_data {
+ u16 address;
+ u8 offset;
+ unsigned int len;
+ int value;
+};
+
+struct fg_learning_data {
+ int64_t cc_uah;
+ int64_t learned_cc_uah;
+ int init_cc_pc_val;
+ bool active;
+ bool feedback_on;
+ struct mutex learning_lock;
+ ktime_t time_stamp;
+ /* configuration properties */
+ int max_start_soc;
+ int max_increment;
+ int max_decrement;
+ int min_temp;
+ int max_temp;
+ int vbat_est_thr_uv;
+};
+
+struct fg_rslow_data {
+ u8 rslow_cfg;
+ u8 rslow_thr;
+ u8 rs_to_rslow[2];
+ u8 rslow_comp[4];
+ uint32_t chg_rs_to_rslow;
+ uint32_t chg_rslow_comp_c1;
+ uint32_t chg_rslow_comp_c2;
+ uint32_t chg_rslow_comp_thr;
+ bool active;
+ struct mutex lock;
+};
+
+struct fg_cyc_ctr_data {
+ bool en;
+ bool started[BUCKET_COUNT];
+ u16 count[BUCKET_COUNT];
+ u8 last_soc[BUCKET_COUNT];
+ int id;
+ struct mutex lock;
+};
+
+struct fg_iadc_comp_data {
+ u8 dfl_gain_reg[2];
+ bool gain_active;
+ int64_t dfl_gain;
+};
+
+struct fg_cc_soc_data {
+ int init_sys_soc;
+ int init_cc_soc;
+ int full_capacity;
+ int delta_soc;
+};
+
+/* FG_MEMIF setting index */
+enum fg_mem_setting_index {
+ FG_MEM_SOFT_COLD = 0,
+ FG_MEM_SOFT_HOT,
+ FG_MEM_HARD_COLD,
+ FG_MEM_HARD_HOT,
+ FG_MEM_RESUME_SOC,
+ FG_MEM_BCL_LM_THRESHOLD,
+ FG_MEM_BCL_MH_THRESHOLD,
+ FG_MEM_TERM_CURRENT,
+ FG_MEM_CHG_TERM_CURRENT,
+ FG_MEM_IRQ_VOLT_EMPTY,
+ FG_MEM_CUTOFF_VOLTAGE,
+ FG_MEM_VBAT_EST_DIFF,
+ FG_MEM_DELTA_SOC,
+ FG_MEM_BATT_LOW,
+ FG_MEM_THERM_DELAY,
+ FG_MEM_SETTING_MAX,
+};
+
+/* FG_MEMIF data index */
+enum fg_mem_data_index {
+ FG_DATA_BATT_TEMP = 0,
+ FG_DATA_OCV,
+ FG_DATA_VOLTAGE,
+ FG_DATA_CURRENT,
+ FG_DATA_BATT_ESR,
+ FG_DATA_BATT_ESR_COUNT,
+ FG_DATA_BATT_SOC,
+ FG_DATA_CC_CHARGE,
+ FG_DATA_VINT_ERR,
+ FG_DATA_CPRED_VOLTAGE,
+ /* values below this only gets read once per profile reload */
+ FG_DATA_BATT_ID,
+ FG_DATA_BATT_ID_INFO,
+ FG_DATA_MAX,
+};
+
+#define SETTING(_idx, _address, _offset, _value) \
+ [FG_MEM_##_idx] = { \
+ .address = _address, \
+ .offset = _offset, \
+ .value = _value, \
+ } \
+
+static struct fg_mem_setting settings[FG_MEM_SETTING_MAX] = {
+ /* ID Address, Offset, Value*/
+ SETTING(SOFT_COLD, 0x454, 0, 100),
+ SETTING(SOFT_HOT, 0x454, 1, 400),
+ SETTING(HARD_COLD, 0x454, 2, 50),
+ SETTING(HARD_HOT, 0x454, 3, 450),
+ SETTING(RESUME_SOC, 0x45C, 1, 0),
+ SETTING(BCL_LM_THRESHOLD, 0x47C, 2, 50),
+ SETTING(BCL_MH_THRESHOLD, 0x47C, 3, 752),
+ SETTING(TERM_CURRENT, 0x40C, 2, 250),
+ SETTING(CHG_TERM_CURRENT, 0x4F8, 2, 250),
+ SETTING(IRQ_VOLT_EMPTY, 0x458, 3, 3100),
+ SETTING(CUTOFF_VOLTAGE, 0x40C, 0, 3200),
+ SETTING(VBAT_EST_DIFF, 0x000, 0, 30),
+ SETTING(DELTA_SOC, 0x450, 3, 1),
+ SETTING(BATT_LOW, 0x458, 0, 4200),
+ SETTING(THERM_DELAY, 0x4AC, 3, 0),
+};
+
+#define DATA(_idx, _address, _offset, _length, _value) \
+ [FG_DATA_##_idx] = { \
+ .address = _address, \
+ .offset = _offset, \
+ .len = _length, \
+ .value = _value, \
+ } \
+
+static struct fg_mem_data fg_data[FG_DATA_MAX] = {
+ /* ID Address, Offset, Length, Value*/
+ DATA(BATT_TEMP, 0x550, 2, 2, -EINVAL),
+ DATA(OCV, 0x588, 3, 2, -EINVAL),
+ DATA(VOLTAGE, 0x5CC, 1, 2, -EINVAL),
+ DATA(CURRENT, 0x5CC, 3, 2, -EINVAL),
+ DATA(BATT_ESR, 0x554, 2, 2, -EINVAL),
+ DATA(BATT_ESR_COUNT, 0x558, 2, 2, -EINVAL),
+ DATA(BATT_SOC, 0x56C, 1, 3, -EINVAL),
+ DATA(CC_CHARGE, 0x570, 0, 4, -EINVAL),
+ DATA(VINT_ERR, 0x560, 0, 4, -EINVAL),
+ DATA(CPRED_VOLTAGE, 0x540, 0, 2, -EINVAL),
+ DATA(BATT_ID, 0x594, 1, 1, -EINVAL),
+ DATA(BATT_ID_INFO, 0x594, 3, 1, -EINVAL),
+};
+
+static int fg_debug_mask;
+module_param_named(
+ debug_mask, fg_debug_mask, int, 00600
+);
+
+static int fg_sense_type = -EINVAL;
+static int fg_restart;
+
+static int fg_est_dump;
+module_param_named(
+ first_est_dump, fg_est_dump, int, 00600
+);
+
+static char *fg_batt_type;
+module_param_named(
+ battery_type, fg_batt_type, charp, 00600
+);
+
+static int fg_sram_update_period_ms = 30000;
+module_param_named(
+ sram_update_period_ms, fg_sram_update_period_ms, int, 00600
+);
+
+struct fg_irq {
+ int irq;
+ unsigned long disabled;
+};
+
+enum fg_soc_irq {
+ HIGH_SOC,
+ LOW_SOC,
+ FULL_SOC,
+ EMPTY_SOC,
+ DELTA_SOC,
+ FIRST_EST_DONE,
+ SW_FALLBK_OCV,
+ SW_FALLBK_NEW_BATT,
+ FG_SOC_IRQ_COUNT,
+};
+
+enum fg_batt_irq {
+ JEITA_SOFT_COLD,
+ JEITA_SOFT_HOT,
+ VBATT_LOW,
+ BATT_IDENTIFIED,
+ BATT_ID_REQ,
+ BATTERY_UNKNOWN,
+ BATT_MISSING,
+ BATT_MATCH,
+ FG_BATT_IRQ_COUNT,
+};
+
+enum fg_mem_if_irq {
+ FG_MEM_AVAIL,
+ TA_RCVRY_SUG,
+ FG_MEM_IF_IRQ_COUNT,
+};
+
+enum fg_batt_aging_mode {
+ FG_AGING_NONE,
+ FG_AGING_ESR,
+ FG_AGING_CC,
+};
+
+enum register_type {
+ MEM_INTF_CFG,
+ MEM_INTF_CTL,
+ MEM_INTF_ADDR_LSB,
+ MEM_INTF_RD_DATA0,
+ MEM_INTF_WR_DATA0,
+ MAX_ADDRESS,
+};
+
+struct register_offset {
+ u16 address[MAX_ADDRESS];
+};
+
+static struct register_offset offset[] = {
+ [0] = {
+ /* CFG CTL LSB RD0 WD0 */
+ .address = {0x40, 0x41, 0x42, 0x4C, 0x48},
+ },
+ [1] = {
+ /* CFG CTL LSB RD0 WD0 */
+ .address = {0x50, 0x51, 0x61, 0x67, 0x63},
+ },
+};
+
+#define MEM_INTF_CFG(chip) \
+ ((chip)->mem_base + (chip)->offset[MEM_INTF_CFG])
+#define MEM_INTF_CTL(chip) \
+ ((chip)->mem_base + (chip)->offset[MEM_INTF_CTL])
+#define MEM_INTF_ADDR_LSB(chip) \
+ ((chip)->mem_base + (chip)->offset[MEM_INTF_ADDR_LSB])
+#define MEM_INTF_RD_DATA0(chip) \
+ ((chip)->mem_base + (chip)->offset[MEM_INTF_RD_DATA0])
+#define MEM_INTF_WR_DATA0(chip) \
+ ((chip)->mem_base + (chip)->offset[MEM_INTF_WR_DATA0])
+
+struct fg_wakeup_source {
+ struct wakeup_source source;
+ unsigned long enabled;
+};
+
+static void fg_stay_awake(struct fg_wakeup_source *source)
+{
+ if (!__test_and_set_bit(0, &source->enabled)) {
+ __pm_stay_awake(&source->source);
+ pr_debug("enabled source %s\n", source->source.name);
+ }
+}
+
+static void fg_relax(struct fg_wakeup_source *source)
+{
+ if (__test_and_clear_bit(0, &source->enabled)) {
+ __pm_relax(&source->source);
+ pr_debug("disabled source %s\n", source->source.name);
+ }
+}
+
+#define THERMAL_COEFF_N_BYTES 6
+struct fg_chip {
+ struct device *dev;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ u8 pmic_subtype;
+ u8 pmic_revision[4];
+ u8 revision[4];
+ u16 soc_base;
+ u16 batt_base;
+ u16 mem_base;
+ u16 vbat_adc_addr;
+ u16 ibat_adc_addr;
+ u16 tp_rev_addr;
+ u32 wa_flag;
+ atomic_t memif_user_cnt;
+ struct fg_irq soc_irq[FG_SOC_IRQ_COUNT];
+ struct fg_irq batt_irq[FG_BATT_IRQ_COUNT];
+ struct fg_irq mem_irq[FG_MEM_IF_IRQ_COUNT];
+ struct completion sram_access_granted;
+ struct completion sram_access_revoked;
+ struct completion batt_id_avail;
+ struct completion first_soc_done;
+ struct power_supply *bms_psy;
+ struct power_supply_desc bms_psy_d;
+ struct mutex rw_lock;
+ struct mutex sysfs_restart_lock;
+ struct delayed_work batt_profile_init;
+ struct work_struct dump_sram;
+ struct work_struct status_change_work;
+ struct work_struct cycle_count_work;
+ struct work_struct battery_age_work;
+ struct work_struct update_esr_work;
+ struct work_struct set_resume_soc_work;
+ struct work_struct rslow_comp_work;
+ struct work_struct sysfs_restart_work;
+ struct work_struct init_work;
+ struct work_struct charge_full_work;
+ struct work_struct gain_comp_work;
+ struct work_struct bcl_hi_power_work;
+ struct power_supply *batt_psy;
+ struct power_supply *usb_psy;
+ struct power_supply *dc_psy;
+ struct fg_wakeup_source memif_wakeup_source;
+ struct fg_wakeup_source profile_wakeup_source;
+ struct fg_wakeup_source empty_check_wakeup_source;
+ struct fg_wakeup_source resume_soc_wakeup_source;
+ struct fg_wakeup_source gain_comp_wakeup_source;
+ struct fg_wakeup_source capacity_learning_wakeup_source;
+ bool first_profile_loaded;
+ struct fg_wakeup_source update_temp_wakeup_source;
+ struct fg_wakeup_source update_sram_wakeup_source;
+ bool fg_restarting;
+ bool profile_loaded;
+ bool use_otp_profile;
+ bool battery_missing;
+ bool power_supply_registered;
+ bool sw_rbias_ctrl;
+ bool use_thermal_coefficients;
+ bool esr_strict_filter;
+ bool soc_empty;
+ bool charge_done;
+ bool resume_soc_lowered;
+ bool vbat_low_irq_enabled;
+ bool charge_full;
+ bool hold_soc_while_full;
+ bool input_present;
+ bool otg_present;
+ bool safety_timer_expired;
+ bool bad_batt_detection_en;
+ bool bcl_lpm_disabled;
+ bool charging_disabled;
+ struct delayed_work update_jeita_setting;
+ struct delayed_work update_sram_data;
+ struct delayed_work update_temp_work;
+ struct delayed_work check_empty_work;
+ char *batt_profile;
+ u8 thermal_coefficients[THERMAL_COEFF_N_BYTES];
+ u32 cc_cv_threshold_mv;
+ unsigned int batt_profile_len;
+ unsigned int batt_max_voltage_uv;
+ const char *batt_type;
+ const char *batt_psy_name;
+ unsigned long last_sram_update_time;
+ unsigned long last_temp_update_time;
+ int64_t ocv_coeffs[12];
+ int64_t cutoff_voltage;
+ int evaluation_current;
+ int ocv_junction_p1p2;
+ int ocv_junction_p2p3;
+ int nom_cap_uah;
+ int actual_cap_uah;
+ int status;
+ int prev_status;
+ int health;
+ enum fg_batt_aging_mode batt_aging_mode;
+ /* capacity learning */
+ struct fg_learning_data learning_data;
+ struct alarm fg_cap_learning_alarm;
+ struct work_struct fg_cap_learning_work;
+ struct fg_cc_soc_data sw_cc_soc_data;
+ /* rslow compensation */
+ struct fg_rslow_data rslow_comp;
+ /* cycle counter */
+ struct fg_cyc_ctr_data cyc_ctr;
+ /* iadc compensation */
+ struct fg_iadc_comp_data iadc_comp_data;
+ /* interleaved memory access */
+ u16 *offset;
+ bool ima_supported;
+ bool init_done;
+ /* jeita hysteresis */
+ bool jeita_hysteresis_support;
+ bool batt_hot;
+ bool batt_cold;
+ int cold_hysteresis;
+ int hot_hysteresis;
+ /* ESR pulse tuning */
+ struct fg_wakeup_source esr_extract_wakeup_source;
+ struct work_struct esr_extract_config_work;
+ bool esr_extract_disabled;
+ bool imptr_pulse_slow_en;
+ bool esr_pulse_tune_en;
+};
+
+/* FG_MEMIF DEBUGFS structures */
+#define ADDR_LEN 4 /* 3 byte address + 1 space character */
+#define CHARS_PER_ITEM 3 /* Format is 'XX ' */
+#define ITEMS_PER_LINE 4 /* 4 data items per line */
+#define MAX_LINE_LENGTH (ADDR_LEN + (ITEMS_PER_LINE * CHARS_PER_ITEM) + 1)
+#define MAX_REG_PER_TRANSACTION (8)
+
+static const char *DFS_ROOT_NAME = "fg_memif";
+static const mode_t DFS_MODE = 00600;
+static const char *default_batt_type = "Unknown Battery";
+static const char *loading_batt_type = "Loading Battery Data";
+static const char *missing_batt_type = "Disconnected Battery";
+
+/* Log buffer */
+struct fg_log_buffer {
+ size_t rpos; /* Current 'read' position in buffer */
+ size_t wpos; /* Current 'write' position in buffer */
+ size_t len; /* Length of the buffer */
+ char data[0]; /* Log buffer */
+};
+
+/* transaction parameters */
+struct fg_trans {
+ u32 cnt; /* Number of bytes to read */
+ u16 addr; /* 12-bit address in SRAM */
+ u32 offset; /* Offset of last read data + byte offset */
+ struct fg_chip *chip;
+ struct fg_log_buffer *log; /* log buffer */
+ u8 *data; /* fg data that is read */
+};
+
+struct fg_dbgfs {
+ u32 cnt;
+ u32 addr;
+ struct fg_chip *chip;
+ struct dentry *root;
+ struct mutex lock;
+ struct debugfs_blob_wrapper help_msg;
+};
+
+static struct fg_dbgfs dbgfs_data = {
+ .lock = __MUTEX_INITIALIZER(dbgfs_data.lock),
+ .help_msg = {
+ .data =
+"FG Debug-FS support\n"
+"\n"
+"Hierarchy schema:\n"
+"/sys/kernel/debug/fg_memif\n"
+" /help -- Static help text\n"
+" /address -- Starting register address for reads or writes\n"
+" /count -- Number of registers to read (only used for reads)\n"
+" /data -- Initiates the SRAM read (formatted output)\n"
+"\n",
+ },
+};
+
+static const struct of_device_id fg_match_table[] = {
+ { .compatible = QPNP_FG_DEV_NAME, },
+ {}
+};
+
+static char *fg_supplicants[] = {
+ "battery",
+ "bcl",
+ "fg_adc"
+};
+
+#define DEBUG_PRINT_BUFFER_SIZE 64
+static void fill_string(char *str, size_t str_len, u8 *buf, int buf_len)
+{
+ int pos = 0;
+ int i;
+
+ for (i = 0; i < buf_len; i++) {
+ pos += scnprintf(str + pos, str_len - pos, "%02X", buf[i]);
+ if (i < buf_len - 1)
+ pos += scnprintf(str + pos, str_len - pos, " ");
+ }
+}
+
+static int fg_write(struct fg_chip *chip, u8 *val, u16 addr, int len)
+{
+ int rc = 0;
+ struct platform_device *pdev = chip->pdev;
+ char str[DEBUG_PRINT_BUFFER_SIZE];
+
+ if ((addr & 0xff00) == 0) {
+ pr_err("addr cannot be zero base=0x%02x sid=0x%02x rc=%d\n",
+ addr, to_spmi_device(pdev->dev.parent)->usid, rc);
+ return -EINVAL;
+ }
+
+ rc = regmap_bulk_write(chip->regmap, addr, val, len);
+ if (rc) {
+ pr_err("write failed addr=0x%02x sid=0x%02x rc=%d\n",
+ addr, to_spmi_device(pdev->dev.parent)->usid, rc);
+ return rc;
+ }
+
+ if (!rc && (fg_debug_mask & FG_SPMI_DEBUG_WRITES)) {
+ str[0] = '\0';
+ fill_string(str, DEBUG_PRINT_BUFFER_SIZE, val, len);
+ pr_info("write(0x%04X), sid=%d, len=%d; %s\n",
+ addr, to_spmi_device(pdev->dev.parent)->usid, len,
+ str);
+ }
+
+ return rc;
+}
+
+static int fg_read(struct fg_chip *chip, u8 *val, u16 addr, int len)
+{
+ int rc = 0;
+ struct platform_device *pdev = chip->pdev;
+ char str[DEBUG_PRINT_BUFFER_SIZE];
+
+ if ((addr & 0xff00) == 0) {
+ pr_err("base cannot be zero base=0x%02x sid=0x%02x rc=%d\n",
+ addr, to_spmi_device(pdev->dev.parent)->usid, rc);
+ return -EINVAL;
+ }
+
+ rc = regmap_bulk_read(chip->regmap, addr, val, len);
+ if (rc) {
+ pr_err("SPMI read failed base=0x%02x sid=0x%02x rc=%d\n", addr,
+ to_spmi_device(pdev->dev.parent)->usid, rc);
+ return rc;
+ }
+
+ if (!rc && (fg_debug_mask & FG_SPMI_DEBUG_READS)) {
+ str[0] = '\0';
+ fill_string(str, DEBUG_PRINT_BUFFER_SIZE, val, len);
+ pr_info("read(0x%04x), sid=%d, len=%d; %s\n",
+ addr, to_spmi_device(pdev->dev.parent)->usid, len,
+ str);
+ }
+
+ return rc;
+}
+
+static int fg_masked_write(struct fg_chip *chip, u16 addr,
+ u8 mask, u8 val, int len)
+{
+ int rc;
+
+ rc = regmap_update_bits(chip->regmap, addr, mask, val);
+ if (rc) {
+ pr_err("spmi write failed: addr=%03X, rc=%d\n", addr, rc);
+ return rc;
+ }
+
+ return rc;
+}
+
+#define RIF_MEM_ACCESS_REQ BIT(7)
+static int fg_check_rif_mem_access(struct fg_chip *chip, bool *status)
+{
+ int rc;
+ u8 mem_if_sts;
+
+ rc = fg_read(chip, &mem_if_sts, MEM_INTF_CFG(chip), 1);
+ if (rc) {
+ pr_err("failed to read rif_mem status rc=%d\n", rc);
+ return rc;
+ }
+
+ *status = mem_if_sts & RIF_MEM_ACCESS_REQ;
+ return 0;
+}
+
+static bool fg_check_sram_access(struct fg_chip *chip)
+{
+ int rc;
+ u8 mem_if_sts;
+ bool rif_mem_sts = false;
+
+ rc = fg_read(chip, &mem_if_sts, INT_RT_STS(chip->mem_base), 1);
+ if (rc) {
+ pr_err("failed to read mem status rc=%d\n", rc);
+ return false;
+ }
+
+ if ((mem_if_sts & BIT(FG_MEM_AVAIL)) == 0)
+ return false;
+
+ rc = fg_check_rif_mem_access(chip, &rif_mem_sts);
+ if (rc)
+ return false;
+
+ return rif_mem_sts;
+}
+
+static inline int fg_assert_sram_access(struct fg_chip *chip)
+{
+ int rc;
+ u8 mem_if_sts;
+
+ rc = fg_read(chip, &mem_if_sts, INT_RT_STS(chip->mem_base), 1);
+ if (rc) {
+ pr_err("failed to read mem status rc=%d\n", rc);
+ return rc;
+ }
+
+ if ((mem_if_sts & BIT(FG_MEM_AVAIL)) == 0) {
+ pr_err("mem_avail not high: %02x\n", mem_if_sts);
+ return -EINVAL;
+ }
+
+ rc = fg_read(chip, &mem_if_sts, MEM_INTF_CFG(chip), 1);
+ if (rc) {
+ pr_err("failed to read mem status rc=%d\n", rc);
+ return rc;
+ }
+
+ if ((mem_if_sts & RIF_MEM_ACCESS_REQ) == 0) {
+ pr_err("mem_avail not high: %02x\n", mem_if_sts);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#define INTF_CTL_BURST BIT(7)
+#define INTF_CTL_WR_EN BIT(6)
+static int fg_config_access(struct fg_chip *chip, bool write,
+ bool burst)
+{
+ int rc;
+ u8 intf_ctl = 0;
+
+ intf_ctl = (write ? INTF_CTL_WR_EN : 0) | (burst ? INTF_CTL_BURST : 0);
+
+ rc = fg_write(chip, &intf_ctl, MEM_INTF_CTL(chip), 1);
+ if (rc) {
+ pr_err("failed to set mem access bit\n");
+ return -EIO;
+ }
+
+ return rc;
+}
+
+static int fg_req_and_wait_access(struct fg_chip *chip, int timeout)
+{
+ int rc = 0, ret = 0;
+ bool tried_again = false;
+
+ if (!fg_check_sram_access(chip)) {
+ rc = fg_masked_write(chip, MEM_INTF_CFG(chip),
+ RIF_MEM_ACCESS_REQ, RIF_MEM_ACCESS_REQ, 1);
+ if (rc) {
+ pr_err("failed to set mem access bit\n");
+ return -EIO;
+ }
+ fg_stay_awake(&chip->memif_wakeup_source);
+ }
+
+wait:
+ /* Wait for MEM_AVAIL IRQ. */
+ ret = wait_for_completion_interruptible_timeout(
+ &chip->sram_access_granted,
+ msecs_to_jiffies(timeout));
+ /* If we were interrupted wait again one more time. */
+ if (ret == -ERESTARTSYS && !tried_again) {
+ tried_again = true;
+ goto wait;
+ } else if (ret <= 0) {
+ rc = -ETIMEDOUT;
+ pr_err("transaction timed out rc=%d\n", rc);
+ return rc;
+ }
+
+ return rc;
+}
+
+static int fg_release_access(struct fg_chip *chip)
+{
+ int rc;
+
+ rc = fg_masked_write(chip, MEM_INTF_CFG(chip),
+ RIF_MEM_ACCESS_REQ, 0, 1);
+ fg_relax(&chip->memif_wakeup_source);
+ reinit_completion(&chip->sram_access_granted);
+
+ return rc;
+}
+
+static void fg_release_access_if_necessary(struct fg_chip *chip)
+{
+ mutex_lock(&chip->rw_lock);
+ if (atomic_sub_return(1, &chip->memif_user_cnt) <= 0)
+ fg_release_access(chip);
+ mutex_unlock(&chip->rw_lock);
+}
+
+/*
+ * fg_mem_lock disallows the fuel gauge to release access until it has been
+ * released.
+ *
+ * an equal number of calls must be made to fg_mem_release for the fuel gauge
+ * driver to release the sram access.
+ */
+static void fg_mem_lock(struct fg_chip *chip)
+{
+ mutex_lock(&chip->rw_lock);
+ atomic_add_return(1, &chip->memif_user_cnt);
+ mutex_unlock(&chip->rw_lock);
+}
+
+static void fg_mem_release(struct fg_chip *chip)
+{
+ fg_release_access_if_necessary(chip);
+}
+
+static int fg_set_ram_addr(struct fg_chip *chip, u16 *address)
+{
+ int rc;
+
+ rc = fg_write(chip, (u8 *) address,
+ chip->mem_base + chip->offset[MEM_INTF_ADDR_LSB], 2);
+ if (rc) {
+ pr_err("spmi write failed: addr=%03X, rc=%d\n",
+ chip->mem_base + chip->offset[MEM_INTF_ADDR_LSB], rc);
+ return rc;
+ }
+
+ return rc;
+}
+
+#define BUF_LEN 4
+static int fg_sub_mem_read(struct fg_chip *chip, u8 *val, u16 address, int len,
+ int offset)
+{
+ int rc, total_len;
+ u8 *rd_data = val;
+ char str[DEBUG_PRINT_BUFFER_SIZE];
+
+ rc = fg_config_access(chip, 0, (len > 4));
+ if (rc)
+ return rc;
+
+ rc = fg_set_ram_addr(chip, &address);
+ if (rc)
+ return rc;
+
+ if (fg_debug_mask & FG_MEM_DEBUG_READS)
+ pr_info("length %d addr=%02X\n", len, address);
+
+ total_len = len;
+ while (len > 0) {
+ if (!offset) {
+ rc = fg_read(chip, rd_data, MEM_INTF_RD_DATA0(chip),
+ min(len, BUF_LEN));
+ } else {
+ rc = fg_read(chip, rd_data,
+ MEM_INTF_RD_DATA0(chip) + offset,
+ min(len, BUF_LEN - offset));
+
+ /* manually set address to allow continuous reads */
+ address += BUF_LEN;
+
+ rc = fg_set_ram_addr(chip, &address);
+ if (rc)
+ return rc;
+ }
+ if (rc) {
+ pr_err("spmi read failed: addr=%03x, rc=%d\n",
+ MEM_INTF_RD_DATA0(chip) + offset, rc);
+ return rc;
+ }
+ rd_data += (BUF_LEN - offset);
+ len -= (BUF_LEN - offset);
+ offset = 0;
+ }
+
+ if (fg_debug_mask & FG_MEM_DEBUG_READS) {
+ fill_string(str, DEBUG_PRINT_BUFFER_SIZE, val, total_len);
+ pr_info("data: %s\n", str);
+ }
+ return rc;
+}
+
+static int fg_conventional_mem_read(struct fg_chip *chip, u8 *val, u16 address,
+ int len, int offset, bool keep_access)
+{
+ int rc = 0, user_cnt = 0, orig_address = address;
+
+ if (offset > 3) {
+ pr_err("offset too large %d\n", offset);
+ return -EINVAL;
+ }
+
+ address = ((orig_address + offset) / 4) * 4;
+ offset = (orig_address + offset) % 4;
+
+ user_cnt = atomic_add_return(1, &chip->memif_user_cnt);
+ if (fg_debug_mask & FG_MEM_DEBUG_READS)
+ pr_info("user_cnt %d\n", user_cnt);
+ mutex_lock(&chip->rw_lock);
+ if (!fg_check_sram_access(chip)) {
+ rc = fg_req_and_wait_access(chip, MEM_IF_TIMEOUT_MS);
+ if (rc)
+ goto out;
+ }
+
+ rc = fg_sub_mem_read(chip, val, address, len, offset);
+
+out:
+ user_cnt = atomic_sub_return(1, &chip->memif_user_cnt);
+ if (fg_debug_mask & FG_MEM_DEBUG_READS)
+ pr_info("user_cnt %d\n", user_cnt);
+
+ fg_assert_sram_access(chip);
+
+ if (!keep_access && (user_cnt == 0) && !rc) {
+ rc = fg_release_access(chip);
+ if (rc) {
+ pr_err("failed to set mem access bit\n");
+ rc = -EIO;
+ }
+ }
+
+ mutex_unlock(&chip->rw_lock);
+ return rc;
+}
+
+static int fg_conventional_mem_write(struct fg_chip *chip, u8 *val, u16 address,
+ int len, int offset, bool keep_access)
+{
+ int rc = 0, user_cnt = 0, sublen;
+ bool access_configured = false;
+ u8 *wr_data = val, word[4];
+ char str[DEBUG_PRINT_BUFFER_SIZE];
+
+ if (address < RAM_OFFSET)
+ return -EINVAL;
+
+ if (offset > 3)
+ return -EINVAL;
+
+ address = ((address + offset) / 4) * 4;
+ offset = (address + offset) % 4;
+
+ user_cnt = atomic_add_return(1, &chip->memif_user_cnt);
+ if (fg_debug_mask & FG_MEM_DEBUG_WRITES)
+ pr_info("user_cnt %d\n", user_cnt);
+ mutex_lock(&chip->rw_lock);
+ if (!fg_check_sram_access(chip)) {
+ rc = fg_req_and_wait_access(chip, MEM_IF_TIMEOUT_MS);
+ if (rc)
+ goto out;
+ }
+
+ if (fg_debug_mask & FG_MEM_DEBUG_WRITES) {
+ pr_info("length %d addr=%02X offset=%d\n",
+ len, address, offset);
+ fill_string(str, DEBUG_PRINT_BUFFER_SIZE, wr_data, len);
+ pr_info("writing: %s\n", str);
+ }
+
+ while (len > 0) {
+ if (offset != 0) {
+ sublen = min(4 - offset, len);
+ rc = fg_sub_mem_read(chip, word, address, 4, 0);
+ if (rc)
+ goto out;
+ memcpy(word + offset, wr_data, sublen);
+ /* configure access as burst if more to write */
+ rc = fg_config_access(chip, 1, (len - sublen) > 0);
+ if (rc)
+ goto out;
+ rc = fg_set_ram_addr(chip, &address);
+ if (rc)
+ goto out;
+ offset = 0;
+ access_configured = true;
+ } else if (len >= 4) {
+ if (!access_configured) {
+ rc = fg_config_access(chip, 1, len > 4);
+ if (rc)
+ goto out;
+ rc = fg_set_ram_addr(chip, &address);
+ if (rc)
+ goto out;
+ access_configured = true;
+ }
+ sublen = 4;
+ memcpy(word, wr_data, 4);
+ } else if (len > 0 && len < 4) {
+ sublen = len;
+ rc = fg_sub_mem_read(chip, word, address, 4, 0);
+ if (rc)
+ goto out;
+ memcpy(word, wr_data, sublen);
+ rc = fg_config_access(chip, 1, 0);
+ if (rc)
+ goto out;
+ rc = fg_set_ram_addr(chip, &address);
+ if (rc)
+ goto out;
+ access_configured = true;
+ } else {
+ pr_err("Invalid length: %d\n", len);
+ break;
+ }
+ rc = fg_write(chip, word, MEM_INTF_WR_DATA0(chip), 4);
+ if (rc) {
+ pr_err("spmi write failed: addr=%03x, rc=%d\n",
+ MEM_INTF_WR_DATA0(chip), rc);
+ goto out;
+ }
+ len -= sublen;
+ wr_data += sublen;
+ address += 4;
+ }
+
+out:
+ user_cnt = atomic_sub_return(1, &chip->memif_user_cnt);
+ if (fg_debug_mask & FG_MEM_DEBUG_WRITES)
+ pr_info("user_cnt %d\n", user_cnt);
+
+ fg_assert_sram_access(chip);
+
+ if (!keep_access && (user_cnt == 0) && !rc) {
+ rc = fg_release_access(chip);
+ if (rc) {
+ pr_err("failed to set mem access bit\n");
+ rc = -EIO;
+ }
+ }
+
+ mutex_unlock(&chip->rw_lock);
+ return rc;
+}
+
+#define MEM_INTF_IMA_CFG 0x52
+#define MEM_INTF_IMA_OPR_STS 0x54
+#define MEM_INTF_IMA_ERR_STS 0x5F
+#define MEM_INTF_IMA_EXP_STS 0x55
+#define MEM_INTF_IMA_HW_STS 0x56
+#define MEM_INTF_IMA_BYTE_EN 0x60
+#define IMA_ADDR_STBL_ERR BIT(7)
+#define IMA_WR_ACS_ERR BIT(6)
+#define IMA_RD_ACS_ERR BIT(5)
+#define IMA_IACS_CLR BIT(2)
+#define IMA_IACS_RDY BIT(1)
+static int fg_check_ima_exception(struct fg_chip *chip)
+{
+ int rc = 0, ret = 0;
+ u8 err_sts, exp_sts = 0, hw_sts = 0;
+
+ rc = fg_read(chip, &err_sts,
+ chip->mem_base + MEM_INTF_IMA_ERR_STS, 1);
+ if (rc) {
+ pr_err("failed to read beat count rc=%d\n", rc);
+ return rc;
+ }
+
+ if (err_sts & (IMA_ADDR_STBL_ERR | IMA_WR_ACS_ERR | IMA_RD_ACS_ERR)) {
+ u8 temp;
+
+ fg_read(chip, &exp_sts,
+ chip->mem_base + MEM_INTF_IMA_EXP_STS, 1);
+ fg_read(chip, &hw_sts,
+ chip->mem_base + MEM_INTF_IMA_HW_STS, 1);
+ pr_err("IMA access failed ima_err_sts=%x ima_exp_sts=%x ima_hw_sts=%x\n",
+ err_sts, exp_sts, hw_sts);
+ rc = err_sts;
+
+ /* clear the error */
+ ret |= fg_masked_write(chip, chip->mem_base + MEM_INTF_IMA_CFG,
+ IMA_IACS_CLR, IMA_IACS_CLR, 1);
+ temp = 0x4;
+ ret |= fg_write(chip, &temp, MEM_INTF_ADDR_LSB(chip) + 1, 1);
+ temp = 0x0;
+ ret |= fg_write(chip, &temp, MEM_INTF_WR_DATA0(chip) + 3, 1);
+ ret |= fg_read(chip, &temp, MEM_INTF_RD_DATA0(chip) + 3, 1);
+ ret |= fg_masked_write(chip, chip->mem_base + MEM_INTF_IMA_CFG,
+ IMA_IACS_CLR, 0, 1);
+ if (!ret)
+ return -EAGAIN;
+
+ pr_err("Error clearing IMA exception ret=%d\n", ret);
+ }
+
+ return rc;
+}
+
+static int fg_check_iacs_ready(struct fg_chip *chip)
+{
+ int rc = 0, timeout = 250;
+ u8 ima_opr_sts = 0;
+
+ /*
+ * Additional delay to make sure IACS ready bit is set after
+ * Read/Write operation.
+ */
+
+ usleep_range(30, 35);
+ while (1) {
+ rc = fg_read(chip, &ima_opr_sts,
+ chip->mem_base + MEM_INTF_IMA_OPR_STS, 1);
+ if (!rc && (ima_opr_sts & IMA_IACS_RDY))
+ break;
+
+ if (!(--timeout) || rc)
+ break;
+ /* delay for iacs_ready to be asserted */
+ usleep_range(5000, 7000);
+ }
+
+ if (!timeout || rc) {
+ pr_err("IACS_RDY not set\n");
+ /* perform IACS_CLR sequence */
+ fg_check_ima_exception(chip);
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+#define IACS_SLCT BIT(5)
+static int __fg_interleaved_mem_write(struct fg_chip *chip, u8 *val,
+ u16 address, int offset, int len)
+{
+ int rc = 0, i;
+ u8 *word = val, byte_enable = 0, num_bytes = 0;
+
+ if (fg_debug_mask & FG_MEM_DEBUG_WRITES)
+ pr_info("length %d addr=%02X offset=%d\n",
+ len, address, offset);
+
+ while (len > 0) {
+ num_bytes = (offset + len) > BUF_LEN ?
+ (BUF_LEN - offset) : len;
+ /* write to byte_enable */
+ for (i = offset; i < (offset + num_bytes); i++)
+ byte_enable |= BIT(i);
+
+ rc = fg_write(chip, &byte_enable,
+ chip->mem_base + MEM_INTF_IMA_BYTE_EN, 1);
+ if (rc) {
+ pr_err("Unable to write to byte_en_reg rc=%d\n", rc);
+ return rc;
+ }
+ /* write data */
+ rc = fg_write(chip, word, MEM_INTF_WR_DATA0(chip) + offset,
+ num_bytes);
+ if (rc) {
+ pr_err("spmi write failed: addr=%03x, rc=%d\n",
+ MEM_INTF_WR_DATA0(chip) + offset, rc);
+ return rc;
+ }
+ /*
+ * The last-byte WR_DATA3 starts the write transaction.
+ * Write a dummy value to WR_DATA3 if it does not have
+ * valid data. This dummy data is not written to the
+ * SRAM as byte_en for WR_DATA3 is not set.
+ */
+ if (!(byte_enable & BIT(3))) {
+ u8 dummy_byte = 0x0;
+
+ rc = fg_write(chip, &dummy_byte,
+ MEM_INTF_WR_DATA0(chip) + 3, 1);
+ if (rc) {
+ pr_err("Unable to write dummy-data to WR_DATA3 rc=%d\n",
+ rc);
+ return rc;
+ }
+ }
+
+ rc = fg_check_iacs_ready(chip);
+ if (rc) {
+ pr_debug("IACS_RDY failed rc=%d\n", rc);
+ return rc;
+ }
+
+ /* check for error condition */
+ rc = fg_check_ima_exception(chip);
+ if (rc) {
+ pr_err("IMA transaction failed rc=%d", rc);
+ return rc;
+ }
+
+ word += num_bytes;
+ len -= num_bytes;
+ offset = byte_enable = 0;
+ }
+
+ return rc;
+}
+
+static int __fg_interleaved_mem_read(struct fg_chip *chip, u8 *val, u16 address,
+ int offset, int len)
+{
+ int rc = 0, total_len;
+ u8 *rd_data = val, num_bytes;
+ char str[DEBUG_PRINT_BUFFER_SIZE];
+
+ if (fg_debug_mask & FG_MEM_DEBUG_READS)
+ pr_info("length %d addr=%02X\n", len, address);
+
+ total_len = len;
+ while (len > 0) {
+ num_bytes = (offset + len) > BUF_LEN ? (BUF_LEN - offset) : len;
+ rc = fg_read(chip, rd_data, MEM_INTF_RD_DATA0(chip) + offset,
+ num_bytes);
+ if (rc) {
+ pr_err("spmi read failed: addr=%03x, rc=%d\n",
+ MEM_INTF_RD_DATA0(chip) + offset, rc);
+ return rc;
+ }
+
+ rd_data += num_bytes;
+ len -= num_bytes;
+ offset = 0;
+
+ rc = fg_check_iacs_ready(chip);
+ if (rc) {
+ pr_debug("IACS_RDY failed rc=%d\n", rc);
+ return rc;
+ }
+
+ /* check for error condition */
+ rc = fg_check_ima_exception(chip);
+ if (rc) {
+ pr_err("IMA transaction failed rc=%d", rc);
+ return rc;
+ }
+
+ if (len && (len + offset) < BUF_LEN) {
+ /* move to single mode */
+ u8 intr_ctl = 0;
+
+ rc = fg_write(chip, &intr_ctl, MEM_INTF_CTL(chip), 1);
+ if (rc) {
+ pr_err("failed to move to single mode rc=%d\n",
+ rc);
+ return -EIO;
+ }
+ }
+ }
+
+ if (fg_debug_mask & FG_MEM_DEBUG_READS) {
+ fill_string(str, DEBUG_PRINT_BUFFER_SIZE, val, total_len);
+ pr_info("data: %s\n", str);
+ }
+
+ return rc;
+}
+
+#define IMA_REQ_ACCESS (IACS_SLCT | RIF_MEM_ACCESS_REQ)
+static int fg_interleaved_mem_config(struct fg_chip *chip, u8 *val,
+ u16 address, int len, int offset, int op)
+{
+ int rc = 0;
+ bool rif_mem_sts = true;
+ int time_count = 0;
+
+ while (1) {
+ rc = fg_check_rif_mem_access(chip, &rif_mem_sts);
+ if (rc)
+ return rc;
+
+ if (!rif_mem_sts)
+ break;
+
+ if (fg_debug_mask & (FG_MEM_DEBUG_READS | FG_MEM_DEBUG_WRITES))
+ pr_info("RIF_MEM_ACCESS_REQ is not clear yet for IMA_%s\n",
+ op ? "write" : "read");
+
+ /*
+ * Try this no more than 4 times. If RIF_MEM_ACCESS_REQ is not
+ * clear, then return an error instead of waiting for it again.
+ */
+ if (time_count > 4) {
+ pr_err("Waited for 1.5 seconds polling RIF_MEM_ACCESS_REQ\n");
+ return -ETIMEDOUT;
+ }
+
+ /* Wait for 4ms before reading RIF_MEM_ACCESS_REQ again */
+ usleep_range(4000, 4100);
+ time_count++;
+ }
+
+ /* configure for IMA access */
+ rc = fg_masked_write(chip, MEM_INTF_CFG(chip),
+ IMA_REQ_ACCESS, IMA_REQ_ACCESS, 1);
+ if (rc) {
+ pr_err("failed to set mem access bit rc = %d\n", rc);
+ return rc;
+ }
+
+ /* configure for the read/write single/burst mode */
+ rc = fg_config_access(chip, op, (offset + len) > 4);
+ if (rc) {
+ pr_err("failed to set configure memory access rc = %d\n", rc);
+ return rc;
+ }
+
+ rc = fg_check_iacs_ready(chip);
+ if (rc) {
+ pr_debug("IACS_RDY failed rc=%d\n", rc);
+ return rc;
+ }
+
+ /* write addresses to the register */
+ rc = fg_set_ram_addr(chip, &address);
+ if (rc) {
+ pr_err("failed to set SRAM address rc = %d\n", rc);
+ return rc;
+ }
+
+ rc = fg_check_iacs_ready(chip);
+ if (rc)
+ pr_debug("IACS_RDY failed rc=%d\n", rc);
+
+ return rc;
+}
+
+#define MEM_INTF_FG_BEAT_COUNT 0x57
+#define BEAT_COUNT_MASK 0x0F
+#define RETRY_COUNT 3
+static int fg_interleaved_mem_read(struct fg_chip *chip, u8 *val, u16 address,
+ int len, int offset)
+{
+ int rc = 0, orig_address = address;
+ u8 start_beat_count, end_beat_count, count = 0;
+ bool retry = false;
+
+ if (offset > 3) {
+ pr_err("offset too large %d\n", offset);
+ return -EINVAL;
+ }
+
+ fg_stay_awake(&chip->memif_wakeup_source);
+ address = ((orig_address + offset) / 4) * 4;
+ offset = (orig_address + offset) % 4;
+
+ if (address < RAM_OFFSET) {
+ /*
+ * OTP memory reads need a conventional memory access, do a
+ * conventional read when SRAM offset < RAM_OFFSET.
+ */
+ rc = fg_conventional_mem_read(chip, val, address, len, offset,
+ 0);
+ if (rc)
+ pr_err("Failed to read OTP memory %d\n", rc);
+ goto exit;
+ }
+
+ mutex_lock(&chip->rw_lock);
+
+retry:
+ rc = fg_interleaved_mem_config(chip, val, address, offset, len, 0);
+ if (rc) {
+ pr_err("failed to configure SRAM for IMA rc = %d\n", rc);
+ goto out;
+ }
+
+ /* read the start beat count */
+ rc = fg_read(chip, &start_beat_count,
+ chip->mem_base + MEM_INTF_FG_BEAT_COUNT, 1);
+ if (rc) {
+ pr_err("failed to read beat count rc=%d\n", rc);
+ goto out;
+ }
+
+ /* read data */
+ rc = __fg_interleaved_mem_read(chip, val, address, offset, len);
+ if (rc) {
+ if ((rc == -EAGAIN) && (count < RETRY_COUNT)) {
+ count++;
+ pr_err("IMA access failed retry_count = %d\n", count);
+ goto retry;
+ } else {
+ pr_err("failed to read SRAM address rc = %d\n", rc);
+ goto out;
+ }
+ }
+
+ /* read the end beat count */
+ rc = fg_read(chip, &end_beat_count,
+ chip->mem_base + MEM_INTF_FG_BEAT_COUNT, 1);
+ if (rc) {
+ pr_err("failed to read beat count rc=%d\n", rc);
+ goto out;
+ }
+
+ start_beat_count &= BEAT_COUNT_MASK;
+ end_beat_count &= BEAT_COUNT_MASK;
+ if (fg_debug_mask & FG_MEM_DEBUG_READS)
+ pr_info("Start beat_count = %x End beat_count = %x\n",
+ start_beat_count, end_beat_count);
+ if (start_beat_count != end_beat_count) {
+ if (fg_debug_mask & FG_MEM_DEBUG_READS)
+ pr_info("Beat count do not match - retry transaction\n");
+ retry = true;
+ }
+out:
+ /* Release IMA access */
+ rc = fg_masked_write(chip, MEM_INTF_CFG(chip), IMA_REQ_ACCESS, 0, 1);
+ if (rc)
+ pr_err("failed to reset IMA access bit rc = %d\n", rc);
+
+ if (retry) {
+ retry = false;
+ goto retry;
+ }
+ mutex_unlock(&chip->rw_lock);
+
+exit:
+ fg_relax(&chip->memif_wakeup_source);
+ return rc;
+}
+
+static int fg_interleaved_mem_write(struct fg_chip *chip, u8 *val, u16 address,
+ int len, int offset)
+{
+ int rc = 0, orig_address = address;
+ u8 count = 0;
+
+ if (address < RAM_OFFSET)
+ return -EINVAL;
+
+ if (offset > 3) {
+ pr_err("offset too large %d\n", offset);
+ return -EINVAL;
+ }
+
+ fg_stay_awake(&chip->memif_wakeup_source);
+ address = ((orig_address + offset) / 4) * 4;
+ offset = (orig_address + offset) % 4;
+
+ mutex_lock(&chip->rw_lock);
+
+retry:
+ rc = fg_interleaved_mem_config(chip, val, address, offset, len, 1);
+ if (rc) {
+ pr_err("failed to xonfigure SRAM for IMA rc = %d\n", rc);
+ goto out;
+ }
+
+ /* write data */
+ rc = __fg_interleaved_mem_write(chip, val, address, offset, len);
+ if (rc) {
+ if ((rc == -EAGAIN) && (count < RETRY_COUNT)) {
+ count++;
+ pr_err("IMA access failed retry_count = %d\n", count);
+ goto retry;
+ } else {
+ pr_err("failed to write SRAM address rc = %d\n", rc);
+ goto out;
+ }
+ }
+
+out:
+ /* Release IMA access */
+ rc = fg_masked_write(chip, MEM_INTF_CFG(chip), IMA_REQ_ACCESS, 0, 1);
+ if (rc)
+ pr_err("failed to reset IMA access bit rc = %d\n", rc);
+
+ mutex_unlock(&chip->rw_lock);
+ fg_relax(&chip->memif_wakeup_source);
+ return rc;
+}
+
+static int fg_mem_read(struct fg_chip *chip, u8 *val, u16 address,
+ int len, int offset, bool keep_access)
+{
+ if (chip->ima_supported)
+ return fg_interleaved_mem_read(chip, val, address,
+ len, offset);
+ else
+ return fg_conventional_mem_read(chip, val, address,
+ len, offset, keep_access);
+}
+
+static int fg_mem_write(struct fg_chip *chip, u8 *val, u16 address,
+ int len, int offset, bool keep_access)
+{
+ if (chip->ima_supported)
+ return fg_interleaved_mem_write(chip, val, address,
+ len, offset);
+ else
+ return fg_conventional_mem_write(chip, val, address,
+ len, offset, keep_access);
+}
+
+static int fg_mem_masked_write(struct fg_chip *chip, u16 addr,
+ u8 mask, u8 val, u8 offset)
+{
+ int rc = 0;
+ u8 reg[4];
+ char str[DEBUG_PRINT_BUFFER_SIZE];
+
+ rc = fg_mem_read(chip, reg, addr, 4, 0, 1);
+ if (rc) {
+ pr_err("spmi read failed: addr=%03X, rc=%d\n", addr, rc);
+ return rc;
+ }
+
+ reg[offset] &= ~mask;
+ reg[offset] |= val & mask;
+
+ str[0] = '\0';
+ fill_string(str, DEBUG_PRINT_BUFFER_SIZE, reg, 4);
+ pr_debug("Writing %s address %03x, offset %d\n", str, addr, offset);
+
+ rc = fg_mem_write(chip, reg, addr, 4, 0, 0);
+ if (rc) {
+ pr_err("spmi write failed: addr=%03X, rc=%d\n", addr, rc);
+ return rc;
+ }
+
+ return rc;
+}
+
+static int soc_to_setpoint(int soc)
+{
+ return DIV_ROUND_CLOSEST(soc * 255, 100);
+}
+
+static void batt_to_setpoint_adc(int vbatt_mv, u8 *data)
+{
+ int val;
+ /* Battery voltage is an offset from 0 V and LSB is 1/2^15. */
+ val = DIV_ROUND_CLOSEST(vbatt_mv * 32768, 5000);
+ data[0] = val & 0xFF;
+ data[1] = val >> 8;
+}
+
+static u8 batt_to_setpoint_8b(int vbatt_mv)
+{
+ int val;
+ /* Battery voltage is an offset from 2.5 V and LSB is 5/2^9. */
+ val = (vbatt_mv - 2500) * 512 / 1000;
+ return DIV_ROUND_CLOSEST(val, 5);
+}
+
+static u8 therm_delay_to_setpoint(u32 delay_us)
+{
+ u8 val;
+
+ if (delay_us < 2560)
+ val = 0;
+ else if (delay_us > 163840)
+ val = 7;
+ else
+ val = ilog2(delay_us / 10) - 7;
+ return val << 5;
+}
+
+static int get_current_time(unsigned long *now_tm_sec)
+{
+ struct rtc_time tm;
+ struct rtc_device *rtc;
+ int rc;
+
+ rtc = rtc_class_open(CONFIG_RTC_HCTOSYS_DEVICE);
+ if (rtc == NULL) {
+ pr_err("%s: unable to open rtc device (%s)\n",
+ __FILE__, CONFIG_RTC_HCTOSYS_DEVICE);
+ return -EINVAL;
+ }
+
+ rc = rtc_read_time(rtc, &tm);
+ if (rc) {
+ pr_err("Error reading rtc device (%s) : %d\n",
+ CONFIG_RTC_HCTOSYS_DEVICE, rc);
+ goto close_time;
+ }
+
+ rc = rtc_valid_tm(&tm);
+ if (rc) {
+ pr_err("Invalid RTC time (%s): %d\n",
+ CONFIG_RTC_HCTOSYS_DEVICE, rc);
+ goto close_time;
+ }
+ rtc_tm_to_time(&tm, now_tm_sec);
+
+close_time:
+ rtc_class_close(rtc);
+ return rc;
+}
+
+#define BATTERY_SOC_REG 0x56C
+#define BATTERY_SOC_OFFSET 1
+#define FULL_PERCENT_3B 0xFFFFFF
+static int get_battery_soc_raw(struct fg_chip *chip)
+{
+ int rc;
+ u8 buffer[3];
+
+ rc = fg_mem_read(chip, buffer, BATTERY_SOC_REG, 3, 1, 0);
+ if (rc) {
+ pr_err("Unable to read battery soc: %d\n", rc);
+ return 0;
+ }
+ return (int)(buffer[2] << 16 | buffer[1] << 8 | buffer[0]);
+}
+
+#define COUNTER_IMPTR_REG 0X558
+#define COUNTER_PULSE_REG 0X55C
+#define SOC_FULL_REG 0x564
+#define COUNTER_IMPTR_OFFSET 2
+#define COUNTER_PULSE_OFFSET 0
+#define SOC_FULL_OFFSET 3
+#define ESR_PULSE_RECONFIG_SOC 0xFFF971
+static int fg_configure_soc(struct fg_chip *chip)
+{
+ u32 batt_soc;
+ u8 cntr[2] = {0, 0};
+ int rc = 0;
+
+ mutex_lock(&chip->rw_lock);
+ atomic_add_return(1, &chip->memif_user_cnt);
+ mutex_unlock(&chip->rw_lock);
+
+ /* Read Battery SOC */
+ batt_soc = get_battery_soc_raw(chip);
+
+ if (batt_soc > ESR_PULSE_RECONFIG_SOC) {
+ if (fg_debug_mask & FG_POWER_SUPPLY)
+ pr_info("Configuring soc registers batt_soc: %x\n",
+ batt_soc);
+ batt_soc = ESR_PULSE_RECONFIG_SOC;
+ rc = fg_mem_write(chip, (u8 *)&batt_soc, BATTERY_SOC_REG, 3,
+ BATTERY_SOC_OFFSET, 1);
+ if (rc) {
+ pr_err("failed to write BATT_SOC rc=%d\n", rc);
+ goto out;
+ }
+
+ rc = fg_mem_write(chip, (u8 *)&batt_soc, SOC_FULL_REG, 3,
+ SOC_FULL_OFFSET, 1);
+ if (rc) {
+ pr_err("failed to write SOC_FULL rc=%d\n", rc);
+ goto out;
+ }
+
+ rc = fg_mem_write(chip, cntr, COUNTER_IMPTR_REG, 2,
+ COUNTER_IMPTR_OFFSET, 1);
+ if (rc) {
+ pr_err("failed to write COUNTER_IMPTR rc=%d\n", rc);
+ goto out;
+ }
+
+ rc = fg_mem_write(chip, cntr, COUNTER_PULSE_REG, 2,
+ COUNTER_PULSE_OFFSET, 0);
+ if (rc)
+ pr_err("failed to write COUNTER_IMPTR rc=%d\n", rc);
+ }
+out:
+ fg_release_access_if_necessary(chip);
+ return rc;
+}
+
+#define SOC_EMPTY BIT(3)
+static bool fg_is_batt_empty(struct fg_chip *chip)
+{
+ u8 fg_soc_sts;
+ int rc;
+
+ rc = fg_read(chip, &fg_soc_sts,
+ INT_RT_STS(chip->soc_base), 1);
+ if (rc) {
+ pr_err("spmi read failed: addr=%03X, rc=%d\n",
+ INT_RT_STS(chip->soc_base), rc);
+ return false;
+ }
+
+ return (fg_soc_sts & SOC_EMPTY) != 0;
+}
+
+static int get_monotonic_soc_raw(struct fg_chip *chip)
+{
+ u8 cap[2];
+ int rc, tries = 0;
+
+ while (tries < MAX_TRIES_SOC) {
+ rc = fg_read(chip, cap,
+ chip->soc_base + SOC_MONOTONIC_SOC, 2);
+ if (rc) {
+ pr_err("spmi read failed: addr=%03x, rc=%d\n",
+ chip->soc_base + SOC_MONOTONIC_SOC, rc);
+ return rc;
+ }
+
+ if (cap[0] == cap[1])
+ break;
+
+ tries++;
+ }
+
+ if (tries == MAX_TRIES_SOC) {
+ pr_err("shadow registers do not match\n");
+ return -EINVAL;
+ }
+
+ if (fg_debug_mask & FG_POWER_SUPPLY)
+ pr_info_ratelimited("raw: 0x%02x\n", cap[0]);
+ return cap[0];
+}
+
+#define EMPTY_CAPACITY 0
+#define DEFAULT_CAPACITY 50
+#define MISSING_CAPACITY 100
+#define FULL_CAPACITY 100
+#define FULL_SOC_RAW 0xFF
+static int get_prop_capacity(struct fg_chip *chip)
+{
+ int msoc;
+
+ if (chip->battery_missing)
+ return MISSING_CAPACITY;
+ if (!chip->profile_loaded && !chip->use_otp_profile)
+ return DEFAULT_CAPACITY;
+ if (chip->charge_full)
+ return FULL_CAPACITY;
+ if (chip->soc_empty) {
+ if (fg_debug_mask & FG_POWER_SUPPLY)
+ pr_info_ratelimited("capacity: %d, EMPTY\n",
+ EMPTY_CAPACITY);
+ return EMPTY_CAPACITY;
+ }
+ msoc = get_monotonic_soc_raw(chip);
+ if (msoc == 0)
+ return EMPTY_CAPACITY;
+ else if (msoc == FULL_SOC_RAW)
+ return FULL_CAPACITY;
+ return DIV_ROUND_CLOSEST((msoc - 1) * (FULL_CAPACITY - 2),
+ FULL_SOC_RAW - 2) + 1;
+}
+
+#define HIGH_BIAS 3
+#define MED_BIAS BIT(1)
+#define LOW_BIAS BIT(0)
+static u8 bias_ua[] = {
+ [HIGH_BIAS] = 150,
+ [MED_BIAS] = 15,
+ [LOW_BIAS] = 5,
+};
+
+static int64_t get_batt_id(unsigned int battery_id_uv, u8 bid_info)
+{
+ u64 battery_id_ohm;
+
+ if ((bid_info & 0x3) == 0) {
+ pr_err("can't determine battery id 0x%02x\n", bid_info);
+ return -EINVAL;
+ }
+
+ battery_id_ohm = div_u64(battery_id_uv, bias_ua[bid_info & 0x3]);
+
+ return battery_id_ohm;
+}
+
+#define DEFAULT_TEMP_DEGC 250
+static int get_sram_prop_now(struct fg_chip *chip, unsigned int type)
+{
+ if (fg_debug_mask & FG_POWER_SUPPLY)
+ pr_info("addr 0x%02X, offset %d value %d\n",
+ fg_data[type].address, fg_data[type].offset,
+ fg_data[type].value);
+
+ if (type == FG_DATA_BATT_ID)
+ return get_batt_id(fg_data[type].value,
+ fg_data[FG_DATA_BATT_ID_INFO].value);
+
+ return fg_data[type].value;
+}
+
+#define MIN_TEMP_DEGC -300
+#define MAX_TEMP_DEGC 970
+static int get_prop_jeita_temp(struct fg_chip *chip, unsigned int type)
+{
+ if (fg_debug_mask & FG_POWER_SUPPLY)
+ pr_info("addr 0x%02X, offset %d\n", settings[type].address,
+ settings[type].offset);
+
+ return settings[type].value;
+}
+
+static int set_prop_jeita_temp(struct fg_chip *chip,
+ unsigned int type, int decidegc)
+{
+ int rc = 0;
+
+ if (fg_debug_mask & FG_POWER_SUPPLY)
+ pr_info("addr 0x%02X, offset %d temp%d\n",
+ settings[type].address,
+ settings[type].offset, decidegc);
+
+ settings[type].value = decidegc;
+
+ cancel_delayed_work_sync(
+ &chip->update_jeita_setting);
+ schedule_delayed_work(
+ &chip->update_jeita_setting, 0);
+
+ return rc;
+}
+
+#define EXTERNAL_SENSE_SELECT 0x4AC
+#define EXTERNAL_SENSE_OFFSET 0x2
+#define EXTERNAL_SENSE_BIT BIT(2)
+static int set_prop_sense_type(struct fg_chip *chip, int ext_sense_type)
+{
+ int rc;
+
+ rc = fg_mem_masked_write(chip, EXTERNAL_SENSE_SELECT,
+ EXTERNAL_SENSE_BIT,
+ ext_sense_type ? EXTERNAL_SENSE_BIT : 0,
+ EXTERNAL_SENSE_OFFSET);
+ if (rc) {
+ pr_err("failed to write profile rc=%d\n", rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+#define EXPONENT_MASK 0xF800
+#define MANTISSA_MASK 0x3FF
+#define SIGN BIT(10)
+#define EXPONENT_SHIFT 11
+#define MICRO_UNIT 1000000ULL
+static int64_t float_decode(u16 reg)
+{
+ int64_t final_val, exponent_val, mantissa_val;
+ int exponent, mantissa, n;
+ bool sign;
+
+ exponent = (reg & EXPONENT_MASK) >> EXPONENT_SHIFT;
+ mantissa = (reg & MANTISSA_MASK);
+ sign = !!(reg & SIGN);
+
+ pr_debug("exponent=%d mantissa=%d sign=%d\n", exponent, mantissa, sign);
+
+ mantissa_val = mantissa * MICRO_UNIT;
+
+ n = exponent - 15;
+ if (n < 0)
+ exponent_val = MICRO_UNIT >> -n;
+ else
+ exponent_val = MICRO_UNIT << n;
+
+ n = n - 10;
+ if (n < 0)
+ mantissa_val >>= -n;
+ else
+ mantissa_val <<= n;
+
+ final_val = exponent_val + mantissa_val;
+
+ if (sign)
+ final_val *= -1;
+
+ return final_val;
+}
+
+#define MIN_HALFFLOAT_EXP_N -15
+#define MAX_HALFFLOAT_EXP_N 16
+static int log2_floor(int64_t uval)
+{
+ int n = 0;
+ int64_t i = MICRO_UNIT;
+
+ if (uval > i) {
+ while (uval > i && n > MIN_HALFFLOAT_EXP_N) {
+ i <<= 1;
+ n += 1;
+ }
+ if (uval < i)
+ n -= 1;
+ } else if (uval < i) {
+ while (uval < i && n < MAX_HALFFLOAT_EXP_N) {
+ i >>= 1;
+ n -= 1;
+ }
+ }
+
+ return n;
+}
+
+static int64_t exp2_int(int64_t n)
+{
+ int p = n - 1;
+
+ if (p > 0)
+ return (2 * MICRO_UNIT) << p;
+ else
+ return (2 * MICRO_UNIT) >> abs(p);
+}
+
+static u16 float_encode(int64_t uval)
+{
+ int sign = 0, n, exp, mantissa;
+ u16 half = 0;
+
+ if (uval < 0) {
+ sign = 1;
+ uval = abs(uval);
+ }
+ n = log2_floor(uval);
+ exp = n + 15;
+ mantissa = div_s64(div_s64((uval - exp2_int(n)) * exp2_int(10 - n),
+ MICRO_UNIT) + MICRO_UNIT / 2, MICRO_UNIT);
+
+ half = (mantissa & MANTISSA_MASK) | ((sign << 10) & SIGN)
+ | ((exp << 11) & EXPONENT_MASK);
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("uval = %lld, m = 0x%02x, sign = 0x%02x, exp = 0x%02x, half = 0x%04x\n",
+ uval, mantissa, sign, exp, half);
+ return half;
+}
+
+#define BATT_IDED BIT(3)
+static int fg_is_batt_id_valid(struct fg_chip *chip)
+{
+ u8 fg_batt_sts;
+ int rc;
+
+ rc = fg_read(chip, &fg_batt_sts,
+ INT_RT_STS(chip->batt_base), 1);
+ if (rc) {
+ pr_err("spmi read failed: addr=%03X, rc=%d\n",
+ INT_RT_STS(chip->batt_base), rc);
+ return rc;
+ }
+
+ if (fg_debug_mask & FG_IRQS)
+ pr_info("fg batt sts 0x%x\n", fg_batt_sts);
+
+ return (fg_batt_sts & BATT_IDED) ? 1 : 0;
+}
+
+static int64_t twos_compliment_extend(int64_t val, int nbytes)
+{
+ int i;
+ int64_t mask;
+
+ mask = 0x80LL << ((nbytes - 1) * 8);
+ if (val & mask) {
+ for (i = 8; i > nbytes; i--) {
+ mask = 0xFFLL << ((i - 1) * 8);
+ val |= mask;
+ }
+ }
+
+ return val;
+}
+
+#define LSB_24B_NUMRTR 596046
+#define LSB_24B_DENMTR 1000000
+#define LSB_16B_NUMRTR 152587
+#define LSB_16B_DENMTR 1000
+#define LSB_8B 9800
+#define TEMP_LSB_16B 625
+#define DECIKELVIN 2730
+#define SRAM_PERIOD_NO_ID_UPDATE_MS 100
+#define FULL_PERCENT_28BIT 0xFFFFFFF
+static void update_sram_data(struct fg_chip *chip, int *resched_ms)
+{
+ int i, j, rc = 0;
+ u8 reg[4];
+ int64_t temp;
+ int battid_valid = fg_is_batt_id_valid(chip);
+
+ fg_stay_awake(&chip->update_sram_wakeup_source);
+ if (chip->fg_restarting)
+ goto resched;
+
+ fg_mem_lock(chip);
+ for (i = 1; i < FG_DATA_MAX; i++) {
+ if (chip->profile_loaded && i >= FG_DATA_BATT_ID)
+ continue;
+ rc = fg_mem_read(chip, reg, fg_data[i].address,
+ fg_data[i].len, fg_data[i].offset, 0);
+ if (rc) {
+ pr_err("Failed to update sram data\n");
+ break;
+ }
+
+ temp = 0;
+ for (j = 0; j < fg_data[i].len; j++)
+ temp |= reg[j] << (8 * j);
+
+ switch (i) {
+ case FG_DATA_OCV:
+ case FG_DATA_VOLTAGE:
+ case FG_DATA_CPRED_VOLTAGE:
+ fg_data[i].value = div_u64(
+ (u64)(u16)temp * LSB_16B_NUMRTR,
+ LSB_16B_DENMTR);
+ break;
+ case FG_DATA_CURRENT:
+ temp = twos_compliment_extend(temp, fg_data[i].len);
+ fg_data[i].value = div_s64(
+ (s64)temp * LSB_16B_NUMRTR,
+ LSB_16B_DENMTR);
+ break;
+ case FG_DATA_BATT_ESR:
+ fg_data[i].value = float_decode((u16) temp);
+ break;
+ case FG_DATA_BATT_ESR_COUNT:
+ fg_data[i].value = (u16)temp;
+ break;
+ case FG_DATA_BATT_ID:
+ if (battid_valid)
+ fg_data[i].value = reg[0] * LSB_8B;
+ break;
+ case FG_DATA_BATT_ID_INFO:
+ if (battid_valid)
+ fg_data[i].value = reg[0];
+ break;
+ case FG_DATA_BATT_SOC:
+ fg_data[i].value = div64_s64((temp * 10000),
+ FULL_PERCENT_3B);
+ break;
+ case FG_DATA_CC_CHARGE:
+ temp = twos_compliment_extend(temp, fg_data[i].len);
+ fg_data[i].value = div64_s64(
+ temp * (int64_t)chip->nom_cap_uah,
+ FULL_PERCENT_28BIT);
+ break;
+ case FG_DATA_VINT_ERR:
+ temp = twos_compliment_extend(temp, fg_data[i].len);
+ fg_data[i].value = div64_s64(temp * chip->nom_cap_uah,
+ FULL_PERCENT_3B);
+ break;
+ };
+
+ if (fg_debug_mask & FG_MEM_DEBUG_READS)
+ pr_info("%d %lld %d\n", i, temp, fg_data[i].value);
+ }
+ fg_mem_release(chip);
+
+ if (!rc)
+ get_current_time(&chip->last_sram_update_time);
+
+resched:
+ if (battid_valid) {
+ complete_all(&chip->batt_id_avail);
+ *resched_ms = fg_sram_update_period_ms;
+ } else {
+ *resched_ms = SRAM_PERIOD_NO_ID_UPDATE_MS;
+ }
+ fg_relax(&chip->update_sram_wakeup_source);
+}
+
+#define SRAM_TIMEOUT_MS 3000
+static void update_sram_data_work(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ update_sram_data.work);
+ int resched_ms = SRAM_PERIOD_NO_ID_UPDATE_MS, ret;
+ bool tried_again = false;
+
+wait:
+ /* Wait for MEMIF access revoked */
+ ret = wait_for_completion_interruptible_timeout(
+ &chip->sram_access_revoked,
+ msecs_to_jiffies(SRAM_TIMEOUT_MS));
+
+ /* If we were interrupted wait again one more time. */
+ if (ret == -ERESTARTSYS && !tried_again) {
+ tried_again = true;
+ goto wait;
+ } else if (ret <= 0) {
+ pr_err("transaction timed out ret=%d\n", ret);
+ goto out;
+ }
+ update_sram_data(chip, &resched_ms);
+
+out:
+ schedule_delayed_work(
+ &chip->update_sram_data,
+ msecs_to_jiffies(resched_ms));
+}
+
+#define BATT_TEMP_OFFSET 3
+#define BATT_TEMP_CNTRL_MASK 0x17
+#define DISABLE_THERM_BIT BIT(0)
+#define TEMP_SENSE_ALWAYS_BIT BIT(1)
+#define TEMP_SENSE_CHARGE_BIT BIT(2)
+#define FORCE_RBIAS_ON_BIT BIT(4)
+#define BATT_TEMP_OFF DISABLE_THERM_BIT
+#define BATT_TEMP_ON (FORCE_RBIAS_ON_BIT | TEMP_SENSE_ALWAYS_BIT | \
+ TEMP_SENSE_CHARGE_BIT)
+#define TEMP_PERIOD_UPDATE_MS 10000
+#define TEMP_PERIOD_TIMEOUT_MS 3000
+static void update_temp_data(struct work_struct *work)
+{
+ s16 temp;
+ u8 reg[2];
+ bool tried_again = false;
+ int rc, ret, timeout = TEMP_PERIOD_TIMEOUT_MS;
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ update_temp_work.work);
+
+ if (chip->fg_restarting)
+ goto resched;
+
+ fg_stay_awake(&chip->update_temp_wakeup_source);
+ if (chip->sw_rbias_ctrl) {
+ rc = fg_mem_masked_write(chip, EXTERNAL_SENSE_SELECT,
+ BATT_TEMP_CNTRL_MASK,
+ BATT_TEMP_ON,
+ BATT_TEMP_OFFSET);
+ if (rc) {
+ pr_err("failed to write BATT_TEMP_ON rc=%d\n", rc);
+ goto out;
+ }
+
+wait:
+ /* Wait for MEMIF access revoked */
+ ret = wait_for_completion_interruptible_timeout(
+ &chip->sram_access_revoked,
+ msecs_to_jiffies(timeout));
+
+ /* If we were interrupted wait again one more time. */
+ if (ret == -ERESTARTSYS && !tried_again) {
+ tried_again = true;
+ goto wait;
+ } else if (ret <= 0) {
+ rc = -ETIMEDOUT;
+ pr_err("transaction timed out ret=%d\n", ret);
+ goto out;
+ }
+ }
+
+ /* Read FG_DATA_BATT_TEMP now */
+ rc = fg_mem_read(chip, reg, fg_data[0].address,
+ fg_data[0].len, fg_data[0].offset,
+ chip->sw_rbias_ctrl ? 1 : 0);
+ if (rc) {
+ pr_err("Failed to update temp data\n");
+ goto out;
+ }
+
+ temp = reg[0] | (reg[1] << 8);
+ fg_data[0].value = (temp * TEMP_LSB_16B / 1000)
+ - DECIKELVIN;
+
+ if (fg_debug_mask & FG_MEM_DEBUG_READS)
+ pr_info("BATT_TEMP %d %d\n", temp, fg_data[0].value);
+
+ get_current_time(&chip->last_temp_update_time);
+
+out:
+ if (chip->sw_rbias_ctrl) {
+ rc = fg_mem_masked_write(chip, EXTERNAL_SENSE_SELECT,
+ BATT_TEMP_CNTRL_MASK,
+ BATT_TEMP_OFF,
+ BATT_TEMP_OFFSET);
+ if (rc)
+ pr_err("failed to write BATT_TEMP_OFF rc=%d\n", rc);
+ }
+ fg_relax(&chip->update_temp_wakeup_source);
+
+resched:
+ schedule_delayed_work(
+ &chip->update_temp_work,
+ msecs_to_jiffies(TEMP_PERIOD_UPDATE_MS));
+}
+
+static void update_jeita_setting(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ update_jeita_setting.work);
+ u8 reg[4];
+ int i, rc;
+
+ for (i = 0; i < 4; i++)
+ reg[i] = (settings[FG_MEM_SOFT_COLD + i].value / 10) + 30;
+
+ rc = fg_mem_write(chip, reg, settings[FG_MEM_SOFT_COLD].address,
+ 4, settings[FG_MEM_SOFT_COLD].offset, 0);
+ if (rc)
+ pr_err("failed to update JEITA setting rc=%d\n", rc);
+}
+
+static int fg_set_resume_soc(struct fg_chip *chip, u8 threshold)
+{
+ u16 address;
+ int offset, rc;
+
+ address = settings[FG_MEM_RESUME_SOC].address;
+ offset = settings[FG_MEM_RESUME_SOC].offset;
+
+ rc = fg_mem_masked_write(chip, address, 0xFF, threshold, offset);
+
+ if (rc)
+ pr_err("write failed rc=%d\n", rc);
+ else
+ pr_debug("setting resume-soc to %x\n", threshold);
+
+ return rc;
+}
+
+#define VBATT_LOW_STS_BIT BIT(2)
+static int fg_get_vbatt_status(struct fg_chip *chip, bool *vbatt_low_sts)
+{
+ int rc = 0;
+ u8 fg_batt_sts;
+
+ rc = fg_read(chip, &fg_batt_sts, INT_RT_STS(chip->batt_base), 1);
+ if (!rc)
+ *vbatt_low_sts = !!(fg_batt_sts & VBATT_LOW_STS_BIT);
+ return rc;
+}
+
+#define BATT_CYCLE_NUMBER_REG 0x5E8
+#define BATT_CYCLE_OFFSET 0
+static void restore_cycle_counter(struct fg_chip *chip)
+{
+ int rc = 0, i, address;
+ u8 data[2];
+
+ fg_mem_lock(chip);
+ for (i = 0; i < BUCKET_COUNT; i++) {
+ address = BATT_CYCLE_NUMBER_REG + i * 2;
+ rc = fg_mem_read(chip, (u8 *)&data, address, 2,
+ BATT_CYCLE_OFFSET, 0);
+ if (rc)
+ pr_err("Failed to read BATT_CYCLE_NUMBER[%d] rc: %d\n",
+ i, rc);
+ else
+ chip->cyc_ctr.count[i] = data[0] | data[1] << 8;
+ }
+ fg_mem_release(chip);
+}
+
+static void clear_cycle_counter(struct fg_chip *chip)
+{
+ int rc = 0, len, i;
+
+ if (!chip->cyc_ctr.en)
+ return;
+
+ len = sizeof(chip->cyc_ctr.count);
+ memset(chip->cyc_ctr.count, 0, len);
+ for (i = 0; i < BUCKET_COUNT; i++) {
+ chip->cyc_ctr.started[i] = false;
+ chip->cyc_ctr.last_soc[i] = 0;
+ }
+ rc = fg_mem_write(chip, (u8 *)&chip->cyc_ctr.count,
+ BATT_CYCLE_NUMBER_REG, len,
+ BATT_CYCLE_OFFSET, 0);
+ if (rc)
+ pr_err("failed to write BATT_CYCLE_NUMBER rc=%d\n", rc);
+}
+
+static int fg_inc_store_cycle_ctr(struct fg_chip *chip, int bucket)
+{
+ int rc = 0, address;
+ u16 cyc_count;
+ u8 data[2];
+
+ if (bucket < 0 || (bucket > BUCKET_COUNT - 1))
+ return 0;
+
+ cyc_count = chip->cyc_ctr.count[bucket];
+ cyc_count++;
+ data[0] = cyc_count & 0xFF;
+ data[1] = cyc_count >> 8;
+
+ address = BATT_CYCLE_NUMBER_REG + bucket * 2;
+
+ rc = fg_mem_write(chip, data, address, 2, BATT_CYCLE_OFFSET, 0);
+ if (rc)
+ pr_err("failed to write BATT_CYCLE_NUMBER[%d] rc=%d\n",
+ bucket, rc);
+ else
+ chip->cyc_ctr.count[bucket] = cyc_count;
+ return rc;
+}
+
+static void update_cycle_count(struct work_struct *work)
+{
+ int rc = 0, bucket, i;
+ u8 reg[3], batt_soc;
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ cycle_count_work);
+
+ mutex_lock(&chip->cyc_ctr.lock);
+ rc = fg_mem_read(chip, reg, BATTERY_SOC_REG, 3,
+ BATTERY_SOC_OFFSET, 0);
+ if (rc) {
+ pr_err("Failed to read battery soc rc: %d\n", rc);
+ goto out;
+ }
+ batt_soc = reg[2];
+
+ if (chip->status == POWER_SUPPLY_STATUS_CHARGING) {
+ /* Find out which bucket the SOC falls in */
+ bucket = batt_soc / BUCKET_SOC_PCT;
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("batt_soc: %x bucket: %d\n", reg[2], bucket);
+
+ /*
+ * If we've started counting for the previous bucket,
+ * then store the counter for that bucket if the
+ * counter for current bucket is getting started.
+ */
+ if (bucket > 0 && chip->cyc_ctr.started[bucket - 1] &&
+ !chip->cyc_ctr.started[bucket]) {
+ rc = fg_inc_store_cycle_ctr(chip, bucket - 1);
+ if (rc) {
+ pr_err("Error in storing cycle_ctr rc: %d\n",
+ rc);
+ goto out;
+ } else {
+ chip->cyc_ctr.started[bucket - 1] = false;
+ chip->cyc_ctr.last_soc[bucket - 1] = 0;
+ }
+ }
+ if (!chip->cyc_ctr.started[bucket]) {
+ chip->cyc_ctr.started[bucket] = true;
+ chip->cyc_ctr.last_soc[bucket] = batt_soc;
+ }
+ } else {
+ for (i = 0; i < BUCKET_COUNT; i++) {
+ if (chip->cyc_ctr.started[i] &&
+ batt_soc > chip->cyc_ctr.last_soc[i]) {
+ rc = fg_inc_store_cycle_ctr(chip, i);
+ if (rc)
+ pr_err("Error in storing cycle_ctr rc: %d\n",
+ rc);
+ chip->cyc_ctr.last_soc[i] = 0;
+ }
+ chip->cyc_ctr.started[i] = false;
+ }
+ }
+out:
+ mutex_unlock(&chip->cyc_ctr.lock);
+}
+
+static int fg_get_cycle_count(struct fg_chip *chip)
+{
+ int count;
+
+ if (!chip->cyc_ctr.en)
+ return 0;
+
+ if ((chip->cyc_ctr.id <= 0) || (chip->cyc_ctr.id > BUCKET_COUNT))
+ return -EINVAL;
+
+ mutex_lock(&chip->cyc_ctr.lock);
+ count = chip->cyc_ctr.count[chip->cyc_ctr.id - 1];
+ mutex_unlock(&chip->cyc_ctr.lock);
+ return count;
+}
+
+static void half_float_to_buffer(int64_t uval, u8 *buffer)
+{
+ u16 raw;
+
+ raw = float_encode(uval);
+ buffer[0] = (u8)(raw & 0xFF);
+ buffer[1] = (u8)((raw >> 8) & 0xFF);
+}
+
+static int64_t half_float(u8 *buffer)
+{
+ u16 val;
+
+ val = buffer[1] << 8 | buffer[0];
+ return float_decode(val);
+}
+
+static int voltage_2b(u8 *buffer)
+{
+ u16 val;
+
+ val = buffer[1] << 8 | buffer[0];
+ /* the range of voltage 2b is [-5V, 5V], so it will fit in an int */
+ return (int)div_u64(((u64)val) * LSB_16B_NUMRTR, LSB_16B_DENMTR);
+}
+
+static int bcap_uah_2b(u8 *buffer)
+{
+ u16 val;
+
+ val = buffer[1] << 8 | buffer[0];
+ return ((int)val) * 1000;
+}
+
+static int lookup_ocv_for_soc(struct fg_chip *chip, int soc)
+{
+ int64_t *coeffs;
+
+ if (soc > chip->ocv_junction_p1p2 * 10)
+ coeffs = chip->ocv_coeffs;
+ else if (soc > chip->ocv_junction_p2p3 * 10)
+ coeffs = chip->ocv_coeffs + 4;
+ else
+ coeffs = chip->ocv_coeffs + 8;
+ /* the range of ocv will fit in a 32 bit int */
+ return (int)(coeffs[0]
+ + div_s64(coeffs[1] * soc, 1000LL)
+ + div_s64(coeffs[2] * soc * soc, 1000000LL)
+ + div_s64(coeffs[3] * soc * soc * soc, 1000000000LL));
+}
+
+static int lookup_soc_for_ocv(struct fg_chip *chip, int ocv)
+{
+ int64_t val;
+ int soc = -EINVAL;
+ /*
+ * binary search variables representing the valid start and end
+ * percentages to search
+ */
+ int start = 0, end = 1000, mid;
+
+ if (fg_debug_mask & FG_AGING)
+ pr_info("target_ocv = %d\n", ocv);
+ /* do a binary search for the closest soc to match the ocv */
+ while (end - start > 1) {
+ mid = (start + end) / 2;
+ val = lookup_ocv_for_soc(chip, mid);
+ if (fg_debug_mask & FG_AGING)
+ pr_info("start = %d, mid = %d, end = %d, ocv = %lld\n",
+ start, mid, end, val);
+ if (ocv < val) {
+ end = mid;
+ } else if (ocv > val) {
+ start = mid;
+ } else {
+ soc = mid;
+ break;
+ }
+ }
+ /*
+ * if the exact soc was not found and there are two or less values
+ * remaining, just compare them and see which one is closest to the ocv
+ */
+ if (soc == -EINVAL) {
+ if (abs(ocv - lookup_ocv_for_soc(chip, start))
+ > abs(ocv - lookup_ocv_for_soc(chip, end)))
+ soc = end;
+ else
+ soc = start;
+ }
+ if (fg_debug_mask & FG_AGING)
+ pr_info("closest = %d, target_ocv = %d, ocv_found = %d\n",
+ soc, ocv, lookup_ocv_for_soc(chip, soc));
+ return soc;
+}
+
+#define ESR_ACTUAL_REG 0x554
+#define BATTERY_ESR_REG 0x4F4
+#define TEMP_RS_TO_RSLOW_REG 0x514
+static int estimate_battery_age(struct fg_chip *chip, int *actual_capacity)
+{
+ int64_t ocv_cutoff_new, ocv_cutoff_aged, temp_rs_to_rslow;
+ int64_t esr_actual, battery_esr, val;
+ int soc_cutoff_aged, soc_cutoff_new, rc;
+ int battery_soc, unusable_soc, batt_temp;
+ u8 buffer[3];
+
+ if (chip->batt_aging_mode != FG_AGING_ESR)
+ return 0;
+
+ if (chip->nom_cap_uah == 0) {
+ if (fg_debug_mask & FG_AGING)
+ pr_info("ocv coefficients not loaded, aborting\n");
+ return 0;
+ }
+ fg_mem_lock(chip);
+
+ batt_temp = get_sram_prop_now(chip, FG_DATA_BATT_TEMP);
+ if (batt_temp < 150 || batt_temp > 400) {
+ if (fg_debug_mask & FG_AGING)
+ pr_info("Battery temp (%d) out of range, aborting\n",
+ (int)batt_temp);
+ rc = 0;
+ goto done;
+ }
+
+ battery_soc = get_battery_soc_raw(chip) * 100 / FULL_PERCENT_3B;
+ if (battery_soc < 25 || battery_soc > 75) {
+ if (fg_debug_mask & FG_AGING)
+ pr_info("Battery SoC (%d) out of range, aborting\n",
+ (int)battery_soc);
+ rc = 0;
+ goto done;
+ }
+
+ rc = fg_mem_read(chip, buffer, ESR_ACTUAL_REG, 2, 2, 0);
+ esr_actual = half_float(buffer);
+ rc |= fg_mem_read(chip, buffer, BATTERY_ESR_REG, 2, 2, 0);
+ battery_esr = half_float(buffer);
+
+ if (rc) {
+ goto error_done;
+ } else if (esr_actual < battery_esr) {
+ if (fg_debug_mask & FG_AGING)
+ pr_info("Batt ESR lower than ESR actual, aborting\n");
+ rc = 0;
+ goto done;
+ }
+ rc = fg_mem_read(chip, buffer, TEMP_RS_TO_RSLOW_REG, 2, 0, 0);
+ temp_rs_to_rslow = half_float(buffer);
+
+ if (rc)
+ goto error_done;
+
+ fg_mem_release(chip);
+
+ if (fg_debug_mask & FG_AGING) {
+ pr_info("batt_soc = %d, cutoff_voltage = %lld, eval current = %d\n",
+ battery_soc, chip->cutoff_voltage,
+ chip->evaluation_current);
+ pr_info("temp_rs_to_rslow = %lld, batt_esr = %lld, esr_actual = %lld\n",
+ temp_rs_to_rslow, battery_esr, esr_actual);
+ }
+
+ /* calculate soc_cutoff_new */
+ val = (1000000LL + temp_rs_to_rslow) * battery_esr;
+ do_div(val, 1000000);
+ ocv_cutoff_new = div64_s64(chip->evaluation_current * val, 1000)
+ + chip->cutoff_voltage;
+
+ /* calculate soc_cutoff_aged */
+ val = (1000000LL + temp_rs_to_rslow) * esr_actual;
+ do_div(val, 1000000);
+ ocv_cutoff_aged = div64_s64(chip->evaluation_current * val, 1000)
+ + chip->cutoff_voltage;
+
+ if (fg_debug_mask & FG_AGING)
+ pr_info("ocv_cutoff_new = %lld, ocv_cutoff_aged = %lld\n",
+ ocv_cutoff_new, ocv_cutoff_aged);
+
+ soc_cutoff_new = lookup_soc_for_ocv(chip, ocv_cutoff_new);
+ soc_cutoff_aged = lookup_soc_for_ocv(chip, ocv_cutoff_aged);
+
+ if (fg_debug_mask & FG_AGING)
+ pr_info("aged soc = %d, new soc = %d\n",
+ soc_cutoff_aged, soc_cutoff_new);
+ unusable_soc = soc_cutoff_aged - soc_cutoff_new;
+
+ *actual_capacity = div64_s64(((int64_t)chip->nom_cap_uah)
+ * (1000 - unusable_soc), 1000);
+ if (fg_debug_mask & FG_AGING)
+ pr_info("nom cap = %d, actual cap = %d\n",
+ chip->nom_cap_uah, *actual_capacity);
+
+ return rc;
+
+error_done:
+ pr_err("some register reads failed: %d\n", rc);
+done:
+ fg_mem_release(chip);
+ return rc;
+}
+
+static void battery_age_work(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ battery_age_work);
+
+ estimate_battery_age(chip, &chip->actual_cap_uah);
+}
+
+static enum power_supply_property fg_power_props[] = {
+ POWER_SUPPLY_PROP_CAPACITY,
+ POWER_SUPPLY_PROP_CAPACITY_RAW,
+ POWER_SUPPLY_PROP_CURRENT_NOW,
+ POWER_SUPPLY_PROP_VOLTAGE_NOW,
+ POWER_SUPPLY_PROP_VOLTAGE_OCV,
+ POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+ POWER_SUPPLY_PROP_CHARGE_NOW,
+ POWER_SUPPLY_PROP_CHARGE_NOW_RAW,
+ POWER_SUPPLY_PROP_CHARGE_NOW_ERROR,
+ POWER_SUPPLY_PROP_CHARGE_FULL,
+ POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
+ POWER_SUPPLY_PROP_TEMP,
+ POWER_SUPPLY_PROP_COOL_TEMP,
+ POWER_SUPPLY_PROP_WARM_TEMP,
+ POWER_SUPPLY_PROP_RESISTANCE,
+ POWER_SUPPLY_PROP_RESISTANCE_ID,
+ POWER_SUPPLY_PROP_BATTERY_TYPE,
+ POWER_SUPPLY_PROP_UPDATE_NOW,
+ POWER_SUPPLY_PROP_ESR_COUNT,
+ POWER_SUPPLY_PROP_VOLTAGE_MIN,
+ POWER_SUPPLY_PROP_CYCLE_COUNT,
+ POWER_SUPPLY_PROP_CYCLE_COUNT_ID,
+ POWER_SUPPLY_PROP_HI_POWER,
+};
+
+static int fg_power_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ struct fg_chip *chip = power_supply_get_drvdata(psy);
+ bool vbatt_low_sts;
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_BATTERY_TYPE:
+ if (chip->battery_missing)
+ val->strval = missing_batt_type;
+ else if (chip->fg_restarting)
+ val->strval = loading_batt_type;
+ else
+ val->strval = chip->batt_type;
+ break;
+ case POWER_SUPPLY_PROP_CAPACITY:
+ val->intval = get_prop_capacity(chip);
+ break;
+ case POWER_SUPPLY_PROP_CAPACITY_RAW:
+ val->intval = get_sram_prop_now(chip, FG_DATA_BATT_SOC);
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_NOW_ERROR:
+ val->intval = get_sram_prop_now(chip, FG_DATA_VINT_ERR);
+ break;
+ case POWER_SUPPLY_PROP_CURRENT_NOW:
+ val->intval = get_sram_prop_now(chip, FG_DATA_CURRENT);
+ break;
+ case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+ val->intval = get_sram_prop_now(chip, FG_DATA_VOLTAGE);
+ break;
+ case POWER_SUPPLY_PROP_VOLTAGE_OCV:
+ val->intval = get_sram_prop_now(chip, FG_DATA_OCV);
+ break;
+ case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+ val->intval = chip->batt_max_voltage_uv;
+ break;
+ case POWER_SUPPLY_PROP_TEMP:
+ val->intval = get_sram_prop_now(chip, FG_DATA_BATT_TEMP);
+ break;
+ case POWER_SUPPLY_PROP_COOL_TEMP:
+ val->intval = get_prop_jeita_temp(chip, FG_MEM_SOFT_COLD);
+ break;
+ case POWER_SUPPLY_PROP_WARM_TEMP:
+ val->intval = get_prop_jeita_temp(chip, FG_MEM_SOFT_HOT);
+ break;
+ case POWER_SUPPLY_PROP_RESISTANCE:
+ val->intval = get_sram_prop_now(chip, FG_DATA_BATT_ESR);
+ break;
+ case POWER_SUPPLY_PROP_ESR_COUNT:
+ val->intval = get_sram_prop_now(chip, FG_DATA_BATT_ESR_COUNT);
+ break;
+ case POWER_SUPPLY_PROP_CYCLE_COUNT:
+ val->intval = fg_get_cycle_count(chip);
+ break;
+ case POWER_SUPPLY_PROP_CYCLE_COUNT_ID:
+ val->intval = chip->cyc_ctr.id;
+ break;
+ case POWER_SUPPLY_PROP_RESISTANCE_ID:
+ val->intval = get_sram_prop_now(chip, FG_DATA_BATT_ID);
+ break;
+ case POWER_SUPPLY_PROP_UPDATE_NOW:
+ val->intval = 0;
+ break;
+ case POWER_SUPPLY_PROP_VOLTAGE_MIN:
+ if (!fg_get_vbatt_status(chip, &vbatt_low_sts))
+ val->intval = (int)vbatt_low_sts;
+ else
+ val->intval = 1;
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
+ val->intval = chip->nom_cap_uah;
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_FULL:
+ val->intval = chip->learning_data.learned_cc_uah;
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_NOW:
+ val->intval = chip->learning_data.cc_uah;
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_NOW_RAW:
+ val->intval = get_sram_prop_now(chip, FG_DATA_CC_CHARGE);
+ break;
+ case POWER_SUPPLY_PROP_HI_POWER:
+ val->intval = !!chip->bcl_lpm_disabled;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int correction_times[] = {
+ 1470,
+ 2940,
+ 4410,
+ 5880,
+ 7350,
+ 8820,
+ 10290,
+ 11760,
+ 13230,
+ 14700,
+ 16170,
+ 17640,
+ 19110,
+ 20580,
+ 22050,
+ 23520,
+ 24990,
+ 26460,
+ 27930,
+ 29400,
+ 30870,
+ 32340,
+ 33810,
+ 35280,
+ 36750,
+ 38220,
+ 39690,
+ 41160,
+ 42630,
+ 44100,
+ 45570,
+ 47040,
+};
+
+static int correction_factors[] = {
+ 1000000,
+ 1007874,
+ 1015789,
+ 1023745,
+ 1031742,
+ 1039780,
+ 1047859,
+ 1055979,
+ 1064140,
+ 1072342,
+ 1080584,
+ 1088868,
+ 1097193,
+ 1105558,
+ 1113964,
+ 1122411,
+ 1130899,
+ 1139427,
+ 1147996,
+ 1156606,
+ 1165256,
+ 1173947,
+ 1182678,
+ 1191450,
+ 1200263,
+ 1209115,
+ 1218008,
+ 1226942,
+ 1235915,
+ 1244929,
+ 1253983,
+ 1263076,
+};
+
+#define FG_CONVERSION_FACTOR (64198531LL)
+static int iavg_3b_to_uah(u8 *buffer, int delta_ms)
+{
+ int64_t val, i_filtered;
+ int i, correction_factor;
+
+ for (i = 0; i < ARRAY_SIZE(correction_times); i++) {
+ if (correction_times[i] > delta_ms)
+ break;
+ }
+ if (i >= ARRAY_SIZE(correction_times)) {
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("fuel gauge took more than 32 cycles\n");
+ i = ARRAY_SIZE(correction_times) - 1;
+ }
+ correction_factor = correction_factors[i];
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("delta_ms = %d, cycles = %d, correction = %d\n",
+ delta_ms, i, correction_factor);
+ val = buffer[2] << 16 | buffer[1] << 8 | buffer[0];
+ /* convert val from signed 24b to signed 64b */
+ i_filtered = (val << 40) >> 40;
+ val = i_filtered * correction_factor;
+ val = div64_s64(val + FG_CONVERSION_FACTOR / 2, FG_CONVERSION_FACTOR);
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("i_filtered = 0x%llx/%lld, cc_uah = %lld\n",
+ i_filtered, i_filtered, val);
+
+ return val;
+}
+
+static bool fg_is_temperature_ok_for_learning(struct fg_chip *chip)
+{
+ int batt_temp = get_sram_prop_now(chip, FG_DATA_BATT_TEMP);
+
+ if (batt_temp > chip->learning_data.max_temp
+ || batt_temp < chip->learning_data.min_temp) {
+ if (fg_debug_mask & FG_AGING)
+ pr_info("temp (%d) out of range [%d, %d], aborting\n",
+ batt_temp,
+ chip->learning_data.min_temp,
+ chip->learning_data.max_temp);
+ return false;
+ }
+ return true;
+}
+
+static void fg_cap_learning_stop(struct fg_chip *chip)
+{
+ chip->learning_data.cc_uah = 0;
+ chip->learning_data.active = false;
+}
+
+#define I_FILTERED_REG 0x584
+static void fg_cap_learning_work(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ fg_cap_learning_work);
+ u8 i_filtered[3], data[3];
+ int rc, cc_uah, delta_ms;
+ ktime_t now_kt, delta_kt;
+
+ mutex_lock(&chip->learning_data.learning_lock);
+ if (!chip->learning_data.active)
+ goto fail;
+ if (!fg_is_temperature_ok_for_learning(chip)) {
+ fg_cap_learning_stop(chip);
+ goto fail;
+ }
+
+ if (chip->wa_flag & USE_CC_SOC_REG) {
+ mutex_unlock(&chip->learning_data.learning_lock);
+ fg_relax(&chip->capacity_learning_wakeup_source);
+ return;
+ }
+
+ fg_mem_lock(chip);
+
+ rc = fg_mem_read(chip, i_filtered, I_FILTERED_REG, 3, 0, 0);
+ if (rc) {
+ pr_err("Failed to read i_filtered: %d\n", rc);
+ fg_mem_release(chip);
+ goto fail;
+ }
+ memset(data, 0, 3);
+ rc = fg_mem_write(chip, data, I_FILTERED_REG, 3, 0, 0);
+ if (rc) {
+ pr_err("Failed to clear i_filtered: %d\n", rc);
+ fg_mem_release(chip);
+ goto fail;
+ }
+ fg_mem_release(chip);
+
+ now_kt = ktime_get_boottime();
+ delta_kt = ktime_sub(now_kt, chip->learning_data.time_stamp);
+ chip->learning_data.time_stamp = now_kt;
+
+ delta_ms = (int)div64_s64(ktime_to_ns(delta_kt), 1000000);
+
+ cc_uah = iavg_3b_to_uah(i_filtered, delta_ms);
+ chip->learning_data.cc_uah -= cc_uah;
+ if (fg_debug_mask & FG_AGING)
+ pr_info("total_cc_uah = %lld\n", chip->learning_data.cc_uah);
+
+fail:
+ mutex_unlock(&chip->learning_data.learning_lock);
+ return;
+
+}
+
+#define CC_SOC_BASE_REG 0x5BC
+#define CC_SOC_OFFSET 3
+#define CC_SOC_MAGNITUDE_MASK 0x1FFFFFFF
+#define CC_SOC_NEGATIVE_BIT BIT(29)
+static int fg_get_cc_soc(struct fg_chip *chip, int *cc_soc)
+{
+ int rc;
+ u8 reg[4];
+ unsigned int temp, magnitude;
+
+ rc = fg_mem_read(chip, reg, CC_SOC_BASE_REG, 4, CC_SOC_OFFSET, 0);
+ if (rc) {
+ pr_err("Failed to read CC_SOC_REG rc=%d\n", rc);
+ return rc;
+ }
+
+ temp = reg[3] << 24 | reg[2] << 16 | reg[1] << 8 | reg[0];
+ magnitude = temp & CC_SOC_MAGNITUDE_MASK;
+ if (temp & CC_SOC_NEGATIVE_BIT)
+ *cc_soc = -1 * (~magnitude + 1);
+ else
+ *cc_soc = magnitude;
+
+ return 0;
+}
+
+static int fg_cap_learning_process_full_data(struct fg_chip *chip)
+{
+ int cc_pc_val, rc = -EINVAL;
+ unsigned int cc_soc_delta_pc;
+ int64_t delta_cc_uah;
+
+ if (!chip->learning_data.active)
+ goto fail;
+
+ if (!fg_is_temperature_ok_for_learning(chip)) {
+ fg_cap_learning_stop(chip);
+ goto fail;
+ }
+
+ rc = fg_get_cc_soc(chip, &cc_pc_val);
+ if (rc) {
+ pr_err("failed to get CC_SOC, stopping capacity learning\n");
+ fg_cap_learning_stop(chip);
+ goto fail;
+ }
+
+ cc_soc_delta_pc = DIV_ROUND_CLOSEST(
+ abs(cc_pc_val - chip->learning_data.init_cc_pc_val)
+ * 100, FULL_PERCENT_28BIT);
+
+ delta_cc_uah = div64_s64(
+ chip->learning_data.learned_cc_uah * cc_soc_delta_pc,
+ 100);
+ chip->learning_data.cc_uah = delta_cc_uah + chip->learning_data.cc_uah;
+
+ if (fg_debug_mask & FG_AGING)
+ pr_info("current cc_soc=%d cc_soc_pc=%d total_cc_uah = %lld\n",
+ cc_pc_val, cc_soc_delta_pc,
+ chip->learning_data.cc_uah);
+
+ return 0;
+
+fail:
+ return rc;
+}
+
+#define FG_CAP_LEARNING_INTERVAL_NS 30000000000
+static enum alarmtimer_restart fg_cap_learning_alarm_cb(struct alarm *alarm,
+ ktime_t now)
+{
+ struct fg_chip *chip = container_of(alarm, struct fg_chip,
+ fg_cap_learning_alarm);
+
+ if (chip->learning_data.active) {
+ if (fg_debug_mask & FG_AGING)
+ pr_info("alarm fired\n");
+ schedule_work(&chip->fg_cap_learning_work);
+ alarm_forward_now(alarm,
+ ns_to_ktime(FG_CAP_LEARNING_INTERVAL_NS));
+ return ALARMTIMER_RESTART;
+ }
+ if (fg_debug_mask & FG_AGING)
+ pr_info("alarm misfired\n");
+ return ALARMTIMER_NORESTART;
+}
+
+#define FG_AGING_STORAGE_REG 0x5E4
+#define ACTUAL_CAPACITY_REG 0x578
+#define MAH_TO_SOC_CONV_REG 0x4A0
+#define CC_SOC_COEFF_OFFSET 0
+#define ACTUAL_CAPACITY_OFFSET 2
+#define MAH_TO_SOC_CONV_CS_OFFSET 0
+static int fg_calc_and_store_cc_soc_coeff(struct fg_chip *chip, int16_t cc_mah)
+{
+ int rc;
+ int64_t cc_to_soc_coeff, mah_to_soc;
+ u8 data[2];
+
+ rc = fg_mem_write(chip, (u8 *)&cc_mah, ACTUAL_CAPACITY_REG, 2,
+ ACTUAL_CAPACITY_OFFSET, 0);
+ if (rc) {
+ pr_err("Failed to store actual capacity: %d\n", rc);
+ return rc;
+ }
+
+ rc = fg_mem_read(chip, (u8 *)&data, MAH_TO_SOC_CONV_REG, 2,
+ MAH_TO_SOC_CONV_CS_OFFSET, 0);
+ if (rc) {
+ pr_err("Failed to read mah_to_soc_conv_cs: %d\n", rc);
+ } else {
+ mah_to_soc = data[1] << 8 | data[0];
+ mah_to_soc *= MICRO_UNIT;
+ cc_to_soc_coeff = div64_s64(mah_to_soc, cc_mah);
+ half_float_to_buffer(cc_to_soc_coeff, data);
+ rc = fg_mem_write(chip, (u8 *)data,
+ ACTUAL_CAPACITY_REG, 2,
+ CC_SOC_COEFF_OFFSET, 0);
+ if (rc)
+ pr_err("Failed to write cc_soc_coeff_offset: %d\n",
+ rc);
+ else if (fg_debug_mask & FG_AGING)
+ pr_info("new cc_soc_coeff %lld [%x %x] saved to sram\n",
+ cc_to_soc_coeff, data[0], data[1]);
+ }
+ return rc;
+}
+
+static void fg_cap_learning_load_data(struct fg_chip *chip)
+{
+ int16_t cc_mah;
+ int64_t old_cap = chip->learning_data.learned_cc_uah;
+ int rc;
+
+ rc = fg_mem_read(chip, (u8 *)&cc_mah, FG_AGING_STORAGE_REG, 2, 0, 0);
+ if (rc) {
+ pr_err("Failed to load aged capacity: %d\n", rc);
+ } else {
+ chip->learning_data.learned_cc_uah = cc_mah * 1000;
+ if (fg_debug_mask & FG_AGING)
+ pr_info("learned capacity %lld-> %lld/%x uah\n",
+ old_cap,
+ chip->learning_data.learned_cc_uah,
+ cc_mah);
+ }
+}
+
+static void fg_cap_learning_save_data(struct fg_chip *chip)
+{
+ int16_t cc_mah;
+ int rc;
+
+ cc_mah = div64_s64(chip->learning_data.learned_cc_uah, 1000);
+
+ rc = fg_mem_write(chip, (u8 *)&cc_mah, FG_AGING_STORAGE_REG, 2, 0, 0);
+ if (rc)
+ pr_err("Failed to store aged capacity: %d\n", rc);
+ else if (fg_debug_mask & FG_AGING)
+ pr_info("learned capacity %lld uah (%d/0x%x uah) saved to sram\n",
+ chip->learning_data.learned_cc_uah,
+ cc_mah, cc_mah);
+
+ if (chip->learning_data.feedback_on) {
+ rc = fg_calc_and_store_cc_soc_coeff(chip, cc_mah);
+ if (rc)
+ pr_err("Error in storing cc_soc_coeff, rc:%d\n", rc);
+ }
+}
+
+static void fg_cap_learning_post_process(struct fg_chip *chip)
+{
+ int64_t max_inc_val, min_dec_val, old_cap;
+
+ max_inc_val = chip->learning_data.learned_cc_uah
+ * (1000 + chip->learning_data.max_increment);
+ do_div(max_inc_val, 1000);
+
+ min_dec_val = chip->learning_data.learned_cc_uah
+ * (1000 - chip->learning_data.max_decrement);
+ do_div(min_dec_val, 1000);
+
+ old_cap = chip->learning_data.learned_cc_uah;
+ if (chip->learning_data.cc_uah > max_inc_val)
+ chip->learning_data.learned_cc_uah = max_inc_val;
+ else if (chip->learning_data.cc_uah < min_dec_val)
+ chip->learning_data.learned_cc_uah = min_dec_val;
+ else
+ chip->learning_data.learned_cc_uah =
+ chip->learning_data.cc_uah;
+
+ fg_cap_learning_save_data(chip);
+ if (fg_debug_mask & FG_AGING)
+ pr_info("final cc_uah = %lld, learned capacity %lld -> %lld uah\n",
+ chip->learning_data.cc_uah,
+ old_cap, chip->learning_data.learned_cc_uah);
+}
+
+static int get_vbat_est_diff(struct fg_chip *chip)
+{
+ return abs(fg_data[FG_DATA_VOLTAGE].value
+ - fg_data[FG_DATA_CPRED_VOLTAGE].value);
+}
+
+#define CBITS_INPUT_FILTER_REG 0x4B4
+#define IBATTF_TAU_MASK 0x38
+#define IBATTF_TAU_99_S 0x30
+static int fg_cap_learning_check(struct fg_chip *chip)
+{
+ u8 data[4];
+ int rc = 0, battery_soc, cc_pc_val;
+ int vbat_est_diff, vbat_est_thr_uv;
+ unsigned int cc_pc_100 = FULL_PERCENT_28BIT;
+
+ mutex_lock(&chip->learning_data.learning_lock);
+ if (chip->status == POWER_SUPPLY_STATUS_CHARGING
+ && !chip->learning_data.active
+ && chip->batt_aging_mode == FG_AGING_CC) {
+ if (chip->learning_data.learned_cc_uah == 0) {
+ if (fg_debug_mask & FG_AGING)
+ pr_info("no capacity, aborting\n");
+ goto fail;
+ }
+
+ if (!fg_is_temperature_ok_for_learning(chip))
+ goto fail;
+
+ fg_mem_lock(chip);
+ if (!chip->learning_data.feedback_on) {
+ vbat_est_diff = get_vbat_est_diff(chip);
+ vbat_est_thr_uv = chip->learning_data.vbat_est_thr_uv;
+ if (vbat_est_diff >= vbat_est_thr_uv &&
+ vbat_est_thr_uv > 0) {
+ if (fg_debug_mask & FG_AGING)
+ pr_info("vbat_est_diff (%d) < threshold (%d)\n",
+ vbat_est_diff, vbat_est_thr_uv);
+ fg_mem_release(chip);
+ fg_cap_learning_stop(chip);
+ goto fail;
+ }
+ }
+ battery_soc = get_battery_soc_raw(chip);
+ if (fg_debug_mask & FG_AGING)
+ pr_info("checking battery soc (%d vs %d)\n",
+ battery_soc * 100 / FULL_PERCENT_3B,
+ chip->learning_data.max_start_soc);
+ /* check if the battery is low enough to start soc learning */
+ if (battery_soc * 100 / FULL_PERCENT_3B
+ > chip->learning_data.max_start_soc) {
+ if (fg_debug_mask & FG_AGING)
+ pr_info("battery soc too low (%d < %d), aborting\n",
+ battery_soc * 100 / FULL_PERCENT_3B,
+ chip->learning_data.max_start_soc);
+ fg_mem_release(chip);
+ fg_cap_learning_stop(chip);
+ goto fail;
+ }
+
+ /* set the coulomb counter to a percentage of the capacity */
+ chip->learning_data.cc_uah = div64_s64(
+ (chip->learning_data.learned_cc_uah * battery_soc),
+ FULL_PERCENT_3B);
+
+ /* Use CC_SOC_REG based capacity learning */
+ if (chip->wa_flag & USE_CC_SOC_REG) {
+ fg_mem_release(chip);
+ /* SW_CC_SOC based capacity learning */
+ if (fg_get_cc_soc(chip, &cc_pc_val)) {
+ pr_err("failed to get CC_SOC, stop capacity learning\n");
+ fg_cap_learning_stop(chip);
+ goto fail;
+ }
+
+ chip->learning_data.init_cc_pc_val = cc_pc_val;
+ chip->learning_data.active = true;
+ if (fg_debug_mask & FG_AGING)
+ pr_info("SW_CC_SOC based learning init_CC_SOC=%d\n",
+ chip->learning_data.init_cc_pc_val);
+ } else {
+ rc = fg_mem_masked_write(chip, CBITS_INPUT_FILTER_REG,
+ IBATTF_TAU_MASK, IBATTF_TAU_99_S, 0);
+ if (rc) {
+ pr_err("Failed to write IF IBAT Tau: %d\n",
+ rc);
+ fg_mem_release(chip);
+ fg_cap_learning_stop(chip);
+ goto fail;
+ }
+
+ /* clear the i_filtered register */
+ memset(data, 0, 4);
+ rc = fg_mem_write(chip, data, I_FILTERED_REG, 3, 0, 0);
+ if (rc) {
+ pr_err("Failed to clear i_filtered: %d\n", rc);
+ fg_mem_release(chip);
+ fg_cap_learning_stop(chip);
+ goto fail;
+ }
+ fg_mem_release(chip);
+ chip->learning_data.time_stamp = ktime_get_boottime();
+ chip->learning_data.active = true;
+
+ if (fg_debug_mask & FG_AGING)
+ pr_info("cap learning started, soc = %d cc_uah = %lld\n",
+ battery_soc * 100 / FULL_PERCENT_3B,
+ chip->learning_data.cc_uah);
+ alarm_start_relative(&chip->fg_cap_learning_alarm,
+ ns_to_ktime(FG_CAP_LEARNING_INTERVAL_NS));
+ }
+ } else if ((chip->status != POWER_SUPPLY_STATUS_CHARGING)
+ && chip->learning_data.active) {
+ if (fg_debug_mask & FG_AGING)
+ pr_info("capacity learning stopped\n");
+ if (!(chip->wa_flag & USE_CC_SOC_REG))
+ alarm_try_to_cancel(&chip->fg_cap_learning_alarm);
+
+ if (chip->status == POWER_SUPPLY_STATUS_FULL) {
+ if (chip->wa_flag & USE_CC_SOC_REG) {
+ rc = fg_cap_learning_process_full_data(chip);
+ if (rc) {
+ fg_cap_learning_stop(chip);
+ goto fail;
+ }
+ /* reset SW_CC_SOC register to 100% */
+ rc = fg_mem_write(chip, (u8 *)&cc_pc_100,
+ CC_SOC_BASE_REG, 4, CC_SOC_OFFSET, 0);
+ if (rc)
+ pr_err("Failed to reset CC_SOC_REG rc=%d\n",
+ rc);
+ }
+ fg_cap_learning_post_process(chip);
+ }
+
+ fg_cap_learning_stop(chip);
+ }
+
+fail:
+ mutex_unlock(&chip->learning_data.learning_lock);
+ return rc;
+}
+
+static bool is_usb_present(struct fg_chip *chip)
+{
+ union power_supply_propval prop = {0,};
+
+ if (!chip->usb_psy)
+ chip->usb_psy = power_supply_get_by_name("usb");
+
+ if (chip->usb_psy)
+ power_supply_get_property(chip->usb_psy,
+ POWER_SUPPLY_PROP_PRESENT, &prop);
+ return prop.intval != 0;
+}
+
+static bool is_dc_present(struct fg_chip *chip)
+{
+ union power_supply_propval prop = {0,};
+
+ if (!chip->dc_psy)
+ chip->dc_psy = power_supply_get_by_name("dc");
+
+ if (chip->dc_psy)
+ power_supply_get_property(chip->dc_psy,
+ POWER_SUPPLY_PROP_PRESENT, &prop);
+ return prop.intval != 0;
+}
+
+static bool is_input_present(struct fg_chip *chip)
+{
+ return is_usb_present(chip) || is_dc_present(chip);
+}
+
+static bool is_otg_present(struct fg_chip *chip)
+{
+ union power_supply_propval prop = {0,};
+
+ if (!chip->usb_psy)
+ chip->usb_psy = power_supply_get_by_name("usb");
+
+ if (chip->usb_psy)
+ power_supply_get_property(chip->usb_psy,
+ POWER_SUPPLY_PROP_USB_OTG, &prop);
+ return prop.intval != 0;
+}
+
+static bool is_charger_available(struct fg_chip *chip)
+{
+ if (!chip->batt_psy_name)
+ return false;
+
+ if (!chip->batt_psy)
+ chip->batt_psy = power_supply_get_by_name(chip->batt_psy_name);
+
+ if (!chip->batt_psy)
+ return false;
+
+ return true;
+}
+
+static int set_prop_enable_charging(struct fg_chip *chip, bool enable)
+{
+ int rc = 0;
+ union power_supply_propval ret = {enable, };
+
+ if (!is_charger_available(chip)) {
+ pr_err("Charger not available yet!\n");
+ return -EINVAL;
+ }
+
+ rc = power_supply_set_property(chip->batt_psy,
+ POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED,
+ &ret);
+ if (rc) {
+ pr_err("couldn't configure batt chg %d\n", rc);
+ return rc;
+ }
+
+ chip->charging_disabled = !enable;
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("%sabling charging\n", enable ? "en" : "dis");
+
+ return rc;
+}
+
+#define MAX_BATTERY_CC_SOC_CAPACITY 150
+static void status_change_work(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ status_change_work);
+ unsigned long current_time = 0;
+ int cc_soc, rc, capacity = get_prop_capacity(chip);
+
+ if (chip->esr_pulse_tune_en) {
+ fg_stay_awake(&chip->esr_extract_wakeup_source);
+ schedule_work(&chip->esr_extract_config_work);
+ }
+
+ if (chip->status == POWER_SUPPLY_STATUS_FULL) {
+ if (capacity >= 99 && chip->hold_soc_while_full
+ && chip->health == POWER_SUPPLY_HEALTH_GOOD) {
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("holding soc at 100\n");
+ chip->charge_full = true;
+ } else if (fg_debug_mask & FG_STATUS) {
+ pr_info("terminated charging at %d/0x%02x\n",
+ capacity, get_monotonic_soc_raw(chip));
+ }
+ }
+ if (chip->status == POWER_SUPPLY_STATUS_FULL ||
+ chip->status == POWER_SUPPLY_STATUS_CHARGING) {
+ if (!chip->vbat_low_irq_enabled) {
+ enable_irq(chip->batt_irq[VBATT_LOW].irq);
+ enable_irq_wake(chip->batt_irq[VBATT_LOW].irq);
+ chip->vbat_low_irq_enabled = true;
+ }
+ if (!!(chip->wa_flag & PULSE_REQUEST_WA) && capacity == 100)
+ fg_configure_soc(chip);
+ } else if (chip->status == POWER_SUPPLY_STATUS_DISCHARGING) {
+ if (chip->vbat_low_irq_enabled) {
+ disable_irq_wake(chip->batt_irq[VBATT_LOW].irq);
+ disable_irq_nosync(chip->batt_irq[VBATT_LOW].irq);
+ chip->vbat_low_irq_enabled = false;
+ }
+ }
+ fg_cap_learning_check(chip);
+ schedule_work(&chip->update_esr_work);
+
+ if (chip->wa_flag & USE_CC_SOC_REG) {
+ if (fg_get_cc_soc(chip, &cc_soc)) {
+ pr_err("failed to get CC_SOC\n");
+ return;
+ }
+ }
+
+ if (chip->prev_status != chip->status && chip->last_sram_update_time) {
+ get_current_time(¤t_time);
+ /*
+ * When charging status changes, update SRAM parameters if it
+ * was not updated before 5 seconds from now.
+ */
+ if (chip->last_sram_update_time + 5 < current_time) {
+ cancel_delayed_work(&chip->update_sram_data);
+ schedule_delayed_work(&chip->update_sram_data,
+ msecs_to_jiffies(0));
+ }
+ if (chip->cyc_ctr.en)
+ schedule_work(&chip->cycle_count_work);
+ if ((chip->wa_flag & USE_CC_SOC_REG) &&
+ chip->bad_batt_detection_en &&
+ chip->status == POWER_SUPPLY_STATUS_CHARGING) {
+ chip->sw_cc_soc_data.init_sys_soc = capacity;
+ chip->sw_cc_soc_data.init_cc_soc = cc_soc;
+ if (fg_debug_mask & FG_STATUS)
+ pr_info(" Init_sys_soc %d init_cc_soc %d\n",
+ chip->sw_cc_soc_data.init_sys_soc,
+ chip->sw_cc_soc_data.init_cc_soc);
+ }
+ }
+ if ((chip->wa_flag & USE_CC_SOC_REG) && chip->bad_batt_detection_en
+ && chip->safety_timer_expired) {
+ chip->sw_cc_soc_data.delta_soc =
+ DIV_ROUND_CLOSEST(abs(cc_soc -
+ chip->sw_cc_soc_data.init_cc_soc)
+ * 100, FULL_PERCENT_28BIT);
+ chip->sw_cc_soc_data.full_capacity =
+ chip->sw_cc_soc_data.delta_soc +
+ chip->sw_cc_soc_data.init_sys_soc;
+ pr_info("Init_sys_soc %d init_cc_soc %d cc_soc %d delta_soc %d full_capacity %d\n",
+ chip->sw_cc_soc_data.init_sys_soc,
+ chip->sw_cc_soc_data.init_cc_soc, cc_soc,
+ chip->sw_cc_soc_data.delta_soc,
+ chip->sw_cc_soc_data.full_capacity);
+ /*
+ * If sw_cc_soc capacity greater than 150, then it's a bad
+ * battery. else, reset timer and restart charging.
+ */
+ if (chip->sw_cc_soc_data.full_capacity >
+ MAX_BATTERY_CC_SOC_CAPACITY) {
+ pr_info("Battery possibly damaged, do not restart charging\n");
+ } else {
+ pr_info("Reset safety-timer and restart charging\n");
+ rc = set_prop_enable_charging(chip, false);
+ if (rc) {
+ pr_err("failed to disable charging %d\n", rc);
+ return;
+ }
+
+ chip->safety_timer_expired = false;
+ msleep(200);
+
+ rc = set_prop_enable_charging(chip, true);
+ if (rc) {
+ pr_err("failed to enable charging %d\n", rc);
+ return;
+ }
+ }
+ }
+}
+
+/*
+ * Check for change in the status of input or OTG and schedule
+ * IADC gain compensation work.
+ */
+static void check_gain_compensation(struct fg_chip *chip)
+{
+ bool input_present = is_input_present(chip);
+ bool otg_present = is_otg_present(chip);
+
+ if ((chip->wa_flag & IADC_GAIN_COMP_WA)
+ && ((chip->input_present ^ input_present)
+ || (chip->otg_present ^ otg_present))) {
+ fg_stay_awake(&chip->gain_comp_wakeup_source);
+ chip->input_present = input_present;
+ chip->otg_present = otg_present;
+ cancel_work_sync(&chip->gain_comp_work);
+ schedule_work(&chip->gain_comp_work);
+ }
+}
+
+static void fg_hysteresis_config(struct fg_chip *chip)
+{
+ int hard_hot = 0, hard_cold = 0;
+
+ hard_hot = get_prop_jeita_temp(chip, FG_MEM_HARD_HOT);
+ hard_cold = get_prop_jeita_temp(chip, FG_MEM_HARD_COLD);
+ if (chip->health == POWER_SUPPLY_HEALTH_OVERHEAT && !chip->batt_hot) {
+ /* turn down the hard hot threshold */
+ chip->batt_hot = true;
+ set_prop_jeita_temp(chip, FG_MEM_HARD_HOT,
+ hard_hot - chip->hot_hysteresis);
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("hard hot hysteresis: old hot=%d, new hot=%d\n",
+ hard_hot, hard_hot - chip->hot_hysteresis);
+ } else if (chip->health == POWER_SUPPLY_HEALTH_COLD &&
+ !chip->batt_cold) {
+ /* turn up the hard cold threshold */
+ chip->batt_cold = true;
+ set_prop_jeita_temp(chip, FG_MEM_HARD_COLD,
+ hard_cold + chip->cold_hysteresis);
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("hard cold hysteresis: old cold=%d, new cold=%d\n",
+ hard_cold, hard_cold + chip->hot_hysteresis);
+ } else if (chip->health != POWER_SUPPLY_HEALTH_OVERHEAT &&
+ chip->batt_hot) {
+ /* restore the hard hot threshold */
+ set_prop_jeita_temp(chip, FG_MEM_HARD_HOT,
+ hard_hot + chip->hot_hysteresis);
+ chip->batt_hot = !chip->batt_hot;
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("restore hard hot threshold: old hot=%d, new hot=%d\n",
+ hard_hot,
+ hard_hot + chip->hot_hysteresis);
+ } else if (chip->health != POWER_SUPPLY_HEALTH_COLD &&
+ chip->batt_cold) {
+ /* restore the hard cold threshold */
+ set_prop_jeita_temp(chip, FG_MEM_HARD_COLD,
+ hard_cold - chip->cold_hysteresis);
+ chip->batt_cold = !chip->batt_cold;
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("restore hard cold threshold: old cold=%d, new cold=%d\n",
+ hard_cold,
+ hard_cold - chip->cold_hysteresis);
+ }
+}
+
+#define BATT_INFO_STS(base) (base + 0x09)
+#define JEITA_HARD_HOT_RT_STS BIT(6)
+#define JEITA_HARD_COLD_RT_STS BIT(5)
+static int fg_init_batt_temp_state(struct fg_chip *chip)
+{
+ int rc = 0;
+ u8 batt_info_sts;
+ int hard_hot = 0, hard_cold = 0;
+
+ /*
+ * read the batt_info_sts register to parse battery's
+ * initial status and do hysteresis config accordingly.
+ */
+ rc = fg_read(chip, &batt_info_sts,
+ BATT_INFO_STS(chip->batt_base), 1);
+ if (rc) {
+ pr_err("failed to read batt info sts, rc=%d\n", rc);
+ return rc;
+ }
+
+ hard_hot = get_prop_jeita_temp(chip, FG_MEM_HARD_HOT);
+ hard_cold = get_prop_jeita_temp(chip, FG_MEM_HARD_COLD);
+ chip->batt_hot =
+ (batt_info_sts & JEITA_HARD_HOT_RT_STS) ? true : false;
+ chip->batt_cold =
+ (batt_info_sts & JEITA_HARD_COLD_RT_STS) ? true : false;
+ if (chip->batt_hot || chip->batt_cold) {
+ if (chip->batt_hot) {
+ chip->health = POWER_SUPPLY_HEALTH_OVERHEAT;
+ set_prop_jeita_temp(chip, FG_MEM_HARD_HOT,
+ hard_hot - chip->hot_hysteresis);
+ } else {
+ chip->health = POWER_SUPPLY_HEALTH_COLD;
+ set_prop_jeita_temp(chip, FG_MEM_HARD_COLD,
+ hard_cold + chip->cold_hysteresis);
+ }
+ }
+
+ return rc;
+}
+
+static int fg_power_set_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ const union power_supply_propval *val)
+{
+ struct fg_chip *chip = power_supply_get_drvdata(psy);
+ int rc = 0, unused;
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_COOL_TEMP:
+ rc = set_prop_jeita_temp(chip, FG_MEM_SOFT_COLD, val->intval);
+ break;
+ case POWER_SUPPLY_PROP_WARM_TEMP:
+ rc = set_prop_jeita_temp(chip, FG_MEM_SOFT_HOT, val->intval);
+ break;
+ case POWER_SUPPLY_PROP_UPDATE_NOW:
+ if (val->intval)
+ update_sram_data(chip, &unused);
+ break;
+ case POWER_SUPPLY_PROP_STATUS:
+ chip->prev_status = chip->status;
+ chip->status = val->intval;
+ schedule_work(&chip->status_change_work);
+ check_gain_compensation(chip);
+ break;
+ case POWER_SUPPLY_PROP_HEALTH:
+ chip->health = val->intval;
+ if (chip->health == POWER_SUPPLY_HEALTH_GOOD) {
+ fg_stay_awake(&chip->resume_soc_wakeup_source);
+ schedule_work(&chip->set_resume_soc_work);
+ }
+
+ if (chip->jeita_hysteresis_support)
+ fg_hysteresis_config(chip);
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_DONE:
+ chip->charge_done = val->intval;
+ if (!chip->resume_soc_lowered) {
+ fg_stay_awake(&chip->resume_soc_wakeup_source);
+ schedule_work(&chip->set_resume_soc_work);
+ }
+ break;
+ case POWER_SUPPLY_PROP_CYCLE_COUNT_ID:
+ if ((val->intval > 0) && (val->intval <= BUCKET_COUNT)) {
+ chip->cyc_ctr.id = val->intval;
+ } else {
+ pr_err("rejecting invalid cycle_count_id = %d\n",
+ val->intval);
+ rc = -EINVAL;
+ }
+ break;
+ case POWER_SUPPLY_PROP_SAFETY_TIMER_EXPIRED:
+ chip->safety_timer_expired = val->intval;
+ schedule_work(&chip->status_change_work);
+ break;
+ case POWER_SUPPLY_PROP_HI_POWER:
+ if (chip->wa_flag & BCL_HI_POWER_FOR_CHGLED_WA) {
+ chip->bcl_lpm_disabled = !!val->intval;
+ schedule_work(&chip->bcl_hi_power_work);
+ }
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ return rc;
+};
+
+static int fg_property_is_writeable(struct power_supply *psy,
+ enum power_supply_property psp)
+{
+ switch (psp) {
+ case POWER_SUPPLY_PROP_COOL_TEMP:
+ case POWER_SUPPLY_PROP_WARM_TEMP:
+ case POWER_SUPPLY_PROP_CYCLE_COUNT_ID:
+ return 1;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+#define SRAM_DUMP_START 0x400
+#define SRAM_DUMP_LEN 0x200
+static void dump_sram(struct work_struct *work)
+{
+ int i, rc;
+ u8 *buffer, rt_sts;
+ char str[16];
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ dump_sram);
+
+ buffer = devm_kzalloc(chip->dev, SRAM_DUMP_LEN, GFP_KERNEL);
+ if (buffer == NULL)
+ return;
+
+ rc = fg_read(chip, &rt_sts, INT_RT_STS(chip->soc_base), 1);
+ if (rc)
+ pr_err("spmi read failed: addr=%03X, rc=%d\n",
+ INT_RT_STS(chip->soc_base), rc);
+ else
+ pr_info("soc rt_sts: 0x%x\n", rt_sts);
+
+ rc = fg_read(chip, &rt_sts, INT_RT_STS(chip->batt_base), 1);
+ if (rc)
+ pr_err("spmi read failed: addr=%03X, rc=%d\n",
+ INT_RT_STS(chip->batt_base), rc);
+ else
+ pr_info("batt rt_sts: 0x%x\n", rt_sts);
+
+ rc = fg_read(chip, &rt_sts, INT_RT_STS(chip->mem_base), 1);
+ if (rc)
+ pr_err("spmi read failed: addr=%03X, rc=%d\n",
+ INT_RT_STS(chip->mem_base), rc);
+ else
+ pr_info("memif rt_sts: 0x%x\n", rt_sts);
+
+ rc = fg_mem_read(chip, buffer, SRAM_DUMP_START, SRAM_DUMP_LEN, 0, 0);
+ if (rc) {
+ pr_err("dump failed: rc = %d\n", rc);
+ return;
+ }
+
+ for (i = 0; i < SRAM_DUMP_LEN; i += 4) {
+ str[0] = '\0';
+ fill_string(str, DEBUG_PRINT_BUFFER_SIZE, buffer + i, 4);
+ pr_info("%03X %s\n", SRAM_DUMP_START + i, str);
+ }
+ devm_kfree(chip->dev, buffer);
+}
+
+#define MAXRSCHANGE_REG 0x434
+#define ESR_VALUE_OFFSET 1
+#define ESR_STRICT_VALUE 0x4120391F391F3019
+#define ESR_DEFAULT_VALUE 0x58CD4A6761C34A67
+static void update_esr_value(struct work_struct *work)
+{
+ union power_supply_propval prop = {0, };
+ u64 esr_value;
+ int rc = 0;
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ update_esr_work);
+
+ if (!is_charger_available(chip))
+ return;
+
+ power_supply_get_property(chip->batt_psy,
+ POWER_SUPPLY_PROP_CHARGE_TYPE, &prop);
+
+ if (!chip->esr_strict_filter) {
+ if ((prop.intval == POWER_SUPPLY_CHARGE_TYPE_TAPER &&
+ chip->status == POWER_SUPPLY_STATUS_CHARGING) ||
+ (chip->status == POWER_SUPPLY_STATUS_FULL)) {
+ esr_value = ESR_STRICT_VALUE;
+ rc = fg_mem_write(chip, (u8 *)&esr_value,
+ MAXRSCHANGE_REG, 8,
+ ESR_VALUE_OFFSET, 0);
+ if (rc)
+ pr_err("failed to write strict ESR value rc=%d\n",
+ rc);
+ else
+ chip->esr_strict_filter = true;
+ }
+ } else if ((prop.intval != POWER_SUPPLY_CHARGE_TYPE_TAPER &&
+ chip->status == POWER_SUPPLY_STATUS_CHARGING) ||
+ (chip->status == POWER_SUPPLY_STATUS_DISCHARGING)) {
+ esr_value = ESR_DEFAULT_VALUE;
+ rc = fg_mem_write(chip, (u8 *)&esr_value, MAXRSCHANGE_REG, 8,
+ ESR_VALUE_OFFSET, 0);
+ if (rc)
+ pr_err("failed to write default ESR value rc=%d\n", rc);
+ else
+ chip->esr_strict_filter = false;
+ }
+}
+
+#define TEMP_COUNTER_REG 0x580
+#define VBAT_FILTERED_OFFSET 1
+#define GAIN_REG 0x424
+#define GAIN_OFFSET 1
+#define K_VCOR_REG 0x484
+#define DEF_GAIN_OFFSET 2
+#define PICO_UNIT 0xE8D4A51000LL
+#define ATTO_UNIT 0xDE0B6B3A7640000LL
+#define VBAT_REF 3800000
+
+/*
+ * IADC Gain compensation steps:
+ * If Input/OTG absent:
+ * - read VBAT_FILTERED, KVCOR, GAIN
+ * - calculate the gain compensation using following formula:
+ * gain = (1 + gain) * (1 + kvcor * (vbat_filtered - 3800000)) - 1;
+ * else
+ * - reset to the default gain compensation
+ */
+static void iadc_gain_comp_work(struct work_struct *work)
+{
+ u8 reg[4];
+ int rc;
+ uint64_t vbat_filtered;
+ int64_t gain, kvcor, temp, numerator;
+ struct fg_chip *chip = container_of(work, struct fg_chip,
+ gain_comp_work);
+ bool input_present = is_input_present(chip);
+ bool otg_present = is_otg_present(chip);
+
+ if (!chip->init_done)
+ goto done;
+
+ if (!input_present && !otg_present) {
+ /* read VBAT_FILTERED */
+ rc = fg_mem_read(chip, reg, TEMP_COUNTER_REG, 3,
+ VBAT_FILTERED_OFFSET, 0);
+ if (rc) {
+ pr_err("Failed to read VBAT: rc=%d\n", rc);
+ goto done;
+ }
+ temp = (reg[2] << 16) | (reg[1] << 8) | reg[0];
+ vbat_filtered = div_u64((u64)temp * LSB_24B_NUMRTR,
+ LSB_24B_DENMTR);
+
+ /* read K_VCOR */
+ rc = fg_mem_read(chip, reg, K_VCOR_REG, 2, 0, 0);
+ if (rc) {
+ pr_err("Failed to KVCOR rc=%d\n", rc);
+ goto done;
+ }
+ kvcor = half_float(reg);
+
+ /* calculate gain */
+ numerator = (MICRO_UNIT + chip->iadc_comp_data.dfl_gain)
+ * (PICO_UNIT + kvcor * (vbat_filtered - VBAT_REF))
+ - ATTO_UNIT;
+ gain = div64_s64(numerator, PICO_UNIT);
+
+ /* write back gain */
+ half_float_to_buffer(gain, reg);
+ rc = fg_mem_write(chip, reg, GAIN_REG, 2, GAIN_OFFSET, 0);
+ if (rc) {
+ pr_err("Failed to write gain reg rc=%d\n", rc);
+ goto done;
+ }
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("IADC gain update [%x %x]\n", reg[1], reg[0]);
+ chip->iadc_comp_data.gain_active = true;
+ } else {
+ /* reset gain register */
+ rc = fg_mem_write(chip, chip->iadc_comp_data.dfl_gain_reg,
+ GAIN_REG, 2, GAIN_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to write gain comp: %d\n", rc);
+ goto done;
+ }
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("IADC gain reset [%x %x]\n",
+ chip->iadc_comp_data.dfl_gain_reg[1],
+ chip->iadc_comp_data.dfl_gain_reg[0]);
+ chip->iadc_comp_data.gain_active = false;
+ }
+
+done:
+ fg_relax(&chip->gain_comp_wakeup_source);
+}
+
+#define BATT_MISSING_STS BIT(6)
+static bool is_battery_missing(struct fg_chip *chip)
+{
+ int rc;
+ u8 fg_batt_sts;
+
+ rc = fg_read(chip, &fg_batt_sts,
+ INT_RT_STS(chip->batt_base), 1);
+ if (rc) {
+ pr_err("spmi read failed: addr=%03X, rc=%d\n",
+ INT_RT_STS(chip->batt_base), rc);
+ return false;
+ }
+
+ return (fg_batt_sts & BATT_MISSING_STS) ? true : false;
+}
+
+#define SOC_FIRST_EST_DONE BIT(5)
+static bool is_first_est_done(struct fg_chip *chip)
+{
+ int rc;
+ u8 fg_soc_sts;
+
+ rc = fg_read(chip, &fg_soc_sts,
+ INT_RT_STS(chip->soc_base), 1);
+ if (rc) {
+ pr_err("spmi read failed: addr=%03X, rc=%d\n",
+ INT_RT_STS(chip->soc_base), rc);
+ return false;
+ }
+
+ return (fg_soc_sts & SOC_FIRST_EST_DONE) ? true : false;
+}
+
+static irqreturn_t fg_vbatt_low_handler(int irq, void *_chip)
+{
+ struct fg_chip *chip = _chip;
+ int rc;
+ bool vbatt_low_sts;
+
+ if (fg_debug_mask & FG_IRQS)
+ pr_info("vbatt-low triggered\n");
+
+ if (chip->status == POWER_SUPPLY_STATUS_CHARGING) {
+ rc = fg_get_vbatt_status(chip, &vbatt_low_sts);
+ if (rc) {
+ pr_err("error in reading vbatt_status, rc:%d\n", rc);
+ goto out;
+ }
+ if (!vbatt_low_sts && chip->vbat_low_irq_enabled) {
+ if (fg_debug_mask & FG_IRQS)
+ pr_info("disabling vbatt_low irq\n");
+ disable_irq_wake(chip->batt_irq[VBATT_LOW].irq);
+ disable_irq_nosync(chip->batt_irq[VBATT_LOW].irq);
+ chip->vbat_low_irq_enabled = false;
+ }
+ }
+ if (chip->power_supply_registered)
+ power_supply_changed(chip->bms_psy);
+out:
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t fg_batt_missing_irq_handler(int irq, void *_chip)
+{
+ struct fg_chip *chip = _chip;
+ bool batt_missing = is_battery_missing(chip);
+
+ if (batt_missing) {
+ chip->battery_missing = true;
+ chip->profile_loaded = false;
+ chip->batt_type = default_batt_type;
+ mutex_lock(&chip->cyc_ctr.lock);
+ if (fg_debug_mask & FG_IRQS)
+ pr_info("battery missing, clearing cycle counters\n");
+ clear_cycle_counter(chip);
+ mutex_unlock(&chip->cyc_ctr.lock);
+ } else {
+ if (!chip->use_otp_profile) {
+ reinit_completion(&chip->batt_id_avail);
+ reinit_completion(&chip->first_soc_done);
+ schedule_delayed_work(&chip->batt_profile_init, 0);
+ cancel_delayed_work(&chip->update_sram_data);
+ schedule_delayed_work(
+ &chip->update_sram_data,
+ msecs_to_jiffies(0));
+ } else {
+ chip->battery_missing = false;
+ }
+ }
+
+ if (fg_debug_mask & FG_IRQS)
+ pr_info("batt-missing triggered: %s\n",
+ batt_missing ? "missing" : "present");
+
+ if (chip->power_supply_registered)
+ power_supply_changed(chip->bms_psy);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t fg_mem_avail_irq_handler(int irq, void *_chip)
+{
+ struct fg_chip *chip = _chip;
+ u8 mem_if_sts;
+ int rc;
+
+ rc = fg_read(chip, &mem_if_sts, INT_RT_STS(chip->mem_base), 1);
+ if (rc) {
+ pr_err("failed to read mem status rc=%d\n", rc);
+ return IRQ_HANDLED;
+ }
+
+ if (fg_check_sram_access(chip)) {
+ if ((fg_debug_mask & FG_IRQS)
+ & (FG_MEM_DEBUG_READS | FG_MEM_DEBUG_WRITES))
+ pr_info("sram access granted\n");
+ reinit_completion(&chip->sram_access_revoked);
+ complete_all(&chip->sram_access_granted);
+ } else {
+ if ((fg_debug_mask & FG_IRQS)
+ & (FG_MEM_DEBUG_READS | FG_MEM_DEBUG_WRITES))
+ pr_info("sram access revoked\n");
+ complete_all(&chip->sram_access_revoked);
+ }
+
+ if (!rc && (fg_debug_mask & FG_IRQS)
+ & (FG_MEM_DEBUG_READS | FG_MEM_DEBUG_WRITES))
+ pr_info("mem_if sts 0x%02x\n", mem_if_sts);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t fg_soc_irq_handler(int irq, void *_chip)
+{
+ struct fg_chip *chip = _chip;
+ u8 soc_rt_sts;
+ int rc;
+
+ rc = fg_read(chip, &soc_rt_sts, INT_RT_STS(chip->soc_base), 1);
+ if (rc) {
+ pr_err("spmi read failed: addr=%03X, rc=%d\n",
+ INT_RT_STS(chip->soc_base), rc);
+ }
+
+ if (fg_debug_mask & FG_IRQS)
+ pr_info("triggered 0x%x\n", soc_rt_sts);
+
+ schedule_work(&chip->battery_age_work);
+
+ if (chip->power_supply_registered)
+ power_supply_changed(chip->bms_psy);
+
+ if (chip->rslow_comp.chg_rs_to_rslow > 0 &&
+ chip->rslow_comp.chg_rslow_comp_c1 > 0 &&
+ chip->rslow_comp.chg_rslow_comp_c2 > 0)
+ schedule_work(&chip->rslow_comp_work);
+ if (chip->cyc_ctr.en)
+ schedule_work(&chip->cycle_count_work);
+ schedule_work(&chip->update_esr_work);
+ if (chip->charge_full)
+ schedule_work(&chip->charge_full_work);
+ if (chip->wa_flag & IADC_GAIN_COMP_WA
+ && chip->iadc_comp_data.gain_active) {
+ fg_stay_awake(&chip->gain_comp_wakeup_source);
+ schedule_work(&chip->gain_comp_work);
+ }
+
+ if (chip->wa_flag & USE_CC_SOC_REG
+ && chip->learning_data.active) {
+ fg_stay_awake(&chip->capacity_learning_wakeup_source);
+ schedule_work(&chip->fg_cap_learning_work);
+ }
+
+ if (chip->esr_pulse_tune_en) {
+ fg_stay_awake(&chip->esr_extract_wakeup_source);
+ schedule_work(&chip->esr_extract_config_work);
+ }
+
+ return IRQ_HANDLED;
+}
+
+#define FG_EMPTY_DEBOUNCE_MS 1500
+static irqreturn_t fg_empty_soc_irq_handler(int irq, void *_chip)
+{
+ struct fg_chip *chip = _chip;
+ u8 soc_rt_sts;
+ int rc;
+
+ rc = fg_read(chip, &soc_rt_sts, INT_RT_STS(chip->soc_base), 1);
+ if (rc) {
+ pr_err("spmi read failed: addr=%03X, rc=%d\n",
+ INT_RT_STS(chip->soc_base), rc);
+ goto done;
+ }
+
+ if (fg_debug_mask & FG_IRQS)
+ pr_info("triggered 0x%x\n", soc_rt_sts);
+ if (fg_is_batt_empty(chip)) {
+ fg_stay_awake(&chip->empty_check_wakeup_source);
+ schedule_delayed_work(&chip->check_empty_work,
+ msecs_to_jiffies(FG_EMPTY_DEBOUNCE_MS));
+ } else {
+ chip->soc_empty = false;
+ }
+
+done:
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t fg_first_soc_irq_handler(int irq, void *_chip)
+{
+ struct fg_chip *chip = _chip;
+
+ if (fg_debug_mask & FG_IRQS)
+ pr_info("triggered\n");
+
+ if (fg_est_dump)
+ schedule_work(&chip->dump_sram);
+
+ if (chip->power_supply_registered)
+ power_supply_changed(chip->bms_psy);
+
+ complete_all(&chip->first_soc_done);
+
+ return IRQ_HANDLED;
+}
+
+static void fg_external_power_changed(struct power_supply *psy)
+{
+ struct fg_chip *chip = power_supply_get_drvdata(psy);
+
+ if (is_input_present(chip) && chip->rslow_comp.active &&
+ chip->rslow_comp.chg_rs_to_rslow > 0 &&
+ chip->rslow_comp.chg_rslow_comp_c1 > 0 &&
+ chip->rslow_comp.chg_rslow_comp_c2 > 0)
+ schedule_work(&chip->rslow_comp_work);
+ if (!is_input_present(chip) && chip->resume_soc_lowered) {
+ fg_stay_awake(&chip->resume_soc_wakeup_source);
+ schedule_work(&chip->set_resume_soc_work);
+ }
+ if (!is_input_present(chip) && chip->charge_full)
+ schedule_work(&chip->charge_full_work);
+}
+
+static void set_resume_soc_work(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ set_resume_soc_work);
+ int rc, resume_soc_raw;
+
+ if (is_input_present(chip) && !chip->resume_soc_lowered) {
+ if (!chip->charge_done)
+ goto done;
+ resume_soc_raw = get_monotonic_soc_raw(chip)
+ - (0xFF - settings[FG_MEM_RESUME_SOC].value);
+ if (resume_soc_raw > 0 && resume_soc_raw < FULL_SOC_RAW) {
+ rc = fg_set_resume_soc(chip, resume_soc_raw);
+ if (rc) {
+ pr_err("Couldn't set resume SOC for FG\n");
+ goto done;
+ }
+ if (fg_debug_mask & FG_STATUS) {
+ pr_info("resume soc lowered to 0x%02x\n",
+ resume_soc_raw);
+ }
+ } else if (settings[FG_MEM_RESUME_SOC].value > 0) {
+ pr_err("bad resume soc 0x%02x\n", resume_soc_raw);
+ }
+ chip->charge_done = false;
+ chip->resume_soc_lowered = true;
+ } else if (chip->resume_soc_lowered && (!is_input_present(chip)
+ || chip->health == POWER_SUPPLY_HEALTH_GOOD)) {
+ resume_soc_raw = settings[FG_MEM_RESUME_SOC].value;
+ if (resume_soc_raw > 0 && resume_soc_raw < FULL_SOC_RAW) {
+ rc = fg_set_resume_soc(chip, resume_soc_raw);
+ if (rc) {
+ pr_err("Couldn't set resume SOC for FG\n");
+ goto done;
+ }
+ if (fg_debug_mask & FG_STATUS) {
+ pr_info("resume soc set to 0x%02x\n",
+ resume_soc_raw);
+ }
+ } else if (settings[FG_MEM_RESUME_SOC].value > 0) {
+ pr_err("bad resume soc 0x%02x\n", resume_soc_raw);
+ }
+ chip->resume_soc_lowered = false;
+ }
+done:
+ fg_relax(&chip->resume_soc_wakeup_source);
+}
+
+
+#define OCV_COEFFS_START_REG 0x4C0
+#define OCV_JUNCTION_REG 0x4D8
+#define NOM_CAP_REG 0x4F4
+#define CUTOFF_VOLTAGE_REG 0x40C
+#define RSLOW_CFG_REG 0x538
+#define RSLOW_CFG_OFFSET 2
+#define RSLOW_THRESH_REG 0x52C
+#define RSLOW_THRESH_OFFSET 0
+#define TEMP_RS_TO_RSLOW_OFFSET 2
+#define RSLOW_COMP_REG 0x528
+#define RSLOW_COMP_C1_OFFSET 0
+#define RSLOW_COMP_C2_OFFSET 2
+static int populate_system_data(struct fg_chip *chip)
+{
+ u8 buffer[24];
+ int rc, i;
+ int16_t cc_mah;
+
+ fg_mem_lock(chip);
+ rc = fg_mem_read(chip, buffer, OCV_COEFFS_START_REG, 24, 0, 0);
+ if (rc) {
+ pr_err("Failed to read ocv coefficients: %d\n", rc);
+ goto done;
+ }
+ for (i = 0; i < 12; i += 1)
+ chip->ocv_coeffs[i] = half_float(buffer + (i * 2));
+ if (fg_debug_mask & FG_AGING) {
+ pr_info("coeffs1 = %lld %lld %lld %lld\n",
+ chip->ocv_coeffs[0], chip->ocv_coeffs[1],
+ chip->ocv_coeffs[2], chip->ocv_coeffs[3]);
+ pr_info("coeffs2 = %lld %lld %lld %lld\n",
+ chip->ocv_coeffs[4], chip->ocv_coeffs[5],
+ chip->ocv_coeffs[6], chip->ocv_coeffs[7]);
+ pr_info("coeffs3 = %lld %lld %lld %lld\n",
+ chip->ocv_coeffs[8], chip->ocv_coeffs[9],
+ chip->ocv_coeffs[10], chip->ocv_coeffs[11]);
+ }
+ rc = fg_mem_read(chip, buffer, OCV_JUNCTION_REG, 1, 0, 0);
+ chip->ocv_junction_p1p2 = buffer[0] * 100 / 255;
+ rc |= fg_mem_read(chip, buffer, OCV_JUNCTION_REG, 1, 1, 0);
+ chip->ocv_junction_p2p3 = buffer[0] * 100 / 255;
+ if (rc) {
+ pr_err("Failed to read ocv junctions: %d\n", rc);
+ goto done;
+ }
+ rc = fg_mem_read(chip, buffer, NOM_CAP_REG, 2, 0, 0);
+ if (rc) {
+ pr_err("Failed to read nominal capacitance: %d\n", rc);
+ goto done;
+ }
+ chip->nom_cap_uah = bcap_uah_2b(buffer);
+ chip->actual_cap_uah = chip->nom_cap_uah;
+ if (chip->learning_data.learned_cc_uah == 0) {
+ chip->learning_data.learned_cc_uah = chip->nom_cap_uah;
+ fg_cap_learning_save_data(chip);
+ } else if (chip->learning_data.feedback_on) {
+ cc_mah = div64_s64(chip->learning_data.learned_cc_uah, 1000);
+ rc = fg_calc_and_store_cc_soc_coeff(chip, cc_mah);
+ if (rc)
+ pr_err("Error in restoring cc_soc_coeff, rc:%d\n", rc);
+ }
+ rc = fg_mem_read(chip, buffer, CUTOFF_VOLTAGE_REG, 2, 0, 0);
+ if (rc) {
+ pr_err("Failed to read cutoff voltage: %d\n", rc);
+ goto done;
+ }
+ chip->cutoff_voltage = voltage_2b(buffer);
+ if (fg_debug_mask & FG_AGING)
+ pr_info("cutoff_voltage = %lld, nom_cap_uah = %d p1p2 = %d, p2p3 = %d\n",
+ chip->cutoff_voltage, chip->nom_cap_uah,
+ chip->ocv_junction_p1p2,
+ chip->ocv_junction_p2p3);
+
+ rc = fg_mem_read(chip, buffer, RSLOW_CFG_REG, 1, RSLOW_CFG_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to read rslow cfg: %d\n", rc);
+ goto done;
+ }
+ chip->rslow_comp.rslow_cfg = buffer[0];
+ rc = fg_mem_read(chip, buffer, RSLOW_THRESH_REG, 1,
+ RSLOW_THRESH_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to read rslow thresh: %d\n", rc);
+ goto done;
+ }
+ chip->rslow_comp.rslow_thr = buffer[0];
+ rc = fg_mem_read(chip, buffer, TEMP_RS_TO_RSLOW_REG, 2,
+ RSLOW_THRESH_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to read rs to rslow: %d\n", rc);
+ goto done;
+ }
+ memcpy(chip->rslow_comp.rs_to_rslow, buffer, 2);
+ rc = fg_mem_read(chip, buffer, RSLOW_COMP_REG, 4,
+ RSLOW_COMP_C1_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to read rslow comp: %d\n", rc);
+ goto done;
+ }
+ memcpy(chip->rslow_comp.rslow_comp, buffer, 4);
+
+done:
+ fg_mem_release(chip);
+ return rc;
+}
+
+#define RSLOW_CFG_MASK (BIT(2) | BIT(3) | BIT(4) | BIT(5))
+#define RSLOW_CFG_ON_VAL (BIT(2) | BIT(3))
+#define RSLOW_THRESH_FULL_VAL 0xFF
+static int fg_rslow_charge_comp_set(struct fg_chip *chip)
+{
+ int rc;
+ u8 buffer[2];
+
+ mutex_lock(&chip->rslow_comp.lock);
+ fg_mem_lock(chip);
+
+ rc = fg_mem_masked_write(chip, RSLOW_CFG_REG,
+ RSLOW_CFG_MASK, RSLOW_CFG_ON_VAL, RSLOW_CFG_OFFSET);
+ if (rc) {
+ pr_err("unable to write rslow cfg: %d\n", rc);
+ goto done;
+ }
+ rc = fg_mem_masked_write(chip, RSLOW_THRESH_REG,
+ 0xFF, RSLOW_THRESH_FULL_VAL, RSLOW_THRESH_OFFSET);
+ if (rc) {
+ pr_err("unable to write rslow thresh: %d\n", rc);
+ goto done;
+ }
+
+ half_float_to_buffer(chip->rslow_comp.chg_rs_to_rslow, buffer);
+ rc = fg_mem_write(chip, buffer,
+ TEMP_RS_TO_RSLOW_REG, 2, TEMP_RS_TO_RSLOW_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to write rs to rslow: %d\n", rc);
+ goto done;
+ }
+ half_float_to_buffer(chip->rslow_comp.chg_rslow_comp_c1, buffer);
+ rc = fg_mem_write(chip, buffer,
+ RSLOW_COMP_REG, 2, RSLOW_COMP_C1_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to write rslow comp: %d\n", rc);
+ goto done;
+ }
+ half_float_to_buffer(chip->rslow_comp.chg_rslow_comp_c2, buffer);
+ rc = fg_mem_write(chip, buffer,
+ RSLOW_COMP_REG, 2, RSLOW_COMP_C2_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to write rslow comp: %d\n", rc);
+ goto done;
+ }
+ chip->rslow_comp.active = true;
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("Activated rslow charge comp values\n");
+
+done:
+ fg_mem_release(chip);
+ mutex_unlock(&chip->rslow_comp.lock);
+ return rc;
+}
+
+#define RSLOW_CFG_ORIG_MASK (BIT(4) | BIT(5))
+static int fg_rslow_charge_comp_clear(struct fg_chip *chip)
+{
+ u8 reg;
+ int rc;
+
+ mutex_lock(&chip->rslow_comp.lock);
+ fg_mem_lock(chip);
+
+ reg = chip->rslow_comp.rslow_cfg & RSLOW_CFG_ORIG_MASK;
+ rc = fg_mem_masked_write(chip, RSLOW_CFG_REG,
+ RSLOW_CFG_MASK, reg, RSLOW_CFG_OFFSET);
+ if (rc) {
+ pr_err("unable to write rslow cfg: %d\n", rc);
+ goto done;
+ }
+ rc = fg_mem_masked_write(chip, RSLOW_THRESH_REG,
+ 0xFF, chip->rslow_comp.rslow_thr, RSLOW_THRESH_OFFSET);
+ if (rc) {
+ pr_err("unable to write rslow thresh: %d\n", rc);
+ goto done;
+ }
+
+ rc = fg_mem_write(chip, chip->rslow_comp.rs_to_rslow,
+ TEMP_RS_TO_RSLOW_REG, 2, TEMP_RS_TO_RSLOW_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to write rs to rslow: %d\n", rc);
+ goto done;
+ }
+ rc = fg_mem_write(chip, chip->rslow_comp.rslow_comp,
+ RSLOW_COMP_REG, 4, RSLOW_COMP_C1_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to write rslow comp: %d\n", rc);
+ goto done;
+ }
+ chip->rslow_comp.active = false;
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("Cleared rslow charge comp values\n");
+
+done:
+ fg_mem_release(chip);
+ mutex_unlock(&chip->rslow_comp.lock);
+ return rc;
+}
+
+static void rslow_comp_work(struct work_struct *work)
+{
+ int battery_soc_1b;
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ rslow_comp_work);
+
+ battery_soc_1b = get_battery_soc_raw(chip) >> 16;
+ if (battery_soc_1b > chip->rslow_comp.chg_rslow_comp_thr
+ && chip->status == POWER_SUPPLY_STATUS_CHARGING) {
+ if (!chip->rslow_comp.active)
+ fg_rslow_charge_comp_set(chip);
+ } else {
+ if (chip->rslow_comp.active)
+ fg_rslow_charge_comp_clear(chip);
+ }
+}
+
+#define MICROUNITS_TO_ADC_RAW(units) \
+ div64_s64(units * LSB_16B_DENMTR, LSB_16B_NUMRTR)
+static int update_chg_iterm(struct fg_chip *chip)
+{
+ u8 data[2];
+ u16 converted_current_raw;
+ s64 current_ma = -settings[FG_MEM_CHG_TERM_CURRENT].value;
+
+ converted_current_raw = (s16)MICROUNITS_TO_ADC_RAW(current_ma * 1000);
+ data[0] = cpu_to_le16(converted_current_raw) & 0xFF;
+ data[1] = cpu_to_le16(converted_current_raw) >> 8;
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("current = %lld, converted_raw = %04x, data = %02x %02x\n",
+ current_ma, converted_current_raw, data[0], data[1]);
+ return fg_mem_write(chip, data,
+ settings[FG_MEM_CHG_TERM_CURRENT].address,
+ 2, settings[FG_MEM_CHG_TERM_CURRENT].offset, 0);
+}
+
+#define CC_CV_SETPOINT_REG 0x4F8
+#define CC_CV_SETPOINT_OFFSET 0
+static void update_cc_cv_setpoint(struct fg_chip *chip)
+{
+ int rc;
+ u8 tmp[2];
+
+ if (!chip->cc_cv_threshold_mv)
+ return;
+ batt_to_setpoint_adc(chip->cc_cv_threshold_mv, tmp);
+ rc = fg_mem_write(chip, tmp, CC_CV_SETPOINT_REG, 2,
+ CC_CV_SETPOINT_OFFSET, 0);
+ if (rc) {
+ pr_err("failed to write CC_CV_VOLT rc=%d\n", rc);
+ return;
+ }
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("Wrote %x %x to address %x for CC_CV setpoint\n",
+ tmp[0], tmp[1], CC_CV_SETPOINT_REG);
+}
+
+#define CBITS_INPUT_FILTER_REG 0x4B4
+#define CBITS_RMEAS1_OFFSET 1
+#define CBITS_RMEAS2_OFFSET 2
+#define CBITS_RMEAS1_DEFAULT_VAL 0x65
+#define CBITS_RMEAS2_DEFAULT_VAL 0x65
+#define IMPTR_FAST_TIME_SHIFT 1
+#define IMPTR_LONG_TIME_SHIFT (1 << 4)
+#define IMPTR_PULSE_CTR_CHG 1
+#define IMPTR_PULSE_CTR_DISCHG (1 << 4)
+static int fg_config_imptr_pulse(struct fg_chip *chip, bool slow)
+{
+ int rc;
+ u8 cntr[2] = {0, 0};
+ u8 val;
+
+ if (slow == chip->imptr_pulse_slow_en) {
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("imptr_pulse_slow is %sabled already\n",
+ slow ? "en" : "dis");
+ return 0;
+ }
+
+ fg_mem_lock(chip);
+
+ val = slow ? (IMPTR_FAST_TIME_SHIFT | IMPTR_LONG_TIME_SHIFT) :
+ CBITS_RMEAS1_DEFAULT_VAL;
+ rc = fg_mem_write(chip, &val, CBITS_INPUT_FILTER_REG, 1,
+ CBITS_RMEAS1_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to write cbits_rmeas1_offset rc=%d\n", rc);
+ goto done;
+ }
+
+ val = slow ? (IMPTR_PULSE_CTR_CHG | IMPTR_PULSE_CTR_DISCHG) :
+ CBITS_RMEAS2_DEFAULT_VAL;
+ rc = fg_mem_write(chip, &val, CBITS_INPUT_FILTER_REG, 1,
+ CBITS_RMEAS2_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to write cbits_rmeas2_offset rc=%d\n", rc);
+ goto done;
+ }
+
+ if (slow) {
+ rc = fg_mem_write(chip, cntr, COUNTER_IMPTR_REG, 4,
+ COUNTER_IMPTR_OFFSET, 0);
+ if (rc) {
+ pr_err("failed to write COUNTER_IMPTR rc=%d\n", rc);
+ goto done;
+ }
+
+ rc = fg_mem_write(chip, cntr, COUNTER_PULSE_REG, 2,
+ COUNTER_PULSE_OFFSET, 0);
+ if (rc) {
+ pr_err("failed to write COUNTER_IMPTR rc=%d\n", rc);
+ goto done;
+ }
+ }
+
+ chip->imptr_pulse_slow_en = slow;
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("imptr_pulse_slow is %sabled\n", slow ? "en" : "dis");
+done:
+ fg_mem_release(chip);
+ return rc;
+}
+
+#define CURRENT_DELTA_MIN_REG 0x42C
+#define CURRENT_DELTA_MIN_OFFSET 1
+#define SYS_CFG_1_REG 0x4AC
+#define SYS_CFG_1_OFFSET 0
+#define CURRENT_DELTA_MIN_DEFAULT 0x16
+#define CURRENT_DELTA_MIN_500MA 0xCD
+#define RSLOW_CFG_USE_FIX_RSER_VAL BIT(7)
+#define ENABLE_ESR_PULSE_VAL BIT(3)
+static int fg_config_esr_extract(struct fg_chip *chip, bool disable)
+{
+ int rc;
+ u8 val;
+
+ if (disable == chip->esr_extract_disabled) {
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("ESR extract already %sabled\n",
+ disable ? "dis" : "en");
+ return 0;
+ }
+
+ fg_mem_lock(chip);
+
+ val = disable ? CURRENT_DELTA_MIN_500MA :
+ CURRENT_DELTA_MIN_DEFAULT;
+ rc = fg_mem_write(chip, &val, CURRENT_DELTA_MIN_REG, 1,
+ CURRENT_DELTA_MIN_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to write curr_delta_min rc=%d\n", rc);
+ goto done;
+ }
+
+ val = disable ? RSLOW_CFG_USE_FIX_RSER_VAL : 0;
+ rc = fg_mem_masked_write(chip, RSLOW_CFG_REG,
+ RSLOW_CFG_USE_FIX_RSER_VAL, val, RSLOW_CFG_OFFSET);
+ if (rc) {
+ pr_err("unable to write rslow cfg rc= %d\n", rc);
+ goto done;
+ }
+
+ val = disable ? 0 : ENABLE_ESR_PULSE_VAL;
+ rc = fg_mem_masked_write(chip, SYS_CFG_1_REG,
+ ENABLE_ESR_PULSE_VAL, val, SYS_CFG_1_OFFSET);
+ if (rc) {
+ pr_err("unable to write sys_cfg_1 rc= %d\n", rc);
+ goto done;
+ }
+
+ chip->esr_extract_disabled = disable;
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("ESR extract is %sabled\n", disable ? "dis" : "en");
+done:
+ fg_mem_release(chip);
+ return rc;
+}
+
+#define ESR_EXTRACT_STOP_SOC 2
+#define IMPTR_PULSE_CONFIG_SOC 5
+static void esr_extract_config_work(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work, struct fg_chip,
+ esr_extract_config_work);
+ bool input_present = is_input_present(chip);
+ int capacity = get_prop_capacity(chip);
+
+ if (input_present && capacity <= ESR_EXTRACT_STOP_SOC) {
+ fg_config_esr_extract(chip, true);
+ } else if (capacity > ESR_EXTRACT_STOP_SOC) {
+ fg_config_esr_extract(chip, false);
+
+ if (capacity <= IMPTR_PULSE_CONFIG_SOC)
+ fg_config_imptr_pulse(chip, true);
+ else
+ fg_config_imptr_pulse(chip, false);
+ }
+
+ fg_relax(&chip->esr_extract_wakeup_source);
+}
+
+#define LOW_LATENCY BIT(6)
+#define BATT_PROFILE_OFFSET 0x4C0
+#define PROFILE_INTEGRITY_REG 0x53C
+#define PROFILE_INTEGRITY_BIT BIT(0)
+#define FIRST_EST_DONE_BIT BIT(5)
+#define MAX_TRIES_FIRST_EST 3
+#define FIRST_EST_WAIT_MS 2000
+#define PROFILE_LOAD_TIMEOUT_MS 5000
+static int fg_do_restart(struct fg_chip *chip, bool write_profile)
+{
+ int rc, ibat_ua;
+ u8 reg = 0;
+ u8 buf[2];
+ bool tried_once = false;
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("restarting fuel gauge...\n");
+
+try_again:
+ if (write_profile) {
+ if (!chip->charging_disabled) {
+ pr_err("Charging not yet disabled!\n");
+ return -EINVAL;
+ }
+
+ ibat_ua = get_sram_prop_now(chip, FG_DATA_CURRENT);
+ if (ibat_ua == -EINVAL) {
+ pr_err("SRAM not updated yet!\n");
+ return ibat_ua;
+ }
+
+ if (ibat_ua < 0) {
+ pr_warn("Charging enabled?, ibat_ua: %d\n", ibat_ua);
+
+ if (!tried_once) {
+ cancel_delayed_work(&chip->update_sram_data);
+ schedule_delayed_work(&chip->update_sram_data,
+ msecs_to_jiffies(0));
+ msleep(1000);
+ tried_once = true;
+ goto try_again;
+ }
+ }
+ }
+
+ chip->fg_restarting = true;
+ /*
+ * save the temperature if the sw rbias control is active so that there
+ * is no gap of time when there is no valid temperature read after the
+ * restart
+ */
+ if (chip->sw_rbias_ctrl) {
+ rc = fg_mem_read(chip, buf,
+ fg_data[FG_DATA_BATT_TEMP].address,
+ fg_data[FG_DATA_BATT_TEMP].len,
+ fg_data[FG_DATA_BATT_TEMP].offset, 0);
+ if (rc) {
+ pr_err("failed to read batt temp rc=%d\n", rc);
+ goto sub_and_fail;
+ }
+ }
+ /*
+ * release the sram access and configure the correct settings
+ * before re-requesting access.
+ */
+ mutex_lock(&chip->rw_lock);
+ fg_release_access(chip);
+
+ rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,
+ NO_OTP_PROF_RELOAD, 0, 1);
+ if (rc) {
+ pr_err("failed to set no otp reload bit\n");
+ goto unlock_and_fail;
+ }
+
+ /* unset the restart bits so the fg doesn't continuously restart */
+ reg = REDO_FIRST_ESTIMATE | RESTART_GO;
+ rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,
+ reg, 0, 1);
+ if (rc) {
+ pr_err("failed to unset fg restart: %d\n", rc);
+ goto unlock_and_fail;
+ }
+
+ rc = fg_masked_write(chip, MEM_INTF_CFG(chip),
+ LOW_LATENCY, LOW_LATENCY, 1);
+ if (rc) {
+ pr_err("failed to set low latency access bit\n");
+ goto unlock_and_fail;
+ }
+ mutex_unlock(&chip->rw_lock);
+
+ /* read once to get a fg cycle in */
+ rc = fg_mem_read(chip, ®, PROFILE_INTEGRITY_REG, 1, 0, 0);
+ if (rc) {
+ pr_err("failed to read profile integrity rc=%d\n", rc);
+ goto fail;
+ }
+
+ /*
+ * If this is not the first time a profile has been loaded, sleep for
+ * 3 seconds to make sure the NO_OTP_RELOAD is cleared in memory
+ */
+ if (chip->first_profile_loaded)
+ msleep(3000);
+
+ mutex_lock(&chip->rw_lock);
+ fg_release_access(chip);
+ rc = fg_masked_write(chip, MEM_INTF_CFG(chip), LOW_LATENCY, 0, 1);
+ if (rc) {
+ pr_err("failed to set low latency access bit\n");
+ goto unlock_and_fail;
+ }
+
+ atomic_add_return(1, &chip->memif_user_cnt);
+ mutex_unlock(&chip->rw_lock);
+
+ if (write_profile) {
+ /* write the battery profile */
+ rc = fg_mem_write(chip, chip->batt_profile, BATT_PROFILE_OFFSET,
+ chip->batt_profile_len, 0, 1);
+ if (rc) {
+ pr_err("failed to write profile rc=%d\n", rc);
+ goto sub_and_fail;
+ }
+ /* write the integrity bits and release access */
+ rc = fg_mem_masked_write(chip, PROFILE_INTEGRITY_REG,
+ PROFILE_INTEGRITY_BIT,
+ PROFILE_INTEGRITY_BIT, 0);
+ if (rc) {
+ pr_err("failed to write profile rc=%d\n", rc);
+ goto sub_and_fail;
+ }
+ }
+
+ /* decrement the user count so that memory access can be released */
+ fg_release_access_if_necessary(chip);
+
+ /*
+ * make sure that the first estimate has completed
+ * in case of a hotswap
+ */
+ rc = wait_for_completion_interruptible_timeout(&chip->first_soc_done,
+ msecs_to_jiffies(PROFILE_LOAD_TIMEOUT_MS));
+ if (rc <= 0) {
+ pr_err("transaction timed out rc=%d\n", rc);
+ rc = -ETIMEDOUT;
+ goto fail;
+ }
+
+ /*
+ * reinitialize the completion so that the driver knows when the restart
+ * finishes
+ */
+ reinit_completion(&chip->first_soc_done);
+
+ if (chip->esr_pulse_tune_en) {
+ fg_stay_awake(&chip->esr_extract_wakeup_source);
+ schedule_work(&chip->esr_extract_config_work);
+ }
+
+ /*
+ * set the restart bits so that the next fg cycle will not reload
+ * the profile
+ */
+ rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,
+ NO_OTP_PROF_RELOAD, NO_OTP_PROF_RELOAD, 1);
+ if (rc) {
+ pr_err("failed to set no otp reload bit\n");
+ goto fail;
+ }
+
+ reg = REDO_FIRST_ESTIMATE | RESTART_GO;
+ rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,
+ reg, reg, 1);
+ if (rc) {
+ pr_err("failed to set fg restart: %d\n", rc);
+ goto fail;
+ }
+
+ /* wait for the first estimate to complete */
+ rc = wait_for_completion_interruptible_timeout(&chip->first_soc_done,
+ msecs_to_jiffies(PROFILE_LOAD_TIMEOUT_MS));
+ if (rc <= 0) {
+ pr_err("transaction timed out rc=%d\n", rc);
+ rc = -ETIMEDOUT;
+ goto fail;
+ }
+ rc = fg_read(chip, ®, INT_RT_STS(chip->soc_base), 1);
+ if (rc) {
+ pr_err("spmi read failed: addr=%03X, rc=%d\n",
+ INT_RT_STS(chip->soc_base), rc);
+ goto fail;
+ }
+ if ((reg & FIRST_EST_DONE_BIT) == 0)
+ pr_err("Battery profile reloading failed, no first estimate\n");
+
+ rc = fg_masked_write(chip, chip->soc_base + SOC_BOOT_MOD,
+ NO_OTP_PROF_RELOAD, 0, 1);
+ if (rc) {
+ pr_err("failed to set no otp reload bit\n");
+ goto fail;
+ }
+ /* unset the restart bits so the fg doesn't continuously restart */
+ reg = REDO_FIRST_ESTIMATE | RESTART_GO;
+ rc = fg_masked_write(chip, chip->soc_base + SOC_RESTART,
+ reg, 0, 1);
+ if (rc) {
+ pr_err("failed to unset fg restart: %d\n", rc);
+ goto fail;
+ }
+
+ /* restore the battery temperature reading here */
+ if (chip->sw_rbias_ctrl) {
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("reloaded 0x%02x%02x into batt temp",
+ buf[0], buf[1]);
+ rc = fg_mem_write(chip, buf,
+ fg_data[FG_DATA_BATT_TEMP].address,
+ fg_data[FG_DATA_BATT_TEMP].len,
+ fg_data[FG_DATA_BATT_TEMP].offset, 0);
+ if (rc) {
+ pr_err("failed to write batt temp rc=%d\n", rc);
+ goto fail;
+ }
+ }
+
+ /* Enable charging now as the first estimate is done now */
+ if (chip->charging_disabled) {
+ rc = set_prop_enable_charging(chip, true);
+ if (rc)
+ pr_err("Failed to enable charging, rc=%d\n", rc);
+ else
+ chip->charging_disabled = false;
+ }
+
+ chip->fg_restarting = false;
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("done!\n");
+ return 0;
+
+unlock_and_fail:
+ mutex_unlock(&chip->rw_lock);
+ goto fail;
+sub_and_fail:
+ fg_release_access_if_necessary(chip);
+ goto fail;
+fail:
+ chip->fg_restarting = false;
+ return -EINVAL;
+}
+
+#define FG_PROFILE_LEN 128
+#define PROFILE_COMPARE_LEN 32
+#define THERMAL_COEFF_ADDR 0x444
+#define THERMAL_COEFF_OFFSET 0x2
+#define BATTERY_PSY_WAIT_MS 2000
+static int fg_batt_profile_init(struct fg_chip *chip)
+{
+ int rc = 0, ret, len, batt_id;
+ struct device_node *node = chip->pdev->dev.of_node;
+ struct device_node *batt_node, *profile_node;
+ const char *data, *batt_type_str;
+ bool tried_again = false, vbat_in_range, profiles_same;
+ u8 reg = 0;
+
+wait:
+ fg_stay_awake(&chip->profile_wakeup_source);
+ ret = wait_for_completion_interruptible_timeout(&chip->batt_id_avail,
+ msecs_to_jiffies(PROFILE_LOAD_TIMEOUT_MS));
+ /* If we were interrupted wait again one more time. */
+ if (ret == -ERESTARTSYS && !tried_again) {
+ tried_again = true;
+ pr_debug("interrupted, waiting again\n");
+ goto wait;
+ } else if (ret <= 0) {
+ rc = -ETIMEDOUT;
+ pr_err("profile loading timed out rc=%d\n", rc);
+ goto no_profile;
+ }
+
+ batt_node = of_find_node_by_name(node, "qcom,battery-data");
+ if (!batt_node) {
+ pr_warn("No available batterydata, using OTP defaults\n");
+ rc = 0;
+ goto no_profile;
+ }
+
+ batt_id = get_sram_prop_now(chip, FG_DATA_BATT_ID);
+ batt_id /= 1000;
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("battery id = %dKOhms\n", batt_id);
+
+ profile_node = of_batterydata_get_best_profile(batt_node, batt_id,
+ fg_batt_type);
+ if (IS_ERR_OR_NULL(profile_node)) {
+ rc = PTR_ERR(profile_node);
+ pr_err("couldn't find profile handle %d\n", rc);
+ goto no_profile;
+ }
+
+ /* read rslow compensation values if they're available */
+ rc = of_property_read_u32(profile_node, "qcom,chg-rs-to-rslow",
+ &chip->rslow_comp.chg_rs_to_rslow);
+ if (rc) {
+ chip->rslow_comp.chg_rs_to_rslow = -EINVAL;
+ if (rc != -EINVAL)
+ pr_err("Could not read rs to rslow: %d\n", rc);
+ }
+ rc = of_property_read_u32(profile_node, "qcom,chg-rslow-comp-c1",
+ &chip->rslow_comp.chg_rslow_comp_c1);
+ if (rc) {
+ chip->rslow_comp.chg_rslow_comp_c1 = -EINVAL;
+ if (rc != -EINVAL)
+ pr_err("Could not read rslow comp c1: %d\n", rc);
+ }
+ rc = of_property_read_u32(profile_node, "qcom,chg-rslow-comp-c2",
+ &chip->rslow_comp.chg_rslow_comp_c2);
+ if (rc) {
+ chip->rslow_comp.chg_rslow_comp_c2 = -EINVAL;
+ if (rc != -EINVAL)
+ pr_err("Could not read rslow comp c2: %d\n", rc);
+ }
+ rc = of_property_read_u32(profile_node, "qcom,chg-rslow-comp-thr",
+ &chip->rslow_comp.chg_rslow_comp_thr);
+ if (rc) {
+ chip->rslow_comp.chg_rslow_comp_thr = -EINVAL;
+ if (rc != -EINVAL)
+ pr_err("Could not read rslow comp thr: %d\n", rc);
+ }
+
+ rc = of_property_read_u32(profile_node, "qcom,max-voltage-uv",
+ &chip->batt_max_voltage_uv);
+
+ if (rc)
+ pr_warn("couldn't find battery max voltage\n");
+
+ /*
+ * Only configure from profile if fg-cc-cv-threshold-mv is not
+ * defined in the charger device node.
+ */
+ if (!of_find_property(chip->pdev->dev.of_node,
+ "qcom,fg-cc-cv-threshold-mv", NULL)) {
+ of_property_read_u32(profile_node,
+ "qcom,fg-cc-cv-threshold-mv",
+ &chip->cc_cv_threshold_mv);
+ }
+
+ data = of_get_property(profile_node, "qcom,fg-profile-data", &len);
+ if (!data) {
+ pr_err("no battery profile loaded\n");
+ rc = 0;
+ goto no_profile;
+ }
+
+ if (len != FG_PROFILE_LEN) {
+ pr_err("battery profile incorrect size: %d\n", len);
+ rc = -EINVAL;
+ goto no_profile;
+ }
+
+ rc = of_property_read_string(profile_node, "qcom,battery-type",
+ &batt_type_str);
+ if (rc) {
+ pr_err("Could not find battery data type: %d\n", rc);
+ rc = 0;
+ goto no_profile;
+ }
+
+ if (!chip->batt_profile)
+ chip->batt_profile = devm_kzalloc(chip->dev,
+ sizeof(char) * len, GFP_KERNEL);
+
+ if (!chip->batt_profile) {
+ pr_err("out of memory\n");
+ rc = -ENOMEM;
+ goto no_profile;
+ }
+
+ rc = fg_mem_read(chip, ®, PROFILE_INTEGRITY_REG, 1, 0, 1);
+ if (rc) {
+ pr_err("failed to read profile integrity rc=%d\n", rc);
+ goto no_profile;
+ }
+
+ rc = fg_mem_read(chip, chip->batt_profile, BATT_PROFILE_OFFSET,
+ len, 0, 1);
+ if (rc) {
+ pr_err("failed to read profile rc=%d\n", rc);
+ goto no_profile;
+ }
+
+ /* Check whether the charger is ready */
+ if (!is_charger_available(chip))
+ goto reschedule;
+
+ /* Disable charging for a FG cycle before calculating vbat_in_range */
+ if (!chip->charging_disabled) {
+ rc = set_prop_enable_charging(chip, false);
+ if (rc)
+ pr_err("Failed to disable charging, rc=%d\n", rc);
+
+ goto reschedule;
+ }
+
+ vbat_in_range = get_vbat_est_diff(chip)
+ < settings[FG_MEM_VBAT_EST_DIFF].value * 1000;
+ profiles_same = memcmp(chip->batt_profile, data,
+ PROFILE_COMPARE_LEN) == 0;
+ if (reg & PROFILE_INTEGRITY_BIT) {
+ fg_cap_learning_load_data(chip);
+ if (vbat_in_range && !fg_is_batt_empty(chip) && profiles_same) {
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("Battery profiles same, using default\n");
+ if (fg_est_dump)
+ schedule_work(&chip->dump_sram);
+ goto done;
+ }
+ } else {
+ pr_info("Battery profile not same, clearing data\n");
+ clear_cycle_counter(chip);
+ chip->learning_data.learned_cc_uah = 0;
+ }
+
+ if (fg_est_dump)
+ dump_sram(&chip->dump_sram);
+
+ if ((fg_debug_mask & FG_STATUS) && !vbat_in_range)
+ pr_info("Vbat out of range: v_current_pred: %d, v:%d\n",
+ fg_data[FG_DATA_CPRED_VOLTAGE].value,
+ fg_data[FG_DATA_VOLTAGE].value);
+
+ if ((fg_debug_mask & FG_STATUS) && fg_is_batt_empty(chip))
+ pr_info("battery empty\n");
+
+ if ((fg_debug_mask & FG_STATUS) && !profiles_same)
+ pr_info("profiles differ\n");
+
+ if (fg_debug_mask & FG_STATUS) {
+ pr_info("Using new profile\n");
+ print_hex_dump(KERN_INFO, "FG: loaded profile: ",
+ DUMP_PREFIX_NONE, 16, 1,
+ chip->batt_profile, len, false);
+ }
+
+ if (chip->power_supply_registered)
+ power_supply_changed(chip->bms_psy);
+
+ memcpy(chip->batt_profile, data, len);
+
+ chip->batt_profile_len = len;
+
+ if (fg_debug_mask & FG_STATUS)
+ print_hex_dump(KERN_INFO, "FG: new profile: ",
+ DUMP_PREFIX_NONE, 16, 1, chip->batt_profile,
+ chip->batt_profile_len, false);
+
+ rc = fg_do_restart(chip, true);
+ if (rc) {
+ pr_err("restart failed: %d\n", rc);
+ goto no_profile;
+ }
+
+ /*
+ * Only configure from profile if thermal-coefficients is not
+ * defined in the FG device node.
+ */
+ if (!of_find_property(chip->pdev->dev.of_node,
+ "qcom,thermal-coefficients", NULL)) {
+ data = of_get_property(profile_node,
+ "qcom,thermal-coefficients", &len);
+ if (data && len == THERMAL_COEFF_N_BYTES) {
+ memcpy(chip->thermal_coefficients, data, len);
+ rc = fg_mem_write(chip, chip->thermal_coefficients,
+ THERMAL_COEFF_ADDR, THERMAL_COEFF_N_BYTES,
+ THERMAL_COEFF_OFFSET, 0);
+ if (rc)
+ pr_err("spmi write failed addr:%03x, ret:%d\n",
+ THERMAL_COEFF_ADDR, rc);
+ else if (fg_debug_mask & FG_STATUS)
+ pr_info("Battery thermal coefficients changed\n");
+ }
+ }
+
+done:
+ if (chip->charging_disabled) {
+ rc = set_prop_enable_charging(chip, true);
+ if (rc)
+ pr_err("Failed to enable charging, rc=%d\n", rc);
+ else
+ chip->charging_disabled = false;
+ }
+
+ if (fg_batt_type)
+ chip->batt_type = fg_batt_type;
+ else
+ chip->batt_type = batt_type_str;
+ chip->first_profile_loaded = true;
+ chip->profile_loaded = true;
+ chip->battery_missing = is_battery_missing(chip);
+ update_chg_iterm(chip);
+ update_cc_cv_setpoint(chip);
+ rc = populate_system_data(chip);
+ if (rc) {
+ pr_err("failed to read ocv properties=%d\n", rc);
+ return rc;
+ }
+ estimate_battery_age(chip, &chip->actual_cap_uah);
+ schedule_work(&chip->status_change_work);
+ if (chip->power_supply_registered)
+ power_supply_changed(chip->bms_psy);
+ fg_relax(&chip->profile_wakeup_source);
+ pr_info("Battery SOC: %d, V: %duV\n", get_prop_capacity(chip),
+ fg_data[FG_DATA_VOLTAGE].value);
+ return rc;
+no_profile:
+ if (chip->charging_disabled) {
+ rc = set_prop_enable_charging(chip, true);
+ if (rc)
+ pr_err("Failed to enable charging, rc=%d\n", rc);
+ else
+ chip->charging_disabled = false;
+ }
+
+ if (chip->power_supply_registered)
+ power_supply_changed(chip->bms_psy);
+ fg_relax(&chip->profile_wakeup_source);
+ return rc;
+reschedule:
+ schedule_delayed_work(
+ &chip->batt_profile_init,
+ msecs_to_jiffies(BATTERY_PSY_WAIT_MS));
+ cancel_delayed_work(&chip->update_sram_data);
+ schedule_delayed_work(
+ &chip->update_sram_data,
+ msecs_to_jiffies(0));
+ fg_relax(&chip->profile_wakeup_source);
+ return 0;
+}
+
+static void check_empty_work(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ check_empty_work.work);
+
+ if (fg_is_batt_empty(chip)) {
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("EMPTY SOC high\n");
+ chip->soc_empty = true;
+ if (chip->power_supply_registered)
+ power_supply_changed(chip->bms_psy);
+ }
+ fg_relax(&chip->empty_check_wakeup_source);
+}
+
+static void batt_profile_init(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ batt_profile_init.work);
+
+ if (fg_batt_profile_init(chip))
+ pr_err("failed to initialize profile\n");
+}
+
+static void sysfs_restart_work(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ sysfs_restart_work);
+ int rc;
+
+ rc = fg_do_restart(chip, false);
+ if (rc)
+ pr_err("fg restart failed: %d\n", rc);
+ mutex_lock(&chip->sysfs_restart_lock);
+ fg_restart = 0;
+ mutex_unlock(&chip->sysfs_restart_lock);
+}
+
+#define SRAM_MONOTONIC_SOC_REG 0x574
+#define SRAM_MONOTONIC_SOC_OFFSET 2
+#define SRAM_RELEASE_TIMEOUT_MS 500
+static void charge_full_work(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ charge_full_work);
+ int rc;
+ u8 buffer[3];
+ int bsoc;
+ int resume_soc_raw = FULL_SOC_RAW - settings[FG_MEM_RESUME_SOC].value;
+ bool disable = false;
+ u8 reg;
+
+ if (chip->status != POWER_SUPPLY_STATUS_FULL) {
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("battery not full: %d\n", chip->status);
+ disable = true;
+ }
+
+ fg_mem_lock(chip);
+ rc = fg_mem_read(chip, buffer, BATTERY_SOC_REG, 3, 1, 0);
+ if (rc) {
+ pr_err("Unable to read battery soc: %d\n", rc);
+ goto out;
+ }
+ if (buffer[2] <= resume_soc_raw) {
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("bsoc = 0x%02x <= resume = 0x%02x\n",
+ buffer[2], resume_soc_raw);
+ disable = true;
+ }
+ if (!disable)
+ goto out;
+
+ rc = fg_mem_write(chip, buffer, SOC_FULL_REG, 3,
+ SOC_FULL_OFFSET, 0);
+ if (rc) {
+ pr_err("failed to write SOC_FULL rc=%d\n", rc);
+ goto out;
+ }
+ /* force a full soc value into the monotonic in order to display 100 */
+ buffer[0] = 0xFF;
+ buffer[1] = 0xFF;
+ rc = fg_mem_write(chip, buffer, SRAM_MONOTONIC_SOC_REG, 2,
+ SRAM_MONOTONIC_SOC_OFFSET, 0);
+ if (rc) {
+ pr_err("failed to write SOC_FULL rc=%d\n", rc);
+ goto out;
+ }
+ if (fg_debug_mask & FG_STATUS) {
+ bsoc = buffer[0] | buffer[1] << 8 | buffer[2] << 16;
+ pr_info("wrote %06x into soc full\n", bsoc);
+ }
+ fg_mem_release(chip);
+ /*
+ * wait one cycle to make sure the soc is updated before clearing
+ * the soc mask bit
+ */
+ fg_mem_lock(chip);
+ fg_mem_read(chip, ®, PROFILE_INTEGRITY_REG, 1, 0, 0);
+out:
+ fg_mem_release(chip);
+ if (disable)
+ chip->charge_full = false;
+}
+
+static void update_bcl_thresholds(struct fg_chip *chip)
+{
+ u8 data[4];
+ u8 mh_offset = 0, lm_offset = 0;
+ u16 address = 0;
+ int ret = 0;
+
+ address = settings[FG_MEM_BCL_MH_THRESHOLD].address;
+ mh_offset = settings[FG_MEM_BCL_MH_THRESHOLD].offset;
+ lm_offset = settings[FG_MEM_BCL_LM_THRESHOLD].offset;
+ ret = fg_mem_read(chip, data, address, 4, 0, 1);
+ if (ret)
+ pr_err("Error reading BCL LM & MH threshold rc:%d\n", ret);
+ else
+ pr_debug("Old BCL LM threshold:%x MH threshold:%x\n",
+ data[lm_offset], data[mh_offset]);
+ BCL_MA_TO_ADC(settings[FG_MEM_BCL_MH_THRESHOLD].value, data[mh_offset]);
+ BCL_MA_TO_ADC(settings[FG_MEM_BCL_LM_THRESHOLD].value, data[lm_offset]);
+
+ ret = fg_mem_write(chip, data, address, 4, 0, 0);
+ if (ret)
+ pr_err("spmi write failed. addr:%03x, ret:%d\n",
+ address, ret);
+ else
+ pr_debug("New BCL LM threshold:%x MH threshold:%x\n",
+ data[lm_offset], data[mh_offset]);
+}
+
+static int disable_bcl_lpm(struct fg_chip *chip)
+{
+ u8 data[4];
+ u8 lm_offset = 0;
+ u16 address = 0;
+ int rc = 0;
+
+ address = settings[FG_MEM_BCL_LM_THRESHOLD].address;
+ lm_offset = settings[FG_MEM_BCL_LM_THRESHOLD].offset;
+ rc = fg_mem_read(chip, data, address, 4, 0, 1);
+ if (rc) {
+ pr_err("Error reading BCL LM & MH threshold rc:%d\n", rc);
+ return rc;
+ }
+ pr_debug("Old BCL LM threshold:%x\n", data[lm_offset]);
+
+ /* Put BCL always above LPM */
+ BCL_MA_TO_ADC(0, data[lm_offset]);
+
+ rc = fg_mem_write(chip, data, address, 4, 0, 0);
+ if (rc)
+ pr_err("spmi write failed. addr:%03x, rc:%d\n",
+ address, rc);
+ else
+ pr_debug("New BCL LM threshold:%x\n", data[lm_offset]);
+
+ return rc;
+}
+
+static void bcl_hi_power_work(struct work_struct *work)
+{
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ bcl_hi_power_work);
+ int rc;
+
+ if (chip->bcl_lpm_disabled) {
+ rc = disable_bcl_lpm(chip);
+ if (rc)
+ pr_err("failed to disable bcl low mode %d\n",
+ rc);
+ } else {
+ update_bcl_thresholds(chip);
+ }
+}
+
+#define VOLT_UV_TO_VOLTCMP8(volt_uv) \
+ ((volt_uv - 2500000) / 9766)
+static int update_irq_volt_empty(struct fg_chip *chip)
+{
+ u8 data;
+ int volt_mv = settings[FG_MEM_IRQ_VOLT_EMPTY].value;
+
+ data = (u8)VOLT_UV_TO_VOLTCMP8(volt_mv * 1000);
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("voltage = %d, converted_raw = %04x\n", volt_mv, data);
+ return fg_mem_write(chip, &data,
+ settings[FG_MEM_IRQ_VOLT_EMPTY].address, 1,
+ settings[FG_MEM_IRQ_VOLT_EMPTY].offset, 0);
+}
+
+static int update_cutoff_voltage(struct fg_chip *chip)
+{
+ u8 data[2];
+ u16 converted_voltage_raw;
+ s64 voltage_mv = settings[FG_MEM_CUTOFF_VOLTAGE].value;
+
+ converted_voltage_raw = (s16)MICROUNITS_TO_ADC_RAW(voltage_mv * 1000);
+ data[0] = cpu_to_le16(converted_voltage_raw) & 0xFF;
+ data[1] = cpu_to_le16(converted_voltage_raw) >> 8;
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("voltage = %lld, converted_raw = %04x, data = %02x %02x\n",
+ voltage_mv, converted_voltage_raw, data[0], data[1]);
+ return fg_mem_write(chip, data, settings[FG_MEM_CUTOFF_VOLTAGE].address,
+ 2, settings[FG_MEM_CUTOFF_VOLTAGE].offset, 0);
+}
+
+static int update_iterm(struct fg_chip *chip)
+{
+ u8 data[2];
+ u16 converted_current_raw;
+ s64 current_ma = -settings[FG_MEM_TERM_CURRENT].value;
+
+ converted_current_raw = (s16)MICROUNITS_TO_ADC_RAW(current_ma * 1000);
+ data[0] = cpu_to_le16(converted_current_raw) & 0xFF;
+ data[1] = cpu_to_le16(converted_current_raw) >> 8;
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("current = %lld, converted_raw = %04x, data = %02x %02x\n",
+ current_ma, converted_current_raw, data[0], data[1]);
+ return fg_mem_write(chip, data, settings[FG_MEM_TERM_CURRENT].address,
+ 2, settings[FG_MEM_TERM_CURRENT].offset, 0);
+}
+
+#define OF_READ_SETTING(type, qpnp_dt_property, retval, optional) \
+do { \
+ if (retval) \
+ break; \
+ \
+ retval = of_property_read_u32(chip->pdev->dev.of_node, \
+ "qcom," qpnp_dt_property, \
+ &settings[type].value); \
+ \
+ if ((retval == -EINVAL) && optional) \
+ retval = 0; \
+ else if (retval) \
+ pr_err("Error reading " #qpnp_dt_property \
+ " property rc = %d\n", rc); \
+} while (0)
+
+#define OF_READ_PROPERTY(store, qpnp_dt_property, retval, default_val) \
+do { \
+ if (retval) \
+ break; \
+ \
+ retval = of_property_read_u32(chip->pdev->dev.of_node, \
+ "qcom," qpnp_dt_property, \
+ &store); \
+ \
+ if (retval == -EINVAL) { \
+ retval = 0; \
+ store = default_val; \
+ } else if (retval) { \
+ pr_err("Error reading " #qpnp_dt_property \
+ " property rc = %d\n", rc); \
+ } \
+} while (0)
+
+#define DEFAULT_EVALUATION_CURRENT_MA 1000
+static int fg_of_init(struct fg_chip *chip)
+{
+ int rc = 0, sense_type, len = 0;
+ const char *data;
+ struct device_node *node = chip->pdev->dev.of_node;
+ u32 temp[2] = {0};
+
+ OF_READ_SETTING(FG_MEM_SOFT_HOT, "warm-bat-decidegc", rc, 1);
+ OF_READ_SETTING(FG_MEM_SOFT_COLD, "cool-bat-decidegc", rc, 1);
+ OF_READ_SETTING(FG_MEM_HARD_HOT, "hot-bat-decidegc", rc, 1);
+ OF_READ_SETTING(FG_MEM_HARD_COLD, "cold-bat-decidegc", rc, 1);
+
+ if (of_find_property(node, "qcom,cold-hot-jeita-hysteresis", NULL)) {
+ int hard_hot = 0, soft_hot = 0, hard_cold = 0, soft_cold = 0;
+
+ rc = of_property_read_u32_array(node,
+ "qcom,cold-hot-jeita-hysteresis", temp, 2);
+ if (rc) {
+ pr_err("Error reading cold-hot-jeita-hysteresis rc=%d\n",
+ rc);
+ return rc;
+ }
+
+ chip->jeita_hysteresis_support = true;
+ chip->cold_hysteresis = temp[0];
+ chip->hot_hysteresis = temp[1];
+ hard_hot = settings[FG_MEM_HARD_HOT].value;
+ soft_hot = settings[FG_MEM_SOFT_HOT].value;
+ hard_cold = settings[FG_MEM_HARD_COLD].value;
+ soft_cold = settings[FG_MEM_SOFT_COLD].value;
+ if (((hard_hot - chip->hot_hysteresis) < soft_hot) ||
+ ((hard_cold + chip->cold_hysteresis) > soft_cold)) {
+ chip->jeita_hysteresis_support = false;
+ pr_err("invalid hysteresis: hot_hysterresis = %d cold_hysteresis = %d\n",
+ chip->hot_hysteresis, chip->cold_hysteresis);
+ } else {
+ pr_debug("cold_hysteresis = %d, hot_hysteresis = %d\n",
+ chip->cold_hysteresis, chip->hot_hysteresis);
+ }
+ }
+
+ OF_READ_SETTING(FG_MEM_BCL_LM_THRESHOLD, "bcl-lm-threshold-ma",
+ rc, 1);
+ OF_READ_SETTING(FG_MEM_BCL_MH_THRESHOLD, "bcl-mh-threshold-ma",
+ rc, 1);
+ OF_READ_SETTING(FG_MEM_TERM_CURRENT, "fg-iterm-ma", rc, 1);
+ OF_READ_SETTING(FG_MEM_CHG_TERM_CURRENT, "fg-chg-iterm-ma", rc, 1);
+ OF_READ_SETTING(FG_MEM_CUTOFF_VOLTAGE, "fg-cutoff-voltage-mv", rc, 1);
+ data = of_get_property(chip->pdev->dev.of_node,
+ "qcom,thermal-coefficients", &len);
+ if (data && len == THERMAL_COEFF_N_BYTES) {
+ memcpy(chip->thermal_coefficients, data, len);
+ chip->use_thermal_coefficients = true;
+ }
+ OF_READ_SETTING(FG_MEM_RESUME_SOC, "resume-soc", rc, 1);
+ settings[FG_MEM_RESUME_SOC].value =
+ DIV_ROUND_CLOSEST(settings[FG_MEM_RESUME_SOC].value
+ * FULL_SOC_RAW, FULL_CAPACITY);
+ OF_READ_SETTING(FG_MEM_RESUME_SOC, "resume-soc-raw", rc, 1);
+ OF_READ_SETTING(FG_MEM_IRQ_VOLT_EMPTY, "irq-volt-empty-mv", rc, 1);
+ OF_READ_SETTING(FG_MEM_VBAT_EST_DIFF, "vbat-estimate-diff-mv", rc, 1);
+ OF_READ_SETTING(FG_MEM_DELTA_SOC, "fg-delta-soc", rc, 1);
+ OF_READ_SETTING(FG_MEM_BATT_LOW, "fg-vbatt-low-threshold", rc, 1);
+ OF_READ_SETTING(FG_MEM_THERM_DELAY, "fg-therm-delay-us", rc, 1);
+ OF_READ_PROPERTY(chip->learning_data.max_increment,
+ "cl-max-increment-deciperc", rc, 5);
+ OF_READ_PROPERTY(chip->learning_data.max_decrement,
+ "cl-max-decrement-deciperc", rc, 100);
+ OF_READ_PROPERTY(chip->learning_data.max_temp,
+ "cl-max-temp-decidegc", rc, 450);
+ OF_READ_PROPERTY(chip->learning_data.min_temp,
+ "cl-min-temp-decidegc", rc, 150);
+ OF_READ_PROPERTY(chip->learning_data.max_start_soc,
+ "cl-max-start-capacity", rc, 15);
+ OF_READ_PROPERTY(chip->learning_data.vbat_est_thr_uv,
+ "cl-vbat-est-thr-uv", rc, 40000);
+ OF_READ_PROPERTY(chip->evaluation_current,
+ "aging-eval-current-ma", rc,
+ DEFAULT_EVALUATION_CURRENT_MA);
+ OF_READ_PROPERTY(chip->cc_cv_threshold_mv,
+ "fg-cc-cv-threshold-mv", rc, 0);
+ if (of_property_read_bool(chip->pdev->dev.of_node,
+ "qcom,capacity-learning-on"))
+ chip->batt_aging_mode = FG_AGING_CC;
+ else if (of_property_read_bool(chip->pdev->dev.of_node,
+ "qcom,capacity-estimation-on"))
+ chip->batt_aging_mode = FG_AGING_ESR;
+ else
+ chip->batt_aging_mode = FG_AGING_NONE;
+ if (chip->batt_aging_mode == FG_AGING_CC) {
+ chip->learning_data.feedback_on
+ = of_property_read_bool(chip->pdev->dev.of_node,
+ "qcom,capacity-learning-feedback");
+ }
+ if (fg_debug_mask & FG_AGING)
+ pr_info("battery aging mode: %d\n", chip->batt_aging_mode);
+
+ /* Get the use-otp-profile property */
+ chip->use_otp_profile = of_property_read_bool(chip->pdev->dev.of_node,
+ "qcom,use-otp-profile");
+ chip->hold_soc_while_full
+ = of_property_read_bool(chip->pdev->dev.of_node,
+ "qcom,hold-soc-while-full");
+
+ sense_type = of_property_read_bool(chip->pdev->dev.of_node,
+ "qcom,ext-sense-type");
+ if (rc == 0) {
+ if (fg_sense_type < 0)
+ fg_sense_type = sense_type;
+
+ if (fg_debug_mask & FG_STATUS) {
+ if (fg_sense_type == INTERNAL_CURRENT_SENSE)
+ pr_info("Using internal sense\n");
+ else if (fg_sense_type == EXTERNAL_CURRENT_SENSE)
+ pr_info("Using external sense\n");
+ else
+ pr_info("Using default sense\n");
+ }
+ } else {
+ rc = 0;
+ }
+
+ chip->bad_batt_detection_en = of_property_read_bool(node,
+ "qcom,bad-battery-detection-enable");
+
+ chip->sw_rbias_ctrl = of_property_read_bool(node,
+ "qcom,sw-rbias-control");
+
+ chip->cyc_ctr.en = of_property_read_bool(node,
+ "qcom,cycle-counter-en");
+ if (chip->cyc_ctr.en)
+ chip->cyc_ctr.id = 1;
+
+ chip->esr_pulse_tune_en = of_property_read_bool(node,
+ "qcom,esr-pulse-tuning-en");
+
+ return rc;
+}
+
+static int fg_init_irqs(struct fg_chip *chip)
+{
+ int rc = 0;
+ unsigned int base;
+ struct device_node *child;
+ u8 subtype;
+ struct platform_device *pdev = chip->pdev;
+
+ if (of_get_available_child_count(pdev->dev.of_node) == 0) {
+ pr_err("no child nodes\n");
+ return -ENXIO;
+ }
+
+ for_each_available_child_of_node(pdev->dev.of_node, child) {
+ rc = of_property_read_u32(child, "reg", &base);
+ if (rc < 0) {
+ dev_err(&pdev->dev,
+ "Couldn't find reg in node = %s rc = %d\n",
+ child->full_name, rc);
+ return rc;
+ }
+
+ if ((base == chip->vbat_adc_addr) ||
+ (base == chip->ibat_adc_addr) ||
+ (base == chip->tp_rev_addr))
+ continue;
+
+ rc = fg_read(chip, &subtype,
+ base + REG_OFFSET_PERP_SUBTYPE, 1);
+ if (rc) {
+ pr_err("Peripheral subtype read failed rc=%d\n", rc);
+ return rc;
+ }
+
+ switch (subtype) {
+ case FG_SOC:
+ chip->soc_irq[FULL_SOC].irq = of_irq_get_byname(child,
+ "full-soc");
+ if (chip->soc_irq[FULL_SOC].irq < 0) {
+ pr_err("Unable to get full-soc irq\n");
+ return rc;
+ }
+ chip->soc_irq[EMPTY_SOC].irq = of_irq_get_byname(child,
+ "empty-soc");
+ if (chip->soc_irq[EMPTY_SOC].irq < 0) {
+ pr_err("Unable to get low-soc irq\n");
+ return rc;
+ }
+ chip->soc_irq[DELTA_SOC].irq = of_irq_get_byname(child,
+ "delta-soc");
+ if (chip->soc_irq[DELTA_SOC].irq < 0) {
+ pr_err("Unable to get delta-soc irq\n");
+ return rc;
+ }
+ chip->soc_irq[FIRST_EST_DONE].irq
+ = of_irq_get_byname(child, "first-est-done");
+ if (chip->soc_irq[FIRST_EST_DONE].irq < 0) {
+ pr_err("Unable to get first-est-done irq\n");
+ return rc;
+ }
+
+ rc = devm_request_irq(chip->dev,
+ chip->soc_irq[FULL_SOC].irq,
+ fg_soc_irq_handler, IRQF_TRIGGER_RISING,
+ "full-soc", chip);
+ if (rc < 0) {
+ pr_err("Can't request %d full-soc: %d\n",
+ chip->soc_irq[FULL_SOC].irq, rc);
+ return rc;
+ }
+ rc = devm_request_irq(chip->dev,
+ chip->soc_irq[EMPTY_SOC].irq,
+ fg_empty_soc_irq_handler,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "empty-soc", chip);
+ if (rc < 0) {
+ pr_err("Can't request %d empty-soc: %d\n",
+ chip->soc_irq[EMPTY_SOC].irq, rc);
+ return rc;
+ }
+ rc = devm_request_irq(chip->dev,
+ chip->soc_irq[DELTA_SOC].irq,
+ fg_soc_irq_handler, IRQF_TRIGGER_RISING,
+ "delta-soc", chip);
+ if (rc < 0) {
+ pr_err("Can't request %d delta-soc: %d\n",
+ chip->soc_irq[DELTA_SOC].irq, rc);
+ return rc;
+ }
+ rc = devm_request_irq(chip->dev,
+ chip->soc_irq[FIRST_EST_DONE].irq,
+ fg_first_soc_irq_handler, IRQF_TRIGGER_RISING,
+ "first-est-done", chip);
+ if (rc < 0) {
+ pr_err("Can't request %d delta-soc: %d\n",
+ chip->soc_irq[FIRST_EST_DONE].irq, rc);
+ return rc;
+ }
+
+ enable_irq_wake(chip->soc_irq[DELTA_SOC].irq);
+ enable_irq_wake(chip->soc_irq[FULL_SOC].irq);
+ enable_irq_wake(chip->soc_irq[EMPTY_SOC].irq);
+ break;
+ case FG_MEMIF:
+ chip->mem_irq[FG_MEM_AVAIL].irq
+ = of_irq_get_byname(child, "mem-avail");
+ if (chip->mem_irq[FG_MEM_AVAIL].irq < 0) {
+ pr_err("Unable to get mem-avail irq\n");
+ return rc;
+ }
+ rc = devm_request_irq(chip->dev,
+ chip->mem_irq[FG_MEM_AVAIL].irq,
+ fg_mem_avail_irq_handler,
+ IRQF_TRIGGER_RISING |
+ IRQF_TRIGGER_FALLING,
+ "mem-avail", chip);
+ if (rc < 0) {
+ pr_err("Can't request %d mem-avail: %d\n",
+ chip->mem_irq[FG_MEM_AVAIL].irq, rc);
+ return rc;
+ }
+ break;
+ case FG_BATT:
+ chip->batt_irq[BATT_MISSING].irq
+ = of_irq_get_byname(child, "batt-missing");
+ if (chip->batt_irq[BATT_MISSING].irq < 0) {
+ pr_err("Unable to get batt-missing irq\n");
+ rc = -EINVAL;
+ return rc;
+ }
+ rc = devm_request_threaded_irq(chip->dev,
+ chip->batt_irq[BATT_MISSING].irq,
+ NULL,
+ fg_batt_missing_irq_handler,
+ IRQF_TRIGGER_RISING |
+ IRQF_TRIGGER_FALLING |
+ IRQF_ONESHOT,
+ "batt-missing", chip);
+ if (rc < 0) {
+ pr_err("Can't request %d batt-missing: %d\n",
+ chip->batt_irq[BATT_MISSING].irq, rc);
+ return rc;
+ }
+ chip->batt_irq[VBATT_LOW].irq
+ = of_irq_get_byname(child, "vbatt-low");
+ if (chip->batt_irq[VBATT_LOW].irq < 0) {
+ pr_err("Unable to get vbatt-low irq\n");
+ rc = -EINVAL;
+ return rc;
+ }
+ rc = devm_request_irq(chip->dev,
+ chip->batt_irq[VBATT_LOW].irq,
+ fg_vbatt_low_handler,
+ IRQF_TRIGGER_RISING |
+ IRQF_TRIGGER_FALLING,
+ "vbatt-low", chip);
+ if (rc < 0) {
+ pr_err("Can't request %d vbatt-low: %d\n",
+ chip->batt_irq[VBATT_LOW].irq, rc);
+ return rc;
+ }
+ disable_irq_nosync(chip->batt_irq[VBATT_LOW].irq);
+ chip->vbat_low_irq_enabled = false;
+ break;
+ case FG_ADC:
+ break;
+ default:
+ pr_err("subtype %d\n", subtype);
+ return -EINVAL;
+ }
+ }
+
+ return rc;
+}
+
+static void fg_cleanup(struct fg_chip *chip)
+{
+ cancel_delayed_work_sync(&chip->update_sram_data);
+ cancel_delayed_work_sync(&chip->update_temp_work);
+ cancel_delayed_work_sync(&chip->update_jeita_setting);
+ cancel_delayed_work_sync(&chip->check_empty_work);
+ cancel_delayed_work_sync(&chip->batt_profile_init);
+ alarm_try_to_cancel(&chip->fg_cap_learning_alarm);
+ cancel_work_sync(&chip->rslow_comp_work);
+ cancel_work_sync(&chip->set_resume_soc_work);
+ cancel_work_sync(&chip->fg_cap_learning_work);
+ cancel_work_sync(&chip->dump_sram);
+ cancel_work_sync(&chip->status_change_work);
+ cancel_work_sync(&chip->cycle_count_work);
+ cancel_work_sync(&chip->update_esr_work);
+ cancel_work_sync(&chip->sysfs_restart_work);
+ cancel_work_sync(&chip->gain_comp_work);
+ cancel_work_sync(&chip->init_work);
+ cancel_work_sync(&chip->charge_full_work);
+ cancel_work_sync(&chip->esr_extract_config_work);
+ mutex_destroy(&chip->rslow_comp.lock);
+ mutex_destroy(&chip->rw_lock);
+ mutex_destroy(&chip->cyc_ctr.lock);
+ mutex_destroy(&chip->learning_data.learning_lock);
+ mutex_destroy(&chip->sysfs_restart_lock);
+ wakeup_source_trash(&chip->resume_soc_wakeup_source.source);
+ wakeup_source_trash(&chip->empty_check_wakeup_source.source);
+ wakeup_source_trash(&chip->memif_wakeup_source.source);
+ wakeup_source_trash(&chip->profile_wakeup_source.source);
+ wakeup_source_trash(&chip->update_temp_wakeup_source.source);
+ wakeup_source_trash(&chip->update_sram_wakeup_source.source);
+ wakeup_source_trash(&chip->gain_comp_wakeup_source.source);
+ wakeup_source_trash(&chip->capacity_learning_wakeup_source.source);
+ wakeup_source_trash(&chip->esr_extract_wakeup_source.source);
+}
+
+static int fg_remove(struct platform_device *pdev)
+{
+ struct fg_chip *chip = dev_get_drvdata(&pdev->dev);
+
+ fg_cleanup(chip);
+ dev_set_drvdata(&pdev->dev, NULL);
+ return 0;
+}
+
+static int fg_memif_data_open(struct inode *inode, struct file *file)
+{
+ struct fg_log_buffer *log;
+ struct fg_trans *trans;
+ u8 *data_buf;
+
+ size_t logbufsize = SZ_4K;
+ size_t databufsize = SZ_4K;
+
+ if (!dbgfs_data.chip) {
+ pr_err("Not initialized data\n");
+ return -EINVAL;
+ }
+
+ /* Per file "transaction" data */
+ trans = kzalloc(sizeof(*trans), GFP_KERNEL);
+ if (!trans)
+ return -ENOMEM;
+
+ /* Allocate log buffer */
+ log = kzalloc(logbufsize, GFP_KERNEL);
+
+ if (!log) {
+ kfree(trans);
+ pr_err("Unable to allocate memory for log buffer\n");
+ return -ENOMEM;
+ }
+
+ log->rpos = 0;
+ log->wpos = 0;
+ log->len = logbufsize - sizeof(*log);
+
+ /* Allocate data buffer */
+ data_buf = kzalloc(databufsize, GFP_KERNEL);
+
+ if (!data_buf) {
+ kfree(trans);
+ kfree(log);
+ pr_err("Unable to allocate memory for data buffer\n");
+ return -ENOMEM;
+ }
+
+ trans->log = log;
+ trans->data = data_buf;
+ trans->cnt = dbgfs_data.cnt;
+ trans->addr = dbgfs_data.addr;
+ trans->chip = dbgfs_data.chip;
+ trans->offset = trans->addr;
+
+ file->private_data = trans;
+ return 0;
+}
+
+static int fg_memif_dfs_close(struct inode *inode, struct file *file)
+{
+ struct fg_trans *trans = file->private_data;
+
+ if (trans && trans->log && trans->data) {
+ file->private_data = NULL;
+ kfree(trans->log);
+ kfree(trans->data);
+ kfree(trans);
+ }
+
+ return 0;
+}
+
+/**
+ * print_to_log: format a string and place into the log buffer
+ * @log: The log buffer to place the result into.
+ * @fmt: The format string to use.
+ * @...: The arguments for the format string.
+ *
+ * The return value is the number of characters written to @log buffer
+ * not including the trailing '\0'.
+ */
+static int print_to_log(struct fg_log_buffer *log, const char *fmt, ...)
+{
+ va_list args;
+ int cnt;
+ char *buf = &log->data[log->wpos];
+ size_t size = log->len - log->wpos;
+
+ va_start(args, fmt);
+ cnt = vscnprintf(buf, size, fmt, args);
+ va_end(args);
+
+ log->wpos += cnt;
+ return cnt;
+}
+
+/**
+ * write_next_line_to_log: Writes a single "line" of data into the log buffer
+ * @trans: Pointer to SRAM transaction data.
+ * @offset: SRAM address offset to start reading from.
+ * @pcnt: Pointer to 'cnt' variable. Indicates the number of bytes to read.
+ *
+ * The 'offset' is a 12-bit SRAM address.
+ *
+ * On a successful read, the pcnt is decremented by the number of data
+ * bytes read from the SRAM. When the cnt reaches 0, all requested bytes have
+ * been read.
+ */
+static int
+write_next_line_to_log(struct fg_trans *trans, int offset, size_t *pcnt)
+{
+ int i, j;
+ u8 data[ITEMS_PER_LINE];
+ struct fg_log_buffer *log = trans->log;
+
+ int cnt = 0;
+ int padding = offset % ITEMS_PER_LINE;
+ int items_to_read = min(ARRAY_SIZE(data) - padding, *pcnt);
+ int items_to_log = min(ITEMS_PER_LINE, padding + items_to_read);
+
+ /* Buffer needs enough space for an entire line */
+ if ((log->len - log->wpos) < MAX_LINE_LENGTH)
+ goto done;
+
+ memcpy(data, trans->data + (offset - trans->addr), items_to_read);
+
+ *pcnt -= items_to_read;
+
+ /* Each line starts with the aligned offset (12-bit address) */
+ cnt = print_to_log(log, "%3.3X ", offset & 0xfff);
+ if (cnt == 0)
+ goto done;
+
+ /* If the offset is unaligned, add padding to right justify items */
+ for (i = 0; i < padding; ++i) {
+ cnt = print_to_log(log, "-- ");
+ if (cnt == 0)
+ goto done;
+ }
+
+ /* Log the data items */
+ for (j = 0; i < items_to_log; ++i, ++j) {
+ cnt = print_to_log(log, "%2.2X ", data[j]);
+ if (cnt == 0)
+ goto done;
+ }
+
+ /* If the last character was a space, then replace it with a newline */
+ if (log->wpos > 0 && log->data[log->wpos - 1] == ' ')
+ log->data[log->wpos - 1] = '\n';
+
+done:
+ return cnt;
+}
+
+/**
+ * get_log_data - reads data from SRAM and saves to the log buffer
+ * @trans: Pointer to SRAM transaction data.
+ *
+ * Returns the number of "items" read or SPMI error code for read failures.
+ */
+static int get_log_data(struct fg_trans *trans)
+{
+ int cnt, rc;
+ int last_cnt;
+ int items_read;
+ int total_items_read = 0;
+ u32 offset = trans->offset;
+ size_t item_cnt = trans->cnt;
+ struct fg_log_buffer *log = trans->log;
+
+ if (item_cnt == 0)
+ return 0;
+
+ if (item_cnt > SZ_4K) {
+ pr_err("Reading too many bytes\n");
+ return -EINVAL;
+ }
+
+ rc = fg_mem_read(trans->chip, trans->data,
+ trans->addr, trans->cnt, 0, 0);
+ if (rc) {
+ pr_err("dump failed: rc = %d\n", rc);
+ return rc;
+ }
+ /* Reset the log buffer 'pointers' */
+ log->wpos = log->rpos = 0;
+
+ /* Keep reading data until the log is full */
+ do {
+ last_cnt = item_cnt;
+ cnt = write_next_line_to_log(trans, offset, &item_cnt);
+ items_read = last_cnt - item_cnt;
+ offset += items_read;
+ total_items_read += items_read;
+ } while (cnt && item_cnt > 0);
+
+ /* Adjust the transaction offset and count */
+ trans->cnt = item_cnt;
+ trans->offset += total_items_read;
+
+ return total_items_read;
+}
+
+/**
+ * fg_memif_dfs_reg_read: reads value(s) from SRAM and fills user's buffer a
+ * byte array (coded as string)
+ * @file: file pointer
+ * @buf: where to put the result
+ * @count: maximum space available in @buf
+ * @ppos: starting position
+ * @return number of user bytes read, or negative error value
+ */
+static ssize_t fg_memif_dfs_reg_read(struct file *file, char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ struct fg_trans *trans = file->private_data;
+ struct fg_log_buffer *log = trans->log;
+ size_t ret;
+ size_t len;
+
+ /* Is the the log buffer empty */
+ if (log->rpos >= log->wpos) {
+ if (get_log_data(trans) <= 0)
+ return 0;
+ }
+
+ len = min(count, log->wpos - log->rpos);
+
+ ret = copy_to_user(buf, &log->data[log->rpos], len);
+ if (ret == len) {
+ pr_err("error copy sram register values to user\n");
+ return -EFAULT;
+ }
+
+ /* 'ret' is the number of bytes not copied */
+ len -= ret;
+
+ *ppos += len;
+ log->rpos += len;
+ return len;
+}
+
+/**
+ * fg_memif_dfs_reg_write: write user's byte array (coded as string) to SRAM.
+ * @file: file pointer
+ * @buf: user data to be written.
+ * @count: maximum space available in @buf
+ * @ppos: starting position
+ * @return number of user byte written, or negative error value
+ */
+static ssize_t fg_memif_dfs_reg_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ int bytes_read;
+ int data;
+ int pos = 0;
+ int cnt = 0;
+ u8 *values;
+ size_t ret = 0;
+
+ struct fg_trans *trans = file->private_data;
+ u32 offset = trans->offset;
+
+ /* Make a copy of the user data */
+ char *kbuf = kmalloc(count + 1, GFP_KERNEL);
+
+ if (!kbuf)
+ return -ENOMEM;
+
+ ret = copy_from_user(kbuf, buf, count);
+ if (ret == count) {
+ pr_err("failed to copy data from user\n");
+ ret = -EFAULT;
+ goto free_buf;
+ }
+
+ count -= ret;
+ *ppos += count;
+ kbuf[count] = '\0';
+
+ /* Override the text buffer with the raw data */
+ values = kbuf;
+
+ /* Parse the data in the buffer. It should be a string of numbers */
+ while ((pos < count) &&
+ sscanf(kbuf + pos, "%i%n", &data, &bytes_read) == 1) {
+ /*
+ * We shouldn't be receiving a string of characters that
+ * exceeds a size of 5 to keep this functionally correct.
+ * Also, we should make sure that pos never gets overflowed
+ * beyond the limit.
+ */
+ if (bytes_read > 5 || bytes_read > INT_MAX - pos) {
+ cnt = 0;
+ ret = -EINVAL;
+ break;
+ }
+ pos += bytes_read;
+ values[cnt++] = data & 0xff;
+ }
+
+ if (!cnt)
+ goto free_buf;
+
+ pr_info("address %x, count %d\n", offset, cnt);
+ /* Perform the write(s) */
+
+ ret = fg_mem_write(trans->chip, values, offset,
+ cnt, 0, 0);
+ if (ret) {
+ pr_err("SPMI write failed, err = %zu\n", ret);
+ } else {
+ ret = count;
+ trans->offset += cnt > 4 ? 4 : cnt;
+ }
+
+free_buf:
+ kfree(kbuf);
+ return ret;
+}
+
+static const struct file_operations fg_memif_dfs_reg_fops = {
+ .open = fg_memif_data_open,
+ .release = fg_memif_dfs_close,
+ .read = fg_memif_dfs_reg_read,
+ .write = fg_memif_dfs_reg_write,
+};
+
+/**
+ * fg_dfs_create_fs: create debugfs file system.
+ * @return pointer to root directory or NULL if failed to create fs
+ */
+static struct dentry *fg_dfs_create_fs(void)
+{
+ struct dentry *root, *file;
+
+ pr_debug("Creating FG_MEM debugfs file-system\n");
+ root = debugfs_create_dir(DFS_ROOT_NAME, NULL);
+ if (IS_ERR_OR_NULL(root)) {
+ pr_err("Error creating top level directory err:%ld",
+ (long)root);
+ if (PTR_ERR(root) == -ENODEV)
+ pr_err("debugfs is not enabled in the kernel");
+ return NULL;
+ }
+
+ dbgfs_data.help_msg.size = strlen(dbgfs_data.help_msg.data);
+
+ file = debugfs_create_blob("help", 0444, root, &dbgfs_data.help_msg);
+ if (!file) {
+ pr_err("error creating help entry\n");
+ goto err_remove_fs;
+ }
+ return root;
+
+err_remove_fs:
+ debugfs_remove_recursive(root);
+ return NULL;
+}
+
+/**
+ * fg_dfs_get_root: return a pointer to FG debugfs root directory.
+ * @return a pointer to the existing directory, or if no root
+ * directory exists then create one. Directory is created with file that
+ * configures SRAM transaction, namely: address, and count.
+ * @returns valid pointer on success or NULL
+ */
+struct dentry *fg_dfs_get_root(void)
+{
+ if (dbgfs_data.root)
+ return dbgfs_data.root;
+
+ if (mutex_lock_interruptible(&dbgfs_data.lock) < 0)
+ return NULL;
+ /* critical section */
+ if (!dbgfs_data.root) { /* double checking idiom */
+ dbgfs_data.root = fg_dfs_create_fs();
+ }
+ mutex_unlock(&dbgfs_data.lock);
+ return dbgfs_data.root;
+}
+
+/*
+ * fg_dfs_create: adds new fg_mem if debugfs entry
+ * @return zero on success
+ */
+int fg_dfs_create(struct fg_chip *chip)
+{
+ struct dentry *root;
+ struct dentry *file;
+
+ root = fg_dfs_get_root();
+ if (!root)
+ return -ENOENT;
+
+ dbgfs_data.chip = chip;
+
+ file = debugfs_create_u32("count", DFS_MODE, root, &(dbgfs_data.cnt));
+ if (!file) {
+ pr_err("error creating 'count' entry\n");
+ goto err_remove_fs;
+ }
+
+ file = debugfs_create_x32("address", DFS_MODE,
+ root, &(dbgfs_data.addr));
+ if (!file) {
+ pr_err("error creating 'address' entry\n");
+ goto err_remove_fs;
+ }
+
+ file = debugfs_create_file("data", DFS_MODE, root, &dbgfs_data,
+ &fg_memif_dfs_reg_fops);
+ if (!file) {
+ pr_err("error creating 'data' entry\n");
+ goto err_remove_fs;
+ }
+
+ return 0;
+
+err_remove_fs:
+ debugfs_remove_recursive(root);
+ return -ENOMEM;
+}
+
+#define EXTERNAL_SENSE_OFFSET_REG 0x41C
+#define EXT_OFFSET_TRIM_REG 0xF8
+#define SEC_ACCESS_REG 0xD0
+#define SEC_ACCESS_UNLOCK 0xA5
+#define BCL_TRIM_REV_FIXED 12
+static int bcl_trim_workaround(struct fg_chip *chip)
+{
+ u8 reg, rc;
+
+ if (chip->tp_rev_addr == 0)
+ return 0;
+
+ rc = fg_read(chip, ®, chip->tp_rev_addr, 1);
+ if (rc) {
+ pr_err("Failed to read tp reg, rc = %d\n", rc);
+ return rc;
+ }
+ if (reg >= BCL_TRIM_REV_FIXED) {
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("workaround not applied, tp_rev = %d\n", reg);
+ return 0;
+ }
+
+ rc = fg_mem_read(chip, ®, EXTERNAL_SENSE_OFFSET_REG, 1, 2, 0);
+ if (rc) {
+ pr_err("Failed to read ext sense offset trim, rc = %d\n", rc);
+ return rc;
+ }
+ rc = fg_masked_write(chip, chip->soc_base + SEC_ACCESS_REG,
+ SEC_ACCESS_UNLOCK, SEC_ACCESS_UNLOCK, 1);
+
+ rc |= fg_masked_write(chip, chip->soc_base + EXT_OFFSET_TRIM_REG,
+ 0xFF, reg, 1);
+ if (rc) {
+ pr_err("Failed to write ext sense offset trim, rc = %d\n", rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+#define FG_ALG_SYSCTL_1 0x4B0
+#define SOC_CNFG 0x450
+#define SOC_DELTA_OFFSET 3
+#define DELTA_SOC_PERCENT 1
+#define I_TERM_QUAL_BIT BIT(1)
+#define PATCH_NEG_CURRENT_BIT BIT(3)
+#define KI_COEFF_PRED_FULL_ADDR 0x408
+#define KI_COEFF_PRED_FULL_4_0_MSB 0x88
+#define KI_COEFF_PRED_FULL_4_0_LSB 0x00
+#define TEMP_FRAC_SHIFT_REG 0x4A4
+#define FG_ADC_CONFIG_REG 0x4B8
+#define FG_BCL_CONFIG_OFFSET 0x3
+#define BCL_FORCED_HPM_IN_CHARGE BIT(2)
+static int fg_common_hw_init(struct fg_chip *chip)
+{
+ int rc;
+ int resume_soc_raw;
+ u8 val;
+
+ update_iterm(chip);
+ update_cutoff_voltage(chip);
+ update_irq_volt_empty(chip);
+ update_bcl_thresholds(chip);
+
+ resume_soc_raw = settings[FG_MEM_RESUME_SOC].value;
+ if (resume_soc_raw > 0) {
+ rc = fg_set_resume_soc(chip, resume_soc_raw);
+ if (rc) {
+ pr_err("Couldn't set resume SOC for FG\n");
+ return rc;
+ }
+ } else {
+ pr_info("FG auto recharge threshold not specified in DT\n");
+ }
+
+ if (fg_sense_type >= 0) {
+ rc = set_prop_sense_type(chip, fg_sense_type);
+ if (rc) {
+ pr_err("failed to config sense type %d rc=%d\n",
+ fg_sense_type, rc);
+ return rc;
+ }
+ }
+
+ rc = fg_mem_masked_write(chip, settings[FG_MEM_DELTA_SOC].address, 0xFF,
+ soc_to_setpoint(settings[FG_MEM_DELTA_SOC].value),
+ settings[FG_MEM_DELTA_SOC].offset);
+ if (rc) {
+ pr_err("failed to write delta soc rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = fg_mem_masked_write(chip, settings[FG_MEM_BATT_LOW].address, 0xFF,
+ batt_to_setpoint_8b(settings[FG_MEM_BATT_LOW].value),
+ settings[FG_MEM_BATT_LOW].offset);
+ if (rc) {
+ pr_err("failed to write Vbatt_low rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = fg_mem_masked_write(chip, settings[FG_MEM_THERM_DELAY].address,
+ THERM_DELAY_MASK,
+ therm_delay_to_setpoint(settings[FG_MEM_THERM_DELAY].value),
+ settings[FG_MEM_THERM_DELAY].offset);
+ if (rc) {
+ pr_err("failed to write therm_delay rc=%d\n", rc);
+ return rc;
+ }
+
+ if (chip->use_thermal_coefficients) {
+ fg_mem_write(chip, chip->thermal_coefficients,
+ THERMAL_COEFF_ADDR, THERMAL_COEFF_N_BYTES,
+ THERMAL_COEFF_OFFSET, 0);
+ }
+
+ if (!chip->sw_rbias_ctrl) {
+ rc = fg_mem_masked_write(chip, EXTERNAL_SENSE_SELECT,
+ BATT_TEMP_CNTRL_MASK,
+ TEMP_SENSE_ALWAYS_BIT,
+ BATT_TEMP_OFFSET);
+ if (rc) {
+ pr_err("failed to write BATT_TEMP_OFFSET rc=%d\n", rc);
+ return rc;
+ }
+ }
+
+ /* Read the cycle counter back from FG SRAM */
+ if (chip->cyc_ctr.en)
+ restore_cycle_counter(chip);
+
+ if (chip->esr_pulse_tune_en) {
+ rc = fg_mem_read(chip, &val, SYS_CFG_1_REG, 1, SYS_CFG_1_OFFSET,
+ 0);
+ if (rc) {
+ pr_err("unable to read sys_cfg_1: %d\n", rc);
+ return rc;
+ }
+
+ if (!(val & ENABLE_ESR_PULSE_VAL))
+ chip->esr_extract_disabled = true;
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("ESR extract is %sabled\n",
+ chip->esr_extract_disabled ? "dis" : "en");
+
+ rc = fg_mem_read(chip, &val, CBITS_INPUT_FILTER_REG, 1,
+ CBITS_RMEAS1_OFFSET, 0);
+ if (rc) {
+ pr_err("unable to read cbits_input_filter_reg: %d\n",
+ rc);
+ return rc;
+ }
+
+ if (val & (IMPTR_FAST_TIME_SHIFT | IMPTR_LONG_TIME_SHIFT))
+ chip->imptr_pulse_slow_en = true;
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("imptr_pulse_slow is %sabled\n",
+ chip->imptr_pulse_slow_en ? "en" : "dis");
+
+ rc = fg_mem_read(chip, &val, RSLOW_CFG_REG, 1, RSLOW_CFG_OFFSET,
+ 0);
+ if (rc) {
+ pr_err("unable to read rslow cfg: %d\n", rc);
+ return rc;
+ }
+
+ if (val & RSLOW_CFG_ON_VAL)
+ chip->rslow_comp.active = true;
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("rslow_comp active is %sabled\n",
+ chip->rslow_comp.active ? "en" : "dis");
+ }
+
+ return 0;
+}
+
+static int fg_8994_hw_init(struct fg_chip *chip)
+{
+ int rc = 0;
+ u8 data[4];
+ u64 esr_value;
+
+ rc = fg_mem_masked_write(chip, EXTERNAL_SENSE_SELECT,
+ PATCH_NEG_CURRENT_BIT,
+ PATCH_NEG_CURRENT_BIT,
+ EXTERNAL_SENSE_OFFSET);
+ if (rc) {
+ pr_err("failed to write patch current bit rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = bcl_trim_workaround(chip);
+ if (rc) {
+ pr_err("failed to redo bcl trim rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = fg_mem_masked_write(chip, FG_ADC_CONFIG_REG,
+ BCL_FORCED_HPM_IN_CHARGE,
+ BCL_FORCED_HPM_IN_CHARGE,
+ FG_BCL_CONFIG_OFFSET);
+ if (rc) {
+ pr_err("failed to force hpm in charge rc=%d\n", rc);
+ return rc;
+ }
+
+ fg_mem_masked_write(chip, FG_ALG_SYSCTL_1, I_TERM_QUAL_BIT, 0, 0);
+
+ data[0] = 0xA2;
+ data[1] = 0x12;
+
+ rc = fg_mem_write(chip, data, TEMP_FRAC_SHIFT_REG, 2, 2, 0);
+ if (rc) {
+ pr_err("failed to write temp ocv constants rc=%d\n", rc);
+ return rc;
+ }
+
+ data[0] = KI_COEFF_PRED_FULL_4_0_LSB;
+ data[1] = KI_COEFF_PRED_FULL_4_0_MSB;
+ fg_mem_write(chip, data, KI_COEFF_PRED_FULL_ADDR, 2, 2, 0);
+
+ esr_value = ESR_DEFAULT_VALUE;
+ rc = fg_mem_write(chip, (u8 *)&esr_value, MAXRSCHANGE_REG, 8,
+ ESR_VALUE_OFFSET, 0);
+ if (rc)
+ pr_err("failed to write default ESR value rc=%d\n", rc);
+ else
+ pr_debug("set default value to esr filter\n");
+
+ return 0;
+}
+
+#define FG_USBID_CONFIG_OFFSET 0x2
+#define DISABLE_USBID_DETECT_BIT BIT(0)
+static int fg_8996_hw_init(struct fg_chip *chip)
+{
+ int rc;
+
+ rc = fg_mem_masked_write(chip, FG_ADC_CONFIG_REG,
+ BCL_FORCED_HPM_IN_CHARGE,
+ BCL_FORCED_HPM_IN_CHARGE,
+ FG_BCL_CONFIG_OFFSET);
+ if (rc) {
+ pr_err("failed to force hpm in charge rc=%d\n", rc);
+ return rc;
+ }
+
+ /* enable usbid conversions for PMi8996 V1.0 */
+ if (chip->pmic_revision[REVID_DIG_MAJOR] == 1
+ && chip->pmic_revision[REVID_ANA_MAJOR] == 0) {
+ rc = fg_mem_masked_write(chip, FG_ADC_CONFIG_REG,
+ DISABLE_USBID_DETECT_BIT,
+ 0, FG_USBID_CONFIG_OFFSET);
+ if (rc) {
+ pr_err("failed to enable usbid conversions: %d\n", rc);
+ return rc;
+ }
+ }
+
+ return rc;
+}
+
+static int fg_8950_hw_init(struct fg_chip *chip)
+{
+ int rc;
+
+ rc = fg_mem_masked_write(chip, FG_ADC_CONFIG_REG,
+ BCL_FORCED_HPM_IN_CHARGE,
+ BCL_FORCED_HPM_IN_CHARGE,
+ FG_BCL_CONFIG_OFFSET);
+ if (rc)
+ pr_err("failed to force hpm in charge rc=%d\n", rc);
+
+ return rc;
+}
+
+static int fg_hw_init(struct fg_chip *chip)
+{
+ int rc = 0;
+
+ rc = fg_common_hw_init(chip);
+ if (rc) {
+ pr_err("Unable to initialize FG HW rc=%d\n", rc);
+ return rc;
+ }
+
+ /* add PMIC specific hw init */
+ switch (chip->pmic_subtype) {
+ case PMI8994:
+ rc = fg_8994_hw_init(chip);
+ chip->wa_flag |= PULSE_REQUEST_WA;
+ break;
+ case PMI8996:
+ rc = fg_8996_hw_init(chip);
+ /* Setup workaround flag based on PMIC type */
+ if (fg_sense_type == INTERNAL_CURRENT_SENSE)
+ chip->wa_flag |= IADC_GAIN_COMP_WA;
+ if (chip->pmic_revision[REVID_DIG_MAJOR] > 1)
+ chip->wa_flag |= USE_CC_SOC_REG;
+
+ break;
+ case PMI8950:
+ case PMI8937:
+ rc = fg_8950_hw_init(chip);
+ /* Setup workaround flag based on PMIC type */
+ chip->wa_flag |= BCL_HI_POWER_FOR_CHGLED_WA;
+ if (fg_sense_type == INTERNAL_CURRENT_SENSE)
+ chip->wa_flag |= IADC_GAIN_COMP_WA;
+ if (chip->pmic_revision[REVID_DIG_MAJOR] > 1)
+ chip->wa_flag |= USE_CC_SOC_REG;
+
+ break;
+ }
+ if (rc)
+ pr_err("Unable to initialize PMIC specific FG HW rc=%d\n", rc);
+
+ pr_debug("wa_flag=0x%x\n", chip->wa_flag);
+
+ return rc;
+}
+
+#define DIG_MINOR 0x0
+#define DIG_MAJOR 0x1
+#define ANA_MINOR 0x2
+#define ANA_MAJOR 0x3
+#define IACS_INTR_SRC_SLCT BIT(3)
+static int fg_setup_memif_offset(struct fg_chip *chip)
+{
+ int rc;
+
+ rc = fg_read(chip, chip->revision, chip->mem_base + DIG_MINOR, 4);
+ if (rc) {
+ pr_err("Unable to read FG revision rc=%d\n", rc);
+ return rc;
+ }
+
+ switch (chip->revision[DIG_MAJOR]) {
+ case DIG_REV_1:
+ case DIG_REV_2:
+ chip->offset = offset[0].address;
+ break;
+ case DIG_REV_3:
+ chip->offset = offset[1].address;
+ chip->ima_supported = true;
+ break;
+ default:
+ pr_err("Digital Major rev=%d not supported\n",
+ chip->revision[DIG_MAJOR]);
+ return -EINVAL;
+ }
+
+ if (chip->ima_supported) {
+ /*
+ * Change the FG_MEM_INT interrupt to track IACS_READY
+ * condition instead of end-of-transaction. This makes sure
+ * that the next transaction starts only after the hw is ready.
+ */
+ rc = fg_masked_write(chip,
+ chip->mem_base + MEM_INTF_IMA_CFG, IACS_INTR_SRC_SLCT,
+ IACS_INTR_SRC_SLCT, 1);
+ if (rc) {
+ pr_err("failed to configure interrupt source %d\n", rc);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int fg_detect_pmic_type(struct fg_chip *chip)
+{
+ struct pmic_revid_data *pmic_rev_id;
+ struct device_node *revid_dev_node;
+
+ revid_dev_node = of_parse_phandle(chip->pdev->dev.of_node,
+ "qcom,pmic-revid", 0);
+ if (!revid_dev_node) {
+ pr_err("Missing qcom,pmic-revid property - driver failed\n");
+ return -EINVAL;
+ }
+
+ pmic_rev_id = get_revid_data(revid_dev_node);
+ if (IS_ERR_OR_NULL(pmic_rev_id)) {
+ pr_err("Unable to get pmic_revid rc=%ld\n",
+ PTR_ERR(pmic_rev_id));
+ /*
+ * the revid peripheral must be registered, any failure
+ * here only indicates that the rev-id module has not
+ * probed yet.
+ */
+ return -EPROBE_DEFER;
+ }
+
+ switch (pmic_rev_id->pmic_subtype) {
+ case PMI8994:
+ case PMI8950:
+ case PMI8937:
+ case PMI8996:
+ chip->pmic_subtype = pmic_rev_id->pmic_subtype;
+ chip->pmic_revision[REVID_RESERVED] = pmic_rev_id->rev1;
+ chip->pmic_revision[REVID_VARIANT] = pmic_rev_id->rev2;
+ chip->pmic_revision[REVID_ANA_MAJOR] = pmic_rev_id->rev3;
+ chip->pmic_revision[REVID_DIG_MAJOR] = pmic_rev_id->rev4;
+ break;
+ default:
+ pr_err("PMIC subtype %d not supported\n",
+ pmic_rev_id->pmic_subtype);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#define INIT_JEITA_DELAY_MS 1000
+
+static void delayed_init_work(struct work_struct *work)
+{
+ u8 reg[2];
+ int rc;
+ struct fg_chip *chip = container_of(work,
+ struct fg_chip,
+ init_work);
+
+ /* hold memory access until initialization finishes */
+ fg_mem_lock(chip);
+
+ rc = fg_hw_init(chip);
+ if (rc) {
+ pr_err("failed to hw init rc = %d\n", rc);
+ fg_mem_release(chip);
+ fg_cleanup(chip);
+ return;
+ }
+ /* release memory access before update_sram_data is called */
+ fg_mem_release(chip);
+
+ schedule_delayed_work(
+ &chip->update_jeita_setting,
+ msecs_to_jiffies(INIT_JEITA_DELAY_MS));
+
+ if (chip->last_sram_update_time == 0)
+ update_sram_data_work(&chip->update_sram_data.work);
+
+ if (chip->last_temp_update_time == 0)
+ update_temp_data(&chip->update_temp_work.work);
+
+ if (!chip->use_otp_profile)
+ schedule_delayed_work(&chip->batt_profile_init, 0);
+
+ if (chip->wa_flag & IADC_GAIN_COMP_WA) {
+ /* read default gain config */
+ rc = fg_mem_read(chip, reg, K_VCOR_REG, 2, DEF_GAIN_OFFSET, 0);
+ if (rc) {
+ pr_err("Failed to read default gain rc=%d\n", rc);
+ goto done;
+ }
+
+ if (reg[1] || reg[0]) {
+ /*
+ * Default gain register has valid value:
+ * - write to gain register.
+ */
+ rc = fg_mem_write(chip, reg, GAIN_REG, 2,
+ GAIN_OFFSET, 0);
+ if (rc) {
+ pr_err("Failed to write gain rc=%d\n", rc);
+ goto done;
+ }
+ } else {
+ /*
+ * Default gain register is invalid:
+ * - read gain register for default gain value
+ * - write to default gain register.
+ */
+ rc = fg_mem_read(chip, reg, GAIN_REG, 2,
+ GAIN_OFFSET, 0);
+ if (rc) {
+ pr_err("Failed to read gain rc=%d\n", rc);
+ goto done;
+ }
+ rc = fg_mem_write(chip, reg, K_VCOR_REG, 2,
+ DEF_GAIN_OFFSET, 0);
+ if (rc) {
+ pr_err("Failed to write default gain rc=%d\n",
+ rc);
+ goto done;
+ }
+ }
+
+ chip->iadc_comp_data.dfl_gain_reg[0] = reg[0];
+ chip->iadc_comp_data.dfl_gain_reg[1] = reg[1];
+ chip->iadc_comp_data.dfl_gain = half_float(reg);
+ chip->input_present = is_input_present(chip);
+ chip->otg_present = is_otg_present(chip);
+ chip->init_done = true;
+
+ pr_debug("IADC gain initial config reg_val 0x%x%x gain %lld\n",
+ reg[1], reg[0], chip->iadc_comp_data.dfl_gain);
+ }
+
+ pr_debug("FG: HW_init success\n");
+
+ return;
+done:
+ fg_cleanup(chip);
+}
+
+static int fg_probe(struct platform_device *pdev)
+{
+ struct device *dev = &(pdev->dev);
+ struct fg_chip *chip;
+ struct device_node *child;
+ unsigned int base;
+ u8 subtype, reg;
+ int rc = 0;
+ struct power_supply_config bms_psy_cfg;
+
+ if (!pdev) {
+ pr_err("no valid spmi pointer\n");
+ return -ENODEV;
+ }
+
+ if (!pdev->dev.of_node) {
+ pr_err("device node missing\n");
+ return -ENODEV;
+ }
+
+ chip = devm_kzalloc(dev, sizeof(struct fg_chip), GFP_KERNEL);
+ if (chip == NULL)
+ return -ENOMEM;
+
+ chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!chip->regmap) {
+ dev_err(&pdev->dev, "Couldn't get parent's regmap\n");
+ return -EINVAL;
+ }
+
+ chip->pdev = pdev;
+ chip->dev = &(pdev->dev);
+
+ wakeup_source_init(&chip->empty_check_wakeup_source.source,
+ "qpnp_fg_empty_check");
+ wakeup_source_init(&chip->memif_wakeup_source.source,
+ "qpnp_fg_memaccess");
+ wakeup_source_init(&chip->profile_wakeup_source.source,
+ "qpnp_fg_profile");
+ wakeup_source_init(&chip->update_temp_wakeup_source.source,
+ "qpnp_fg_update_temp");
+ wakeup_source_init(&chip->update_sram_wakeup_source.source,
+ "qpnp_fg_update_sram");
+ wakeup_source_init(&chip->resume_soc_wakeup_source.source,
+ "qpnp_fg_set_resume_soc");
+ wakeup_source_init(&chip->gain_comp_wakeup_source.source,
+ "qpnp_fg_gain_comp");
+ wakeup_source_init(&chip->capacity_learning_wakeup_source.source,
+ "qpnp_fg_cap_learning");
+ wakeup_source_init(&chip->esr_extract_wakeup_source.source,
+ "qpnp_fg_esr_extract");
+ mutex_init(&chip->rw_lock);
+ mutex_init(&chip->cyc_ctr.lock);
+ mutex_init(&chip->learning_data.learning_lock);
+ mutex_init(&chip->rslow_comp.lock);
+ mutex_init(&chip->sysfs_restart_lock);
+ INIT_DELAYED_WORK(&chip->update_jeita_setting, update_jeita_setting);
+ INIT_DELAYED_WORK(&chip->update_sram_data, update_sram_data_work);
+ INIT_DELAYED_WORK(&chip->update_temp_work, update_temp_data);
+ INIT_DELAYED_WORK(&chip->check_empty_work, check_empty_work);
+ INIT_DELAYED_WORK(&chip->batt_profile_init, batt_profile_init);
+ INIT_WORK(&chip->rslow_comp_work, rslow_comp_work);
+ INIT_WORK(&chip->fg_cap_learning_work, fg_cap_learning_work);
+ INIT_WORK(&chip->dump_sram, dump_sram);
+ INIT_WORK(&chip->status_change_work, status_change_work);
+ INIT_WORK(&chip->cycle_count_work, update_cycle_count);
+ INIT_WORK(&chip->battery_age_work, battery_age_work);
+ INIT_WORK(&chip->update_esr_work, update_esr_value);
+ INIT_WORK(&chip->set_resume_soc_work, set_resume_soc_work);
+ INIT_WORK(&chip->sysfs_restart_work, sysfs_restart_work);
+ INIT_WORK(&chip->init_work, delayed_init_work);
+ INIT_WORK(&chip->charge_full_work, charge_full_work);
+ INIT_WORK(&chip->gain_comp_work, iadc_gain_comp_work);
+ INIT_WORK(&chip->bcl_hi_power_work, bcl_hi_power_work);
+ INIT_WORK(&chip->esr_extract_config_work, esr_extract_config_work);
+ alarm_init(&chip->fg_cap_learning_alarm, ALARM_BOOTTIME,
+ fg_cap_learning_alarm_cb);
+ init_completion(&chip->sram_access_granted);
+ init_completion(&chip->sram_access_revoked);
+ complete_all(&chip->sram_access_revoked);
+ init_completion(&chip->batt_id_avail);
+ init_completion(&chip->first_soc_done);
+ dev_set_drvdata(&pdev->dev, chip);
+
+ if (of_get_available_child_count(pdev->dev.of_node) == 0) {
+ pr_err("no child nodes\n");
+ rc = -ENXIO;
+ goto of_init_fail;
+ }
+
+ for_each_available_child_of_node(pdev->dev.of_node, child) {
+ rc = of_property_read_u32(child, "reg", &base);
+ if (rc < 0) {
+ dev_err(&pdev->dev,
+ "Couldn't find reg in node = %s rc = %d\n",
+ child->full_name, rc);
+ goto of_init_fail;
+ }
+
+ if (strcmp("qcom,fg-adc-vbat", child->name) == 0) {
+ chip->vbat_adc_addr = base;
+ continue;
+ } else if (strcmp("qcom,fg-adc-ibat", child->name) == 0) {
+ chip->ibat_adc_addr = base;
+ continue;
+ } else if (strcmp("qcom,revid-tp-rev", child->name) == 0) {
+ chip->tp_rev_addr = base;
+ continue;
+ }
+
+ rc = fg_read(chip, &subtype,
+ base + REG_OFFSET_PERP_SUBTYPE, 1);
+ if (rc) {
+ pr_err("Peripheral subtype read failed rc=%d\n", rc);
+ goto of_init_fail;
+ }
+
+ switch (subtype) {
+ case FG_SOC:
+ chip->soc_base = base;
+ break;
+ case FG_MEMIF:
+ chip->mem_base = base;
+ break;
+ case FG_BATT:
+ chip->batt_base = base;
+ break;
+ default:
+ pr_err("Invalid peripheral subtype=0x%x\n", subtype);
+ rc = -EINVAL;
+ }
+ }
+
+ rc = fg_detect_pmic_type(chip);
+ if (rc) {
+ pr_err("Unable to detect PMIC type rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = fg_setup_memif_offset(chip);
+ if (rc) {
+ pr_err("Unable to setup mem_if offsets rc=%d\n", rc);
+ goto of_init_fail;
+ }
+
+ rc = fg_of_init(chip);
+ if (rc) {
+ pr_err("failed to parse devicetree rc%d\n", rc);
+ goto of_init_fail;
+ }
+
+ if (chip->jeita_hysteresis_support) {
+ rc = fg_init_batt_temp_state(chip);
+ if (rc) {
+ pr_err("failed to get battery status rc%d\n", rc);
+ goto of_init_fail;
+ }
+ }
+
+ /* check if the first estimate is already finished at this time */
+ if (is_first_est_done(chip))
+ complete_all(&chip->first_soc_done);
+
+ reg = 0xFF;
+ rc = fg_write(chip, ®, INT_EN_CLR(chip->mem_base), 1);
+ if (rc) {
+ pr_err("failed to clear interrupts %d\n", rc);
+ goto of_init_fail;
+ }
+
+ rc = fg_init_irqs(chip);
+ if (rc) {
+ pr_err("failed to request interrupts %d\n", rc);
+ goto cancel_work;
+ }
+
+ chip->batt_type = default_batt_type;
+
+ chip->bms_psy_d.name = "bms";
+ chip->bms_psy_d.type = POWER_SUPPLY_TYPE_BMS;
+ chip->bms_psy_d.properties = fg_power_props;
+ chip->bms_psy_d.num_properties = ARRAY_SIZE(fg_power_props);
+ chip->bms_psy_d.get_property = fg_power_get_property;
+ chip->bms_psy_d.set_property = fg_power_set_property;
+ chip->bms_psy_d.external_power_changed = fg_external_power_changed;
+ chip->bms_psy_d.property_is_writeable = fg_property_is_writeable;
+
+ bms_psy_cfg.drv_data = chip;
+ bms_psy_cfg.supplied_to = fg_supplicants;
+ bms_psy_cfg.num_supplicants = ARRAY_SIZE(fg_supplicants);
+ bms_psy_cfg.of_node = NULL;
+ chip->bms_psy = devm_power_supply_register(chip->dev,
+ &chip->bms_psy_d,
+ &bms_psy_cfg);
+ if (IS_ERR(chip->bms_psy)) {
+ pr_err("batt failed to register rc = %ld\n",
+ PTR_ERR(chip->bms_psy));
+ goto of_init_fail;
+ }
+ chip->power_supply_registered = true;
+ /*
+ * Just initialize the batt_psy_name here. Power supply
+ * will be obtained later.
+ */
+ chip->batt_psy_name = "battery";
+
+ if (chip->mem_base) {
+ rc = fg_dfs_create(chip);
+ if (rc < 0) {
+ pr_err("failed to create debugfs rc = %d\n", rc);
+ goto cancel_work;
+ }
+ }
+
+ schedule_work(&chip->init_work);
+
+ pr_info("FG Probe success - FG Revision DIG:%d.%d ANA:%d.%d PMIC subtype=%d\n",
+ chip->revision[DIG_MAJOR], chip->revision[DIG_MINOR],
+ chip->revision[ANA_MAJOR], chip->revision[ANA_MINOR],
+ chip->pmic_subtype);
+
+ return rc;
+
+cancel_work:
+ cancel_delayed_work_sync(&chip->update_jeita_setting);
+ cancel_delayed_work_sync(&chip->update_sram_data);
+ cancel_delayed_work_sync(&chip->update_temp_work);
+ cancel_delayed_work_sync(&chip->check_empty_work);
+ cancel_delayed_work_sync(&chip->batt_profile_init);
+ alarm_try_to_cancel(&chip->fg_cap_learning_alarm);
+ cancel_work_sync(&chip->set_resume_soc_work);
+ cancel_work_sync(&chip->fg_cap_learning_work);
+ cancel_work_sync(&chip->dump_sram);
+ cancel_work_sync(&chip->status_change_work);
+ cancel_work_sync(&chip->cycle_count_work);
+ cancel_work_sync(&chip->update_esr_work);
+ cancel_work_sync(&chip->rslow_comp_work);
+ cancel_work_sync(&chip->sysfs_restart_work);
+ cancel_work_sync(&chip->gain_comp_work);
+ cancel_work_sync(&chip->init_work);
+ cancel_work_sync(&chip->charge_full_work);
+ cancel_work_sync(&chip->bcl_hi_power_work);
+ cancel_work_sync(&chip->esr_extract_config_work);
+of_init_fail:
+ mutex_destroy(&chip->rslow_comp.lock);
+ mutex_destroy(&chip->rw_lock);
+ mutex_destroy(&chip->cyc_ctr.lock);
+ mutex_destroy(&chip->learning_data.learning_lock);
+ mutex_destroy(&chip->sysfs_restart_lock);
+ wakeup_source_trash(&chip->resume_soc_wakeup_source.source);
+ wakeup_source_trash(&chip->empty_check_wakeup_source.source);
+ wakeup_source_trash(&chip->memif_wakeup_source.source);
+ wakeup_source_trash(&chip->profile_wakeup_source.source);
+ wakeup_source_trash(&chip->update_temp_wakeup_source.source);
+ wakeup_source_trash(&chip->update_sram_wakeup_source.source);
+ wakeup_source_trash(&chip->gain_comp_wakeup_source.source);
+ wakeup_source_trash(&chip->capacity_learning_wakeup_source.source);
+ wakeup_source_trash(&chip->esr_extract_wakeup_source.source);
+ return rc;
+}
+
+static void check_and_update_sram_data(struct fg_chip *chip)
+{
+ unsigned long current_time = 0, next_update_time, time_left;
+
+ get_current_time(¤t_time);
+
+ next_update_time = chip->last_temp_update_time
+ + (TEMP_PERIOD_UPDATE_MS / 1000);
+
+ if (next_update_time > current_time)
+ time_left = next_update_time - current_time;
+ else
+ time_left = 0;
+
+ schedule_delayed_work(
+ &chip->update_temp_work, msecs_to_jiffies(time_left * 1000));
+
+ next_update_time = chip->last_sram_update_time
+ + (fg_sram_update_period_ms / 1000);
+
+ if (next_update_time > current_time)
+ time_left = next_update_time - current_time;
+ else
+ time_left = 0;
+
+ schedule_delayed_work(
+ &chip->update_sram_data, msecs_to_jiffies(time_left * 1000));
+}
+
+static int fg_suspend(struct device *dev)
+{
+ struct fg_chip *chip = dev_get_drvdata(dev);
+
+ if (!chip->sw_rbias_ctrl)
+ return 0;
+
+ cancel_delayed_work(&chip->update_temp_work);
+ cancel_delayed_work(&chip->update_sram_data);
+
+ return 0;
+}
+
+static int fg_resume(struct device *dev)
+{
+ struct fg_chip *chip = dev_get_drvdata(dev);
+
+ if (!chip->sw_rbias_ctrl)
+ return 0;
+
+ check_and_update_sram_data(chip);
+ return 0;
+}
+
+static const struct dev_pm_ops qpnp_fg_pm_ops = {
+ .suspend = fg_suspend,
+ .resume = fg_resume,
+};
+
+static int fg_sense_type_set(const char *val, const struct kernel_param *kp)
+{
+ int rc;
+ struct power_supply *bms_psy;
+ struct fg_chip *chip;
+ int old_fg_sense_type = fg_sense_type;
+
+ rc = param_set_int(val, kp);
+ if (rc) {
+ pr_err("Unable to set fg_sense_type: %d\n", rc);
+ return rc;
+ }
+
+ if (fg_sense_type != 0 && fg_sense_type != 1) {
+ pr_err("Bad value %d\n", fg_sense_type);
+ fg_sense_type = old_fg_sense_type;
+ return -EINVAL;
+ }
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("fg_sense_type set to %d\n", fg_sense_type);
+
+ bms_psy = power_supply_get_by_name("bms");
+ if (!bms_psy) {
+ pr_err("bms psy not found\n");
+ return 0;
+ }
+
+ chip = power_supply_get_drvdata(bms_psy);
+ rc = set_prop_sense_type(chip, fg_sense_type);
+ return rc;
+}
+
+static struct kernel_param_ops fg_sense_type_ops = {
+ .set = fg_sense_type_set,
+ .get = param_get_int,
+};
+
+module_param_cb(sense_type, &fg_sense_type_ops, &fg_sense_type, 0644);
+
+static int fg_restart_set(const char *val, const struct kernel_param *kp)
+{
+ struct power_supply *bms_psy;
+ struct fg_chip *chip;
+
+ bms_psy = power_supply_get_by_name("bms");
+ if (!bms_psy) {
+ pr_err("bms psy not found\n");
+ return 0;
+ }
+ chip = power_supply_get_drvdata(bms_psy);
+
+ mutex_lock(&chip->sysfs_restart_lock);
+ if (fg_restart != 0) {
+ mutex_unlock(&chip->sysfs_restart_lock);
+ return 0;
+ }
+ fg_restart = 1;
+ mutex_unlock(&chip->sysfs_restart_lock);
+
+ if (fg_debug_mask & FG_STATUS)
+ pr_info("fuel gauge restart initiated from sysfs...\n");
+
+ schedule_work(&chip->sysfs_restart_work);
+ return 0;
+}
+
+static struct kernel_param_ops fg_restart_ops = {
+ .set = fg_restart_set,
+ .get = param_get_int,
+};
+
+module_param_cb(restart, &fg_restart_ops, &fg_restart, 0644);
+
+static struct platform_driver fg_driver = {
+ .driver = {
+ .name = QPNP_FG_DEV_NAME,
+ .of_match_table = fg_match_table,
+ .pm = &qpnp_fg_pm_ops,
+ },
+ .probe = fg_probe,
+ .remove = fg_remove,
+};
+
+static int __init fg_init(void)
+{
+ return platform_driver_register(&fg_driver);
+}
+
+static void __exit fg_exit(void)
+{
+ return platform_driver_unregister(&fg_driver);
+}
+
+module_init(fg_init);
+module_exit(fg_exit);
+
+MODULE_DESCRIPTION("QPNP Fuel Gauge Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" QPNP_FG_DEV_NAME);
diff --git a/drivers/scsi/ufs/ufs-qcom-debugfs.c b/drivers/scsi/ufs/ufs-qcom-debugfs.c
index 4547a6d..4d0dcee 100644
--- a/drivers/scsi/ufs/ufs-qcom-debugfs.c
+++ b/drivers/scsi/ufs/ufs-qcom-debugfs.c
@@ -111,7 +111,7 @@
loff_t *ppos)
{
struct ufs_qcom_host *host = file->f_mapping->host->i_private;
- char configuration[TESTBUS_CFG_BUFF_LINE_SIZE] = {0};
+ char configuration[TESTBUS_CFG_BUFF_LINE_SIZE] = {'\0'};
loff_t buff_pos = 0;
char *comma;
int ret = 0;
@@ -125,6 +125,7 @@
__func__);
goto out;
}
+ configuration[ret] = '\0';
comma = strnchr(configuration, TESTBUS_CFG_BUFF_LINE_SIZE, ',');
if (!comma || comma == configuration) {
diff --git a/drivers/scsi/ufs/ufs_quirks.c b/drivers/scsi/ufs/ufs_quirks.c
index da2bfd5..a2b98fb 100644
--- a/drivers/scsi/ufs/ufs_quirks.c
+++ b/drivers/scsi/ufs/ufs_quirks.c
@@ -18,8 +18,6 @@
/* UFS cards deviations table */
UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
- UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
- UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
UFS_DEVICE_NO_FASTAUTO),
UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 8405537..b98d2ae 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -172,6 +172,9 @@
}
#endif
+#define PWR_INFO_MASK 0xF
+#define PWR_RX_OFFSET 4
+
#define UFSHCD_REQ_SENSE_SIZE 18
#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
@@ -408,8 +411,8 @@
#if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
static struct devfreq_simple_ondemand_data ufshcd_ondemand_data = {
- .upthreshold = 35,
- .downdifferential = 30,
+ .upthreshold = 70,
+ .downdifferential = 65,
.simple_scaling = 1,
};
@@ -419,7 +422,7 @@
#endif
static struct devfreq_dev_profile ufs_devfreq_profile = {
- .polling_ms = 40,
+ .polling_ms = 60,
.target = ufshcd_devfreq_target,
.get_dev_status = ufshcd_devfreq_get_dev_status,
};
@@ -4802,8 +4805,9 @@
int ret = 0;
/* if already configured to the requested pwr_mode */
- if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
- pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
+ if (!hba->restore_needed &&
+ pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
+ pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
@@ -6471,6 +6475,52 @@
reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
}
+static void ufshcd_rls_handler(struct work_struct *work)
+{
+ struct ufs_hba *hba;
+ int ret = 0;
+ u32 mode;
+
+ hba = container_of(work, struct ufs_hba, rls_work);
+ ufshcd_scsi_block_requests(hba);
+ pm_runtime_get_sync(hba->dev);
+ ret = ufshcd_wait_for_doorbell_clr(hba, U64_MAX);
+ if (ret) {
+ dev_err(hba->dev,
+ "Timed out (%d) waiting for DB to clear\n",
+ ret);
+ goto out;
+ }
+
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
+ if (hba->pwr_info.pwr_rx != ((mode >> PWR_RX_OFFSET) & PWR_INFO_MASK))
+ hba->restore_needed = true;
+
+ if (hba->pwr_info.pwr_tx != (mode & PWR_INFO_MASK))
+ hba->restore_needed = true;
+
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_RXGEAR), &mode);
+ if (hba->pwr_info.gear_rx != mode)
+ hba->restore_needed = true;
+
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TXGEAR), &mode);
+ if (hba->pwr_info.gear_tx != mode)
+ hba->restore_needed = true;
+
+ if (hba->restore_needed)
+ ret = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
+
+ if (ret)
+ dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
+ __func__, ret);
+ else
+ hba->restore_needed = false;
+
+out:
+ ufshcd_scsi_unblock_requests(hba);
+ pm_runtime_put_sync(hba->dev);
+}
+
/**
* ufshcd_update_uic_error - check and set fatal UIC error flags.
* @hba: per-adapter instance
@@ -6510,6 +6560,8 @@
hba->full_init_linereset = true;
}
}
+ if (!hba->full_init_linereset)
+ schedule_work(&hba->rls_work);
}
retval |= IRQ_HANDLED;
}
@@ -10450,6 +10502,7 @@
INIT_WORK(&hba->eh_work, ufshcd_err_handler);
INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
INIT_WORK(&hba->card_detect_work, ufshcd_card_detect_handler);
+ INIT_WORK(&hba->rls_work, ufshcd_rls_handler);
/* Initialize UIC command mutex */
mutex_init(&hba->uic_cmd_mutex);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 1b21238..1f5c404 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -873,6 +873,7 @@
/* Work Queues */
struct work_struct eh_work;
struct work_struct eeh_work;
+ struct work_struct rls_work;
/* HBA Errors */
u32 errors;
@@ -987,6 +988,7 @@
int latency_hist_enabled;
struct io_latency_state io_lat_s;
struct ufs_desc_size desc_size;
+ bool restore_needed;
};
static inline void ufshcd_mark_shutdown_ongoing(struct ufs_hba *hba)
diff --git a/drivers/slimbus/slim-msm-ngd.c b/drivers/slimbus/slim-msm-ngd.c
index ca56462..5fb0c29 100644
--- a/drivers/slimbus/slim-msm-ngd.c
+++ b/drivers/slimbus/slim-msm-ngd.c
@@ -422,9 +422,11 @@
u8 txn_mt;
u16 txn_mc = txn->mc;
u8 wbuf[SLIM_MSGQ_BUF_LEN];
+ const u8 *old_wbuf = NULL;
bool report_sat = false;
bool sync_wr = true;
+ memset(wbuf, 0, sizeof(wbuf));
if (txn->mc & SLIM_MSG_CLK_PAUSE_SEQ_FLG)
return -EPROTONOSUPPORT;
@@ -590,6 +592,7 @@
goto ngd_xfer_err;
}
txn->len = i;
+ old_wbuf = txn->wbuf;
txn->wbuf = wbuf;
txn->rl = txn->len + 4;
}
@@ -758,13 +761,18 @@
ctrl->txnt[txn->tid] = NULL;
spin_unlock_irqrestore(&ctrl->txn_lock, flags);
}
- return ret ? ret : dev->err;
+ goto ngd_xfer_ret;
}
ngd_xfer_err:
if (!report_sat) {
mutex_unlock(&dev->tx_lock);
msm_slim_put_ctrl(dev);
}
+ngd_xfer_ret:
+ if (txn->wbuf == wbuf)
+ txn->wbuf = old_wbuf;
+ if (txn->comp == &done)
+ txn->comp = NULL;
return ret ? ret : dev->err;
}
diff --git a/drivers/slimbus/slimbus.c b/drivers/slimbus/slimbus.c
index 3ae9a10..4c9210a 100644
--- a/drivers/slimbus/slimbus.c
+++ b/drivers/slimbus/slimbus.c
@@ -2512,7 +2512,7 @@
}
}
/* schedule 4k family channels */
- while (coeff1 < ctrl->sched.num_cc1 &&
+ while (coeff1 < ctrl->sched.num_cc1 && slc1 &&
curexp == (int)slc1->rootexp + expshft) {
/* searchorder effective when opensl valid */
static const int srcho[] = { 5, 2, 4, 1, 3, 0 };
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index c94f915..62306bad 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -590,13 +590,6 @@
trusted apps, unloading them and marshalling buffers to the
trusted fingerprint app.
-config APSS_CORE_EA
- depends on CPU_FREQ && PM_OPP
- bool "Qualcomm Technology Inc specific power aware driver"
- help
- Platform specific power aware driver to provide power
- and temperature information to the scheduler.
-
if MSM_PM
menuconfig MSM_IDLE_STATS
bool "Collect idle statistics"
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 4966c04..9a4e010 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -73,7 +73,6 @@
obj-$(CONFIG_MSM_QBT1000) += qbt1000.o
obj-$(CONFIG_MSM_EVENT_TIMER) += event_timer.o
obj-$(CONFIG_MSM_IDLE_STATS) += lpm-stats.o
-obj-$(CONFIG_APSS_CORE_EA) += msm-core.o debug_core.o
obj-$(CONFIG_QCOM_DCC_V2) += dcc_v2.o
obj-$(CONFIG_QTI_RPM_STATS_LOG) += rpm_stats.o
obj-$(CONFIG_QCOM_SMCINVOKE) += smcinvoke.o
diff --git a/drivers/soc/qcom/icnss.c b/drivers/soc/qcom/icnss.c
index 9be0821..04c611c 100644
--- a/drivers/soc/qcom/icnss.c
+++ b/drivers/soc/qcom/icnss.c
@@ -73,6 +73,8 @@
#define ICNSS_THRESHOLD_LOW 3450000
#define ICNSS_THRESHOLD_GUARD 20000
+#define ICNSS_MAX_PROBE_CNT 2
+
#define icnss_ipc_log_string(_x...) do { \
if (icnss_ipc_log_context) \
ipc_log_string(icnss_ipc_log_context, _x); \
@@ -2103,7 +2105,8 @@
static int icnss_call_driver_probe(struct icnss_priv *priv)
{
- int ret;
+ int ret = 0;
+ int probe_cnt = 0;
if (!priv->ops || !priv->ops->probe)
return 0;
@@ -2115,10 +2118,15 @@
icnss_hw_power_on(priv);
- ret = priv->ops->probe(&priv->pdev->dev);
+ while (probe_cnt < ICNSS_MAX_PROBE_CNT) {
+ ret = priv->ops->probe(&priv->pdev->dev);
+ probe_cnt++;
+ if (ret != -EPROBE_DEFER)
+ break;
+ }
if (ret < 0) {
- icnss_pr_err("Driver probe failed: %d, state: 0x%lx\n",
- ret, priv->state);
+ icnss_pr_err("Driver probe failed: %d, state: 0x%lx, probe_cnt: %d\n",
+ ret, priv->state, probe_cnt);
goto out;
}
@@ -2226,6 +2234,7 @@
static int icnss_driver_event_register_driver(void *data)
{
int ret = 0;
+ int probe_cnt = 0;
if (penv->ops)
return -EEXIST;
@@ -2245,11 +2254,15 @@
if (ret)
goto out;
- ret = penv->ops->probe(&penv->pdev->dev);
-
+ while (probe_cnt < ICNSS_MAX_PROBE_CNT) {
+ ret = penv->ops->probe(&penv->pdev->dev);
+ probe_cnt++;
+ if (ret != -EPROBE_DEFER)
+ break;
+ }
if (ret) {
- icnss_pr_err("Driver probe failed: %d, state: 0x%lx\n",
- ret, penv->state);
+ icnss_pr_err("Driver probe failed: %d, state: 0x%lx, probe_cnt: %d\n",
+ ret, penv->state, probe_cnt);
goto power_off;
}
diff --git a/drivers/soc/qcom/llcc-sdm670.c b/drivers/soc/qcom/llcc-sdm670.c
index 68ad755..494b93b 100644
--- a/drivers/soc/qcom/llcc-sdm670.c
+++ b/drivers/soc/qcom/llcc-sdm670.c
@@ -57,13 +57,14 @@
}
static struct llcc_slice_config sdm670_data[] = {
- SCT_ENTRY("cpuss", 1, 1, 512, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 1),
- SCT_ENTRY("vidsc0", 2, 2, 64, 2, 1, 0xF, 0x0, 0, 0, 0, 1, 0),
- SCT_ENTRY("vidsc1", 3, 3, 64, 2, 1, 0xF, 0x0, 0, 0, 0, 1, 0),
- SCT_ENTRY("rotator", 4, 4, 384, 2, 1, 0xF, 0x0, 0, 0, 0, 1, 0),
- SCT_ENTRY("modem", 8, 8, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 0),
- SCT_ENTRY("gpuhtw", 11, 11, 128, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0),
- SCT_ENTRY("gpu", 12, 12, 384, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0),
+ SCT_ENTRY("cpuss", 1, 1, 512, 1, 0, 0xF, 0x0, 0, 0, 1, 1, 1),
+ SCT_ENTRY("rotator", 4, 4, 384, 2, 1, 0x0, 0xE, 2, 0, 1, 1, 0),
+ SCT_ENTRY("voice", 5, 5, 512, 1, 0, 0xF, 0x0, 0, 0, 1, 1, 0),
+ SCT_ENTRY("audio", 6, 6, 512, 1, 0, 0xF, 0x0, 0, 0, 1, 1, 0),
+ SCT_ENTRY("modem", 8, 8, 512, 1, 0, 0xF, 0x0, 0, 0, 1, 1, 0),
+ SCT_ENTRY("gpu", 12, 12, 384, 1, 1, 0x0, 0x0, 0, 0, 1, 1, 0),
+ SCT_ENTRY("mmuhwt", 13, 13, 512, 1, 0, 0x0, 0x8, 0, 0, 1, 0, 1),
+ SCT_ENTRY("audiohw", 22, 22, 512, 1, 1, 0xF, 0x0, 0, 0, 1, 1, 0),
};
static int sdm670_qcom_llcc_probe(struct platform_device *pdev)
diff --git a/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c b/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c
index a40efcb..437984c 100644
--- a/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c
+++ b/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c
@@ -1294,7 +1294,7 @@
src = pdata->usecase->vectors[i].src;
dest = pdata->usecase->vectors[i].dst;
- if ((src < 0) || (dest < 0)) {
+ if ((src < 0) || (dest < 0) || (src == dest)) {
MSM_BUS_ERR("%s:Invalid src/dst.src %d dest %d",
__func__, src, dest);
goto exit_invalid_data;
diff --git a/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c b/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c
index bdcdf29..282f2ac 100644
--- a/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c
+++ b/drivers/soc/qcom/msm_bus/msm_bus_noc_rpmh.c
@@ -33,6 +33,7 @@
#define MAX_SAT_FIELD (NOC_QOS_SATn_SAT_BMSK >> NOC_QOS_SATn_SAT_SHFT)
#define MIN_SAT_FIELD 1
#define MIN_BW_FIELD 1
+#define QM_BASE 0x010B8000
#define MSM_BUS_FAB_MEM_NOC 6152
#define NOC_QOS_REG_BASE(b, o) ((b) + (o))
@@ -107,6 +108,16 @@
NOC_QOS_SATn_SAT_SHFT = 0x0,
};
+#define QM_CLn_TH_LVL_MUX_ADDR(b, o, n, d) \
+ (NOC_QOS_REG_BASE(b, o) + 0x8C0 + (d) * (n))
+enum qm_cl_id_th_lvl_mux_cfg {
+ QM_CLn_TH_LVL_SW_OVERRD_BMSK = 0x80000000,
+ QM_CLn_TH_LVL_SW_OVERRD_SHFT = 0x1F,
+ QM_CLn_TH_LVL_SW_BMSK = 0x00000007,
+ QM_CLn_TH_LVL_SW_SHFT = 0x0,
+};
+
+static void __iomem *qm_base;
static void __iomem *memnoc_qos_base;
static int noc_div(uint64_t *a, uint32_t b)
@@ -159,6 +170,18 @@
}
#define MAX_WS(bw, timebase) noc_ws((bw), MAX_SAT_FIELD, (timebase))
+static void noc_set_qm_th_lvl_cfg(void __iomem *base, uint32_t off,
+ uint32_t n, uint32_t delta,
+ uint32_t override_val, uint32_t override)
+{
+ writel_relaxed(((override << QM_CLn_TH_LVL_SW_OVERRD_SHFT) |
+ (override_val & QM_CLn_TH_LVL_SW_BMSK)),
+ QM_CLn_TH_LVL_MUX_ADDR(base, off, n, delta));
+
+ /* Ensure QM CFG is set before exiting */
+ wmb();
+}
+
static void noc_set_qos_dflt_prio(void __iomem *base, uint32_t qos_off,
uint32_t mport, uint32_t qos_delta,
uint32_t prio)
@@ -355,6 +378,16 @@
goto err_qos_init;
}
+ if (!qm_base) {
+ qm_base = ioremap_nocache(QM_BASE, 0x4000);
+ if (!qm_base) {
+ MSM_BUS_ERR("%s: Error remapping address 0x%zx",
+ __func__, (size_t)QM_BASE);
+ ret = -ENOMEM;
+ goto err_qos_init;
+ }
+ }
+
spin_lock_irqsave(&noc_lock, flags);
if (fabdev->node_info->id == MSM_BUS_FAB_MEM_NOC)
@@ -395,45 +428,17 @@
spin_lock_irqsave(&noc_lock, flags);
- if (!memnoc_qos_base) {
- MSM_BUS_ERR("Memnoc QoS Base address not found!");
+ if (!qm_base) {
+ MSM_BUS_ERR("QM CFG base address not found!");
goto noc_throttle_exit;
}
if (enable) {
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 2,
- 0x1000, 0x1B);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 3,
- 0x1000, 0x1B);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 10,
- 0x1000, 0x30);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 11,
- 0x1000, 0x30);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 10,
- 0x1000, 1);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 11,
- 0x1000, 1);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 2,
- 0x1000, 1);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 3,
- 0x1000, 1);
+ noc_set_qm_th_lvl_cfg(qm_base, 0x1000, 8, 0x4, 0x3, 0x1);
+ noc_set_qm_th_lvl_cfg(qm_base, 0x1000, 9, 0x4, 0x3, 0x1);
} else {
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 2,
- 0x1000, 0);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 3,
- 0x1000, 0);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 10,
- 0x1000, 0);
- noc_enable_qos_limiter(memnoc_qos_base, 0x10000, 11,
- 0x1000, 0);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 2,
- 0x1000, 0);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 3,
- 0x1000, 0);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 10,
- 0x1000, 0);
- noc_set_qos_limit_bw(memnoc_qos_base, 0x10000, 11,
- 0x1000, 0);
+ noc_set_qm_th_lvl_cfg(qm_base, 0x1000, 8, 0x4, 0, 0);
+ noc_set_qm_th_lvl_cfg(qm_base, 0x1000, 9, 0x4, 0, 0);
}
noc_throttle_exit:
diff --git a/drivers/soc/qcom/pil-msa.c b/drivers/soc/qcom/pil-msa.c
index ec3063e..a3eb551 100644
--- a/drivers/soc/qcom/pil-msa.c
+++ b/drivers/soc/qcom/pil-msa.c
@@ -124,13 +124,6 @@
int ret = 0;
u32 regval;
- if (drv->vreg) {
- ret = regulator_enable(drv->vreg);
- if (ret)
- dev_err(drv->desc.dev, "Failed to enable modem regulator(rc:%d)\n",
- ret);
- }
-
if (drv->cxrail_bhs) {
regval = readl_relaxed(drv->cxrail_bhs);
regval |= EXTERNAL_BHS_ON;
@@ -153,9 +146,6 @@
writel_relaxed(regval, drv->cxrail_bhs);
}
- if (drv->vreg)
- return regulator_disable(drv->vreg);
-
return 0;
}
@@ -456,7 +446,44 @@
return ret;
}
+ if (drv->vreg) {
+ ret = of_property_read_u32(pil->dev->of_node, "vdd_mss-uV",
+ &uv);
+ if (ret) {
+ dev_err(pil->dev,
+ "missing vdd_mss-uV property(rc:%d)\n", ret);
+ goto out;
+ }
+
+ ret = regulator_set_voltage(drv->vreg, uv,
+ INT_MAX);
+ if (ret) {
+ dev_err(pil->dev, "Failed to set vreg voltage(rc:%d)\n",
+ ret);
+ goto out;
+ }
+
+ ret = regulator_set_load(drv->vreg, 100000);
+ if (ret < 0) {
+ dev_err(pil->dev, "Failed to set vreg mode(rc:%d)\n",
+ ret);
+ goto out;
+ }
+ ret = regulator_enable(drv->vreg);
+ if (ret) {
+ dev_err(pil->dev, "Failed to enable vreg(rc:%d)\n",
+ ret);
+ regulator_set_voltage(drv->vreg, 0, INT_MAX);
+ goto out;
+ }
+ }
+
ret = pil_q6v5_make_proxy_votes(pil);
+ if (ret && drv->vreg) {
+ regulator_disable(drv->vreg);
+ regulator_set_voltage(drv->vreg, 0, INT_MAX);
+ }
+out:
if (ret) {
regulator_disable(drv->vreg_mx);
regulator_set_voltage(drv->vreg_mx, 0, INT_MAX);
@@ -472,6 +499,10 @@
pil_q6v5_remove_proxy_votes(pil);
regulator_disable(drv->vreg_mx);
regulator_set_voltage(drv->vreg_mx, 0, INT_MAX);
+ if (drv->vreg) {
+ regulator_disable(drv->vreg);
+ regulator_set_voltage(drv->vreg, 0, INT_MAX);
+ }
}
static int pil_mss_mem_setup(struct pil_desc *pil,
diff --git a/drivers/soc/qcom/pil-msa.h b/drivers/soc/qcom/pil-msa.h
index 7a6a3cc..0f1e75b 100644
--- a/drivers/soc/qcom/pil-msa.h
+++ b/drivers/soc/qcom/pil-msa.h
@@ -17,8 +17,6 @@
#include "peripheral-loader.h"
-#define VDD_MSS_UV 1000000
-
struct modem_data {
struct q6v5_data *q6;
struct subsys_device *subsys;
diff --git a/drivers/soc/qcom/pil-q6v5-mss.c b/drivers/soc/qcom/pil-q6v5-mss.c
index cf5f7e4..0477064 100644
--- a/drivers/soc/qcom/pil-q6v5-mss.c
+++ b/drivers/soc/qcom/pil-q6v5-mss.c
@@ -35,7 +35,6 @@
#include "pil-q6v5.h"
#include "pil-msa.h"
-#define MAX_VDD_MSS_UV 1150000
#define PROXY_TIMEOUT_MS 10000
#define MAX_SSR_REASON_LEN 256U
#define STOP_ACK_TIMEOUT_MS 1000
@@ -332,19 +331,6 @@
q6->vreg = devm_regulator_get(&pdev->dev, "vdd_mss");
if (IS_ERR(q6->vreg))
return PTR_ERR(q6->vreg);
-
- ret = regulator_set_voltage(q6->vreg, VDD_MSS_UV,
- MAX_VDD_MSS_UV);
- if (ret)
- dev_err(&pdev->dev, "Failed to set vreg voltage(rc:%d)\n",
- ret);
-
- ret = regulator_set_load(q6->vreg, 100000);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to set vreg mode(rc:%d)\n",
- ret);
- return ret;
- }
}
q6->vreg_mx = devm_regulator_get(&pdev->dev, "vdd_mx");
diff --git a/drivers/soc/qcom/rpm_stats.c b/drivers/soc/qcom/rpm_stats.c
index a3fe7b3..e60a7ad 100644
--- a/drivers/soc/qcom/rpm_stats.c
+++ b/drivers/soc/qcom/rpm_stats.c
@@ -173,7 +173,7 @@
if (prvdata.read_idx < prvdata.num_records)
prvdata.len = msm_rpmstats_copy_stats(&prvdata);
- return snprintf(buf, prvdata.len, prvdata.buf);
+ return snprintf(buf, prvdata.len, "%s", prvdata.buf);
}
static int msm_rpmstats_create_sysfs(struct msm_rpmstats_platform_data *pd)
diff --git a/drivers/soc/qcom/watchdog_v2.c b/drivers/soc/qcom/watchdog_v2.c
index 8bf5659..9aea6db 100644
--- a/drivers/soc/qcom/watchdog_v2.c
+++ b/drivers/soc/qcom/watchdog_v2.c
@@ -50,7 +50,7 @@
#define SCM_SET_REGSAVE_CMD 0x2
#define SCM_SVC_SEC_WDOG_DIS 0x7
#define MAX_CPU_CTX_SIZE 2048
-#define MAX_CPU_SCANDUMP_SIZE 0x10000
+#define MAX_CPU_SCANDUMP_SIZE 0x10100
static struct msm_watchdog_data *wdog_data;
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index 8dc42ac..7aaf08b 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -716,7 +716,7 @@
if (mas->cur_xfer_mode == FIFO_MODE) {
geni_se_select_mode(mas->base, FIFO_MODE);
reinit_completion(&mas->xfer_done);
- setup_fifo_params(spi_msg->spi, spi);
+ ret = setup_fifo_params(spi_msg->spi, spi);
} else if (mas->cur_xfer_mode == GSI_DMA) {
mas->num_tx_eot = 0;
mas->num_rx_eot = 0;
@@ -1199,6 +1199,7 @@
struct resource *res;
struct platform_device *wrapper_pdev;
struct device_node *wrapper_ph_node;
+ bool rt_pri;
spi = spi_alloc_master(&pdev->dev, sizeof(struct spi_geni_master));
if (!spi) {
@@ -1293,6 +1294,10 @@
goto spi_geni_probe_err;
}
+ rt_pri = of_property_read_bool(pdev->dev.of_node, "qcom,rt");
+ if (rt_pri)
+ spi->rt = true;
+
geni_mas->phys_addr = res->start;
geni_mas->size = resource_size(res);
geni_mas->base = devm_ioremap(&pdev->dev, res->start,
diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c
index af119f4..9c819fb 100644
--- a/drivers/tty/serial/msm_geni_serial.c
+++ b/drivers/tty/serial/msm_geni_serial.c
@@ -117,7 +117,7 @@
#define WAIT_XFER_MAX_TIMEOUT_US (10000)
#define WAIT_XFER_MIN_TIMEOUT_US (9000)
#define IPC_LOG_PWR_PAGES (6)
-#define IPC_LOG_MISC_PAGES (6)
+#define IPC_LOG_MISC_PAGES (10)
#define IPC_LOG_TX_RX_PAGES (8)
#define DATA_BYTES_PER_LINE (32)
@@ -184,6 +184,7 @@
static void msm_geni_serial_power_off(struct uart_port *uport);
static int msm_geni_serial_poll_bit(struct uart_port *uport,
int offset, int bit_field, bool set);
+static void msm_geni_serial_stop_rx(struct uart_port *uport);
static atomic_t uart_line_id = ATOMIC_INIT(0);
@@ -241,26 +242,40 @@
(unsigned int)addr, size, buf);
}
+static bool device_pending_suspend(struct uart_port *uport)
+{
+ int usage_count = atomic_read(&uport->dev->power.usage_count);
+
+ return (pm_runtime_suspended(uport->dev) || !usage_count);
+}
+
static bool check_transfers_inflight(struct uart_port *uport)
{
bool xfer_on = false;
bool tx_active = false;
- bool tx_empty = false;
+ bool tx_fifo_status = false;
bool m_cmd_active = false;
bool rx_active = false;
u32 rx_fifo_status = 0;
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
u32 geni_status = geni_read_reg_nolog(uport->membase,
SE_GENI_STATUS);
+ struct circ_buf *xmit = &uport->state->xmit;
+
/* Possible stop tx is called multiple times. */
m_cmd_active = geni_status & M_GENI_CMD_ACTIVE;
- tx_empty = msm_geni_serial_tx_empty(uport);
- tx_active = m_cmd_active || !tx_empty;
+ if (port->xfer_mode == SE_DMA)
+ tx_fifo_status = port->tx_dma ? 1 : 0;
+ else
+ tx_fifo_status = geni_read_reg_nolog(uport->membase,
+ SE_GENI_TX_FIFO_STATUS);
+ tx_active = m_cmd_active || tx_fifo_status;
rx_fifo_status = geni_read_reg_nolog(uport->membase,
SE_GENI_RX_FIFO_STATUS);
if (rx_fifo_status)
rx_active = true;
- if (rx_active || tx_active)
+ if (rx_active || tx_active || !uart_circ_empty(xmit))
xfer_on = true;
return xfer_on;
@@ -329,6 +344,7 @@
__func__, port->ioctl_count);
return -EPERM;
}
+ wait_for_transfers_inflight(uport);
port->ioctl_count--;
msm_geni_serial_power_off(uport);
IPC_LOG_MSG(port->ipc_log_pwr, "%s%s ioctl %d\n", __func__,
@@ -362,8 +378,13 @@
static void msm_geni_serial_break_ctl(struct uart_port *uport, int ctl)
{
- if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev))
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
+
+ if (!uart_console(uport) && device_pending_suspend(uport)) {
+ IPC_LOG_MSG(port->ipc_log_misc,
+ "%s.Device is suspended.\n", __func__);
return;
+ }
if (ctl) {
wait_for_transfers_inflight(uport);
@@ -384,9 +405,13 @@
{
u32 geni_ios = 0;
unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
- if (pm_runtime_status_suspended(uport->dev))
+ if (device_pending_suspend(uport)) {
+ IPC_LOG_MSG(port->ipc_log_misc,
+ "%s.Device is suspended.\n", __func__);
return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
+ }
geni_ios = geni_read_reg_nolog(uport->membase, SE_GENI_IOS);
if (!(geni_ios & IO2_DATA_IN))
@@ -404,9 +429,13 @@
unsigned int mctrl)
{
u32 uart_manual_rfr = 0;
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
- if (pm_runtime_status_suspended(uport->dev))
+ if (device_pending_suspend(uport)) {
+ IPC_LOG_MSG(port->ipc_log_misc,
+ "%s.Device is suspended.\n", __func__);
return;
+ }
if (!(mctrl & TIOCM_RTS))
uart_manual_rfr |= (UART_MANUAL_RFR_EN | UART_RFR_NOT_READY);
geni_write_reg_nolog(uart_manual_rfr, uport->membase,
@@ -456,6 +485,14 @@
static void msm_geni_serial_power_off(struct uart_port *uport)
{
+ struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
+ int usage_count = atomic_read(&uport->dev->power.usage_count);
+
+ if (!usage_count) {
+ IPC_LOG_MSG(port->ipc_log_pwr, "%s: Usage Count is already 0\n",
+ __func__);
+ return;
+ }
pm_runtime_mark_last_busy(uport->dev);
pm_runtime_put_autosuspend(uport->dev);
}
@@ -541,6 +578,7 @@
msm_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
S_GENI_CMD_ABORT, false);
geni_write_reg_nolog(irq_clear, uport->membase, SE_GENI_S_IRQ_CLEAR);
+ geni_write_reg(FORCE_DEFAULT, uport->membase, GENI_FORCE_DEFAULT_REG);
}
#ifdef CONFIG_CONSOLE_POLL
@@ -789,13 +827,16 @@
unsigned int geni_status;
unsigned int geni_ios;
- if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
- dev_err(uport->dev, "%s.Device is suspended.\n", __func__);
+ if (!uart_console(uport) && !pm_runtime_active(uport->dev)) {
IPC_LOG_MSG(msm_port->ipc_log_misc,
- "%s.Device is suspended.\n", __func__);
- return;
+ "%s.Putting in async RPM vote\n", __func__);
+ pm_runtime_get(uport->dev);
+ goto exit_start_tx;
}
+ if (!uart_console(uport))
+ pm_runtime_get(uport->dev);
+
if (msm_port->xfer_mode == FIFO_MODE) {
geni_status = geni_read_reg_nolog(uport->membase,
SE_GENI_STATUS);
@@ -828,6 +869,9 @@
if (!(geni_ios & IO2_DATA_IN))
IPC_LOG_MSG(msm_port->ipc_log_misc, "%s: ios: 0x%08x\n",
__func__, geni_ios);
+exit_start_tx:
+ if (!uart_console(uport))
+ msm_geni_serial_power_off(uport);
}
static void msm_geni_serial_tx_fsm_rst(struct uart_port *uport)
@@ -855,7 +899,7 @@
unsigned int geni_status;
struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
- if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
+ if (!uart_console(uport) && device_pending_suspend(uport)) {
dev_err(uport->dev, "%s.Device is suspended.\n", __func__);
IPC_LOG_MSG(port->ipc_log_misc,
"%s.Device is suspended.\n", __func__);
@@ -907,7 +951,7 @@
struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
int ret;
- if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
+ if (!uart_console(uport) && device_pending_suspend(uport)) {
dev_err(uport->dev, "%s.Device is suspended.\n", __func__);
IPC_LOG_MSG(port->ipc_log_misc,
"%s.Device is suspended.\n", __func__);
@@ -916,7 +960,8 @@
geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS);
if (geni_status & S_GENI_CMD_ACTIVE)
- msm_geni_serial_abort_rx(uport);
+ msm_geni_serial_stop_rx(uport);
+
geni_setup_s_cmd(uport->membase, UART_START_READ, 0);
if (port->xfer_mode == FIFO_MODE) {
@@ -938,8 +983,8 @@
if (ret) {
dev_err(uport->dev, "%s: RX Prep dma failed %d\n",
__func__, ret);
- msm_geni_serial_abort_rx(uport);
- return;
+ msm_geni_serial_stop_rx(uport);
+ goto exit_geni_serial_start_rx;
}
}
/*
@@ -948,6 +993,7 @@
*/
mb();
geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS);
+exit_geni_serial_start_rx:
IPC_LOG_MSG(port->ipc_log_misc, "%s 0x%x\n", __func__, geni_status);
}
@@ -976,9 +1022,9 @@
unsigned int geni_m_irq_en;
unsigned int geni_status;
struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
+ u32 irq_clear = S_CMD_DONE_EN;
- if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
- dev_err(uport->dev, "%s.Device is suspended.\n", __func__);
+ if (!uart_console(uport) && device_pending_suspend(uport)) {
IPC_LOG_MSG(port->ipc_log_misc,
"%s.Device is suspended.\n", __func__);
return;
@@ -1007,7 +1053,17 @@
/* Possible stop rx is called multiple times. */
if (!(geni_status & S_GENI_CMD_ACTIVE))
return;
- msm_geni_serial_abort_rx(uport);
+ geni_cancel_s_cmd(uport->membase);
+ /*
+ * Ensure that the cancel goes through before polling for the
+ * cancel control bit.
+ */
+ mb();
+ msm_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
+ S_GENI_CMD_CANCEL, false);
+ geni_write_reg_nolog(irq_clear, uport->membase, SE_GENI_S_IRQ_CLEAR);
+ if ((geni_status & S_GENI_CMD_ACTIVE))
+ msm_geni_serial_abort_rx(uport);
}
static int handle_rx_hs(struct uart_port *uport,
@@ -1096,6 +1152,15 @@
tx_fifo_status = geni_read_reg_nolog(uport->membase,
SE_GENI_TX_FIFO_STATUS);
if (uart_circ_empty(xmit) && !tx_fifo_status) {
+ /*
+ * This will balance out the power vote put in during start_tx
+ * allowing the device to suspend.
+ */
+ if (!uart_console(uport)) {
+ IPC_LOG_MSG(msm_port->ipc_log_misc,
+ "%s.Power Off.\n", __func__);
+ msm_geni_serial_power_off(uport);
+ }
msm_geni_serial_stop_tx(uport);
goto exit_handle_tx;
}
@@ -1152,8 +1217,7 @@
msm_port->xmit_size = xmit_size;
}
exit_handle_tx:
- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
- uart_write_wakeup(uport);
+ uart_write_wakeup(uport);
return ret;
}
@@ -1220,8 +1284,18 @@
if (!uart_circ_empty(xmit))
msm_geni_serial_prep_dma_tx(uport);
- else
+ else {
+ /*
+ * This will balance out the power vote put in during start_tx
+ * allowing the device to suspend.
+ */
+ if (!uart_console(uport)) {
+ IPC_LOG_MSG(msm_port->ipc_log_misc,
+ "%s.Power Off.\n", __func__);
+ msm_geni_serial_power_off(uport);
+ }
uart_write_wakeup(uport);
+ }
return 0;
}
@@ -1241,7 +1315,7 @@
spin_lock_irqsave(&uport->lock, flags);
if (uart_console(uport) && uport->suspended)
goto exit_geni_serial_isr;
- if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
+ if (!uart_console(uport) && pm_runtime_suspended(uport->dev)) {
dev_err(uport->dev, "%s.Device is suspended.\n", __func__);
IPC_LOG_MSG(msm_port->ipc_log_misc,
"%s.Device is suspended.\n", __func__);
@@ -1511,47 +1585,6 @@
* framework.
*/
mb();
- if (!uart_console(uport)) {
- char name[30];
-
- memset(name, 0, sizeof(name));
- if (!msm_port->ipc_log_rx) {
- scnprintf(name, sizeof(name), "%s%s",
- dev_name(uport->dev), "_rx");
- msm_port->ipc_log_rx = ipc_log_context_create(
- IPC_LOG_TX_RX_PAGES, name, 0);
- if (!msm_port->ipc_log_rx)
- dev_info(uport->dev, "Err in Rx IPC Log\n");
- }
- memset(name, 0, sizeof(name));
- if (!msm_port->ipc_log_tx) {
- scnprintf(name, sizeof(name), "%s%s",
- dev_name(uport->dev), "_tx");
- msm_port->ipc_log_tx = ipc_log_context_create(
- IPC_LOG_TX_RX_PAGES, name, 0);
- if (!msm_port->ipc_log_tx)
- dev_info(uport->dev, "Err in Tx IPC Log\n");
- }
- memset(name, 0, sizeof(name));
- if (!msm_port->ipc_log_pwr) {
- scnprintf(name, sizeof(name), "%s%s",
- dev_name(uport->dev), "_pwr");
- msm_port->ipc_log_pwr = ipc_log_context_create(
- IPC_LOG_PWR_PAGES, name, 0);
- if (!msm_port->ipc_log_pwr)
- dev_info(uport->dev, "Err in Pwr IPC Log\n");
- }
- memset(name, 0, sizeof(name));
- if (!msm_port->ipc_log_misc) {
- scnprintf(name, sizeof(name), "%s%s",
- dev_name(uport->dev), "_misc");
- msm_port->ipc_log_misc = ipc_log_context_create(
- IPC_LOG_MISC_PAGES, name, 0);
- if (!msm_port->ipc_log_misc)
- dev_info(uport->dev, "Err in Misc IPC Log\n");
- }
-
- }
exit_portsetup:
return ret;
}
@@ -1586,7 +1619,6 @@
goto exit_startup;
}
- msm_geni_serial_start_rx(uport);
/*
* Ensure that all the port configuration writes complete
* before returning to the framework.
@@ -1707,11 +1739,17 @@
struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
unsigned long clk_rate;
- if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
- IPC_LOG_MSG(port->ipc_log_pwr,
- "%s Device suspended,vote clocks on.\n", __func__);
- return;
+ if (!uart_console(uport)) {
+ int ret = msm_geni_serial_power_on(uport);
+
+ if (ret) {
+ IPC_LOG_MSG(port->ipc_log_misc,
+ "%s: Failed to vote clock on:%d\n",
+ __func__, ret);
+ return;
+ }
}
+ msm_geni_serial_stop_rx(uport);
/* baud rate */
baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
port->cur_baud = baud;
@@ -1800,6 +1838,9 @@
IPC_LOG_MSG(port->ipc_log_misc, "BitsChar%d stop bit%d\n",
bits_per_char, stop_bit_len);
exit_set_termios:
+ msm_geni_serial_start_rx(uport);
+ if (!uart_console(uport))
+ msm_geni_serial_power_off(uport);
return;
}
@@ -1810,10 +1851,10 @@
unsigned int is_tx_empty = 1;
struct msm_geni_serial_port *port = GET_DEV_PORT(uport);
- if (!uart_console(uport) && pm_runtime_status_suspended(uport->dev)) {
+ if (!uart_console(uport) && device_pending_suspend(uport)) {
IPC_LOG_MSG(port->ipc_log_pwr,
"%s Device suspended,vote clocks on.\n", __func__);
- return 1;
+ return 0;
}
if (port->xfer_mode == SE_DMA)
@@ -2069,13 +2110,54 @@
}
#endif /* defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(CONFIG_CONSOLE_POLL) */
-static void msm_geni_serial_debug_init(struct uart_port *uport)
+static void msm_geni_serial_debug_init(struct uart_port *uport, bool console)
{
struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);
msm_port->dbg = debugfs_create_dir(dev_name(uport->dev), NULL);
if (IS_ERR_OR_NULL(msm_port->dbg))
dev_err(uport->dev, "Failed to create dbg dir\n");
+
+ if (!console) {
+ char name[30];
+
+ memset(name, 0, sizeof(name));
+ if (!msm_port->ipc_log_rx) {
+ scnprintf(name, sizeof(name), "%s%s",
+ dev_name(uport->dev), "_rx");
+ msm_port->ipc_log_rx = ipc_log_context_create(
+ IPC_LOG_TX_RX_PAGES, name, 0);
+ if (!msm_port->ipc_log_rx)
+ dev_info(uport->dev, "Err in Rx IPC Log\n");
+ }
+ memset(name, 0, sizeof(name));
+ if (!msm_port->ipc_log_tx) {
+ scnprintf(name, sizeof(name), "%s%s",
+ dev_name(uport->dev), "_tx");
+ msm_port->ipc_log_tx = ipc_log_context_create(
+ IPC_LOG_TX_RX_PAGES, name, 0);
+ if (!msm_port->ipc_log_tx)
+ dev_info(uport->dev, "Err in Tx IPC Log\n");
+ }
+ memset(name, 0, sizeof(name));
+ if (!msm_port->ipc_log_pwr) {
+ scnprintf(name, sizeof(name), "%s%s",
+ dev_name(uport->dev), "_pwr");
+ msm_port->ipc_log_pwr = ipc_log_context_create(
+ IPC_LOG_PWR_PAGES, name, 0);
+ if (!msm_port->ipc_log_pwr)
+ dev_info(uport->dev, "Err in Pwr IPC Log\n");
+ }
+ memset(name, 0, sizeof(name));
+ if (!msm_port->ipc_log_misc) {
+ scnprintf(name, sizeof(name), "%s%s",
+ dev_name(uport->dev), "_misc");
+ msm_port->ipc_log_misc = ipc_log_context_create(
+ IPC_LOG_MISC_PAGES, name, 0);
+ if (!msm_port->ipc_log_misc)
+ dev_info(uport->dev, "Err in Misc IPC Log\n");
+ }
+ }
}
static void msm_geni_serial_cons_pm(struct uart_port *uport,
@@ -2319,7 +2401,7 @@
line, uport->fifosize, is_console);
device_create_file(uport->dev, &dev_attr_loopback);
device_create_file(uport->dev, &dev_attr_xfer_mode);
- msm_geni_serial_debug_init(uport);
+ msm_geni_serial_debug_init(uport, is_console);
dev_port->port_setup = false;
return uart_add_one_port(drv, uport);
@@ -2347,12 +2429,12 @@
int ret = 0;
wait_for_transfers_inflight(&port->uport);
+ disable_irq(port->uport.irq);
ret = se_geni_resources_off(&port->serial_rsc);
if (ret) {
dev_err(dev, "%s: Error ret %d\n", __func__, ret);
goto exit_runtime_suspend;
}
- disable_irq(port->uport.irq);
if (port->wakeup_irq > 0) {
struct se_geni_rsc *rsc = &port->serial_rsc;
diff --git a/drivers/uio/msm_sharedmem/msm_sharedmem.c b/drivers/uio/msm_sharedmem/msm_sharedmem.c
index b25f55a..8be3e36 100644
--- a/drivers/uio/msm_sharedmem/msm_sharedmem.c
+++ b/drivers/uio/msm_sharedmem/msm_sharedmem.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -107,10 +107,12 @@
struct resource *clnt_res = NULL;
u32 client_id = ((u32)~0U);
u32 shared_mem_size = 0;
+ u32 shared_mem_tot_sz = 0;
void *shared_mem = NULL;
phys_addr_t shared_mem_pyhsical = 0;
bool is_addr_dynamic = false;
struct sharemem_qmi_entry qmi_entry;
+ bool guard_memory = false;
/* Get the addresses from platform-data */
if (!pdev->dev.of_node) {
@@ -145,13 +147,30 @@
if (shared_mem_pyhsical == 0) {
is_addr_dynamic = true;
- shared_mem = dma_alloc_coherent(&pdev->dev, shared_mem_size,
+
+ /*
+ * If guard_memory is set, then the shared memory region
+ * will be guarded by SZ_4K at the start and at the end.
+ * This is needed to overcome the XPU limitation on few
+ * MSM HW, so as to make this memory not contiguous with
+ * other allocations that may possibly happen from other
+ * clients in the system.
+ */
+ guard_memory = of_property_read_bool(pdev->dev.of_node,
+ "qcom,guard-memory");
+
+ shared_mem_tot_sz = guard_memory ? shared_mem_size + SZ_8K :
+ shared_mem_size;
+
+ shared_mem = dma_alloc_coherent(&pdev->dev, shared_mem_tot_sz,
&shared_mem_pyhsical, GFP_KERNEL);
if (shared_mem == NULL) {
pr_err("Shared mem alloc client=%s, size=%u\n",
clnt_res->name, shared_mem_size);
return -ENOMEM;
}
+ if (guard_memory)
+ shared_mem_pyhsical += SZ_4K;
}
/* Set up the permissions for the shared ram that was allocated. */
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 4b78e02..5ca987a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -977,41 +977,14 @@
struct device *dev = dwc->dev;
int ret;
- switch (dwc->dr_mode) {
- case USB_DR_MODE_PERIPHERAL:
+ if (dwc->dr_mode == USB_DR_MODE_OTG ||
+ dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
ret = dwc3_gadget_init(dwc);
if (ret) {
if (ret != -EPROBE_DEFER)
dev_err(dev, "failed to initialize gadget\n");
return ret;
}
- break;
- case USB_DR_MODE_HOST:
- ret = dwc3_host_init(dwc);
- if (ret) {
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "failed to initialize host\n");
- return ret;
- }
- break;
- case USB_DR_MODE_OTG:
- ret = dwc3_host_init(dwc);
- if (ret) {
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "failed to initialize host\n");
- return ret;
- }
-
- ret = dwc3_gadget_init(dwc);
- if (ret) {
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "failed to initialize gadget\n");
- return ret;
- }
- break;
- default:
- dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
- return -EINVAL;
}
return 0;
@@ -1019,21 +992,9 @@
static void dwc3_core_exit_mode(struct dwc3 *dwc)
{
- switch (dwc->dr_mode) {
- case USB_DR_MODE_PERIPHERAL:
+ if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL ||
+ dwc->dr_mode == USB_DR_MODE_OTG)
dwc3_gadget_exit(dwc);
- break;
- case USB_DR_MODE_HOST:
- dwc3_host_exit(dwc);
- break;
- case USB_DR_MODE_OTG:
- dwc3_host_exit(dwc);
- dwc3_gadget_exit(dwc);
- break;
- default:
- /* do nothing */
- break;
- }
}
/* XHCI reset, resets other CORE registers as well, re-init those */
@@ -1210,6 +1171,10 @@
"snps,is-utmi-l1-suspend");
device_property_read_u8(dev, "snps,hird-threshold",
&hird_threshold);
+
+ device_property_read_u32(dev, "snps,xhci-imod-value",
+ &dwc->xhci_imod_value);
+
dwc->usb3_lpm_capable = device_property_read_bool(dev,
"snps,usb3_lpm_capable");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 5af75fd..63d0a3e 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -952,6 +952,7 @@
* @imod_interval: set the interrupt moderation interval in 250ns
* increments or 0 to disable.
* @create_reg_debugfs: create debugfs entry to allow dwc3 register dump
+ * @xhci_imod_value: imod value to use with xhci
*/
struct dwc3 {
struct usb_ctrlrequest *ctrl_req;
@@ -1147,6 +1148,7 @@
int last_fifo_depth;
struct dwc3_gadget_events dbg_gadget_events;
bool create_reg_debugfs;
+ u32 xhci_imod_value;
};
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index 351f9a2..d0fc511 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -3667,9 +3667,6 @@
struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3);
int ret = 0;
- if (!dwc->xhci)
- return -EINVAL;
-
/*
* The vbus_reg pointer could have multiple values
* NULL: regulator_get() hasn't been called, or was previously deferred
@@ -3720,15 +3717,7 @@
mdwc->usbdev_nb.notifier_call = msm_dwc3_usbdev_notify;
usb_register_atomic_notify(&mdwc->usbdev_nb);
- /*
- * FIXME If micro A cable is disconnected during system suspend,
- * xhci platform device will be removed before runtime pm is
- * enabled for xhci device. Due to this, disable_depth becomes
- * greater than one and runtimepm is not enabled for next microA
- * connect. Fix this by calling pm_runtime_init for xhci device.
- */
- pm_runtime_init(&dwc->xhci->dev);
- ret = platform_device_add(dwc->xhci);
+ ret = dwc3_host_init(dwc);
if (ret) {
dev_err(mdwc->dev,
"%s: failed to add XHCI pdev ret=%d\n",
@@ -3796,7 +3785,7 @@
}
mdwc->hs_phy->flags &= ~PHY_HOST_MODE;
- platform_device_del(dwc->xhci);
+ dwc3_host_exit(dwc);
usb_unregister_notify(&mdwc->host_nb);
dwc3_usb3_phy_suspend(dwc, false);
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index ec9ffc1..1c33051 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -878,10 +878,7 @@
dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
- if (r)
- dwc3_gadget_giveback(ep0, r, -ECONNRESET);
-
- return;
+ dbg_event(0x0, "SETUPPEND", status);
}
ur = &r->request;
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index af3ce4f..3f79aa4 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -52,14 +52,16 @@
return irq;
}
+#define NUMBER_OF_PROPS 4
int dwc3_host_init(struct dwc3 *dwc)
{
- struct property_entry props[3];
+ struct property_entry props[NUMBER_OF_PROPS];
struct platform_device *xhci;
int ret, irq;
struct resource *res;
struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
int prop_idx = 0;
+ struct property_entry imod_prop;
irq = dwc3_host_get_irq(dwc);
if (irq < 0)
@@ -101,6 +103,15 @@
if (dwc->usb3_lpm_capable)
props[prop_idx++].name = "usb3-lpm-capable";
+ if (dwc->xhci_imod_value) {
+ imod_prop.name = "xhci-imod-value";
+ imod_prop.length = sizeof(u32);
+ imod_prop.is_string = false;
+ imod_prop.is_array = false;
+ imod_prop.value.u32_data = dwc->xhci_imod_value;
+ props[prop_idx++] = imod_prop;
+ }
+
/**
* WORKAROUND: dwc3 revisions <=3.00a have a limitation
* where Port Disable command doesn't work.
@@ -126,7 +137,11 @@
phy_create_lookup(dwc->usb3_generic_phy, "usb3-phy",
dev_name(dwc->dev));
- /* Platform device gets added as part of state machine */
+ ret = platform_device_add(xhci);
+ if (ret) {
+ dev_err(dwc->dev, "failed to register xHCI device\n");
+ goto err1;
+ }
return 0;
err1:
@@ -140,6 +155,5 @@
dev_name(dwc->dev));
phy_remove_lookup(dwc->usb3_generic_phy, "usb3-phy",
dev_name(dwc->dev));
- if (!dwc->is_drd)
- platform_device_unregister(dwc->xhci);
+ platform_device_unregister(dwc->xhci);
}
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 02adc93..e32de9a 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -2013,8 +2013,9 @@
if (value < 0) {
DBG(cdev, "ep_queue --> %d\n", value);
req->status = 0;
- composite_setup_complete(gadget->ep0,
- req);
+ if (value != -ESHUTDOWN)
+ composite_setup_complete(
+ gadget->ep0, req);
}
}
return value;
@@ -2108,7 +2109,8 @@
if (value < 0) {
DBG(cdev, "ep_queue --> %d\n", value);
req->status = 0;
- composite_setup_complete(gadget->ep0, req);
+ if (value != -ESHUTDOWN)
+ composite_setup_complete(gadget->ep0, req);
}
} else if (value == USB_GADGET_DELAYED_STATUS && w_length != 0) {
WARN(cdev,
diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c
index c11629d..a26d6df 100644
--- a/drivers/usb/gadget/function/f_gsi.c
+++ b/drivers/usb/gadget/function/f_gsi.c
@@ -19,7 +19,14 @@
MODULE_PARM_DESC(qti_packet_debug, "Print QTI Packet's Raw Data");
static struct workqueue_struct *ipa_usb_wq;
+static struct gsi_inst_status {
+ struct mutex gsi_lock;
+ bool inst_exist;
+ struct gsi_opts *opts;
+} inst_status[IPA_USB_MAX_TETH_PROT_SIZE];
+/* Deregister misc device and free instance structures */
+static void gsi_inst_clean(struct gsi_opts *opts);
static void gsi_rndis_ipa_reset_trigger(struct gsi_data_port *d_port);
static void ipa_disconnect_handler(struct gsi_data_port *d_port);
static int gsi_ctrl_send_notification(struct f_gsi *gsi);
@@ -919,40 +926,69 @@
struct gsi_ctrl_port *c_port = container_of(fp->private_data,
struct gsi_ctrl_port,
ctrl_device);
- struct f_gsi *gsi = c_port_to_gsi(c_port);
+ struct f_gsi *gsi;
+ struct gsi_inst_status *inst_cur;
if (!c_port) {
- log_event_err("%s: gsi ctrl port %p", __func__, c_port);
+ pr_err_ratelimited("%s: gsi ctrl port %p", __func__, c_port);
return -ENODEV;
}
+ gsi = container_of(c_port, struct f_gsi, c_port);
+ inst_cur = &inst_status[gsi->prot_id];
log_event_dbg("%s: open ctrl dev %s", __func__, c_port->name);
+ mutex_lock(&inst_cur->gsi_lock);
+
+ fp->private_data = &gsi->prot_id;
+
+ if (!inst_cur->inst_exist) {
+ mutex_unlock(&inst_cur->gsi_lock);
+ log_event_err("%s: [prot_id = %d], GSI instance freed already\n",
+ __func__, gsi->prot_id);
+ return -ENODEV;
+ }
+
if (c_port->is_open) {
- log_event_err("%s: Already opened", __func__);
+ mutex_unlock(&inst_cur->gsi_lock);
+ log_event_err("%s: Already opened\n", __func__);
return -EBUSY;
}
c_port->is_open = true;
+ mutex_unlock(&inst_cur->gsi_lock);
+
return 0;
}
static int gsi_ctrl_dev_release(struct inode *ip, struct file *fp)
{
- struct gsi_ctrl_port *c_port = container_of(fp->private_data,
- struct gsi_ctrl_port,
- ctrl_device);
- struct f_gsi *gsi = c_port_to_gsi(c_port);
+ enum ipa_usb_teth_prot prot_id =
+ *(enum ipa_usb_teth_prot *)(fp->private_data);
+ struct gsi_inst_status *inst_cur = &inst_status[prot_id];
+ struct f_gsi *gsi;
- if (!c_port) {
- log_event_err("%s: gsi ctrl port %p", __func__, c_port);
+ mutex_lock(&inst_cur->gsi_lock);
+
+ if (unlikely(inst_cur->inst_exist == false)) {
+ if (inst_cur->opts) {
+ /* GSI instance clean up */
+ gsi_inst_clean(inst_cur->opts);
+ inst_cur->opts = NULL;
+ }
+ mutex_unlock(&inst_cur->gsi_lock);
+ pr_err_ratelimited("%s: prot_id:%d: delayed free memory\n",
+ __func__, prot_id);
return -ENODEV;
}
- log_event_dbg("close ctrl dev %s", c_port->name);
+ inst_cur->opts->gsi->c_port.is_open = false;
+ gsi = inst_cur->opts->gsi;
+ mutex_unlock(&inst_cur->gsi_lock);
- c_port->is_open = false;
+ log_event_dbg("close ctrl dev %s\n",
+ inst_cur->opts->gsi->c_port.name);
return 0;
}
@@ -960,16 +996,28 @@
static ssize_t
gsi_ctrl_dev_read(struct file *fp, char __user *buf, size_t count, loff_t *pos)
{
- struct gsi_ctrl_port *c_port = container_of(fp->private_data,
- struct gsi_ctrl_port,
- ctrl_device);
- struct f_gsi *gsi = c_port_to_gsi(c_port);
+ struct gsi_ctrl_port *c_port;
struct gsi_ctrl_pkt *cpkt = NULL;
+ enum ipa_usb_teth_prot prot_id =
+ *(enum ipa_usb_teth_prot *)(fp->private_data);
+ struct gsi_inst_status *inst_cur = &inst_status[prot_id];
+ struct f_gsi *gsi;
unsigned long flags;
int ret = 0;
- log_event_dbg("%s: Enter %zu", __func__, count);
+ pr_debug("%s: Enter %zu", __func__, count);
+ mutex_lock(&inst_cur->gsi_lock);
+ if (unlikely(inst_cur->inst_exist == false)) {
+ mutex_unlock(&inst_cur->gsi_lock);
+ pr_err_ratelimited("%s: free_inst is called and being freed\n",
+ __func__);
+ return -ENODEV;
+ }
+ mutex_unlock(&inst_cur->gsi_lock);
+
+ gsi = inst_cur->opts->gsi;
+ c_port = &inst_cur->opts->gsi->c_port;
if (!c_port) {
log_event_err("%s: gsi ctrl port %p", __func__, c_port);
return -ENODEV;
@@ -1037,13 +1085,27 @@
int ret = 0;
unsigned long flags;
struct gsi_ctrl_pkt *cpkt;
- struct gsi_ctrl_port *c_port = container_of(fp->private_data,
- struct gsi_ctrl_port,
- ctrl_device);
- struct f_gsi *gsi = c_port_to_gsi(c_port);
- struct usb_request *req = c_port->notify_req;
+ struct gsi_ctrl_port *c_port;
+ struct usb_request *req;
+ enum ipa_usb_teth_prot prot_id =
+ *(enum ipa_usb_teth_prot *)(fp->private_data);
+ struct gsi_inst_status *inst_cur = &inst_status[prot_id];
+ struct f_gsi *gsi;
- log_event_dbg("Enter %zu", count);
+ pr_debug("Enter %zu", count);
+
+ mutex_lock(&inst_cur->gsi_lock);
+ if (unlikely(inst_cur->inst_exist == false)) {
+ mutex_unlock(&inst_cur->gsi_lock);
+ pr_err_ratelimited("%s: free_inst is called and being freed\n",
+ __func__);
+ return -ENODEV;
+ }
+ mutex_unlock(&inst_cur->gsi_lock);
+
+ gsi = inst_cur->opts->gsi;
+ c_port = &gsi->c_port;
+ req = c_port->notify_req;
if (!c_port || !req || !req->buf) {
log_event_err("%s: c_port %p req %p req->buf %p",
@@ -1101,15 +1163,28 @@
static long gsi_ctrl_dev_ioctl(struct file *fp, unsigned int cmd,
unsigned long arg)
{
- struct gsi_ctrl_port *c_port = container_of(fp->private_data,
- struct gsi_ctrl_port,
- ctrl_device);
- struct f_gsi *gsi = c_port_to_gsi(c_port);
+ struct gsi_ctrl_port *c_port;
+ struct f_gsi *gsi;
struct gsi_ctrl_pkt *cpkt;
struct ep_info info;
+ enum ipa_usb_teth_prot prot_id =
+ *(enum ipa_usb_teth_prot *)(fp->private_data);
+ struct gsi_inst_status *inst_cur = &inst_status[prot_id];
int val, ret = 0;
unsigned long flags;
+ mutex_lock(&inst_cur->gsi_lock);
+ if (unlikely(inst_cur->inst_exist == false)) {
+ mutex_unlock(&inst_cur->gsi_lock);
+ pr_err_ratelimited("%s: free_inst is called and being freed\n",
+ __func__);
+ return -ENODEV;
+ }
+ mutex_unlock(&inst_cur->gsi_lock);
+
+ gsi = inst_cur->opts->gsi;
+ c_port = &gsi->c_port;
+
if (!c_port) {
log_event_err("%s: gsi ctrl port %p", __func__, c_port);
return -ENODEV;
@@ -1230,13 +1305,25 @@
static unsigned int gsi_ctrl_dev_poll(struct file *fp, poll_table *wait)
{
- struct gsi_ctrl_port *c_port = container_of(fp->private_data,
- struct gsi_ctrl_port,
- ctrl_device);
- struct f_gsi *gsi = c_port_to_gsi(c_port);
+ struct gsi_ctrl_port *c_port;
+ enum ipa_usb_teth_prot prot_id =
+ *(enum ipa_usb_teth_prot *)(fp->private_data);
+ struct gsi_inst_status *inst_cur = &inst_status[prot_id];
+ struct f_gsi *gsi;
unsigned long flags;
unsigned int mask = 0;
+ mutex_lock(&inst_cur->gsi_lock);
+ if (unlikely(inst_cur->inst_exist == false)) {
+ mutex_unlock(&inst_cur->gsi_lock);
+ pr_err_ratelimited("%s: free_inst is called and being freed\n",
+ __func__);
+ return -ENODEV;
+ }
+ mutex_unlock(&inst_cur->gsi_lock);
+
+ gsi = inst_cur->opts->gsi;
+ c_port = &inst_cur->opts->gsi->c_port;
if (!c_port) {
log_event_err("%s: gsi ctrl port %p", __func__, c_port);
return -ENODEV;
@@ -2679,8 +2766,12 @@
f->name,
gadget_is_superspeed(c->cdev->gadget) ? "super" :
gadget_is_dualspeed(c->cdev->gadget) ? "dual" : "full",
- gsi->d_port.in_ep->name, gsi->d_port.out_ep->name,
- gsi->c_port.notify->name);
+ (gsi->d_port.in_ep == NULL ? "NULL" :
+ gsi->d_port.in_ep->name),
+ (gsi->d_port.out_ep == NULL ? "NULL" :
+ gsi->d_port.out_ep->name),
+ (gsi->c_port.notify == NULL ? "NULL" :
+ gsi->c_port.notify->name));
return 0;
dereg_rndis:
@@ -2827,7 +2918,11 @@
static void gsi_opts_release(struct config_item *item)
{
struct gsi_opts *opts = to_gsi_opts(item);
+ struct f_gsi *gsi;
+ gsi = opts->gsi;
+ log_event_dbg("%s: releasing %s instance\n",
+ __func__, gsi->function.name);
usb_put_function_instance(&opts->func_inst);
}
@@ -2991,26 +3086,52 @@
.ct_owner = THIS_MODULE,
};
+static void gsi_inst_clean(struct gsi_opts *opts)
+{
+ if (opts->gsi->c_port.ctrl_device.fops)
+ misc_deregister(&opts->gsi->c_port.ctrl_device);
+
+ kfree(opts->gsi);
+ kfree(opts);
+}
+
static int gsi_set_inst_name(struct usb_function_instance *fi,
const char *name)
{
- int ret, name_len;
+ int prot_id, name_len;
struct f_gsi *gsi;
char gsi_inst_name[MAX_INST_NAME_LEN + sizeof("gsi.") + 1];
- struct gsi_opts *opts = container_of(fi, struct gsi_opts, func_inst);
void *ipc_log_ctxt;
+ struct gsi_opts *opts, *opts_prev;
+
+ opts = container_of(fi, struct gsi_opts, func_inst);
name_len = strlen(name) + 1;
if (name_len > MAX_INST_NAME_LEN)
return -ENAMETOOLONG;
- ret = name_to_prot_id(name);
- if (ret < 0) {
+ prot_id = name_to_prot_id(name);
+ if (prot_id < 0) {
pr_err("%s: failed to find prot id for %s instance\n",
- __func__, name);
+ __func__, name);
return -EINVAL;
}
+ mutex_lock(&inst_status[prot_id].gsi_lock);
+ opts_prev = inst_status[prot_id].opts;
+ if (opts_prev) {
+ mutex_unlock(&inst_status[prot_id].gsi_lock);
+ pr_err("%s: prot_id = %d, prev inst do not freed yet\n",
+ __func__, prot_id);
+ return -EBUSY;
+ }
+ mutex_unlock(&inst_status[prot_id].gsi_lock);
+
+ gsi = gsi_function_init(prot_id);
+ if (IS_ERR(gsi))
+ return PTR_ERR(gsi);
+
+ opts->gsi = gsi;
/*
* create instance name with prefixing "gsi." to differentiate
* ipc log debugfs entry
@@ -3020,31 +3141,45 @@
if (!ipc_log_ctxt)
pr_err("%s: Err allocating ipc_log_ctxt for prot:%s\n",
__func__, gsi_inst_name);
-
- gsi = gsi_function_init(ret);
- if (IS_ERR(gsi)) {
- ipc_log_context_destroy(ipc_log_ctxt);
- return PTR_ERR(gsi);
- }
-
- opts->gsi = gsi;
opts->gsi->ipc_log_ctxt = ipc_log_ctxt;
+
+ /* Set instance status */
+ mutex_lock(&inst_status[prot_id].gsi_lock);
+ inst_status[prot_id].inst_exist = true;
+ inst_status[prot_id].opts = opts;
+ mutex_unlock(&inst_status[prot_id].gsi_lock);
+
return 0;
}
static void gsi_free_inst(struct usb_function_instance *f)
{
struct gsi_opts *opts = container_of(f, struct gsi_opts, func_inst);
+ enum ipa_usb_teth_prot prot_id;
+ struct f_gsi *gsi;
if (!opts->gsi)
return;
- if (opts->gsi->c_port.ctrl_device.fops)
- misc_deregister(&opts->gsi->c_port.ctrl_device);
+ prot_id = opts->gsi->prot_id;
+ gsi = opts->gsi;
+ mutex_lock(&inst_status[prot_id].gsi_lock);
+ if (opts->gsi->c_port.is_open) {
+ /* Mark instance exist as false */
+ inst_status[prot_id].inst_exist = false;
+ mutex_unlock(&inst_status[prot_id].gsi_lock);
+ log_event_err(
+ "%s: [prot_id = %d] Dev is open, free mem when dev close\n",
+ __func__, prot_id);
+ return;
+ }
ipc_log_context_destroy(opts->gsi->ipc_log_ctxt);
- kfree(opts->gsi);
- kfree(opts);
+ /* Clear instance status */
+ gsi_inst_clean(opts);
+ inst_status[prot_id].inst_exist = false;
+ inst_status[prot_id].opts = NULL;
+ mutex_unlock(&inst_status[prot_id].gsi_lock);
}
static struct usb_function_instance *gsi_alloc_inst(void)
@@ -3058,7 +3193,7 @@
opts->func_inst.set_inst_name = gsi_set_inst_name;
opts->func_inst.free_func_inst = gsi_free_inst;
config_group_init_type_name(&opts->func_inst.group, "",
- &gsi_func_type);
+ &gsi_func_type);
return &opts->func_inst;
}
@@ -3083,6 +3218,8 @@
static int fgsi_init(void)
{
+ int i;
+
ipa_usb_wq = alloc_workqueue("k_ipa_usb",
WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_FREEZABLE, 1);
if (!ipa_usb_wq) {
@@ -3090,6 +3227,9 @@
return -ENOMEM;
}
+ for (i = 0; i < IPA_USB_MAX_TETH_PROT_SIZE; i++)
+ mutex_init(&inst_status[i].gsi_lock);
+
return usb_function_register(&gsiusb_func);
}
module_init(fgsi_init);
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 14c0203..588546a 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -313,7 +313,7 @@
if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
xhci->quirks |= XHCI_BROKEN_PORT_PED;
- if (device_property_read_u32(sysdev, "snps,xhci-imod-value", &imod))
+ if (device_property_read_u32(&pdev->dev, "xhci-imod-value", &imod))
imod = 0;
if (device_property_read_u32(sysdev, "usb-core-id", &xhci->core_id))
diff --git a/drivers/usb/pd/policy_engine.c b/drivers/usb/pd/policy_engine.c
index e8961b5..aabfb41 100644
--- a/drivers/usb/pd/policy_engine.c
+++ b/drivers/usb/pd/policy_engine.c
@@ -1038,6 +1038,16 @@
static void phy_shutdown(struct usbpd *pd)
{
usbpd_dbg(&pd->dev, "shutdown");
+
+ if (pd->vconn_enabled) {
+ regulator_disable(pd->vconn);
+ pd->vconn_enabled = false;
+ }
+
+ if (pd->vbus_enabled) {
+ regulator_disable(pd->vbus);
+ pd->vbus_enabled = false;
+ }
}
static enum hrtimer_restart pd_timeout(struct hrtimer *timer)
@@ -1211,14 +1221,13 @@
case PE_SRC_READY:
pd->in_explicit_contract = true;
- if (pd->current_dr == DR_DFP) {
- /* don't start USB host until after SVDM discovery */
- if (pd->vdm_state == VDM_NONE)
- usbpd_send_svdm(pd, USBPD_SID,
- USBPD_SVDM_DISCOVER_IDENTITY,
- SVDM_CMD_TYPE_INITIATOR, 0,
- NULL, 0);
- }
+
+ if (pd->vdm_tx)
+ kick_sm(pd, 0);
+ else if (pd->current_dr == DR_DFP && pd->vdm_state == VDM_NONE)
+ usbpd_send_svdm(pd, USBPD_SID,
+ USBPD_SVDM_DISCOVER_IDENTITY,
+ SVDM_CMD_TYPE_INITIATOR, 0, NULL, 0);
kobject_uevent(&pd->dev.kobj, KOBJ_CHANGE);
complete(&pd->is_ready);
@@ -1358,6 +1367,14 @@
case PE_SNK_READY:
pd->in_explicit_contract = true;
+
+ if (pd->vdm_tx)
+ kick_sm(pd, 0);
+ else if (pd->current_dr == DR_DFP && pd->vdm_state == VDM_NONE)
+ usbpd_send_svdm(pd, USBPD_SID,
+ USBPD_SVDM_DISCOVER_IDENTITY,
+ SVDM_CMD_TYPE_INITIATOR, 0, NULL, 0);
+
kobject_uevent(&pd->dev.kobj, KOBJ_CHANGE);
complete(&pd->is_ready);
dual_role_instance_changed(pd->dual_role);
@@ -2046,6 +2063,10 @@
switch (pd->current_state) {
case PE_UNKNOWN:
+ val.intval = 0;
+ power_supply_set_property(pd->usb_psy,
+ POWER_SUPPLY_PROP_PD_IN_HARD_RESET, &val);
+
if (pd->current_pr == PR_SINK) {
usbpd_set_state(pd, PE_SNK_STARTUP);
} else if (pd->current_pr == PR_SRC) {
@@ -2208,8 +2229,11 @@
case PE_SRC_TRANSITION_TO_DEFAULT:
if (pd->vconn_enabled)
regulator_disable(pd->vconn);
+ pd->vconn_enabled = false;
+
if (pd->vbus_enabled)
regulator_disable(pd->vbus);
+ pd->vbus_enabled = false;
if (pd->current_dr != DR_DFP) {
extcon_set_state_sync(pd->extcon, EXTCON_USB, 0);
@@ -2217,24 +2241,9 @@
pd_phy_update_roles(pd->current_dr, pd->current_pr);
}
- msleep(SRC_RECOVER_TIME);
-
- pd->vbus_enabled = false;
- enable_vbus(pd);
-
- if (pd->vconn_enabled) {
- ret = regulator_enable(pd->vconn);
- if (ret) {
- usbpd_err(&pd->dev, "Unable to enable vconn\n");
- pd->vconn_enabled = false;
- }
- }
-
- val.intval = 0;
- power_supply_set_property(pd->usb_psy,
- POWER_SUPPLY_PROP_PD_IN_HARD_RESET, &val);
-
- usbpd_set_state(pd, PE_SRC_STARTUP);
+ /* PE_UNKNOWN will turn on VBUS and go back to PE_SRC_STARTUP */
+ pd->current_state = PE_UNKNOWN;
+ kick_sm(pd, SRC_RECOVER_TIME);
break;
case PE_SRC_HARD_RESET:
diff --git a/drivers/usb/pd/qpnp-pdphy.c b/drivers/usb/pd/qpnp-pdphy.c
index 735774a..6395ca2 100644
--- a/drivers/usb/pd/qpnp-pdphy.c
+++ b/drivers/usb/pd/qpnp-pdphy.c
@@ -112,7 +112,6 @@
int tx_status;
u8 frame_filter_val;
bool in_test_data_mode;
- bool rx_busy;
enum data_role data_role;
enum power_role power_role;
@@ -490,7 +489,7 @@
}
ret = pdphy_reg_read(pdphy, &val, USB_PDPHY_RX_ACKNOWLEDGE, 1);
- if (ret || val || pdphy->rx_busy) {
+ if (ret || val) {
dev_err(pdphy->dev, "%s: RX message pending\n", __func__);
return -EBUSY;
}
@@ -668,15 +667,6 @@
BIST_MODE_MASK | BIST_ENABLE, bist_mode | BIST_ENABLE);
}
-static irqreturn_t pdphy_msg_rx_irq(int irq, void *data)
-{
- struct usb_pdphy *pdphy = data;
-
- pdphy->rx_busy = true;
-
- return IRQ_WAKE_THREAD;
-}
-
static irqreturn_t pdphy_msg_rx_irq_thread(int irq, void *data)
{
u8 size, rx_status, frame_type;
@@ -733,7 +723,6 @@
false);
pdphy->rx_bytes += size + 1;
done:
- pdphy->rx_busy = false;
return IRQ_HANDLED;
}
@@ -819,7 +808,7 @@
return ret;
ret = pdphy_request_irq(pdphy, pdev->dev.of_node,
- &pdphy->msg_rx_irq, "msg-rx", pdphy_msg_rx_irq,
+ &pdphy->msg_rx_irq, "msg-rx", NULL,
pdphy_msg_rx_irq_thread, (IRQF_TRIGGER_RISING | IRQF_ONESHOT));
if (ret < 0)
return ret;
diff --git a/drivers/usb/phy/phy-msm-qusb-v2.c b/drivers/usb/phy/phy-msm-qusb-v2.c
index 68bd576..7ac7f1e 100644
--- a/drivers/usb/phy/phy-msm-qusb-v2.c
+++ b/drivers/usb/phy/phy-msm-qusb-v2.c
@@ -1049,6 +1049,21 @@
if (ret)
return ret;
+ /* ldo24 is turned on and eud is pet irrespective of cable
+ * cable connection status by boot sw. Assume usb cable is not
+ * connected and perform detach pet. If usb cable is connected,
+ * eud hw will be pet in the dpdm callback.
+ */
+ if (qphy->eud_base) {
+ if (qphy->cfg_ahb_clk)
+ clk_prepare_enable(qphy->cfg_ahb_clk);
+
+ writel_relaxed(0, qphy->eud_base + EUD_SW_ATTACH_DET);
+
+ if (qphy->cfg_ahb_clk)
+ clk_disable_unprepare(qphy->cfg_ahb_clk);
+ }
+
ret = qusb_phy_regulator_init(qphy);
if (ret)
usb_remove_phy(&qphy->phy);
diff --git a/include/dt-bindings/clock/qcom,cpucc-sdm845.h b/include/dt-bindings/clock/qcom,cpucc-sdm845.h
index db3c940..88c48e3 100644
--- a/include/dt-bindings/clock/qcom,cpucc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,cpucc-sdm845.h
@@ -27,5 +27,6 @@
#define CPU5_PERFCL_CLK 10
#define CPU6_PERFCL_CLK 11
#define CPU7_PERFCL_CLK 12
+#define L3_MISC_VOTE_CLK 13
#endif
diff --git a/include/dt-bindings/msm/msm-bus-ids.h b/include/dt-bindings/msm/msm-bus-ids.h
index e20175d..b073c5f 100644
--- a/include/dt-bindings/msm/msm-bus-ids.h
+++ b/include/dt-bindings/msm/msm-bus-ids.h
@@ -89,6 +89,13 @@
#define MSM_BUS_BCM_ACV 7037
#define MSM_BUS_BCM_ALC 7038
#define MSM_BUS_BCM_QUP0 7039
+#define MSM_BUS_BCM_CE 7040
+#define MSM_BUS_BCM_PN0 7041
+#define MSM_BUS_BCM_PN1 7042
+#define MSM_BUS_BCM_PN2 7043
+#define MSM_BUS_BCM_PN3 7044
+#define MSM_BUS_BCM_PN4 7045
+#define MSM_BUS_BCM_PN5 7046
#define MSM_BUS_RSC_APPS 8000
#define MSM_BUS_RSC_DISP 8001
@@ -252,7 +259,10 @@
#define MSM_BUS_MASTER_CAMNOC_SF_UNCOMP 148
#define MSM_BUS_MASTER_GIC 149
#define MSM_BUS_MASTER_EMMC 150
-#define MSM_BUS_MASTER_MASTER_LAST 151
+#define MSM_BUS_MASTER_SPMI_FETCHER 151
+#define MSM_BUS_MASTER_ANOC_SNOC 152
+#define MSM_BUS_MASTER_ANOC_IPA 153
+#define MSM_BUS_MASTER_MASTER_LAST 154
#define MSM_BUS_MASTER_LLCC_DISPLAY 20000
#define MSM_BUS_MASTER_MNOC_HF_MEM_NOC_DISPLAY 20001
@@ -593,7 +603,10 @@
#define MSM_BUS_SLAVE_MEM_NOC_SNOC 776
#define MSM_BUS_SLAVE_IPA_CORE 777
#define MSM_BUS_SLAVE_CAMNOC_UNCOMP 778
-#define MSM_BUS_SLAVE_LAST 779
+#define MSM_BUS_SLAVE_ANOC_SNOC 779
+#define MSM_BUS_SLAVE_ANOC_IPA 780
+#define MSM_BUS_SLAVE_EMAC_CFG 781
+#define MSM_BUS_SLAVE_LAST 782
#define MSM_BUS_SLAVE_EBI_CH0_DISPLAY 20512
#define MSM_BUS_SLAVE_LLCC_DISPLAY 20513
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 6be0299..7a2ae2f 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -128,6 +128,7 @@
CPUHP_AP_WORKQUEUE_ONLINE,
CPUHP_AP_RCUTREE_ONLINE,
CPUHP_AP_NOTIFY_ONLINE,
+ CPUHP_AP_NOTIFY_PERF_ONLINE,
CPUHP_AP_ONLINE_DYN,
CPUHP_AP_ONLINE_DYN_END = CPUHP_AP_ONLINE_DYN + 30,
CPUHP_AP_X86_HPET_ONLINE,
diff --git a/include/linux/if_bridge.h b/include/linux/if_bridge.h
index c6587c0..6638a22 100644
--- a/include/linux/if_bridge.h
+++ b/include/linux/if_bridge.h
@@ -53,6 +53,8 @@
typedef int br_should_route_hook_t(struct sk_buff *skb);
extern br_should_route_hook_t __rcu *br_should_route_hook;
+extern struct net_device *br_port_dev_get(struct net_device *dev,
+ unsigned char *addr);
#if IS_ENABLED(CONFIG_BRIDGE) && IS_ENABLED(CONFIG_BRIDGE_IGMP_SNOOPING)
int br_multicast_list_adjacent(struct net_device *dev,
diff --git a/include/linux/ipa_wdi3.h b/include/linux/ipa_wdi3.h
new file mode 100644
index 0000000..aed8c59
--- /dev/null
+++ b/include/linux/ipa_wdi3.h
@@ -0,0 +1,254 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _IPA_WDI3_H_
+#define _IPA_WDI3_H_
+
+#include <linux/ipa.h>
+
+#define IPA_HW_WDI3_TCL_DATA_CMD_ER_DESC_SIZE 32
+#define IPA_HW_WDI3_IPA2FW_ER_DESC_SIZE 8
+
+#define IPA_HW_WDI3_MAX_ER_DESC_SIZE \
+ (((IPA_HW_WDI3_TCL_DATA_CMD_ER_DESC_SIZE) > \
+ (IPA_HW_WDI3_IPA2FW_ER_DESC_SIZE)) ? \
+ (IPA_HW_WDI3_TCL_DATA_CMD_ER_DESC_SIZE) : \
+ (IPA_HW_WDI3_IPA2FW_ER_DESC_SIZE))
+
+/**
+ * struct ipa_wdi3_hdr_info - Header to install on IPA HW
+ *
+ * @hdr: header to install on IPA HW
+ * @hdr_len: length of header
+ * @dst_mac_addr_offset: destination mac address offset
+ * @hdr_type: layer two header type
+ */
+struct ipa_wdi3_hdr_info {
+ u8 *hdr;
+ u8 hdr_len;
+ u8 dst_mac_addr_offset;
+ enum ipa_hdr_l2_type hdr_type;
+};
+
+/**
+ * struct ipa_wdi3_reg_intf_in_params - parameters for uC offload
+ * interface registration
+ *
+ * @netdev_name: network interface name
+ * @hdr_info: header information
+ * @is_meta_data_valid: if meta data is valid
+ * @meta_data: meta data if any
+ * @meta_data_mask: meta data mask
+ */
+struct ipa_wdi3_reg_intf_in_params {
+ const char *netdev_name;
+ struct ipa_wdi3_hdr_info hdr_info[IPA_IP_MAX];
+ u8 is_meta_data_valid;
+ u32 meta_data;
+ u32 meta_data_mask;
+};
+
+/**
+ * struct ipa_wdi3_setup_info - WDI3 TX/Rx configuration
+ * @ipa_ep_cfg: ipa endpoint configuration
+ * @client: type of "client"
+ * @transfer_ring_base_pa: physical address of the base of the transfer ring
+ * @transfer_ring_size: size of the transfer ring
+ * @transfer_ring_doorbell_pa: physical address of the doorbell that
+ IPA uC will update the tailpointer of the transfer ring
+ * @event_ring_base_pa: physical address of the base of the event ring
+ * @event_ring_size: event ring size
+ * @event_ring_doorbell_pa: physical address of the doorbell that IPA uC
+ will update the headpointer of the event ring
+ * @num_pkt_buffers: Number of pkt buffers allocated. The size of the event
+ ring and the transfer ring has to be atleast ( num_pkt_buffers + 1)
+ * @pkt_offset: packet offset (wdi3 header length)
+ * @desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE]: Holds a cached
+ template of the desc format
+ */
+struct ipa_wdi3_setup_info {
+ struct ipa_ep_cfg ipa_ep_cfg;
+ enum ipa_client_type client;
+ dma_addr_t transfer_ring_base_pa;
+ u32 transfer_ring_size;
+ dma_addr_t transfer_ring_doorbell_pa;
+
+ dma_addr_t event_ring_base_pa;
+ u32 event_ring_size;
+ dma_addr_t event_ring_doorbell_pa;
+ u16 num_pkt_buffers;
+
+ u16 pkt_offset;
+
+ u32 desc_format_template[IPA_HW_WDI3_MAX_ER_DESC_SIZE];
+};
+
+/**
+ * struct ipa_wdi3_conn_in_params - information provided by
+ * uC offload client
+ * @notify: client callback function
+ * @priv: client cookie
+ * @tx: parameters to connect TX pipe(from IPA to WLAN)
+ * @rx: parameters to connect RX pipe(from WLAN to IPA)
+ */
+struct ipa_wdi3_conn_in_params {
+ ipa_notify_cb notify;
+ void *priv;
+ struct ipa_wdi3_setup_info tx;
+ struct ipa_wdi3_setup_info rx;
+};
+
+/**
+ * struct ipa_wdi3_conn_out_params - information provided
+ * to WLAN driver
+ * @tx_uc_db_pa: physical address of IPA uC doorbell for TX
+ * @tx_uc_db_va: virtual address of IPA uC doorbell for TX
+ * @rx_uc_db_pa: physical address of IPA uC doorbell for RX
+ */
+struct ipa_wdi3_conn_out_params {
+ dma_addr_t tx_uc_db_pa;
+ void __iomem *tx_uc_db_va;
+ dma_addr_t rx_uc_db_pa;
+};
+
+/**
+ * struct ipa_wdi3_perf_profile - To set BandWidth profile
+ *
+ * @client: type of client
+ * @max_supported_bw_mbps: maximum bandwidth needed (in Mbps)
+ */
+struct ipa_wdi3_perf_profile {
+ enum ipa_client_type client;
+ u32 max_supported_bw_mbps;
+};
+
+#if defined CONFIG_IPA || defined CONFIG_IPA3
+
+/**
+ * ipa_wdi3_reg_intf - Client should call this function to
+ * init WDI3 IPA offload data path
+ *
+ * Note: Should not be called from atomic context and only
+ * after checking IPA readiness using ipa_register_ipa_ready_cb()
+ *
+ * @Return 0 on success, negative on failure
+ */
+int ipa_wdi3_reg_intf(
+ struct ipa_wdi3_reg_intf_in_params *in);
+
+/**
+ * ipa_wdi3_dereg_intf - Client Driver should call this
+ * function to deregister before unload and after disconnect
+ *
+ * @Return 0 on success, negative on failure
+ */
+int ipa_wdi3_dereg_intf(const char *netdev_name);
+
+/**
+ * ipa_wdi3_conn_pipes - Client should call this
+ * function to connect pipes
+ *
+ * @in: [in] input parameters from client
+ * @out: [out] output params to client
+ *
+ * Note: Should not be called from atomic context and only
+ * after checking IPA readiness using ipa_register_ipa_ready_cb()
+ *
+ * @Return 0 on success, negative on failure
+ */
+int ipa_wdi3_conn_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out);
+
+/**
+ * ipa_wdi3_disconn_pipes() - Client should call this
+ * function to disconnect pipes
+ *
+ * Note: Should not be called from atomic context
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_wdi3_disconn_pipes(void);
+
+/**
+ * ipa_wdi3_enable_pipes() - Client should call this
+ * function to enable IPA offload data path
+ *
+ * Note: Should not be called from atomic context
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_wdi3_enable_pipes(void);
+
+/**
+ * ipa_wdi3_disable_pipes() - Client should call this
+ * function to disable IPA offload data path
+ *
+ * Note: Should not be called from atomic context
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_wdi3_disable_pipes(void);
+
+/**
+ * ipa_wdi3_set_perf_profile() - Client should call this function to
+ * set IPA clock bandwidth based on data rates
+ *
+ * @profile: [in] BandWidth profile to use
+ *
+ * Returns: 0 on success, negative on failure
+ */
+int ipa_wdi3_set_perf_profile(struct ipa_wdi3_perf_profile *profile);
+
+
+#else /* (CONFIG_IPA || CONFIG_IPA3) */
+
+static inline int ipa_wdi3_reg_intf(
+ struct ipa_wdi3_reg_intf_in_params *in)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_dereg_intf(const char *netdev_name)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_conn_pipes(struct ipa_wdi3_conn_in_params *in,
+ struct ipa_wdi3_conn_out_params *out)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_disconn_pipes(void)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_enable_pipes(void)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_disable_pipes(void)
+{
+ return -EPERM;
+}
+
+static inline int ipa_wdi3_set_perf_profile(
+ struct ipa_wdi3_perf_profile *profile)
+{
+ return -EPERM;
+}
+
+#endif /* CONFIG_IPA3 */
+
+#endif /* _IPA_WDI3_H_ */
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 1e07ed2..089c18b 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -96,6 +96,23 @@
MMC_LOAD_LOW,
};
+enum {
+ MMC_ERR_CMD_TIMEOUT,
+ MMC_ERR_CMD_CRC,
+ MMC_ERR_DAT_TIMEOUT,
+ MMC_ERR_DAT_CRC,
+ MMC_ERR_AUTO_CMD,
+ MMC_ERR_ADMA,
+ MMC_ERR_TUNING,
+ MMC_ERR_CMDQ_RED,
+ MMC_ERR_CMDQ_GCE,
+ MMC_ERR_CMDQ_ICCE,
+ MMC_ERR_REQ_TIMEOUT,
+ MMC_ERR_CMDQ_REQ_TIMEOUT,
+ MMC_ERR_ICE_CFG,
+ MMC_ERR_MAX,
+};
+
struct mmc_cmdq_host_ops {
int (*init)(struct mmc_host *host);
int (*enable)(struct mmc_host *host);
@@ -563,6 +580,7 @@
struct dentry *debugfs_root;
bool err_occurred;
+ u32 err_stats[MMC_ERR_MAX];
struct mmc_async_req *areq; /* active async req */
struct mmc_context_info context_info; /* async synchronization info */
diff --git a/include/net/neighbour.h b/include/net/neighbour.h
index 8b68384..ddfb742 100644
--- a/include/net/neighbour.h
+++ b/include/net/neighbour.h
@@ -62,6 +62,7 @@
NEIGH_VAR_GC_THRESH1,
NEIGH_VAR_GC_THRESH2,
NEIGH_VAR_GC_THRESH3,
+ NEIGH_VAR_PROBE,
NEIGH_VAR_MAX
};
diff --git a/include/net/netfilter/nf_conntrack.h b/include/net/netfilter/nf_conntrack.h
index d9d52c0..7815545 100644
--- a/include/net/netfilter/nf_conntrack.h
+++ b/include/net/netfilter/nf_conntrack.h
@@ -314,6 +314,7 @@
extern unsigned int nf_conntrack_htable_size;
extern seqcount_t nf_conntrack_generation;
extern unsigned int nf_conntrack_max;
+extern unsigned int nf_conntrack_pkt_threshold;
/* must be called with rcu read lock held */
static inline void
diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h
index 1ed100b..d0f76d0 100644
--- a/include/soc/qcom/spm.h
+++ b/include/soc/qcom/spm.h
@@ -125,6 +125,27 @@
return false;
}
+static inline int msm_spm_is_avs_enabled(unsigned int cpu)
+{
+ return -ENODEV;
+}
+
+static inline int msm_spm_avs_enable(unsigned int cpu)
+{
+ return -ENODEV;
+}
+
+static inline int msm_spm_avs_disable(unsigned int cpu)
+{
+ return -ENODEV;
+}
+
+static inline int msm_spm_avs_set_limit(unsigned int cpu, uint32_t min_lvl,
+ uint32_t max_lvl)
+{
+ return -ENODEV;
+}
+
static inline int msm_spm_avs_enable_irq(unsigned int cpu,
enum msm_spm_avs_irq irq)
{
diff --git a/include/sound/pcm.h b/include/sound/pcm.h
index 8495824..b6fdf29 100644
--- a/include/sound/pcm.h
+++ b/include/sound/pcm.h
@@ -106,7 +106,7 @@
#endif
#define SNDRV_PCM_IOCTL1_RESET 0
-#define SNDRV_PCM_IOCTL1_INFO 1
+/* 1 is absent slot. */
#define SNDRV_PCM_IOCTL1_CHANNEL_INFO 2
#define SNDRV_PCM_IOCTL1_GSTATE 3
#define SNDRV_PCM_IOCTL1_FIFO_SIZE 4
diff --git a/include/trace/events/cpuhp.h b/include/trace/events/cpuhp.h
index 996953d..7f4eba4 100644
--- a/include/trace/events/cpuhp.h
+++ b/include/trace/events/cpuhp.h
@@ -88,6 +88,34 @@
__entry->cpu, __entry->state, __entry->idx, __entry->ret)
);
+TRACE_EVENT(cpuhp_latency,
+
+ TP_PROTO(unsigned int cpu, unsigned int state,
+ u64 start_time, int ret),
+
+ TP_ARGS(cpu, state, start_time, ret),
+
+ TP_STRUCT__entry(
+ __field(unsigned int, cpu)
+ __field(unsigned int, state)
+ __field(u64, time)
+ __field(int, ret)
+ ),
+
+ TP_fast_assign(
+ __entry->cpu = cpu;
+ __entry->state = state;
+ __entry->time = div64_u64(sched_clock() - start_time, 1000);
+ __entry->ret = ret;
+ ),
+
+ TP_printk(" cpu:%d state:%s latency:%llu USEC ret: %d",
+ __entry->cpu, __entry->state ? "online" : "offline",
+ __entry->time, __entry->ret)
+);
+
+
+
#endif
/* This part must be outside protection */
diff --git a/include/trace/events/power.h b/include/trace/events/power.h
index cecfb8f..408fa57 100644
--- a/include/trace/events/power.h
+++ b/include/trace/events/power.h
@@ -702,9 +702,10 @@
TRACE_EVENT(memlat_dev_meas,
TP_PROTO(const char *name, unsigned int dev_id, unsigned long inst,
- unsigned long mem, unsigned long freq, unsigned int ratio),
+ unsigned long mem, unsigned long freq, unsigned int stall,
+ unsigned int ratio),
- TP_ARGS(name, dev_id, inst, mem, freq, ratio),
+ TP_ARGS(name, dev_id, inst, mem, freq, stall, ratio),
TP_STRUCT__entry(
__string(name, name)
@@ -712,6 +713,7 @@
__field(unsigned long, inst)
__field(unsigned long, mem)
__field(unsigned long, freq)
+ __field(unsigned int, stall)
__field(unsigned int, ratio)
),
@@ -721,15 +723,17 @@
__entry->inst = inst;
__entry->mem = mem;
__entry->freq = freq;
+ __entry->stall = stall;
__entry->ratio = ratio;
),
- TP_printk("dev: %s, id=%u, inst=%lu, mem=%lu, freq=%lu, ratio=%u",
+ TP_printk("dev: %s, id=%u, inst=%lu, mem=%lu, freq=%lu, stall=%u, ratio=%u",
__get_str(name),
__entry->dev_id,
__entry->inst,
__entry->mem,
__entry->freq,
+ __entry->stall,
__entry->ratio)
);
@@ -797,6 +801,29 @@
__entry->pl, __entry->flags)
);
+TRACE_EVENT(sugov_next_freq,
+ TP_PROTO(unsigned int cpu, unsigned long util, unsigned long max,
+ unsigned int freq),
+ TP_ARGS(cpu, util, max, freq),
+ TP_STRUCT__entry(
+ __field( unsigned int, cpu)
+ __field( unsigned long, util)
+ __field( unsigned long, max)
+ __field( unsigned int, freq)
+ ),
+ TP_fast_assign(
+ __entry->cpu = cpu;
+ __entry->util = util;
+ __entry->max = max;
+ __entry->freq = freq;
+ ),
+ TP_printk("cpu=%u util=%lu max=%lu freq=%u",
+ __entry->cpu,
+ __entry->util,
+ __entry->max,
+ __entry->freq)
+);
+
DECLARE_EVENT_CLASS(kpm_module,
TP_PROTO(unsigned int managed_cpus, unsigned int max_cpus),
diff --git a/include/uapi/drm/msm_drm_pp.h b/include/uapi/drm/msm_drm_pp.h
index 0765527..fcf84e3 100644
--- a/include/uapi/drm/msm_drm_pp.h
+++ b/include/uapi/drm/msm_drm_pp.h
@@ -69,7 +69,39 @@
__u32 val[PA_VLUT_SIZE];
};
-/* struct drm_msm_memcol - Memory color feature strucuture.
+#define PA_HSIC_HUE_ENABLE (1 << 0)
+#define PA_HSIC_SAT_ENABLE (1 << 1)
+#define PA_HSIC_VAL_ENABLE (1 << 2)
+#define PA_HSIC_CONT_ENABLE (1 << 3)
+/**
+ * struct drm_msm_pa_hsic - pa hsic feature structure
+ * @flags: flags for the feature customization, values can be:
+ * - PA_HSIC_HUE_ENABLE: Enable hue adjustment
+ * - PA_HSIC_SAT_ENABLE: Enable saturation adjustment
+ * - PA_HSIC_VAL_ENABLE: Enable value adjustment
+ * - PA_HSIC_CONT_ENABLE: Enable contrast adjustment
+ *
+ * @hue: hue setting
+ * @saturation: saturation setting
+ * @value: value setting
+ * @contrast: contrast setting
+ */
+#define DRM_MSM_PA_HSIC
+struct drm_msm_pa_hsic {
+ __u64 flags;
+ __u32 hue;
+ __u32 saturation;
+ __u32 value;
+ __u32 contrast;
+};
+
+#define MEMCOL_PROT_HUE (1 << 0)
+#define MEMCOL_PROT_SAT (1 << 1)
+#define MEMCOL_PROT_VAL (1 << 2)
+#define MEMCOL_PROT_CONT (1 << 3)
+#define MEMCOL_PROT_SIXZONE (1 << 4)
+#define MEMCOL_PROT_BLEND (1 << 5)
+/* struct drm_msm_memcol - Memory color feature structure.
* Skin, sky, foliage features are supported.
* @prot_flags: Bit mask for enabling protection feature.
* @color_adjust_p0: Adjustment curve.
@@ -96,6 +128,42 @@
__u32 val_region;
};
+#define DRM_MSM_SIXZONE
+#define SIXZONE_LUT_SIZE 384
+#define SIXZONE_HUE_ENABLE (1 << 0)
+#define SIXZONE_SAT_ENABLE (1 << 1)
+#define SIXZONE_VAL_ENABLE (1 << 2)
+/* struct drm_msm_sixzone_curve - Sixzone HSV adjustment curve structure.
+ * @p0: Hue adjustment.
+ * @p1: Saturation/Value adjustment.
+ */
+struct drm_msm_sixzone_curve {
+ __u32 p1;
+ __u32 p0;
+};
+
+/* struct drm_msm_sixzone - Sixzone feature structure.
+ * @flags: for feature customization, values can be:
+ * - SIXZONE_HUE_ENABLE: Enable hue adjustment
+ * - SIXZONE_SAT_ENABLE: Enable saturation adjustment
+ * - SIXZONE_VAL_ENABLE: Enable value adjustment
+ * @threshold: threshold qualifier.
+ * @adjust_p0: Adjustment curve.
+ * @adjust_p1: Adjustment curve.
+ * @sat_hold: Saturation hold info.
+ * @val_hold: Value hold info.
+ * @curve: HSV adjustment curve lut.
+ */
+struct drm_msm_sixzone {
+ __u64 flags;
+ __u32 threshold;
+ __u32 adjust_p0;
+ __u32 adjust_p1;
+ __u32 sat_hold;
+ __u32 val_hold;
+ struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE];
+};
+
#define GAMUT_3D_MODE_17 1
#define GAMUT_3D_MODE_5 2
#define GAMUT_3D_MODE_13 3
diff --git a/include/uapi/linux/netfilter/nf_conntrack_common.h b/include/uapi/linux/netfilter/nf_conntrack_common.h
index 6d074d1..1d7cd67 100644
--- a/include/uapi/linux/netfilter/nf_conntrack_common.h
+++ b/include/uapi/linux/netfilter/nf_conntrack_common.h
@@ -113,8 +113,11 @@
IPCT_NATSEQADJ = IPCT_SEQADJ,
IPCT_SECMARK, /* new security mark has been set */
IPCT_LABEL, /* new connlabel has been set */
+ IPCT_COUNTER, /* Packet counters have matched. */
};
+#define IPCT_COUNTER IPCT_COUNTER
+
enum ip_conntrack_expect_events {
IPEXP_NEW, /* new expectation */
IPEXP_DESTROY, /* destroyed expectation */
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index e5a2e68..2c5810a 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -674,6 +674,7 @@
#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
+#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
@@ -977,4 +978,19 @@
#define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */
#define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */
+/* L1 PM Substates */
+#define PCI_L1SS_CAP 4 /* capability register */
+#define PCI_L1SS_CAP_PCIPM_L1_2 1 /* PCI PM L1.2 Support */
+#define PCI_L1SS_CAP_PCIPM_L1_1 2 /* PCI PM L1.1 Support */
+#define PCI_L1SS_CAP_ASPM_L1_2 4 /* ASPM L1.2 Support */
+#define PCI_L1SS_CAP_ASPM_L1_1 8 /* ASPM L1.1 Support */
+#define PCI_L1SS_CAP_L1_PM_SS 16 /* L1 PM Substates Support */
+#define PCI_L1SS_CTL1 8 /* Control Register 1 */
+#define PCI_L1SS_CTL1_PCIPM_L1_2 1 /* PCI PM L1.2 Enable */
+#define PCI_L1SS_CTL1_PCIPM_L1_1 2 /* PCI PM L1.1 Support */
+#define PCI_L1SS_CTL1_ASPM_L1_2 4 /* ASPM L1.2 Support */
+#define PCI_L1SS_CTL1_ASPM_L1_1 8 /* ASPM L1.1 Support */
+#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000F
+#define PCI_L1SS_CTL2 0xC /* Control Register 2 */
+
#endif /* LINUX_PCI_REGS_H */
diff --git a/kernel/cpu.c b/kernel/cpu.c
index d2df1ce..0d10ef5 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -898,6 +898,7 @@
struct cpuhp_cpu_state *st = per_cpu_ptr(&cpuhp_state, cpu);
int prev_state, ret = 0;
bool hasdied = false;
+ u64 start_time = 0;
if (num_online_cpus() == 1)
return -EBUSY;
@@ -909,6 +910,8 @@
return -EBUSY;
cpu_hotplug_begin();
+ if (trace_cpuhp_latency_enabled())
+ start_time = sched_clock();
cpuhp_tasks_frozen = tasks_frozen;
@@ -947,6 +950,7 @@
hasdied = prev_state != st->state && st->state == CPUHP_OFFLINE;
out:
+ trace_cpuhp_latency(cpu, 0, start_time, ret);
cpu_hotplug_done();
/* This post dead nonsense must die */
if (!ret && hasdied)
@@ -1020,8 +1024,11 @@
struct cpuhp_cpu_state *st = per_cpu_ptr(&cpuhp_state, cpu);
struct task_struct *idle;
int ret = 0;
+ u64 start_time = 0;
cpu_hotplug_begin();
+ if (trace_cpuhp_latency_enabled())
+ start_time = sched_clock();
if (!cpu_present(cpu)) {
ret = -EINVAL;
@@ -1069,6 +1076,7 @@
target = min((int)target, CPUHP_BRINGUP_CPU);
ret = cpuhp_up_callbacks(cpu, st, target);
out:
+ trace_cpuhp_latency(cpu, 1, start_time, ret);
cpu_hotplug_done();
return ret;
}
diff --git a/kernel/locking/osq_lock.c b/kernel/locking/osq_lock.c
index 99b8d99..0befa20 100644
--- a/kernel/locking/osq_lock.c
+++ b/kernel/locking/osq_lock.c
@@ -106,6 +106,19 @@
prev = decode_cpu(old);
node->prev = prev;
+
+ /*
+ * osq_lock() unqueue
+ *
+ * node->prev = prev osq_wait_next()
+ * WMB MB
+ * prev->next = node next->prev = prev // unqueue-C
+ *
+ * Here 'node->prev' and 'next->prev' are the same variable and we need
+ * to ensure these stores happen in-order to avoid corrupting the list.
+ */
+ smp_wmb();
+
WRITE_ONCE(prev->next, node);
/*
diff --git a/kernel/locking/rwsem-xadd.c b/kernel/locking/rwsem-xadd.c
index 2337b4b..a4112df 100644
--- a/kernel/locking/rwsem-xadd.c
+++ b/kernel/locking/rwsem-xadd.c
@@ -574,6 +574,33 @@
WAKE_Q(wake_q);
/*
+ * __rwsem_down_write_failed_common(sem)
+ * rwsem_optimistic_spin(sem)
+ * osq_unlock(sem->osq)
+ * ...
+ * atomic_long_add_return(&sem->count)
+ *
+ * - VS -
+ *
+ * __up_write()
+ * if (atomic_long_sub_return_release(&sem->count) < 0)
+ * rwsem_wake(sem)
+ * osq_is_locked(&sem->osq)
+ *
+ * And __up_write() must observe !osq_is_locked() when it observes the
+ * atomic_long_add_return() in order to not miss a wakeup.
+ *
+ * This boils down to:
+ *
+ * [S.rel] X = 1 [RmW] r0 = (Y += 0)
+ * MB RMB
+ * [RmW] Y += 1 [L] r1 = X
+ *
+ * exists (r0=1 /\ r1=0)
+ */
+ smp_rmb();
+
+ /*
* If a spinner is present, it is not necessary to do the wakeup.
* Try to do wakeup only if the trylock succeeds to minimize
* spinlock contention which may introduce too much delay in the
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 401d0c1..58c4341 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -1218,7 +1218,6 @@
if (cpumask_test_cpu(task_cpu(p), &allowed_mask))
goto out;
- dest_cpu = cpumask_any_and(cpu_valid_mask, new_mask);
if (task_running(rq, p) || p->state == TASK_WAKING) {
struct migration_arg arg = { p, dest_cpu };
/* Need help from migration thread: drop lock and wait. */
diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c
index 2eb966c..801c8f0 100644
--- a/kernel/sched/cpufreq_schedutil.c
+++ b/kernel/sched/cpufreq_schedutil.c
@@ -86,6 +86,7 @@
static DEFINE_PER_CPU(struct sugov_cpu, sugov_cpu);
static unsigned int stale_ns;
+static DEFINE_PER_CPU(struct sugov_tunables *, cached_tunables);
/************************ Governor internals ***********************/
@@ -162,6 +163,7 @@
policy->cpuinfo.max_freq : policy->cur;
freq = (freq + (freq >> 2)) * util / max;
+ trace_sugov_next_freq(policy->cpu, util, max, freq);
if (freq == sg_policy->cached_raw_freq && sg_policy->next_freq != UINT_MAX)
return sg_policy->next_freq;
@@ -375,7 +377,7 @@
j_util = j_sg_cpu->util;
j_max = j_sg_cpu->max;
- if (j_util * max > j_max * util) {
+ if (j_util * max >= j_max * util) {
util = j_util;
max = j_max;
}
@@ -513,7 +515,7 @@
{
struct sugov_tunables *tunables = to_sugov_tunables(attr_set);
- return sprintf(buf, "%u\n", tunables->hispeed_load);
+ return scnprintf(buf, PAGE_SIZE, "%u\n", tunables->hispeed_load);
}
static ssize_t hispeed_load_store(struct gov_attr_set *attr_set,
@@ -533,7 +535,7 @@
{
struct sugov_tunables *tunables = to_sugov_tunables(attr_set);
- return sprintf(buf, "%u\n", tunables->hispeed_freq);
+ return scnprintf(buf, PAGE_SIZE, "%u\n", tunables->hispeed_freq);
}
static ssize_t hispeed_freq_store(struct gov_attr_set *attr_set,
@@ -565,7 +567,7 @@
{
struct sugov_tunables *tunables = to_sugov_tunables(attr_set);
- return sprintf(buf, "%u\n", tunables->pl);
+ return scnprintf(buf, PAGE_SIZE, "%u\n", tunables->pl);
}
static ssize_t pl_store(struct gov_attr_set *attr_set, const char *buf,
@@ -681,6 +683,31 @@
return tunables;
}
+static void sugov_tunables_save(struct cpufreq_policy *policy,
+ struct sugov_tunables *tunables)
+{
+ int cpu;
+ struct sugov_tunables *cached = per_cpu(cached_tunables, policy->cpu);
+
+ if (!have_governor_per_policy())
+ return;
+
+ if (!cached) {
+ cached = kzalloc(sizeof(*tunables), GFP_KERNEL);
+ if (!cached) {
+ pr_warn("Couldn't allocate tunables for caching\n");
+ return;
+ }
+ for_each_cpu(cpu, policy->related_cpus)
+ per_cpu(cached_tunables, cpu) = cached;
+ }
+
+ cached->pl = tunables->pl;
+ cached->hispeed_load = tunables->hispeed_load;
+ cached->hispeed_freq = tunables->hispeed_freq;
+ cached->rate_limit_us = tunables->rate_limit_us;
+}
+
static void sugov_tunables_free(struct sugov_tunables *tunables)
{
if (!have_governor_per_policy())
@@ -689,6 +716,23 @@
kfree(tunables);
}
+static void sugov_tunables_restore(struct cpufreq_policy *policy)
+{
+ struct sugov_policy *sg_policy = policy->governor_data;
+ struct sugov_tunables *tunables = sg_policy->tunables;
+ struct sugov_tunables *cached = per_cpu(cached_tunables, policy->cpu);
+
+ if (!cached)
+ return;
+
+ tunables->pl = cached->pl;
+ tunables->hispeed_load = cached->hispeed_load;
+ tunables->hispeed_freq = cached->hispeed_freq;
+ tunables->rate_limit_us = cached->rate_limit_us;
+ sg_policy->freq_update_delay_ns =
+ tunables->rate_limit_us * NSEC_PER_USEC;
+}
+
static int sugov_init(struct cpufreq_policy *policy)
{
struct sugov_policy *sg_policy;
@@ -743,6 +787,8 @@
sg_policy->tunables = tunables;
stale_ns = sched_ravg_window + (sched_ravg_window >> 3);
+ sugov_tunables_restore(policy);
+
ret = kobject_init_and_add(&tunables->attr_set.kobj, &sugov_tunables_ktype,
get_governor_parent_kobj(policy), "%s",
schedutil_gov.name);
@@ -782,8 +828,10 @@
count = gov_attr_set_put(&tunables->attr_set, &sg_policy->tunables_hook);
policy->governor_data = NULL;
- if (!count)
+ if (!count) {
+ sugov_tunables_save(policy, tunables);
sugov_tunables_free(tunables);
+ }
mutex_unlock(&global_tunables_lock);
diff --git a/kernel/sched/cputime.c b/kernel/sched/cputime.c
index 0d8cc06..e4f48f1 100644
--- a/kernel/sched/cputime.c
+++ b/kernel/sched/cputime.c
@@ -71,12 +71,12 @@
else
account = false;
+ u64_stats_update_end(&irqtime->sync);
+
if (account)
sched_account_irqtime(cpu, curr, delta, wallclock);
else if (curr != this_cpu_ksoftirqd())
sched_account_irqstart(cpu, curr, wallclock);
-
- u64_stats_update_end(&irqtime->sync);
}
EXPORT_SYMBOL_GPL(irqtime_account_irq);
diff --git a/kernel/sched/walt.c b/kernel/sched/walt.c
index 316c276..f50add7 100644
--- a/kernel/sched/walt.c
+++ b/kernel/sched/walt.c
@@ -2833,14 +2833,11 @@
rcu_read_unlock();
}
- if (cpu_max_table_freq[cpu] &&
- unlikely(thermal_max_freq && thermal_max_freq
- != cpu_max_table_freq[cpu])) {
+ if (cpu_max_table_freq[cpu])
return div64_ul(thermal_max_freq * max_cap[cpu],
cpu_max_table_freq[cpu]);
- } else {
+ else
return rq->cpu_capacity_orig;
- }
}
static DEFINE_SPINLOCK(cpu_freq_min_max_lock);
diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c
index ed0dd33..9218931 100644
--- a/net/bridge/br_if.c
+++ b/net/bridge/br_if.c
@@ -655,3 +655,34 @@
if (mask & BR_AUTO_MASK)
nbp_update_port_count(br);
}
+
+/* br_port_dev_get()
+ * Using the given addr, identify the port to which it is reachable,
+ * returing a reference to the net device associated with that port.
+ *
+ * NOTE: Return NULL if given dev is not a bridge or
+ * the mac has no associated port
+ */
+struct net_device *br_port_dev_get(struct net_device *dev, unsigned char *addr)
+{
+ struct net_bridge_fdb_entry *fdbe;
+ struct net_bridge *br;
+ struct net_device *netdev = NULL;
+
+ /* Is this a bridge? */
+ if (!(dev->priv_flags & IFF_EBRIDGE))
+ return NULL;
+
+ br = netdev_priv(dev);
+
+ /* Lookup the fdb entry and get reference to the port dev */
+ rcu_read_lock();
+ fdbe = __br_fdb_get(br, addr, 0);
+ if (fdbe && fdbe->dst) {
+ netdev = fdbe->dst->dev; /* port device */
+ dev_hold(netdev);
+ }
+ rcu_read_unlock();
+ return netdev;
+}
+EXPORT_SYMBOL(br_port_dev_get);
diff --git a/net/core/neighbour.c b/net/core/neighbour.c
index 227c249..62893eb 100644
--- a/net/core/neighbour.c
+++ b/net/core/neighbour.c
@@ -56,6 +56,7 @@
static void neigh_update_notify(struct neighbour *neigh);
static int pneigh_ifdown(struct neigh_table *tbl, struct net_device *dev);
+static unsigned int neigh_probe_enable;
#ifdef CONFIG_PROC_FS
static const struct file_operations neigh_stat_seq_fops;
#endif
@@ -1258,9 +1259,20 @@
{
struct neighbour *neigh = __neigh_lookup(tbl, saddr, dev,
lladdr || !dev->addr_len);
- if (neigh)
- neigh_update(neigh, lladdr, NUD_STALE,
- NEIGH_UPDATE_F_OVERRIDE);
+ if (neigh) {
+ if (neigh_probe_enable) {
+ if (!(neigh->nud_state == NUD_REACHABLE)) {
+ neigh_update(neigh, lladdr, NUD_STALE,
+ NEIGH_UPDATE_F_OVERRIDE);
+ write_lock(&neigh->lock);
+ neigh_probe(neigh);
+ neigh_update_notify(neigh);
+ }
+ } else {
+ neigh_update(neigh, lladdr, NUD_STALE,
+ NEIGH_UPDATE_F_OVERRIDE);
+ }
+ }
return neigh;
}
EXPORT_SYMBOL(neigh_event_ns);
@@ -3107,6 +3119,12 @@
.extra2 = &int_max,
.proc_handler = proc_dointvec_minmax,
},
+ [NEIGH_VAR_PROBE] = {
+ .procname = "neigh_probe",
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = proc_dointvec,
+ },
{},
},
};
@@ -3142,6 +3160,7 @@
t->neigh_vars[NEIGH_VAR_GC_THRESH1].data = &tbl->gc_thresh1;
t->neigh_vars[NEIGH_VAR_GC_THRESH2].data = &tbl->gc_thresh2;
t->neigh_vars[NEIGH_VAR_GC_THRESH3].data = &tbl->gc_thresh3;
+ t->neigh_vars[NEIGH_VAR_PROBE].data = &neigh_probe_enable;
}
if (handler) {
diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c
index ff2d32e..d5b49fc 100644
--- a/net/netfilter/nf_conntrack_core.c
+++ b/net/netfilter/nf_conntrack_core.c
@@ -181,6 +181,9 @@
unsigned int nf_conntrack_max __read_mostly;
seqcount_t nf_conntrack_generation __read_mostly;
+unsigned int nf_conntrack_pkt_threshold __read_mostly;
+EXPORT_SYMBOL(nf_conntrack_pkt_threshold);
+
DEFINE_PER_CPU(struct nf_conn, nf_conntrack_untracked);
EXPORT_PER_CPU_SYMBOL(nf_conntrack_untracked);
@@ -1434,6 +1437,9 @@
unsigned long extra_jiffies,
int do_acct)
{
+ struct nf_conn_acct *acct;
+ u64 pkts;
+
NF_CT_ASSERT(skb);
/* Only update if this is not a fixed timeout */
@@ -1446,8 +1452,27 @@
ct->timeout = extra_jiffies;
acct:
- if (do_acct)
- nf_ct_acct_update(ct, ctinfo, skb->len);
+ if (do_acct) {
+ acct = nf_conn_acct_find(ct);
+ if (acct) {
+ struct nf_conn_counter *counter = acct->counter;
+
+ atomic64_inc(&counter[CTINFO2DIR(ctinfo)].packets);
+ atomic64_add(skb->len, &counter
+ [CTINFO2DIR(ctinfo)].bytes);
+
+ pkts =
+ atomic64_read(&counter[CTINFO2DIR(ctinfo)].packets) +
+ atomic64_read(&counter[!CTINFO2DIR(ctinfo)].packets);
+ /* Report if the packet threshold is reached. */
+ if ((nf_conntrack_pkt_threshold > 0) &&
+ (pkts == nf_conntrack_pkt_threshold)) {
+ nf_conntrack_event_cache(IPCT_COUNTER, ct);
+ nf_conntrack_event_cache(IPCT_PROTOINFO, ct);
+ nf_ct_deliver_cached_events(ct);
+ }
+ }
+ }
}
EXPORT_SYMBOL_GPL(__nf_ct_refresh_acct);
diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c
index 04111c1..08b24a9 100644
--- a/net/netfilter/nf_conntrack_netlink.c
+++ b/net/netfilter/nf_conntrack_netlink.c
@@ -729,6 +729,10 @@
if (events & (1 << IPCT_SEQADJ) &&
ctnetlink_dump_ct_seq_adj(skb, ct) < 0)
goto nla_put_failure;
+
+ if (events & (1 << IPCT_COUNTER) &&
+ ctnetlink_dump_acct(skb, ct, 0) < 0)
+ goto nla_put_failure;
}
#ifdef CONFIG_NF_CONNTRACK_MARK
diff --git a/net/netfilter/nf_conntrack_standalone.c b/net/netfilter/nf_conntrack_standalone.c
index 5f446cd..2f1014e 100644
--- a/net/netfilter/nf_conntrack_standalone.c
+++ b/net/netfilter/nf_conntrack_standalone.c
@@ -517,6 +517,14 @@
.mode = 0644,
.proc_handler = proc_dointvec,
},
+ {
+ .procname = "nf_conntrack_pkt_threshold",
+ .data = &nf_conntrack_pkt_threshold,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = proc_dointvec,
+ },
+
{ }
};
diff --git a/net/netfilter/nf_nat_sip.c b/net/netfilter/nf_nat_sip.c
index 791fac4..2f2414e2 100644
--- a/net/netfilter/nf_nat_sip.c
+++ b/net/netfilter/nf_nat_sip.c
@@ -111,13 +111,26 @@
newaddr = ct->tuplehash[!dir].tuple.src.u3;
newport = ct_sip_info->forced_dport ? :
ct->tuplehash[!dir].tuple.src.u.udp.port;
+ } else if (nf_inet_addr_cmp(&ct->tuplehash[dir].tuple.src.u3, addr) &&
+ ct->tuplehash[dir].tuple.src.u.udp.port != port) {
+ newaddr = ct->tuplehash[!dir].tuple.dst.u3;
+ newport = 0;
+ } else if (nf_inet_addr_cmp(&ct->tuplehash[dir].tuple.dst.u3, addr) &&
+ ct->tuplehash[dir].tuple.dst.u.udp.port != port) {
+ newaddr = ct->tuplehash[!dir].tuple.src.u3;
+ newport = 0;
} else
return 1;
if (nf_inet_addr_cmp(&newaddr, addr) && newport == port)
return 1;
- buflen = sip_sprintf_addr_port(ct, buffer, &newaddr, ntohs(newport));
+ if (newport == 0)
+ buflen = sip_sprintf_addr(ct, buffer, &newaddr, false);
+ else
+ buflen = sip_sprintf_addr_port(ct, buffer, &newaddr,
+ ntohs(newport));
+
return mangle_packet(skb, protoff, dataoff, dptr, datalen,
matchoff, matchlen, buffer, buflen);
}
diff --git a/net/wireless/db.txt b/net/wireless/db.txt
index cad82a4..f323faf 100644
--- a/net/wireless/db.txt
+++ b/net/wireless/db.txt
@@ -737,7 +737,7 @@
(5170 - 5250 @ 80), (23)
(5735 - 5835 @ 80), (23)
# 60 gHz band channels 1-4, ref: Etsi En 302 567
- ((57000 - 66000 @ 2160), (40)
+ (57000 - 66000 @ 2160), (40)
country JP: DFS-JP
(2402 - 2482 @ 40), (20)
diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index adf7d03..3dd7b21 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -560,6 +560,14 @@
[NL80211_NAN_SRF_MAC_ADDRS] = { .type = NLA_NESTED },
};
+/* policy for packet pattern attributes */
+static const struct nla_policy
+nl80211_packet_pattern_policy[MAX_NL80211_PKTPAT + 1] = {
+ [NL80211_PKTPAT_MASK] = { .type = NLA_BINARY, },
+ [NL80211_PKTPAT_PATTERN] = { .type = NLA_BINARY, },
+ [NL80211_PKTPAT_OFFSET] = { .type = NLA_U32 },
+};
+
static int nl80211_prepare_wdev_dump(struct sk_buff *skb,
struct netlink_callback *cb,
struct cfg80211_registered_device **rdev,
@@ -10233,7 +10241,7 @@
u8 *mask_pat;
nla_parse(pat_tb, MAX_NL80211_PKTPAT, nla_data(pat),
- nla_len(pat), NULL);
+ nla_len(pat), nl80211_packet_pattern_policy);
err = -EINVAL;
if (!pat_tb[NL80211_PKTPAT_MASK] ||
!pat_tb[NL80211_PKTPAT_PATTERN])
@@ -10483,7 +10491,7 @@
u8 *mask_pat;
nla_parse(pat_tb, MAX_NL80211_PKTPAT, nla_data(pat),
- nla_len(pat), NULL);
+ nla_len(pat), nl80211_packet_pattern_policy);
if (!pat_tb[NL80211_PKTPAT_MASK] ||
!pat_tb[NL80211_PKTPAT_PATTERN])
return -EINVAL;
diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c
index 6faddfb..f8d0bd8 100644
--- a/sound/core/pcm_lib.c
+++ b/sound/core/pcm_lib.c
@@ -1857,8 +1857,6 @@
unsigned int cmd, void *arg)
{
switch (cmd) {
- case SNDRV_PCM_IOCTL1_INFO:
- return 0;
case SNDRV_PCM_IOCTL1_RESET:
return snd_pcm_lib_ioctl_reset(substream, arg);
case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index 3d9ff6d..8e5649a 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -197,7 +197,6 @@
int snd_pcm_info(struct snd_pcm_substream *substream, struct snd_pcm_info *info)
{
- struct snd_pcm_runtime *runtime;
struct snd_pcm *pcm = substream->pcm;
struct snd_pcm_str *pstr = substream->pstr;
@@ -213,12 +212,7 @@
info->subdevices_count = pstr->substream_count;
info->subdevices_avail = pstr->substream_count - pstr->substream_opened;
strlcpy(info->subname, substream->name, sizeof(info->subname));
- runtime = substream->runtime;
- /* AB: FIXME!!! This is definitely nonsense */
- if (runtime) {
- info->sync = runtime->sync;
- substream->ops->ioctl(substream, SNDRV_PCM_IOCTL1_INFO, info);
- }
+
return 0;
}
diff --git a/sound/soc/soc-ops.c b/sound/soc/soc-ops.c
index 19d6af8..fc9c9b0 100644
--- a/sound/soc/soc-ops.c
+++ b/sound/soc/soc-ops.c
@@ -379,7 +379,7 @@
unsigned int rshift = mc->rshift;
int max = mc->max;
int min = mc->min;
- int mask = (1 << (fls(min + max) - 1)) - 1;
+ unsigned int mask = (1 << (fls(min + max) - 1)) - 1;
unsigned int val;
int ret;
@@ -424,7 +424,7 @@
unsigned int rshift = mc->rshift;
int max = mc->max;
int min = mc->min;
- int mask = (1 << (fls(min + max) - 1)) - 1;
+ unsigned int mask = (1 << (fls(min + max) - 1)) - 1;
int err = 0;
unsigned int val, val_mask, val2 = 0;