| /* |
| * Copyright © 2006-2010 Intel Corporation |
| * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: |
| * Eric Anholt <eric@anholt.net> |
| * Dave Airlie <airlied@linux.ie> |
| * Jesse Barnes <jesse.barnes@intel.com> |
| * Chris Wilson <chris@chris-wilson.co.uk> |
| */ |
| |
| #include "intel_drv.h" |
| |
| #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ |
| |
| void |
| intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
| struct drm_display_mode *adjusted_mode) |
| { |
| adjusted_mode->hdisplay = fixed_mode->hdisplay; |
| adjusted_mode->hsync_start = fixed_mode->hsync_start; |
| adjusted_mode->hsync_end = fixed_mode->hsync_end; |
| adjusted_mode->htotal = fixed_mode->htotal; |
| |
| adjusted_mode->vdisplay = fixed_mode->vdisplay; |
| adjusted_mode->vsync_start = fixed_mode->vsync_start; |
| adjusted_mode->vsync_end = fixed_mode->vsync_end; |
| adjusted_mode->vtotal = fixed_mode->vtotal; |
| |
| adjusted_mode->clock = fixed_mode->clock; |
| |
| drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
| } |
| |
| /* adjusted_mode has been preset to be the panel's fixed mode */ |
| void |
| intel_pch_panel_fitting(struct drm_device *dev, |
| int fitting_mode, |
| struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode) |
| { |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| int x, y, width, height; |
| |
| x = y = width = height = 0; |
| |
| /* Native modes don't need fitting */ |
| if (adjusted_mode->hdisplay == mode->hdisplay && |
| adjusted_mode->vdisplay == mode->vdisplay) |
| goto done; |
| |
| switch (fitting_mode) { |
| case DRM_MODE_SCALE_CENTER: |
| width = mode->hdisplay; |
| height = mode->vdisplay; |
| x = (adjusted_mode->hdisplay - width + 1)/2; |
| y = (adjusted_mode->vdisplay - height + 1)/2; |
| break; |
| |
| case DRM_MODE_SCALE_ASPECT: |
| /* Scale but preserve the aspect ratio */ |
| { |
| u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
| u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; |
| if (scaled_width > scaled_height) { /* pillar */ |
| width = scaled_height / mode->vdisplay; |
| x = (adjusted_mode->hdisplay - width + 1) / 2; |
| y = 0; |
| height = adjusted_mode->vdisplay; |
| } else if (scaled_width < scaled_height) { /* letter */ |
| height = scaled_width / mode->hdisplay; |
| y = (adjusted_mode->vdisplay - height + 1) / 2; |
| x = 0; |
| width = adjusted_mode->hdisplay; |
| } else { |
| x = y = 0; |
| width = adjusted_mode->hdisplay; |
| height = adjusted_mode->vdisplay; |
| } |
| } |
| break; |
| |
| default: |
| case DRM_MODE_SCALE_FULLSCREEN: |
| x = y = 0; |
| width = adjusted_mode->hdisplay; |
| height = adjusted_mode->vdisplay; |
| break; |
| } |
| |
| done: |
| dev_priv->pch_pf_pos = (x << 16) | y; |
| dev_priv->pch_pf_size = (width << 16) | height; |
| } |
| |
| static int is_backlight_combination_mode(struct drm_device *dev) |
| { |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| |
| if (INTEL_INFO(dev)->gen >= 4) |
| return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE; |
| |
| if (IS_GEN2(dev)) |
| return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; |
| |
| return 0; |
| } |
| |
| u32 intel_panel_get_max_backlight(struct drm_device *dev) |
| { |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| u32 max; |
| |
| if (HAS_PCH_SPLIT(dev)) { |
| max = I915_READ(BLC_PWM_PCH_CTL2) >> 16; |
| } else { |
| max = I915_READ(BLC_PWM_CTL); |
| if (IS_PINEVIEW(dev)) { |
| max >>= 17; |
| } else { |
| max >>= 16; |
| if (INTEL_INFO(dev)->gen < 4) |
| max &= ~1; |
| } |
| |
| if (is_backlight_combination_mode(dev)) |
| max *= 0xff; |
| } |
| |
| if (max == 0) { |
| /* XXX add code here to query mode clock or hardware clock |
| * and program max PWM appropriately. |
| */ |
| DRM_ERROR("fixme: max PWM is zero.\n"); |
| max = 1; |
| } |
| |
| DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max); |
| return max; |
| } |
| |
| u32 intel_panel_get_backlight(struct drm_device *dev) |
| { |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| u32 val; |
| |
| if (HAS_PCH_SPLIT(dev)) { |
| val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
| } else { |
| val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
| if (IS_PINEVIEW(dev)) |
| val >>= 1; |
| |
| if (is_backlight_combination_mode(dev)){ |
| u8 lbpc; |
| |
| val &= ~1; |
| pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc); |
| val *= lbpc; |
| val >>= 1; |
| } |
| } |
| |
| DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); |
| return val; |
| } |
| |
| static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level) |
| { |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; |
| I915_WRITE(BLC_PWM_CPU_CTL, val | level); |
| } |
| |
| void intel_panel_set_backlight(struct drm_device *dev, u32 level) |
| { |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| u32 tmp; |
| |
| DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); |
| |
| if (HAS_PCH_SPLIT(dev)) |
| return intel_pch_panel_set_backlight(dev, level); |
| |
| if (is_backlight_combination_mode(dev)){ |
| u32 max = intel_panel_get_max_backlight(dev); |
| u8 lpbc; |
| |
| lpbc = level * 0xfe / max + 1; |
| level /= lpbc; |
| pci_write_config_byte(dev->pdev, PCI_LBPC, lpbc); |
| } |
| |
| tmp = I915_READ(BLC_PWM_CTL); |
| if (IS_PINEVIEW(dev)) { |
| tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1); |
| level <<= 1; |
| } else |
| tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK; |
| I915_WRITE(BLC_PWM_CTL, tmp | level); |
| } |