commit d1f317d8254413447bcd6b6adbde24a985d256c2
author Vineet Gupta <vgupta@synopsys.com> Mon Apr 06 17:23:57 2015 +0530
committer Vineet Gupta <vgupta@synopsys.com> Mon Jun 22 14:06:55 2015 +0530
tree 4b0ba3c3a5335e844edbf97403c12b88b04f69d5
parent d7a512bfe0be3790bae8465b4cb6c1bbca03c616

ARCv2: MMUv4: cache programming model changes

Caveats about cache flush on ARCv2 based cores

- dcache is PIPT so paddr is sufficient for cache maintenance ops (no
  need to setup PTAG reg

- icache is still VIPT but only aliasing configs need PTAG setup

So basically this is departure from MMU-v3 which always need vaddr in
line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG,
IC_PTAG respectively.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

arch/arc/Kconfig

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 6568977..974ed90 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -223,7 +223,7 @@
 
 config ARC_CACHE_VIPT_ALIASING
 	bool "Support VIPT Aliasing D$"
-	depends on ARC_HAS_DCACHE
+	depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
 	default n
 
 endif	#ARC_CACHE