| /* |
| * This file is part of wlcore |
| * |
| * Copyright (C) 2011 Texas Instruments Inc. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License |
| * version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, but |
| * WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| * General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| * 02110-1301 USA |
| * |
| */ |
| |
| #ifndef __REG_H__ |
| #define __REG_H__ |
| |
| #define WL18XX_REGISTERS_BASE 0x00800000 |
| #define WL18XX_CODE_BASE 0x00000000 |
| #define WL18XX_DATA_BASE 0x00400000 |
| #define WL18XX_DOUBLE_BUFFER_BASE 0x00600000 |
| #define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000 |
| #define WL18XX_PHY_BASE 0x00900000 |
| #define WL18XX_TOP_OCP_BASE 0x00A00000 |
| #define WL18XX_PACKET_RAM_BASE 0x00B00000 |
| #define WL18XX_HOST_BASE 0x00C00000 |
| |
| #define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000 |
| |
| #define WL18XX_REG_BOOT_PART_START 0x00802000 |
| #define WL18XX_REG_BOOT_PART_SIZE 0x00014578 |
| |
| #define WL18XX_PHY_INIT_MEM_ADDR 0x80926000 |
| |
| #define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE) |
| #define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000) |
| #define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000) |
| #define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000) |
| #define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000) |
| #define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000) |
| #define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000) |
| #define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000) |
| #define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000) |
| #define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000) |
| #define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800) |
| #define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00) |
| #define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000) |
| #define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400) |
| |
| #define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004) |
| #define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8) |
| #define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0) |
| #define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074) |
| #define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078) |
| #define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC) |
| |
| #define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C) |
| |
| #define WL18XX_SLV_MEM_DATA (WL18XX_HOST_BASE + 0x0018) |
| #define WL18XX_SLV_REG_DATA (WL18XX_HOST_BASE + 0x0008) |
| |
| /* Scratch Pad registers*/ |
| #define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC) |
| #define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0) |
| #define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4) |
| #define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8) |
| #define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC) |
| #define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504) |
| #define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500) |
| #define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508) |
| #define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510) |
| #define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C) |
| #define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514) |
| #define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518) |
| #define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C) |
| #define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520) |
| |
| /* Spare registers*/ |
| #define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194) |
| #define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198) |
| #define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C) |
| #define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0) |
| #define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4) |
| #define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8) |
| #define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC) |
| #define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0) |
| #define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524) |
| #define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528) |
| #define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C) |
| #define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530) |
| #define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534) |
| #define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538) |
| #define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C) |
| #define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540) |
| |
| #define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0) |
| #define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1) |
| #define WL18XX_EEPROMLESS_IND (WL18XX_SCR_PAD4) |
| |
| #define WL18XX_WELP_ARM_COMMAND (WL18XX_REGISTERS_BASE + 0x7100) |
| #define WL18XX_ENABLE (WL18XX_REGISTERS_BASE + 0x01543C) |
| |
| #define WL18XX_CMD_MBOX_ADDRESS 0xB007B4 |
| |
| #define WL18XX_FW_STATUS_ADDR 0x50F8 |
| |
| #define CHIP_ID_185x_PG10 (0x06030101) |
| |
| /* |
| * Host Command Interrupt. Setting this bit masks |
| * the interrupt that the host issues to inform |
| * the FW that it has sent a command |
| * to the Wlan hardware Command Mailbox. |
| */ |
| #define WL18XX_INTR_TRIG_CMD BIT(28) |
| |
| /* |
| * Host Event Acknowlegde Interrupt. The host |
| * sets this bit to acknowledge that it received |
| * the unsolicited information from the event |
| * mailbox. |
| */ |
| #define WL18XX_INTR_TRIG_EVENT_ACK BIT(29) |
| |
| /* TODO: maybe move elsewhere? */ |
| #define NUM_OF_CHANNELS_11_ABG 150 |
| #define NUM_OF_CHANNELS_11_P 7 |
| #define WL18XX_NUM_OF_SUB_BANDS 9 |
| #define SRF_TABLE_LEN 16 |
| #define PIN_MUXING_SIZE 2 |
| |
| enum { |
| COMPONENT_NO_SWITCH = 0x0, |
| COMPONENT_2_WAY_SWITCH = 0x1, |
| COMPONENT_3_WAY_SWITCH = 0x2, |
| COMPONENT_MATCHING = 0x3, |
| }; |
| |
| enum { |
| FEM_NONE = 0x0, |
| FEM_VENDOR_1 = 0x1, |
| FEM_VENDOR_2 = 0x2, |
| FEM_VENDOR_3 = 0x3, |
| }; |
| |
| enum { |
| BOARD_TYPE_FPGA_18XX = 0, |
| BOARD_TYPE_HDK_18XX = 1, |
| BOARD_TYPE_DVP_EVB_18XX = 2, |
| |
| NUM_BOARD_TYPES, |
| }; |
| |
| /* board type values used by the firmware in the SCR_PAD2 register */ |
| enum { |
| SCR_PAD2_BOARD_TYPE_FPGA = 0xB1, |
| SCR_PAD2_BOARD_TYPE_HDK = 0xB2, |
| SCR_PAD2_BOARD_TYPE_DVP_EVB = 0xB3, |
| }; |
| |
| struct wl18xx_mac_and_phy_params { |
| u8 phy_standalone; |
| u8 rdl; |
| u8 enable_clpc; |
| u8 enable_tx_low_pwr_on_siso_rdl; |
| u8 auto_detect; |
| u8 dedicated_fem; |
| |
| u8 low_band_component; |
| |
| /* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */ |
| u8 low_band_component_type; |
| |
| u8 high_band_component; |
| |
| /* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */ |
| u8 high_band_component_type; |
| u8 number_of_assembled_ant2_4; |
| u8 number_of_assembled_ant5; |
| u8 pin_muxing_platform_options[PIN_MUXING_SIZE]; |
| u8 external_pa_dc2dc; |
| u8 tcxo_ldo_voltage; |
| u8 xtal_itrim_val; |
| u8 srf_state; |
| u8 srf1[SRF_TABLE_LEN]; |
| u8 srf2[SRF_TABLE_LEN]; |
| u8 srf3[SRF_TABLE_LEN]; |
| u8 io_configuration; |
| u8 sdio_configuration; |
| u8 settings; |
| u8 rx_profile; |
| u8 per_chan_pwr_limit_arr_11abg[NUM_OF_CHANNELS_11_ABG]; |
| u8 pwr_limit_reference_11_abg; |
| u8 per_chan_pwr_limit_arr_11p[NUM_OF_CHANNELS_11_P]; |
| u8 pwr_limit_reference_11p; |
| u8 per_sub_band_tx_trace_loss[WL18XX_NUM_OF_SUB_BANDS]; |
| u8 per_sub_band_rx_trace_loss[WL18XX_NUM_OF_SUB_BANDS]; |
| u8 primary_clock_setting_time; |
| u8 clock_valid_on_wake_up; |
| u8 secondary_clock_setting_time; |
| u8 board_type; |
| u8 padding[1]; |
| } __packed; |
| |
| #endif /* __REG_H__ */ |